import PULS_20160108

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / kernel / entry-armv.S

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 32640ae7750f78ce294cba0b22d6e2ad3168927c..ea4e710f4774f377ff2e57e2a48720c96d2c9949 100644 (file)
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -685,6 +685,28 @@ ENDPROC(ret_from_exception)
 ENTRY(__switch_to)
  UNWIND(.fnstart       )
  UNWIND(.cantunwind    )
+#ifdef CONFIG_VFP_OPT
+       add     ip, r1, #TI_CPU_SAVE
+       stmfa   ip!, {r0, r1, r2, r5, r6, r8, lr}
+
+       @1. save vfp state for previous thread_info
+       mov     r0, r1
+       add     r0, r0, #TI_VFPSTATE    @ r0 = workspace
+       VFPFMRX r1, FPEXC
+       mov     r5, ip                  @ save ip to r5, because vfp_save_state may change ip
+       mov     r6, r2                  @ save r2 to r6, because vfp_save_state may change r2
+       bl      vfp_save_state
+       mov     ip, r5
+       mov     r2, r6
+
+       @ 2. restore vfp state from next thread_info
+       add     r2, r2, #TI_VFPSTATE    @ r2 = workspace
+       VFPFLDMIA       r2, r0          @ reload the working registers while
+                                       @ FPEXC is in a safe state
+       ldmia   r2, {r1, r5, r6, r8}    @ load FPEXC, FPSCR, FPINST, FPINST2
+       VFPFMXR FPSCR, r5               @ restore status
+       ldmfa   ip!, {r0, r1, r2, r5, r6, r8, lr}
+#endif
        add     ip, r1, #TI_CPU_SAVE
        ldr     r3, [r2, #TI_TP_VALUE]
  ARM(  stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack