import PULS_20160108

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / include / asm / hardware / coresight.h

diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 0cf7a6b842ff4ad40847394ea5ff8fd77bce29e7..4aee45da6d599501cc1afd08bc1bdf6593f240ec 100644 (file)
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -17,15 +17,23 @@
 #define TRACER_ACCESSED_BIT    0
 #define TRACER_RUNNING_BIT     1
 #define TRACER_CYCLE_ACC_BIT   2
+#define TRACER_TRACE_DATA_BIT  3
+#define TRACER_TIMESTAMP_BIT   4
+#define TRACER_BRANCHOUTPUT_BIT        5
+#define TRACER_RETURN_STACK_BIT        6
 #define TRACER_ACCESSED                BIT(TRACER_ACCESSED_BIT)
 #define TRACER_RUNNING         BIT(TRACER_RUNNING_BIT)
 #define TRACER_CYCLE_ACC       BIT(TRACER_CYCLE_ACC_BIT)
+#define TRACER_TRACE_DATA      BIT(TRACER_TRACE_DATA_BIT)
+#define TRACER_TIMESTAMP       BIT(TRACER_TIMESTAMP_BIT)
+#define TRACER_BRANCHOUTPUT    BIT(TRACER_BRANCHOUTPUT_BIT)
+#define TRACER_RETURN_STACK    BIT(TRACER_RETURN_STACK_BIT)
 
 #define TRACER_TIMEOUT 10000
 
-#define etm_writel(t, v, x) \
-       (__raw_writel((v), (t)->etm_regs + (x)))
-#define etm_readl(t, x) (__raw_readl((t)->etm_regs + (x)))
+#define etm_writel(t, id, v, x) \
+       (__raw_writel((v), (t)->etm_regs[(id)] + (x)))
+#define etm_readl(t, id, x) (__raw_readl((t)->etm_regs[(id)] + (x)))
 
 /* CoreSight Management Registers */
 #define CSMR_LOCKACCESS 0xfb0
@@ -43,7 +51,7 @@
 #define ETMCTRL_POWERDOWN      1
 #define ETMCTRL_PROGRAM                (1 << 10)
 #define ETMCTRL_PORTSEL                (1 << 11)
-#define ETMCTRL_DO_CONTEXTID   (3 << 14)
+#define ETMCTRL_CONTEXTIDSIZE(x) (((x) & 3) << 14)
 #define ETMCTRL_PORTMASK1      (7 << 4)
 #define ETMCTRL_PORTMASK2      (1 << 21)
 #define ETMCTRL_PORTMASK       (ETMCTRL_PORTMASK1 | ETMCTRL_PORTMASK2)
@@ -55,9 +63,12 @@
 #define ETMCTRL_DATA_DO_BOTH   (ETMCTRL_DATA_DO_DATA | ETMCTRL_DATA_DO_ADDR)
 #define ETMCTRL_BRANCH_OUTPUT  (1 << 8)
 #define ETMCTRL_CYCLEACCURATE  (1 << 12)
+#define ETMCTRL_TIMESTAMP_EN   (1 << 28)
+#define ETMCTRL_RETURN_STACK_EN        (1 << 29)
 
 /* ETM configuration code register */
 #define ETMR_CONFCODE          (0x04)
+#define ETMCCR_ETMIDR_PRESENT  BIT(31)
 
 /* ETM trace start/stop resource control register */
 #define ETMR_TRACESSCTRL       (0x18)
@@ -113,10 +124,25 @@
 #define ETMR_TRACEENCTRL       0x24
 #define ETMTE_INCLEXCL         BIT(24)
 #define ETMR_TRACEENEVT                0x20
-#define ETMCTRL_OPTS           (ETMCTRL_DO_CPRT | \
-                               ETMCTRL_DATA_DO_ADDR | \
-                               ETMCTRL_BRANCH_OUTPUT | \
-                               ETMCTRL_DO_CONTEXTID)
+
+#define ETMR_VIEWDATAEVT       0x30
+#define ETMR_VIEWDATACTRL1     0x34
+#define ETMR_VIEWDATACTRL2     0x38
+#define ETMR_VIEWDATACTRL3     0x3c
+#define ETMVDC3_EXCLONLY       BIT(16)
+
+#define ETMCTRL_OPTS           (ETMCTRL_DO_CPRT)
+
+#define ETMR_ID                        0x1e4
+#define ETMIDR_VERSION(x)      (((x) >> 4) & 0xff)
+#define ETMIDR_VERSION_3_1     0x21
+#define ETMIDR_VERSION_PFT_1_0 0x30
+
+#define ETMR_CCE               0x1e8
+#define ETMCCER_RETURN_STACK_IMPLEMENTED       BIT(23)
+#define ETMCCER_TIMESTAMPING_IMPLEMENTED       BIT(22)
+
+#define ETMR_TRACEIDR          0x200
 
 /* ETM management registers, "ETM Architecture", 3.5.24 */
 #define ETMMR_OSLAR    0x300
@@ -140,14 +166,16 @@
 #define ETBFF_TRIGIN           BIT(8)
 #define ETBFF_TRIGEVT          BIT(9)
 #define ETBFF_TRIGFL           BIT(10)
+#define ETBFF_STOPFL           BIT(12)
 
 #define etb_writel(t, v, x) \
        (__raw_writel((v), (t)->etb_regs + (x)))
 #define etb_readl(t, x) (__raw_readl((t)->etb_regs + (x)))
 
-#define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
-#define etm_unlock(t) \
-       do { etm_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
+#define etm_lock(t, id) \
+       do { etm_writel((t), (id), 0, CSMR_LOCKACCESS); } while (0)
+#define etm_unlock(t, id) \
+       do { etm_writel((t), (id), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
 
 #define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
 #define etb_unlock(t) \