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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git]
/
arch
/
arm
/
include
/
asm
/
cputype.h
diff --git
a/arch/arm/include/asm/cputype.h
b/arch/arm/include/asm/cputype.h
index 7652712d1d149ea07a8e5052746391014124ffdf..9347a1c69e372c55b3b8d3294e6a515e1fbdfe4a 100644
(file)
--- a/
arch/arm/include/asm/cputype.h
+++ b/
arch/arm/include/asm/cputype.h
@@
-9,6
+9,7
@@
#define CPUID_TCM 2
#define CPUID_TLBTYPE 3
#define CPUID_MPIDR 5
#define CPUID_TCM 2
#define CPUID_TLBTYPE 3
#define CPUID_MPIDR 5
+#define CPUID_REVIDR 6
#define CPUID_EXT_PFR0 "c1, 0"
#define CPUID_EXT_PFR1 "c1, 1"
#define CPUID_EXT_PFR0 "c1, 0"
#define CPUID_EXT_PFR1 "c1, 1"
@@
-32,6
+33,8
@@
#define MPIDR_HWID_BITMASK 0xFFFFFF
#define MPIDR_HWID_BITMASK 0xFFFFFF
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
#define MPIDR_LEVEL_BITS 8
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
#define MPIDR_LEVEL_BITS 8
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
@@
-50,6
+53,9
@@
#define ARM_CPU_PART_CORTEX_A5 0xC050
#define ARM_CPU_PART_CORTEX_A15 0xC0F0
#define ARM_CPU_PART_CORTEX_A7 0xC070
#define ARM_CPU_PART_CORTEX_A5 0xC050
#define ARM_CPU_PART_CORTEX_A15 0xC0F0
#define ARM_CPU_PART_CORTEX_A7 0xC070
+#define ARM_CPU_PART_CORTEX_A12 0xC0D0
+#define ARM_CPU_PART_CORTEX_A17 0xC0E0
+#define ARM_CPU_PART_CORTEX_A53 0xD030
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
#define ARM_CPU_XSCALE_ARCH_V1 0x2000
#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
#define ARM_CPU_XSCALE_ARCH_V1 0x2000