import PULS_20160108

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / include / asm / cacheflush.h

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index bff71388e72a163c4c18c93fc745f72db9b29e00..3d553d80878610bda754499a765e899d75ac95d5 100644 (file)
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -16,6 +16,7 @@
 #include <asm/shmparam.h>
 #include <asm/cachetype.h>
 #include <asm/outercache.h>
+#include <asm/rodata.h>
 
 #define CACHE_COLOUR(vaddr)    ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
 
@@ -184,15 +185,34 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
  */
 
 /* Invalidate I-cache */
+#ifdef CONFIG_ARM_ERRATA_831171                                         
+#define __flush_icache_all_generic()                                   \
+       do {                                                            \
+       asm("mcr        p15, 0, %0, c7, c5, 0"                          \
+           : : "r" (0));                                               \
+       asm("mcr        p15, 0, %0, c7, c5, 0"                          \
+           : : "r" (0));                                               \
+       } while (0)
+#else
 #define __flush_icache_all_generic()                                   \
        asm("mcr        p15, 0, %0, c7, c5, 0"                          \
            : : "r" (0));
+#endif
 
 /* Invalidate I-cache inner shareable */
+#ifdef CONFIG_ARM_ERRATA_831171
+#define __flush_icache_all_v7_smp()                                    \
+       do {                                                            \
+       asm("mcr        p15, 0, %0, c7, c1, 0"                          \
+           : : "r" (0));                                               \
+       asm("mcr        p15, 0, %0, c7, c1, 0"                          \
+           : : "r" (0));                                               \
+       } while (0)
+#else
 #define __flush_icache_all_v7_smp()                                    \
        asm("mcr        p15, 0, %0, c7, c1, 0"                          \
            : : "r" (0));
-
+#endif
 /*
  * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
  * will fall through to use __flush_icache_all_generic.
@@ -212,6 +232,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 static inline void __flush_icache_all(void)
 {
        __flush_icache_preferred();
+       dsb();
 }
 
 /*
@@ -320,9 +341,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 }
 
 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
-static inline void flush_kernel_dcache_page(struct page *page)
-{
-}
+extern void flush_kernel_dcache_page(struct page *);
 
 #define flush_dcache_mmap_lock(mapping) \
        spin_lock_irq(&(mapping)->tree_lock)