#include <asm/shmparam.h>
#include <asm/cachetype.h>
#include <asm/outercache.h>
+#include <asm/rodata.h>
#define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
*/
/* Invalidate I-cache */
+#ifdef CONFIG_ARM_ERRATA_831171
+#define __flush_icache_all_generic() \
+ do { \
+ asm("mcr p15, 0, %0, c7, c5, 0" \
+ : : "r" (0)); \
+ asm("mcr p15, 0, %0, c7, c5, 0" \
+ : : "r" (0)); \
+ } while (0)
+#else
#define __flush_icache_all_generic() \
asm("mcr p15, 0, %0, c7, c5, 0" \
: : "r" (0));
+#endif
/* Invalidate I-cache inner shareable */
+#ifdef CONFIG_ARM_ERRATA_831171
+#define __flush_icache_all_v7_smp() \
+ do { \
+ asm("mcr p15, 0, %0, c7, c1, 0" \
+ : : "r" (0)); \
+ asm("mcr p15, 0, %0, c7, c1, 0" \
+ : : "r" (0)); \
+ } while (0)
+#else
#define __flush_icache_all_v7_smp() \
asm("mcr p15, 0, %0, c7, c1, 0" \
: : "r" (0));
-
+#endif
/*
* Optimized __flush_icache_all for the common cases. Note that UP ARMv7
* will fall through to use __flush_icache_all_generic.
static inline void __flush_icache_all(void)
{
__flush_icache_preferred();
+ dsb();
}
/*
}
#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
-static inline void flush_kernel_dcache_page(struct page *page)
-{
-}
+extern void flush_kernel_dcache_page(struct page *);
#define flush_dcache_mmap_lock(mapping) \
spin_lock_irq(&(mapping)->tree_lock)