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Merge tag 'v3.10.55' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / max98090.c
1 /*
2 * max98090.c -- MAX98090 ALSA SoC Audio driver
3 *
4 * Copyright 2011-2012 Maxim Integrated Products
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/pm.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <sound/jack.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 #include <sound/max98090.h>
24 #include "max98090.h"
25
26 #define DEBUG
27 #define EXTMIC_METHOD
28 #define EXTMIC_METHOD_TEST
29
30 /* Allows for sparsely populated register maps */
31 static struct reg_default max98090_reg[] = {
32 { 0x00, 0x00 }, /* 00 Software Reset */
33 { 0x03, 0x04 }, /* 03 Interrupt Masks */
34 { 0x04, 0x00 }, /* 04 System Clock Quick */
35 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
36 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
37 { 0x07, 0x00 }, /* 07 DAC Path Quick */
38 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
39 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
40 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
41 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
42 { 0x0C, 0x00 }, /* 0C Reserved */
43 { 0x0D, 0x00 }, /* 0D Input Config */
44 { 0x0E, 0x1B }, /* 0E Line Input Level */
45 { 0x0F, 0x00 }, /* 0F Line Config */
46
47 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
48 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
49 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
50 { 0x13, 0x00 }, /* 13 Digital Mic Config */
51 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
52 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
53 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
54 { 0x17, 0x03 }, /* 17 Left ADC Level */
55 { 0x18, 0x03 }, /* 18 Right ADC Level */
56 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
57 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
58 { 0x1B, 0x00 }, /* 1B System Clock */
59 { 0x1C, 0x00 }, /* 1C Clock Mode */
60 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
61 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
62 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
63
64 { 0x20, 0x00 }, /* 20 Any Clock 4 */
65 { 0x21, 0x00 }, /* 21 Master Mode */
66 { 0x22, 0x00 }, /* 22 Interface Format */
67 { 0x23, 0x00 }, /* 23 TDM Format 1*/
68 { 0x24, 0x00 }, /* 24 TDM Format 2*/
69 { 0x25, 0x00 }, /* 25 I/O Configuration */
70 { 0x26, 0x80 }, /* 26 Filter Config */
71 { 0x27, 0x00 }, /* 27 DAI Playback Level */
72 { 0x28, 0x00 }, /* 28 EQ Playback Level */
73 { 0x29, 0x00 }, /* 29 Left HP Mixer */
74 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
75 { 0x2B, 0x00 }, /* 2B HP Control */
76 { 0x2C, 0x1A }, /* 2C Left HP Volume */
77 { 0x2D, 0x1A }, /* 2D Right HP Volume */
78 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
79 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
80
81 { 0x30, 0x00 }, /* 30 Spk Control */
82 { 0x31, 0x2C }, /* 31 Left Spk Volume */
83 { 0x32, 0x2C }, /* 32 Right Spk Volume */
84 { 0x33, 0x00 }, /* 33 ALC Timing */
85 { 0x34, 0x00 }, /* 34 ALC Compressor */
86 { 0x35, 0x00 }, /* 35 ALC Expander */
87 { 0x36, 0x00 }, /* 36 ALC Gain */
88 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
89 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
90 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
91 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
92 { 0x3B, 0x00 }, /* 3B Line OutR Control */
93 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
94 { 0x3D, 0x00 }, /* 3D Jack Detect */
95 { 0x3E, 0x00 }, /* 3E Input Enable */
96 { 0x3F, 0x00 }, /* 3F Output Enable */
97
98 { 0x40, 0x00 }, /* 40 Level Control */
99 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
100 { 0x42, 0x00 }, /* 42 Bias Control */
101 { 0x43, 0x00 }, /* 43 DAC Control */
102 { 0x44, 0x06 }, /* 44 ADC Control */
103 { 0x45, 0x00 }, /* 45 Device Shutdown */
104 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
105 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
106 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
107 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
108 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
109 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
110 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
111 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
112 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
113 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
114
115 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
116 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
117 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
118 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
119 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
120 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
121 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
122 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
123 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
124 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
125 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
126 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
127 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
128 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
129 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
130 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
131
132 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
133 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
134 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
135 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
136 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
137 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
138 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
139 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
140 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
141 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
142 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
143 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
144 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
145 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
146 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
147 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
148
149 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
150 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
151 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
152 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
153 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
154 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
155 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
156 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
157 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
158 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
159 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
160 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
161 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
162 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
163 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
164 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
165
166 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
167 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
168 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
169 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
170 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
171 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
172 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
173 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
174 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
175 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
176 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
177 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
178 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
179 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
180 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
181 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
182
183 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
184 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
185 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
186 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
187 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
188 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
189 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
190 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
191 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
192 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
193 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
194 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
195 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
196 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
197 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
198 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
199
200 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
201 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
202 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
203 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
204 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
205 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
206 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
207 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
208 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
209 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
210 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
211 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
212 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
213 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
214 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
215 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
216
217 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
218 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
219 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
220 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
221 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
222 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
223 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
224 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
225 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
226 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
227 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
228 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
229 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
230 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
231 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
232 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
233
234 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
235 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
236 { 0xC2, 0x00 }, /* C2 Sample Rate */
237 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
238 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
239 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
240 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
241 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
242 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
243 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
244 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
245 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
246 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
247 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
248 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
249 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
250
251 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
252 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
253 };
254
255 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
256 {
257 switch (reg) {
258 case M98090_REG_SOFTWARE_RESET:
259 case M98090_REG_DEVICE_STATUS:
260 case M98090_REG_JACK_STATUS:
261 case M98090_REG_REVISION_ID:
262 return true;
263 default:
264 return false;
265 }
266 }
267
268 static bool max98090_readable_register(struct device *dev, unsigned int reg)
269 {
270 switch (reg) {
271 case M98090_REG_DEVICE_STATUS:
272 case M98090_REG_JACK_STATUS:
273 case M98090_REG_INTERRUPT_S:
274 case M98090_REG_RESERVED:
275 case M98090_REG_LINE_INPUT_CONFIG:
276 case M98090_REG_LINE_INPUT_LEVEL:
277 case M98090_REG_INPUT_MODE:
278 case M98090_REG_MIC1_INPUT_LEVEL:
279 case M98090_REG_MIC2_INPUT_LEVEL:
280 case M98090_REG_MIC_BIAS_VOLTAGE:
281 case M98090_REG_DIGITAL_MIC_ENABLE:
282 case M98090_REG_DIGITAL_MIC_CONFIG:
283 case M98090_REG_LEFT_ADC_MIXER:
284 case M98090_REG_RIGHT_ADC_MIXER:
285 case M98090_REG_LEFT_ADC_LEVEL:
286 case M98090_REG_RIGHT_ADC_LEVEL:
287 case M98090_REG_ADC_BIQUAD_LEVEL:
288 case M98090_REG_ADC_SIDETONE:
289 case M98090_REG_SYSTEM_CLOCK:
290 case M98090_REG_CLOCK_MODE:
291 case M98090_REG_CLOCK_RATIO_NI_MSB:
292 case M98090_REG_CLOCK_RATIO_NI_LSB:
293 case M98090_REG_CLOCK_RATIO_MI_MSB:
294 case M98090_REG_CLOCK_RATIO_MI_LSB:
295 case M98090_REG_MASTER_MODE:
296 case M98090_REG_INTERFACE_FORMAT:
297 case M98090_REG_TDM_CONTROL:
298 case M98090_REG_TDM_FORMAT:
299 case M98090_REG_IO_CONFIGURATION:
300 case M98090_REG_FILTER_CONFIG:
301 case M98090_REG_DAI_PLAYBACK_LEVEL:
302 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
303 case M98090_REG_LEFT_HP_MIXER:
304 case M98090_REG_RIGHT_HP_MIXER:
305 case M98090_REG_HP_CONTROL:
306 case M98090_REG_LEFT_HP_VOLUME:
307 case M98090_REG_RIGHT_HP_VOLUME:
308 case M98090_REG_LEFT_SPK_MIXER:
309 case M98090_REG_RIGHT_SPK_MIXER:
310 case M98090_REG_SPK_CONTROL:
311 case M98090_REG_LEFT_SPK_VOLUME:
312 case M98090_REG_RIGHT_SPK_VOLUME:
313 case M98090_REG_DRC_TIMING:
314 case M98090_REG_DRC_COMPRESSOR:
315 case M98090_REG_DRC_EXPANDER:
316 case M98090_REG_DRC_GAIN:
317 case M98090_REG_RCV_LOUTL_MIXER:
318 case M98090_REG_RCV_LOUTL_CONTROL:
319 case M98090_REG_RCV_LOUTL_VOLUME:
320 case M98090_REG_LOUTR_MIXER:
321 case M98090_REG_LOUTR_CONTROL:
322 case M98090_REG_LOUTR_VOLUME:
323 case M98090_REG_JACK_DETECT:
324 case M98090_REG_INPUT_ENABLE:
325 case M98090_REG_OUTPUT_ENABLE:
326 case M98090_REG_LEVEL_CONTROL:
327 case M98090_REG_DSP_FILTER_ENABLE:
328 case M98090_REG_BIAS_CONTROL:
329 case M98090_REG_DAC_CONTROL:
330 case M98090_REG_ADC_CONTROL:
331 case M98090_REG_DEVICE_SHUTDOWN:
332 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
333 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
334 case M98090_REG_DMIC3_VOLUME:
335 case M98090_REG_DMIC4_VOLUME:
336 case M98090_REG_DMIC34_BQ_PREATTEN:
337 case M98090_REG_RECORD_TDM_SLOT:
338 case M98090_REG_SAMPLE_RATE:
339 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
340 case M98090_REG_REVISION_ID:
341 return true;
342 default:
343 return false;
344 }
345 }
346
347 static int max98090_reset(struct max98090_priv *max98090)
348 {
349 int ret;
350
351 /* Reset the codec by writing to this write-only reset register */
352 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
353 M98090_SWRESET_MASK);
354 if (ret < 0) {
355 dev_err(max98090->codec->dev,
356 "Failed to reset codec: %d\n", ret);
357 return ret;
358 }
359
360 msleep(20);
361 return ret;
362 }
363
364 static const unsigned int max98090_micboost_tlv[] = {
365 TLV_DB_RANGE_HEAD(2),
366 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
367 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
368 };
369
370 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
371
372 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
373 -600, 600, 0);
374
375 static const unsigned int max98090_line_tlv[] = {
376 TLV_DB_RANGE_HEAD(2),
377 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
378 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
379 };
380
381 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
382 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
383
384 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
385 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
386
387 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
388
389 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
390 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
391 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
392 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
393
394 static const unsigned int max98090_mixout_tlv[] = {
395 TLV_DB_RANGE_HEAD(2),
396 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
397 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
398 };
399
400 static const unsigned int max98090_hp_tlv[] = {
401 TLV_DB_RANGE_HEAD(5),
402 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
403 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
404 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
405 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
406 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
407 };
408
409 static const unsigned int max98090_spk_tlv[] = {
410 TLV_DB_RANGE_HEAD(5),
411 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
412 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
413 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
414 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
415 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
416 };
417
418 static const unsigned int max98090_rcv_lout_tlv[] = {
419 TLV_DB_RANGE_HEAD(5),
420 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
421 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
422 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
423 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
424 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
425 };
426
427 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
428 struct snd_ctl_elem_value *ucontrol)
429 {
430 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
431 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
432 struct soc_mixer_control *mc =
433 (struct soc_mixer_control *)kcontrol->private_value;
434 unsigned int mask = (1 << fls(mc->max)) - 1;
435 unsigned int val = snd_soc_read(codec, mc->reg);
436 unsigned int *select;
437
438 switch (mc->reg) {
439 case M98090_REG_MIC1_INPUT_LEVEL:
440 select = &(max98090->pa1en);
441 break;
442 case M98090_REG_MIC2_INPUT_LEVEL:
443 select = &(max98090->pa2en);
444 break;
445 case M98090_REG_ADC_SIDETONE:
446 select = &(max98090->sidetone);
447 break;
448 default:
449 return -EINVAL;
450 }
451
452 val = (val >> mc->shift) & mask;
453
454 if (val >= 1) {
455 /* If on, return the volume */
456 val = val - 1;
457 *select = val;
458 } else {
459 /* If off, return last stored value */
460 val = *select;
461 }
462
463 ucontrol->value.integer.value[0] = val;
464 return 0;
465 }
466
467 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
468 struct snd_ctl_elem_value *ucontrol)
469 {
470 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
471 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
472 struct soc_mixer_control *mc =
473 (struct soc_mixer_control *)kcontrol->private_value;
474 unsigned int mask = (1 << fls(mc->max)) - 1;
475 unsigned int sel = ucontrol->value.integer.value[0];
476 unsigned int val = snd_soc_read(codec, mc->reg);
477 unsigned int *select;
478
479 switch (mc->reg) {
480 case M98090_REG_MIC1_INPUT_LEVEL:
481 select = &(max98090->pa1en);
482 break;
483 case M98090_REG_MIC2_INPUT_LEVEL:
484 select = &(max98090->pa2en);
485 break;
486 case M98090_REG_ADC_SIDETONE:
487 select = &(max98090->sidetone);
488 break;
489 default:
490 return -EINVAL;
491 }
492
493 val = (val >> mc->shift) & mask;
494
495 *select = sel;
496
497 /* Setting a volume is only valid if it is already On */
498 if (val >= 1) {
499 sel = sel + 1;
500 } else {
501 /* Write what was already there */
502 sel = val;
503 }
504
505 snd_soc_update_bits(codec, mc->reg,
506 mask << mc->shift,
507 sel << mc->shift);
508
509 return 0;
510 }
511
512 static const char *max98090_perf_pwr_text[] =
513 { "High Performance", "Low Power" };
514 static const char *max98090_pwr_perf_text[] =
515 { "Low Power", "High Performance" };
516
517 static const struct soc_enum max98090_vcmbandgap_enum =
518 SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_SHIFT,
519 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
520
521 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
522
523 static const struct soc_enum max98090_osr128_enum =
524 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_OSR128_SHIFT,
525 ARRAY_SIZE(max98090_osr128_text), max98090_osr128_text);
526
527 static const char *max98090_mode_text[] = { "Voice", "Music" };
528
529 static const struct soc_enum max98090_mode_enum =
530 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, M98090_MODE_SHIFT,
531 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
532
533 static const struct soc_enum max98090_filter_dmic34mode_enum =
534 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG,
535 M98090_FLT_DMIC34MODE_SHIFT,
536 ARRAY_SIZE(max98090_mode_text), max98090_mode_text);
537
538 static const char *max98090_drcatk_text[] =
539 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
540
541 static const struct soc_enum max98090_drcatk_enum =
542 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCATK_SHIFT,
543 ARRAY_SIZE(max98090_drcatk_text), max98090_drcatk_text);
544
545 static const char *max98090_drcrls_text[] =
546 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
547
548 static const struct soc_enum max98090_drcrls_enum =
549 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCRLS_SHIFT,
550 ARRAY_SIZE(max98090_drcrls_text), max98090_drcrls_text);
551
552 static const char *max98090_alccmp_text[] =
553 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
554
555 static const struct soc_enum max98090_alccmp_enum =
556 SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR, M98090_DRCCMP_SHIFT,
557 ARRAY_SIZE(max98090_alccmp_text), max98090_alccmp_text);
558
559 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
560
561 static const struct soc_enum max98090_drcexp_enum =
562 SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER, M98090_DRCEXP_SHIFT,
563 ARRAY_SIZE(max98090_drcexp_text), max98090_drcexp_text);
564
565 static const struct soc_enum max98090_dac_perfmode_enum =
566 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_PERFMODE_SHIFT,
567 ARRAY_SIZE(max98090_perf_pwr_text), max98090_perf_pwr_text);
568
569 static const struct soc_enum max98090_dachp_enum =
570 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_DACHP_SHIFT,
571 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
572
573 static const struct soc_enum max98090_adchp_enum =
574 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_ADCHP_SHIFT,
575 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text);
576
577 static const struct snd_kcontrol_new max98090_snd_controls[] = {
578 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
579
580 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
581 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
582
583 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
584 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
585 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
586 max98090_put_enab_tlv, max98090_micboost_tlv),
587
588 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
589 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
590 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
591 max98090_put_enab_tlv, max98090_micboost_tlv),
592
593 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
594 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
595 max98090_mic_tlv),
596
597 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
598 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
599 max98090_mic_tlv),
600
601 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
602 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
603 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
604
605 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
606 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
607 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
608
609 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
610 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
611 max98090_line_tlv),
612
613 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
614 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
615 max98090_line_tlv),
616
617 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
618 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
619 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
620 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
621
622 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
623 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
624 max98090_avg_tlv),
625 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
626 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
627 max98090_avg_tlv),
628
629 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
630 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
631 max98090_av_tlv),
632 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
633 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
634 max98090_av_tlv),
635
636 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
637 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
638 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
639 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
640
641 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
642 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
643 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
644 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
645 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
646 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
647 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
648 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
649 SOC_ENUM("Filter Mode", max98090_mode_enum),
650 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
651 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
652 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
653 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
654 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
655 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
656 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
657 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
658 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
659 max98090_put_enab_tlv, max98090_micboost_tlv),
660 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
661 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
662 max98090_dvg_tlv),
663 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
664 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
665 max98090_dv_tlv),
666 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
667 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
668 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
669 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
670 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
671 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
672 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
673 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
674 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
675 1),
676 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
677 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
678 max98090_dv_tlv),
679
680 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
681 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
682 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
683 SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
684 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
685 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
686 max98090_alcmakeup_tlv),
687 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
688 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
689 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
690 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
691 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
692 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
693 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
694 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
695
696 SOC_ENUM("DAC HP Playback Performance Mode",
697 max98090_dac_perfmode_enum),
698 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
699
700 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
701 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
702 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
703 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
704 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
705 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
706
707 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
708 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
709 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
710 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
711 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
712 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
713
714 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
715 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
716 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
717 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
718 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
719 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
720
721 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
722 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
723 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
724
725 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
726 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
727 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
728 0, max98090_spk_tlv),
729
730 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
731 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
732 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
733
734 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
735 M98090_HPLM_SHIFT, 1, 1),
736 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
737 M98090_HPRM_SHIFT, 1, 1),
738
739 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
740 M98090_SPLM_SHIFT, 1, 1),
741 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
742 M98090_SPRM_SHIFT, 1, 1),
743
744 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
745 M98090_RCVLM_SHIFT, 1, 1),
746 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
747 M98090_RCVRM_SHIFT, 1, 1),
748
749 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
750 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
751 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
752 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
753 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
754 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
755
756 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
757 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
758 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
759 };
760
761 static const struct snd_kcontrol_new max98091_snd_controls[] = {
762
763 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
764 M98090_DMIC34_ZEROPAD_SHIFT,
765 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
766
767 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
768 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
769 M98090_FLT_DMIC34HPF_SHIFT,
770 M98090_FLT_DMIC34HPF_NUM - 1, 0),
771
772 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
773 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
774 max98090_avg_tlv),
775 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
776 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
777 max98090_avg_tlv),
778
779 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
780 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
781 max98090_av_tlv),
782 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
783 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
784 max98090_av_tlv),
785
786 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
787 M98090_REG_DMIC34_BIQUAD_BASE, 15),
788 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
789 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
790
791 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
792 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
793 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
794 };
795
796 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
797 struct snd_kcontrol *kcontrol, int event)
798 {
799 struct snd_soc_codec *codec = w->codec;
800 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
801
802 unsigned int val = snd_soc_read(codec, w->reg);
803
804 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
805 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
806 else
807 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
808
809
810 if (val >= 1) {
811 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
812 max98090->pa1en = val - 1; /* Update for volatile */
813 } else {
814 max98090->pa2en = val - 1; /* Update for volatile */
815 }
816 }
817
818 switch (event) {
819 case SND_SOC_DAPM_POST_PMU:
820 /* If turning on, set to most recently selected volume */
821 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
822 val = max98090->pa1en + 1;
823 else
824 val = max98090->pa2en + 1;
825 break;
826 case SND_SOC_DAPM_POST_PMD:
827 /* If turning off, turn off */
828 val = 0;
829 break;
830 default:
831 return -EINVAL;
832 }
833
834 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
835 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
836 val << M98090_MIC_PA1EN_SHIFT);
837 else
838 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
839 val << M98090_MIC_PA2EN_SHIFT);
840
841 return 0;
842 }
843
844 static const char *mic1_mux_text[] = { "IN12", "IN56" };
845
846 static const struct soc_enum mic1_mux_enum =
847 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC1_SHIFT,
848 ARRAY_SIZE(mic1_mux_text), mic1_mux_text);
849
850 static const struct snd_kcontrol_new max98090_mic1_mux =
851 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
852
853 static const char *mic2_mux_text[] = { "IN34", "IN56" };
854
855 static const struct soc_enum mic2_mux_enum =
856 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC2_SHIFT,
857 ARRAY_SIZE(mic2_mux_text), mic2_mux_text);
858
859 static const struct snd_kcontrol_new max98090_mic2_mux =
860 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
861
862 static const char *max98090_micpre_text[] = { "Off", "On" };
863
864 static const struct soc_enum max98090_pa1en_enum =
865 SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
866 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
867
868 static const struct soc_enum max98090_pa2en_enum =
869 SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
870 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text);
871
872 /* LINEA mixer switch */
873 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
874 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
875 M98090_IN1SEEN_SHIFT, 1, 0),
876 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
877 M98090_IN3SEEN_SHIFT, 1, 0),
878 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
879 M98090_IN5SEEN_SHIFT, 1, 0),
880 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
881 M98090_IN34DIFF_SHIFT, 1, 0),
882 };
883
884 /* LINEB mixer switch */
885 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
886 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
887 M98090_IN2SEEN_SHIFT, 1, 0),
888 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
889 M98090_IN4SEEN_SHIFT, 1, 0),
890 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
891 M98090_IN6SEEN_SHIFT, 1, 0),
892 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
893 M98090_IN56DIFF_SHIFT, 1, 0),
894 };
895
896 /* Left ADC mixer switch */
897 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
898 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
899 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
900 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
901 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
902 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
903 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
904 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
905 M98090_MIXADL_LINEA_SHIFT, 1, 0),
906 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
907 M98090_MIXADL_LINEB_SHIFT, 1, 0),
908 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
909 M98090_MIXADL_MIC1_SHIFT, 1, 0),
910 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
911 M98090_MIXADL_MIC2_SHIFT, 1, 0),
912 };
913
914 /* Right ADC mixer switch */
915 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
916 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
917 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
918 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
919 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
920 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
921 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
922 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
923 M98090_MIXADR_LINEA_SHIFT, 1, 0),
924 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
925 M98090_MIXADR_LINEB_SHIFT, 1, 0),
926 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
927 M98090_MIXADR_MIC1_SHIFT, 1, 0),
928 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
929 M98090_MIXADR_MIC2_SHIFT, 1, 0),
930 };
931
932 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
933
934 static const struct soc_enum ltenl_mux_enum =
935 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
936 ARRAY_SIZE(lten_mux_text), lten_mux_text);
937
938 static const struct soc_enum ltenr_mux_enum =
939 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT,
940 ARRAY_SIZE(lten_mux_text), lten_mux_text);
941
942 static const struct snd_kcontrol_new max98090_ltenl_mux =
943 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
944
945 static const struct snd_kcontrol_new max98090_ltenr_mux =
946 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
947
948 static const char *lben_mux_text[] = { "Normal", "Loopback" };
949
950 static const struct soc_enum lbenl_mux_enum =
951 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
952 ARRAY_SIZE(lben_mux_text), lben_mux_text);
953
954 static const struct soc_enum lbenr_mux_enum =
955 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT,
956 ARRAY_SIZE(lben_mux_text), lben_mux_text);
957
958 static const struct snd_kcontrol_new max98090_lbenl_mux =
959 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
960
961 static const struct snd_kcontrol_new max98090_lbenr_mux =
962 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
963
964 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
965
966 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
967
968 static const struct soc_enum stenl_mux_enum =
969 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSL_SHIFT,
970 ARRAY_SIZE(stenl_mux_text), stenl_mux_text);
971
972 static const struct soc_enum stenr_mux_enum =
973 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSR_SHIFT,
974 ARRAY_SIZE(stenr_mux_text), stenr_mux_text);
975
976 static const struct snd_kcontrol_new max98090_stenl_mux =
977 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
978
979 static const struct snd_kcontrol_new max98090_stenr_mux =
980 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
981
982 /* Left speaker mixer switch */
983 static const struct
984 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
985 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
986 M98090_MIXSPL_DACL_SHIFT, 1, 0),
987 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
988 M98090_MIXSPL_DACR_SHIFT, 1, 0),
989 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
990 M98090_MIXSPL_LINEA_SHIFT, 1, 0),
991 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
992 M98090_MIXSPL_LINEB_SHIFT, 1, 0),
993 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
994 M98090_MIXSPL_MIC1_SHIFT, 1, 0),
995 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
996 M98090_MIXSPL_MIC2_SHIFT, 1, 0),
997 };
998
999 /* Right speaker mixer switch */
1000 static const struct
1001 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1002 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1003 M98090_MIXSPR_DACL_SHIFT, 1, 0),
1004 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1005 M98090_MIXSPR_DACR_SHIFT, 1, 0),
1006 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1007 M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1008 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1009 M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1010 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1011 M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1012 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1013 M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1014 };
1015
1016 /* Left headphone mixer switch */
1017 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1018 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1019 M98090_MIXHPL_DACL_SHIFT, 1, 0),
1020 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1021 M98090_MIXHPL_DACR_SHIFT, 1, 0),
1022 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1023 M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1024 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1025 M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1026 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1027 M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1028 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1029 M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1030 };
1031
1032 /* Right headphone mixer switch */
1033 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1034 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1035 M98090_MIXHPR_DACL_SHIFT, 1, 0),
1036 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1037 M98090_MIXHPR_DACR_SHIFT, 1, 0),
1038 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1039 M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1040 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1041 M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1042 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1043 M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1044 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1045 M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1046 };
1047
1048 /* Left receiver mixer switch */
1049 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1050 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1051 M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1052 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1053 M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1054 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1055 M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1056 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1057 M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1058 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1059 M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1060 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1061 M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1062 };
1063
1064 /* Right receiver mixer switch */
1065 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1066 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1067 M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1068 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1069 M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1070 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1071 M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1072 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1073 M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1074 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1075 M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1076 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1077 M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1078 };
1079
1080 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1081
1082 static const struct soc_enum linmod_mux_enum =
1083 SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER, M98090_LINMOD_SHIFT,
1084 ARRAY_SIZE(linmod_mux_text), linmod_mux_text);
1085
1086 static const struct snd_kcontrol_new max98090_linmod_mux =
1087 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1088
1089 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1090
1091 /*
1092 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1093 */
1094 static const struct soc_enum mixhplsel_mux_enum =
1095 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPLSEL_SHIFT,
1096 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1097
1098 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1099 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1100
1101 static const struct soc_enum mixhprsel_mux_enum =
1102 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPRSEL_SHIFT,
1103 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text);
1104
1105 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1106 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1107
1108 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1109
1110 SND_SOC_DAPM_INPUT("MIC1"),
1111 SND_SOC_DAPM_INPUT("MIC2"),
1112 SND_SOC_DAPM_INPUT("DMICL"),
1113 SND_SOC_DAPM_INPUT("DMICR"),
1114 SND_SOC_DAPM_INPUT("IN1"),
1115 SND_SOC_DAPM_INPUT("IN2"),
1116 SND_SOC_DAPM_INPUT("IN3"),
1117 SND_SOC_DAPM_INPUT("IN4"),
1118 SND_SOC_DAPM_INPUT("IN5"),
1119 SND_SOC_DAPM_INPUT("IN6"),
1120 SND_SOC_DAPM_INPUT("IN12"),
1121 SND_SOC_DAPM_INPUT("IN34"),
1122 SND_SOC_DAPM_INPUT("IN56"),
1123
1124 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1125 M98090_MBEN_SHIFT, 0, NULL, 0),
1126 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1127 M98090_SHDNN_SHIFT, 0, NULL, 0),
1128 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1129 M98090_SDIEN_SHIFT, 0, NULL, 0),
1130 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1131 M98090_SDOEN_SHIFT, 0, NULL, 0),
1132 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1133 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1134 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1135 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1136 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1137 M98090_AHPF_SHIFT, 0, NULL, 0),
1138
1139 /*
1140 * Note: Sysclk and misc power supplies are taken care of by SHDN
1141 */
1142
1143 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1144 0, 0, &max98090_mic1_mux),
1145
1146 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1147 0, 0, &max98090_mic2_mux),
1148
1149 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1150 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1151 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1152
1153 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1154 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1155 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1156
1157 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1158 &max98090_linea_mixer_controls[0],
1159 ARRAY_SIZE(max98090_linea_mixer_controls)),
1160
1161 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1162 &max98090_lineb_mixer_controls[0],
1163 ARRAY_SIZE(max98090_lineb_mixer_controls)),
1164
1165 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1166 M98090_LINEAEN_SHIFT, 0, NULL, 0),
1167 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1168 M98090_LINEBEN_SHIFT, 0, NULL, 0),
1169
1170 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1171 &max98090_left_adc_mixer_controls[0],
1172 ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1173
1174 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1175 &max98090_right_adc_mixer_controls[0],
1176 ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1177
1178 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1179 M98090_ADLEN_SHIFT, 0),
1180 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1181 M98090_ADREN_SHIFT, 0),
1182
1183 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1184 SND_SOC_NOPM, 0, 0),
1185 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1186 SND_SOC_NOPM, 0, 0),
1187
1188 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1189 0, 0, &max98090_lbenl_mux),
1190
1191 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1192 0, 0, &max98090_lbenr_mux),
1193
1194 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1195 0, 0, &max98090_ltenl_mux),
1196
1197 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1198 0, 0, &max98090_ltenr_mux),
1199
1200 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1201 0, 0, &max98090_stenl_mux),
1202
1203 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1204 0, 0, &max98090_stenr_mux),
1205
1206 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1207 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1208
1209 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1210 M98090_DALEN_SHIFT, 0),
1211 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1212 M98090_DAREN_SHIFT, 0),
1213
1214 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1215 &max98090_left_hp_mixer_controls[0],
1216 ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1217
1218 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1219 &max98090_right_hp_mixer_controls[0],
1220 ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1221
1222 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1223 &max98090_left_speaker_mixer_controls[0],
1224 ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1225
1226 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1227 &max98090_right_speaker_mixer_controls[0],
1228 ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1229
1230 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1231 &max98090_left_rcv_mixer_controls[0],
1232 ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1233
1234 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1235 &max98090_right_rcv_mixer_controls[0],
1236 ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1237
1238 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1239 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1240
1241 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1242 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1243
1244 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1245 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1246
1247 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1248 M98090_HPLEN_SHIFT, 0, NULL, 0),
1249 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1250 M98090_HPREN_SHIFT, 0, NULL, 0),
1251
1252 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1253 M98090_SPLEN_SHIFT, 0, NULL, 0),
1254 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1255 M98090_SPREN_SHIFT, 0, NULL, 0),
1256
1257 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1258 M98090_RCVLEN_SHIFT, 0, NULL, 0),
1259 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1260 M98090_RCVREN_SHIFT, 0, NULL, 0),
1261
1262 SND_SOC_DAPM_OUTPUT("HPL"),
1263 SND_SOC_DAPM_OUTPUT("HPR"),
1264 SND_SOC_DAPM_OUTPUT("SPKL"),
1265 SND_SOC_DAPM_OUTPUT("SPKR"),
1266 SND_SOC_DAPM_OUTPUT("RCVL"),
1267 SND_SOC_DAPM_OUTPUT("RCVR"),
1268 };
1269
1270 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1271
1272 SND_SOC_DAPM_INPUT("DMIC3"),
1273 SND_SOC_DAPM_INPUT("DMIC4"),
1274
1275 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1276 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1277 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1278 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1279 };
1280
1281 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1282
1283 {"MIC1 Input", NULL, "MIC1"},
1284 {"MIC2 Input", NULL, "MIC2"},
1285
1286 {"DMICL", NULL, "DMICL_ENA"},
1287 {"DMICR", NULL, "DMICR_ENA"},
1288 {"DMICL", NULL, "AHPF"},
1289 {"DMICR", NULL, "AHPF"},
1290
1291 /* MIC1 input mux */
1292 {"MIC1 Mux", "IN12", "IN12"},
1293 {"MIC1 Mux", "IN56", "IN56"},
1294
1295 /* MIC2 input mux */
1296 {"MIC2 Mux", "IN34", "IN34"},
1297 {"MIC2 Mux", "IN56", "IN56"},
1298
1299 {"MIC1 Input", NULL, "MIC1 Mux"},
1300 {"MIC2 Input", NULL, "MIC2 Mux"},
1301
1302 /* Left ADC input mixer */
1303 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1304 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1305 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1306 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1307 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1308 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1309 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1310
1311 /* Right ADC input mixer */
1312 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1313 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1314 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1315 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1316 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1317 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1318 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1319
1320 /* Line A input mixer */
1321 {"LINEA Mixer", "IN1 Switch", "IN1"},
1322 {"LINEA Mixer", "IN3 Switch", "IN3"},
1323 {"LINEA Mixer", "IN5 Switch", "IN5"},
1324 {"LINEA Mixer", "IN34 Switch", "IN34"},
1325
1326 /* Line B input mixer */
1327 {"LINEB Mixer", "IN2 Switch", "IN2"},
1328 {"LINEB Mixer", "IN4 Switch", "IN4"},
1329 {"LINEB Mixer", "IN6 Switch", "IN6"},
1330 {"LINEB Mixer", "IN56 Switch", "IN56"},
1331
1332 {"LINEA Input", NULL, "LINEA Mixer"},
1333 {"LINEB Input", NULL, "LINEB Mixer"},
1334
1335 /* Inputs */
1336 {"ADCL", NULL, "Left ADC Mixer"},
1337 {"ADCR", NULL, "Right ADC Mixer"},
1338 {"ADCL", NULL, "SHDN"},
1339 {"ADCR", NULL, "SHDN"},
1340
1341 {"LBENL Mux", "Normal", "ADCL"},
1342 {"LBENL Mux", "Normal", "DMICL"},
1343 {"LBENL Mux", "Loopback", "LTENL Mux"},
1344 {"LBENR Mux", "Normal", "ADCR"},
1345 {"LBENR Mux", "Normal", "DMICR"},
1346 {"LBENR Mux", "Loopback", "LTENR Mux"},
1347
1348 {"AIFOUTL", NULL, "LBENL Mux"},
1349 {"AIFOUTR", NULL, "LBENR Mux"},
1350 {"AIFOUTL", NULL, "SHDN"},
1351 {"AIFOUTR", NULL, "SHDN"},
1352 {"AIFOUTL", NULL, "SDOEN"},
1353 {"AIFOUTR", NULL, "SDOEN"},
1354
1355 {"LTENL Mux", "Normal", "AIFINL"},
1356 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1357 {"LTENR Mux", "Normal", "AIFINR"},
1358 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1359
1360 {"DACL", NULL, "LTENL Mux"},
1361 {"DACR", NULL, "LTENR Mux"},
1362
1363 {"STENL Mux", "Sidetone Left", "ADCL"},
1364 {"STENL Mux", "Sidetone Left", "DMICL"},
1365 {"STENR Mux", "Sidetone Right", "ADCR"},
1366 {"STENR Mux", "Sidetone Right", "DMICR"},
1367 {"DACL", "NULL", "STENL Mux"},
1368 {"DACR", "NULL", "STENL Mux"},
1369
1370 {"AIFINL", NULL, "SHDN"},
1371 {"AIFINR", NULL, "SHDN"},
1372 {"AIFINL", NULL, "SDIEN"},
1373 {"AIFINR", NULL, "SDIEN"},
1374 {"DACL", NULL, "SHDN"},
1375 {"DACR", NULL, "SHDN"},
1376
1377 /* Left headphone output mixer */
1378 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1379 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1380 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1381 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1382 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1383 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1384
1385 /* Right headphone output mixer */
1386 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1387 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1388 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1389 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1390 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1391 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1392
1393 /* Left speaker output mixer */
1394 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1395 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1396 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1397 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1398 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1399 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1400
1401 /* Right speaker output mixer */
1402 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1403 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1404 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1405 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1406 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1407 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1408
1409 /* Left Receiver output mixer */
1410 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1411 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1412 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1413 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1414 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1415 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1416
1417 /* Right Receiver output mixer */
1418 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1419 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1420 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1421 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1422 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1423 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1424
1425 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1426
1427 /*
1428 * Disable this for lowest power if bypassing
1429 * the DAC with an analog signal
1430 */
1431 {"HP Left Out", NULL, "DACL"},
1432 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1433
1434 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1435
1436 /*
1437 * Disable this for lowest power if bypassing
1438 * the DAC with an analog signal
1439 */
1440 {"HP Right Out", NULL, "DACR"},
1441 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1442
1443 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1444 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1445 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1446
1447 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1448 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1449 {"RCV Right Out", NULL, "LINMOD Mux"},
1450
1451 {"HPL", NULL, "HP Left Out"},
1452 {"HPR", NULL, "HP Right Out"},
1453 {"SPKL", NULL, "SPK Left Out"},
1454 {"SPKR", NULL, "SPK Right Out"},
1455 {"RCVL", NULL, "RCV Left Out"},
1456 {"RCVR", NULL, "RCV Right Out"},
1457
1458 };
1459
1460 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1461
1462 /* DMIC inputs */
1463 {"DMIC3", NULL, "DMIC3_ENA"},
1464 {"DMIC4", NULL, "DMIC4_ENA"},
1465 {"DMIC3", NULL, "AHPF"},
1466 {"DMIC4", NULL, "AHPF"},
1467
1468 };
1469
1470 static int max98090_add_widgets(struct snd_soc_codec *codec)
1471 {
1472 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1473 struct snd_soc_dapm_context *dapm = &codec->dapm;
1474
1475 snd_soc_add_codec_controls(codec, max98090_snd_controls,
1476 ARRAY_SIZE(max98090_snd_controls));
1477
1478 if (max98090->devtype == MAX98091) {
1479 snd_soc_add_codec_controls(codec, max98091_snd_controls,
1480 ARRAY_SIZE(max98091_snd_controls));
1481 }
1482
1483 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1484 ARRAY_SIZE(max98090_dapm_widgets));
1485
1486 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1487 ARRAY_SIZE(max98090_dapm_routes));
1488
1489 if (max98090->devtype == MAX98091) {
1490 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1491 ARRAY_SIZE(max98091_dapm_widgets));
1492
1493 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1494 ARRAY_SIZE(max98091_dapm_routes));
1495
1496 }
1497
1498 return 0;
1499 }
1500
1501 static const int pclk_rates[] = {
1502 12000000, 12000000, 13000000, 13000000,
1503 16000000, 16000000, 19200000, 19200000
1504 };
1505
1506 static const int lrclk_rates[] = {
1507 8000, 16000, 8000, 16000,
1508 8000, 16000, 8000, 16000
1509 };
1510
1511 static const int user_pclk_rates[] = {
1512 13000000, 13000000
1513 };
1514
1515 static const int user_lrclk_rates[] = {
1516 44100, 48000
1517 };
1518
1519 static const unsigned long long ni_value[] = {
1520 3528, 768
1521 };
1522
1523 static const unsigned long long mi_value[] = {
1524 8125, 1625
1525 };
1526
1527 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1528 {
1529 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1530 unsigned long long ni;
1531 int i;
1532
1533 if (!max98090->sysclk) {
1534 dev_err(codec->dev, "No SYSCLK configured\n");
1535 return;
1536 }
1537
1538 if (!max98090->bclk || !max98090->lrclk) {
1539 dev_err(codec->dev, "No audio clocks configured\n");
1540 return;
1541 }
1542
1543 /* Skip configuration when operating as slave */
1544 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1545 M98090_MAS_MASK)) {
1546 return;
1547 }
1548
1549 /* Check for supported PCLK to LRCLK ratios */
1550 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1551 if ((pclk_rates[i] == max98090->sysclk) &&
1552 (lrclk_rates[i] == max98090->lrclk)) {
1553 dev_dbg(codec->dev,
1554 "Found supported PCLK to LRCLK rates 0x%x\n",
1555 i + 0x8);
1556
1557 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1558 M98090_FREQ_MASK,
1559 (i + 0x8) << M98090_FREQ_SHIFT);
1560 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1561 M98090_USE_M1_MASK, 0);
1562 return;
1563 }
1564 }
1565
1566 /* Check for user calculated MI and NI ratios */
1567 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1568 if ((user_pclk_rates[i] == max98090->sysclk) &&
1569 (user_lrclk_rates[i] == max98090->lrclk)) {
1570 dev_dbg(codec->dev,
1571 "Found user supported PCLK to LRCLK rates\n");
1572 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1573 i, ni_value[i], mi_value[i]);
1574
1575 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1576 M98090_FREQ_MASK, 0);
1577 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1578 M98090_USE_M1_MASK,
1579 1 << M98090_USE_M1_SHIFT);
1580
1581 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1582 (ni_value[i] >> 8) & 0x7F);
1583 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1584 ni_value[i] & 0xFF);
1585 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1586 (mi_value[i] >> 8) & 0x7F);
1587 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1588 mi_value[i] & 0xFF);
1589
1590 return;
1591 }
1592 }
1593
1594 /*
1595 * Calculate based on MI = 65536 (not as good as either method above)
1596 */
1597 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1598 M98090_FREQ_MASK, 0);
1599 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1600 M98090_USE_M1_MASK, 0);
1601
1602 /*
1603 * Configure NI when operating as master
1604 * Note: There is a small, but significant audio quality improvement
1605 * by calculating ni and mi.
1606 */
1607 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1608 * (unsigned long long int)max98090->lrclk;
1609 do_div(ni, (unsigned long long int)max98090->sysclk);
1610 dev_info(codec->dev, "No better method found\n");
1611 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1612 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1613 (ni >> 8) & 0x7F);
1614 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1615 }
1616
1617 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1618 unsigned int fmt)
1619 {
1620 struct snd_soc_codec *codec = codec_dai->codec;
1621 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1622 struct max98090_cdata *cdata;
1623 u8 regval;
1624
1625 max98090->dai_fmt = fmt;
1626 cdata = &max98090->dai[0];
1627
1628 if (fmt != cdata->fmt) {
1629 cdata->fmt = fmt;
1630
1631 regval = 0;
1632 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1633 case SND_SOC_DAIFMT_CBS_CFS:
1634 /* Set to slave mode PLL - MAS mode off */
1635 snd_soc_write(codec,
1636 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1637 snd_soc_write(codec,
1638 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1639 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1640 M98090_USE_M1_MASK, 0);
1641 break;
1642 case SND_SOC_DAIFMT_CBM_CFM:
1643 /* Set to master mode */
1644 if (max98090->tdm_slots == 4) {
1645 /* TDM */
1646 regval |= M98090_MAS_MASK |
1647 M98090_BSEL_64;
1648 } else if (max98090->tdm_slots == 3) {
1649 /* TDM */
1650 regval |= M98090_MAS_MASK |
1651 M98090_BSEL_48;
1652 } else {
1653 /* Few TDM slots, or No TDM */
1654 regval |= M98090_MAS_MASK |
1655 M98090_BSEL_32;
1656 }
1657 break;
1658 case SND_SOC_DAIFMT_CBS_CFM:
1659 case SND_SOC_DAIFMT_CBM_CFS:
1660 default:
1661 dev_err(codec->dev, "DAI clock mode unsupported");
1662 return -EINVAL;
1663 }
1664 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1665
1666 regval = 0;
1667 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1668 case SND_SOC_DAIFMT_I2S:
1669 regval |= M98090_DLY_MASK;
1670 break;
1671 case SND_SOC_DAIFMT_LEFT_J:
1672 break;
1673 case SND_SOC_DAIFMT_RIGHT_J:
1674 regval |= M98090_RJ_MASK;
1675 break;
1676 case SND_SOC_DAIFMT_DSP_A:
1677 /* Not supported mode */
1678 default:
1679 dev_err(codec->dev, "DAI format unsupported");
1680 return -EINVAL;
1681 }
1682
1683 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1684 case SND_SOC_DAIFMT_NB_NF:
1685 break;
1686 case SND_SOC_DAIFMT_NB_IF:
1687 regval |= M98090_WCI_MASK;
1688 break;
1689 case SND_SOC_DAIFMT_IB_NF:
1690 regval |= M98090_BCI_MASK;
1691 break;
1692 case SND_SOC_DAIFMT_IB_IF:
1693 regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1694 break;
1695 default:
1696 dev_err(codec->dev, "DAI invert mode unsupported");
1697 return -EINVAL;
1698 }
1699
1700 /*
1701 * This accommodates an inverted logic in the MAX98090 chip
1702 * for Bit Clock Invert (BCI). The inverted logic is only
1703 * seen for the case of TDM mode. The remaining cases have
1704 * normal logic.
1705 */
1706 if (max98090->tdm_slots > 1)
1707 regval ^= M98090_BCI_MASK;
1708
1709 snd_soc_write(codec,
1710 M98090_REG_INTERFACE_FORMAT, regval);
1711 }
1712
1713 return 0;
1714 }
1715
1716 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1717 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1718 {
1719 struct snd_soc_codec *codec = codec_dai->codec;
1720 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1721 struct max98090_cdata *cdata;
1722 cdata = &max98090->dai[0];
1723
1724 if (slots < 0 || slots > 4)
1725 return -EINVAL;
1726
1727 max98090->tdm_slots = slots;
1728 max98090->tdm_width = slot_width;
1729
1730 if (max98090->tdm_slots > 1) {
1731 /* SLOTL SLOTR SLOTDLY */
1732 snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1733 0 << M98090_TDM_SLOTL_SHIFT |
1734 1 << M98090_TDM_SLOTR_SHIFT |
1735 0 << M98090_TDM_SLOTDLY_SHIFT);
1736
1737 /* FSW TDM */
1738 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1739 M98090_TDM_MASK,
1740 M98090_TDM_MASK);
1741 }
1742
1743 /*
1744 * Normally advisable to set TDM first, but this permits either order
1745 */
1746 cdata->fmt = 0;
1747 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1748
1749 return 0;
1750 }
1751
1752 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1753 enum snd_soc_bias_level level)
1754 {
1755 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1756 int ret;
1757
1758 switch (level) {
1759 case SND_SOC_BIAS_ON:
1760 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) {
1761 /*
1762 * Set to normal bias level.
1763 */
1764 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
1765 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
1766 }
1767 break;
1768
1769 case SND_SOC_BIAS_PREPARE:
1770 break;
1771
1772 case SND_SOC_BIAS_STANDBY:
1773 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1774 ret = regcache_sync(max98090->regmap);
1775 if (ret != 0) {
1776 dev_err(codec->dev,
1777 "Failed to sync cache: %d\n", ret);
1778 return ret;
1779 }
1780 }
1781 break;
1782
1783 case SND_SOC_BIAS_OFF:
1784 /* Set internal pull-up to lowest power mode */
1785 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1786 M98090_JDWK_MASK, M98090_JDWK_MASK);
1787 regcache_mark_dirty(max98090->regmap);
1788 break;
1789 }
1790 codec->dapm.bias_level = level;
1791 return 0;
1792 }
1793
1794 static const int comp_pclk_rates[] = {
1795 11289600, 12288000, 12000000, 13000000, 19200000
1796 };
1797
1798 static const int dmic_micclk[] = {
1799 2, 2, 2, 2, 4, 2
1800 };
1801
1802 static const int comp_lrclk_rates[] = {
1803 8000, 16000, 32000, 44100, 48000, 96000
1804 };
1805
1806 static const int dmic_comp[6][6] = {
1807 {7, 8, 3, 3, 3, 3},
1808 {7, 8, 3, 3, 3, 3},
1809 {7, 8, 3, 3, 3, 3},
1810 {7, 8, 3, 1, 1, 1},
1811 {7, 8, 3, 1, 2, 2},
1812 {7, 8, 3, 3, 3, 3}
1813 };
1814
1815 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1816 struct snd_pcm_hw_params *params,
1817 struct snd_soc_dai *dai)
1818 {
1819 struct snd_soc_codec *codec = dai->codec;
1820 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1821 struct max98090_cdata *cdata;
1822 int i, j;
1823
1824 cdata = &max98090->dai[0];
1825 max98090->bclk = snd_soc_params_to_bclk(params);
1826 if (params_channels(params) == 1)
1827 max98090->bclk *= 2;
1828
1829 max98090->lrclk = params_rate(params);
1830
1831 switch (params_format(params)) {
1832 case SNDRV_PCM_FORMAT_S16_LE:
1833 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1834 M98090_WS_MASK, 0);
1835 break;
1836 default:
1837 return -EINVAL;
1838 }
1839
1840 max98090_configure_bclk(codec);
1841
1842 cdata->rate = max98090->lrclk;
1843
1844 /* Update filter mode */
1845 if (max98090->lrclk < 24000)
1846 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1847 M98090_MODE_MASK, 0);
1848 else
1849 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1850 M98090_MODE_MASK, M98090_MODE_MASK);
1851
1852 /* Update sample rate mode */
1853 if (max98090->lrclk < 50000)
1854 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1855 M98090_DHF_MASK, 0);
1856 else
1857 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
1858 M98090_DHF_MASK, M98090_DHF_MASK);
1859
1860 /* Check for supported PCLK to LRCLK ratios */
1861 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) {
1862 if (comp_pclk_rates[j] == max98090->sysclk) {
1863 break;
1864 }
1865 }
1866
1867 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1868 if (max98090->lrclk <= (comp_lrclk_rates[i] +
1869 comp_lrclk_rates[i + 1]) / 2) {
1870 break;
1871 }
1872 }
1873
1874 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE,
1875 M98090_MICCLK_MASK,
1876 dmic_micclk[j] << M98090_MICCLK_SHIFT);
1877
1878 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG,
1879 M98090_DMIC_COMP_MASK,
1880 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT);
1881
1882 return 0;
1883 }
1884
1885 /*
1886 * PLL / Sysclk
1887 */
1888 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
1889 int clk_id, unsigned int freq, int dir)
1890 {
1891 struct snd_soc_codec *codec = dai->codec;
1892 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1893
1894 /* Requested clock frequency is already setup */
1895 if (freq == max98090->sysclk)
1896 return 0;
1897
1898 /* Setup clocks for slave mode, and using the PLL
1899 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1900 * 0x02 (when master clk is 20MHz to 40MHz)..
1901 * 0x03 (when master clk is 40MHz to 60MHz)..
1902 */
1903 if ((freq >= 10000000) && (freq < 20000000)) {
1904 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1905 M98090_PSCLK_DIV1);
1906 } else if ((freq >= 20000000) && (freq < 40000000)) {
1907 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1908 M98090_PSCLK_DIV2);
1909 } else if ((freq >= 40000000) && (freq < 60000000)) {
1910 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
1911 M98090_PSCLK_DIV4);
1912 } else {
1913 dev_err(codec->dev, "Invalid master clock frequency\n");
1914 return -EINVAL;
1915 }
1916
1917 max98090->sysclk = freq;
1918
1919 max98090_configure_bclk(codec);
1920
1921 return 0;
1922 }
1923
1924 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1925 {
1926 struct snd_soc_codec *codec = codec_dai->codec;
1927 int regval;
1928
1929 regval = mute ? M98090_DVM_MASK : 0;
1930 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
1931 M98090_DVM_MASK, regval);
1932
1933 return 0;
1934 }
1935
1936 static void max98090_jack_work(struct work_struct *work)
1937 {
1938 struct max98090_priv *max98090 = container_of(work,
1939 struct max98090_priv,
1940 jack_work.work);
1941 struct snd_soc_codec *codec = max98090->codec;
1942 struct snd_soc_dapm_context *dapm = &codec->dapm;
1943 int status = 0;
1944 int reg;
1945
1946 /* Read a second time */
1947 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
1948
1949 /* Strong pull up allows mic detection */
1950 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1951 M98090_JDWK_MASK, 0);
1952
1953 msleep(50);
1954
1955 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1956
1957 /* Weak pull up allows only insertion detection */
1958 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1959 M98090_JDWK_MASK, M98090_JDWK_MASK);
1960 } else {
1961 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1962 }
1963
1964 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
1965
1966 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
1967 case M98090_LSNS_MASK | M98090_JKSNS_MASK:
1968 dev_dbg(codec->dev, "No Headset Detected\n");
1969
1970 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
1971
1972 status |= 0;
1973
1974 break;
1975
1976 case 0:
1977 if (max98090->jack_state ==
1978 M98090_JACK_STATE_HEADSET) {
1979
1980 dev_dbg(codec->dev,
1981 "Headset Button Down Detected\n");
1982
1983 /*
1984 * max98090_headset_button_event(codec)
1985 * could be defined, then called here.
1986 */
1987
1988 status |= SND_JACK_HEADSET;
1989 status |= SND_JACK_BTN_0;
1990
1991 break;
1992 }
1993
1994 /* Line is reported as Headphone */
1995 /* Nokia Headset is reported as Headphone */
1996 /* Mono Headphone is reported as Headphone */
1997 dev_dbg(codec->dev, "Headphone Detected\n");
1998
1999 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2000
2001 status |= SND_JACK_HEADPHONE;
2002
2003 break;
2004
2005 case M98090_JKSNS_MASK:
2006 dev_dbg(codec->dev, "Headset Detected\n");
2007
2008 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2009
2010 status |= SND_JACK_HEADSET;
2011
2012 break;
2013
2014 default:
2015 dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2016 break;
2017 }
2018
2019 snd_soc_jack_report(max98090->jack, status,
2020 SND_JACK_HEADSET | SND_JACK_BTN_0);
2021
2022 snd_soc_dapm_sync(dapm);
2023 }
2024
2025 static irqreturn_t max98090_interrupt(int irq, void *data)
2026 {
2027 struct snd_soc_codec *codec = data;
2028 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2029 int ret;
2030 unsigned int mask;
2031 unsigned int active;
2032
2033 dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2034
2035 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2036
2037 if (ret != 0) {
2038 dev_err(codec->dev,
2039 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2040 ret);
2041 return IRQ_NONE;
2042 }
2043
2044 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2045
2046 if (ret != 0) {
2047 dev_err(codec->dev,
2048 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2049 ret);
2050 return IRQ_NONE;
2051 }
2052
2053 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2054 active, mask, active & mask);
2055
2056 active &= mask;
2057
2058 if (!active)
2059 return IRQ_NONE;
2060
2061 if (active & M98090_CLD_MASK)
2062 dev_err(codec->dev, "M98090_CLD_MASK\n");
2063
2064 if (active & M98090_SLD_MASK)
2065 dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2066
2067 if (active & M98090_ULK_MASK)
2068 dev_err(codec->dev, "M98090_ULK_MASK\n");
2069
2070 if (active & M98090_JDET_MASK) {
2071 dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2072
2073 pm_wakeup_event(codec->dev, 100);
2074
2075 schedule_delayed_work(&max98090->jack_work,
2076 msecs_to_jiffies(100));
2077 }
2078
2079 if (active & M98090_DRCACT_MASK)
2080 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2081
2082 if (active & M98090_DRCCLP_MASK)
2083 dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2084
2085 return IRQ_HANDLED;
2086 }
2087
2088 /**
2089 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2090 *
2091 * @codec: MAX98090 codec
2092 * @jack: jack to report detection events on
2093 *
2094 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2095 * being used to bring out signals to the processor then only platform
2096 * data configuration is needed for MAX98090 and processor GPIOs should
2097 * be configured using snd_soc_jack_add_gpios() instead.
2098 *
2099 * If no jack is supplied detection will be disabled.
2100 */
2101 int max98090_mic_detect(struct snd_soc_codec *codec,
2102 struct snd_soc_jack *jack)
2103 {
2104 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2105
2106 dev_dbg(codec->dev, "max98090_mic_detect\n");
2107
2108 max98090->jack = jack;
2109 if (jack) {
2110 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2111 M98090_IJDET_MASK,
2112 1 << M98090_IJDET_SHIFT);
2113 } else {
2114 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2115 M98090_IJDET_MASK,
2116 0);
2117 }
2118
2119 /* Send an initial empty report */
2120 snd_soc_jack_report(max98090->jack, 0,
2121 SND_JACK_HEADSET | SND_JACK_BTN_0);
2122
2123 schedule_delayed_work(&max98090->jack_work,
2124 msecs_to_jiffies(100));
2125
2126 return 0;
2127 }
2128 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2129
2130 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2131 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2132
2133 static struct snd_soc_dai_ops max98090_dai_ops = {
2134 .set_sysclk = max98090_dai_set_sysclk,
2135 .set_fmt = max98090_dai_set_fmt,
2136 .set_tdm_slot = max98090_set_tdm_slot,
2137 .hw_params = max98090_dai_hw_params,
2138 .digital_mute = max98090_dai_digital_mute,
2139 };
2140
2141 static struct snd_soc_dai_driver max98090_dai[] = {
2142 {
2143 .name = "HiFi",
2144 .playback = {
2145 .stream_name = "HiFi Playback",
2146 .channels_min = 2,
2147 .channels_max = 2,
2148 .rates = MAX98090_RATES,
2149 .formats = MAX98090_FORMATS,
2150 },
2151 .capture = {
2152 .stream_name = "HiFi Capture",
2153 .channels_min = 1,
2154 .channels_max = 2,
2155 .rates = MAX98090_RATES,
2156 .formats = MAX98090_FORMATS,
2157 },
2158 .ops = &max98090_dai_ops,
2159 }
2160 };
2161
2162 static void max98090_handle_pdata(struct snd_soc_codec *codec)
2163 {
2164 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2165 struct max98090_pdata *pdata = max98090->pdata;
2166
2167 if (!pdata) {
2168 dev_err(codec->dev, "No platform data\n");
2169 return;
2170 }
2171
2172 }
2173
2174 static int max98090_probe(struct snd_soc_codec *codec)
2175 {
2176 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2177 struct max98090_cdata *cdata;
2178 int ret = 0;
2179
2180 dev_dbg(codec->dev, "max98090_probe\n");
2181
2182 max98090->codec = codec;
2183
2184 codec->control_data = max98090->regmap;
2185
2186 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
2187 if (ret != 0) {
2188 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2189 return ret;
2190 }
2191
2192 /* Reset the codec, the DSP core, and disable all interrupts */
2193 max98090_reset(max98090);
2194
2195 /* Initialize private data */
2196
2197 max98090->sysclk = (unsigned)-1;
2198
2199 cdata = &max98090->dai[0];
2200 cdata->rate = (unsigned)-1;
2201 cdata->fmt = (unsigned)-1;
2202
2203 max98090->lin_state = 0;
2204 max98090->pa1en = 0;
2205 max98090->pa2en = 0;
2206 max98090->extmic_mux = 0;
2207
2208 ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2209 if (ret < 0) {
2210 dev_err(codec->dev, "Failed to read device revision: %d\n",
2211 ret);
2212 goto err_access;
2213 }
2214
2215 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2216 max98090->devtype = MAX98090;
2217 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2218 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2219 max98090->devtype = MAX98091;
2220 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2221 } else {
2222 max98090->devtype = MAX98090;
2223 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2224 }
2225
2226 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2227
2228 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2229
2230 /* Enable jack detection */
2231 snd_soc_write(codec, M98090_REG_JACK_DETECT,
2232 M98090_JDETEN_MASK | M98090_JDEB_25MS);
2233
2234 /* Register for interrupts */
2235 dev_dbg(codec->dev, "irq = %d\n", max98090->irq);
2236
2237 ret = devm_request_threaded_irq(codec->dev, max98090->irq, NULL,
2238 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2239 "max98090_interrupt", codec);
2240 if (ret < 0) {
2241 dev_err(codec->dev, "request_irq failed: %d\n",
2242 ret);
2243 }
2244
2245 /*
2246 * Clear any old interrupts.
2247 * An old interrupt ocurring prior to installing the ISR
2248 * can keep a new interrupt from generating a trigger.
2249 */
2250 snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2251
2252 /* High Performance is default */
2253 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2254 M98090_DACHP_MASK,
2255 1 << M98090_DACHP_SHIFT);
2256 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2257 M98090_PERFMODE_MASK,
2258 0 << M98090_PERFMODE_SHIFT);
2259 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2260 M98090_ADCHP_MASK,
2261 1 << M98090_ADCHP_SHIFT);
2262
2263 /* Turn on VCM bandgap reference */
2264 snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2265 M98090_VCM_MODE_MASK);
2266
2267 max98090_handle_pdata(codec);
2268
2269 max98090_add_widgets(codec);
2270
2271 err_access:
2272 return ret;
2273 }
2274
2275 static int max98090_remove(struct snd_soc_codec *codec)
2276 {
2277 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2278
2279 cancel_delayed_work_sync(&max98090->jack_work);
2280
2281 return 0;
2282 }
2283
2284 static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2285 .probe = max98090_probe,
2286 .remove = max98090_remove,
2287 .set_bias_level = max98090_set_bias_level,
2288 };
2289
2290 static const struct regmap_config max98090_regmap = {
2291 .reg_bits = 8,
2292 .val_bits = 8,
2293
2294 .max_register = MAX98090_MAX_REGISTER,
2295 .reg_defaults = max98090_reg,
2296 .num_reg_defaults = ARRAY_SIZE(max98090_reg),
2297 .volatile_reg = max98090_volatile_register,
2298 .readable_reg = max98090_readable_register,
2299 .cache_type = REGCACHE_RBTREE,
2300 };
2301
2302 static int max98090_i2c_probe(struct i2c_client *i2c,
2303 const struct i2c_device_id *id)
2304 {
2305 struct max98090_priv *max98090;
2306 int ret;
2307
2308 pr_debug("max98090_i2c_probe\n");
2309
2310 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2311 GFP_KERNEL);
2312 if (max98090 == NULL)
2313 return -ENOMEM;
2314
2315 max98090->devtype = id->driver_data;
2316 i2c_set_clientdata(i2c, max98090);
2317 max98090->control_data = i2c;
2318 max98090->pdata = i2c->dev.platform_data;
2319 max98090->irq = i2c->irq;
2320
2321 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2322 if (IS_ERR(max98090->regmap)) {
2323 ret = PTR_ERR(max98090->regmap);
2324 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2325 goto err_enable;
2326 }
2327
2328 ret = snd_soc_register_codec(&i2c->dev,
2329 &soc_codec_dev_max98090, max98090_dai,
2330 ARRAY_SIZE(max98090_dai));
2331 err_enable:
2332 return ret;
2333 }
2334
2335 static int max98090_i2c_remove(struct i2c_client *client)
2336 {
2337 snd_soc_unregister_codec(&client->dev);
2338 return 0;
2339 }
2340
2341 static int max98090_runtime_resume(struct device *dev)
2342 {
2343 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2344
2345 regcache_cache_only(max98090->regmap, false);
2346
2347 max98090_reset(max98090);
2348
2349 regcache_sync(max98090->regmap);
2350
2351 return 0;
2352 }
2353
2354 static int max98090_runtime_suspend(struct device *dev)
2355 {
2356 struct max98090_priv *max98090 = dev_get_drvdata(dev);
2357
2358 regcache_cache_only(max98090->regmap, true);
2359
2360 return 0;
2361 }
2362
2363 static const struct dev_pm_ops max98090_pm = {
2364 SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2365 max98090_runtime_resume, NULL)
2366 };
2367
2368 static const struct i2c_device_id max98090_i2c_id[] = {
2369 { "max98090", MAX98090 },
2370 { }
2371 };
2372 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2373
2374 static struct i2c_driver max98090_i2c_driver = {
2375 .driver = {
2376 .name = "max98090",
2377 .owner = THIS_MODULE,
2378 .pm = &max98090_pm,
2379 },
2380 .probe = max98090_i2c_probe,
2381 .remove = max98090_i2c_remove,
2382 .id_table = max98090_i2c_id,
2383 };
2384
2385 module_i2c_driver(max98090_i2c_driver);
2386
2387 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2388 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2389 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)