2 * max98090.c -- MAX98090 ALSA SoC Audio driver
4 * Copyright 2011-2012 Maxim Integrated Products
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <sound/jack.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
22 #include <sound/tlv.h>
23 #include <sound/max98090.h>
28 #define EXTMIC_METHOD_TEST
30 /* Allows for sparsely populated register maps */
31 static struct reg_default max98090_reg
[] = {
32 { 0x00, 0x00 }, /* 00 Software Reset */
33 { 0x03, 0x04 }, /* 03 Interrupt Masks */
34 { 0x04, 0x00 }, /* 04 System Clock Quick */
35 { 0x05, 0x00 }, /* 05 Sample Rate Quick */
36 { 0x06, 0x00 }, /* 06 DAI Interface Quick */
37 { 0x07, 0x00 }, /* 07 DAC Path Quick */
38 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
39 { 0x09, 0x00 }, /* 09 Line to ADC Quick */
40 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
41 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
42 { 0x0C, 0x00 }, /* 0C Reserved */
43 { 0x0D, 0x00 }, /* 0D Input Config */
44 { 0x0E, 0x1B }, /* 0E Line Input Level */
45 { 0x0F, 0x00 }, /* 0F Line Config */
47 { 0x10, 0x14 }, /* 10 Mic1 Input Level */
48 { 0x11, 0x14 }, /* 11 Mic2 Input Level */
49 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */
50 { 0x13, 0x00 }, /* 13 Digital Mic Config */
51 { 0x14, 0x00 }, /* 14 Digital Mic Mode */
52 { 0x15, 0x00 }, /* 15 Left ADC Mixer */
53 { 0x16, 0x00 }, /* 16 Right ADC Mixer */
54 { 0x17, 0x03 }, /* 17 Left ADC Level */
55 { 0x18, 0x03 }, /* 18 Right ADC Level */
56 { 0x19, 0x00 }, /* 19 ADC Biquad Level */
57 { 0x1A, 0x00 }, /* 1A ADC Sidetone */
58 { 0x1B, 0x00 }, /* 1B System Clock */
59 { 0x1C, 0x00 }, /* 1C Clock Mode */
60 { 0x1D, 0x00 }, /* 1D Any Clock 1 */
61 { 0x1E, 0x00 }, /* 1E Any Clock 2 */
62 { 0x1F, 0x00 }, /* 1F Any Clock 3 */
64 { 0x20, 0x00 }, /* 20 Any Clock 4 */
65 { 0x21, 0x00 }, /* 21 Master Mode */
66 { 0x22, 0x00 }, /* 22 Interface Format */
67 { 0x23, 0x00 }, /* 23 TDM Format 1*/
68 { 0x24, 0x00 }, /* 24 TDM Format 2*/
69 { 0x25, 0x00 }, /* 25 I/O Configuration */
70 { 0x26, 0x80 }, /* 26 Filter Config */
71 { 0x27, 0x00 }, /* 27 DAI Playback Level */
72 { 0x28, 0x00 }, /* 28 EQ Playback Level */
73 { 0x29, 0x00 }, /* 29 Left HP Mixer */
74 { 0x2A, 0x00 }, /* 2A Right HP Mixer */
75 { 0x2B, 0x00 }, /* 2B HP Control */
76 { 0x2C, 0x1A }, /* 2C Left HP Volume */
77 { 0x2D, 0x1A }, /* 2D Right HP Volume */
78 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */
79 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */
81 { 0x30, 0x00 }, /* 30 Spk Control */
82 { 0x31, 0x2C }, /* 31 Left Spk Volume */
83 { 0x32, 0x2C }, /* 32 Right Spk Volume */
84 { 0x33, 0x00 }, /* 33 ALC Timing */
85 { 0x34, 0x00 }, /* 34 ALC Compressor */
86 { 0x35, 0x00 }, /* 35 ALC Expander */
87 { 0x36, 0x00 }, /* 36 ALC Gain */
88 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
89 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
90 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
91 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */
92 { 0x3B, 0x00 }, /* 3B Line OutR Control */
93 { 0x3C, 0x15 }, /* 3C Line OutR Volume */
94 { 0x3D, 0x00 }, /* 3D Jack Detect */
95 { 0x3E, 0x00 }, /* 3E Input Enable */
96 { 0x3F, 0x00 }, /* 3F Output Enable */
98 { 0x40, 0x00 }, /* 40 Level Control */
99 { 0x41, 0x00 }, /* 41 DSP Filter Enable */
100 { 0x42, 0x00 }, /* 42 Bias Control */
101 { 0x43, 0x00 }, /* 43 DAC Control */
102 { 0x44, 0x06 }, /* 44 ADC Control */
103 { 0x45, 0x00 }, /* 45 Device Shutdown */
104 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
105 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
106 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
107 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
108 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
109 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
110 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
111 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
112 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
113 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
115 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
116 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
117 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
118 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
119 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
120 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
121 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
122 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
123 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
124 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
125 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
126 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
127 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
128 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
129 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
130 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
132 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
133 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
134 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
135 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
136 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
137 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
138 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
139 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
140 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
141 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
142 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
143 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
144 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
145 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
146 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
147 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
149 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
150 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
151 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
152 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
153 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
154 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
155 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
156 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
157 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
158 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
159 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
160 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
161 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
162 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
163 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
164 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
166 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
167 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
168 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
169 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
170 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
171 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
172 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
173 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
174 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
175 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
176 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
177 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
178 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
179 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
180 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
181 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
183 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
184 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
185 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
186 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
187 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
188 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
189 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
190 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
191 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
192 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
193 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
194 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
195 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
196 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
197 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
198 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
200 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
201 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
202 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
203 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
204 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
205 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
206 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
207 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
208 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
209 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
210 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
211 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
212 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
213 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
214 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
215 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
217 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
218 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
219 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
220 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
221 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
222 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
223 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
224 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
225 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
226 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
227 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
228 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
229 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
230 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
231 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
232 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
234 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
235 { 0xC1, 0x00 }, /* C1 Record TDM Slot */
236 { 0xC2, 0x00 }, /* C2 Sample Rate */
237 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
238 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
239 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
240 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
241 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
242 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
243 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
244 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
245 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
246 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
247 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
248 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
249 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
251 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
252 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
255 static bool max98090_volatile_register(struct device
*dev
, unsigned int reg
)
258 case M98090_REG_DEVICE_STATUS
:
259 case M98090_REG_JACK_STATUS
:
260 case M98090_REG_REVISION_ID
:
267 static bool max98090_readable_register(struct device
*dev
, unsigned int reg
)
270 case M98090_REG_DEVICE_STATUS
:
271 case M98090_REG_JACK_STATUS
:
272 case M98090_REG_INTERRUPT_S
:
273 case M98090_REG_RESERVED
:
274 case M98090_REG_LINE_INPUT_CONFIG
:
275 case M98090_REG_LINE_INPUT_LEVEL
:
276 case M98090_REG_INPUT_MODE
:
277 case M98090_REG_MIC1_INPUT_LEVEL
:
278 case M98090_REG_MIC2_INPUT_LEVEL
:
279 case M98090_REG_MIC_BIAS_VOLTAGE
:
280 case M98090_REG_DIGITAL_MIC_ENABLE
:
281 case M98090_REG_DIGITAL_MIC_CONFIG
:
282 case M98090_REG_LEFT_ADC_MIXER
:
283 case M98090_REG_RIGHT_ADC_MIXER
:
284 case M98090_REG_LEFT_ADC_LEVEL
:
285 case M98090_REG_RIGHT_ADC_LEVEL
:
286 case M98090_REG_ADC_BIQUAD_LEVEL
:
287 case M98090_REG_ADC_SIDETONE
:
288 case M98090_REG_SYSTEM_CLOCK
:
289 case M98090_REG_CLOCK_MODE
:
290 case M98090_REG_CLOCK_RATIO_NI_MSB
:
291 case M98090_REG_CLOCK_RATIO_NI_LSB
:
292 case M98090_REG_CLOCK_RATIO_MI_MSB
:
293 case M98090_REG_CLOCK_RATIO_MI_LSB
:
294 case M98090_REG_MASTER_MODE
:
295 case M98090_REG_INTERFACE_FORMAT
:
296 case M98090_REG_TDM_CONTROL
:
297 case M98090_REG_TDM_FORMAT
:
298 case M98090_REG_IO_CONFIGURATION
:
299 case M98090_REG_FILTER_CONFIG
:
300 case M98090_REG_DAI_PLAYBACK_LEVEL
:
301 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ
:
302 case M98090_REG_LEFT_HP_MIXER
:
303 case M98090_REG_RIGHT_HP_MIXER
:
304 case M98090_REG_HP_CONTROL
:
305 case M98090_REG_LEFT_HP_VOLUME
:
306 case M98090_REG_RIGHT_HP_VOLUME
:
307 case M98090_REG_LEFT_SPK_MIXER
:
308 case M98090_REG_RIGHT_SPK_MIXER
:
309 case M98090_REG_SPK_CONTROL
:
310 case M98090_REG_LEFT_SPK_VOLUME
:
311 case M98090_REG_RIGHT_SPK_VOLUME
:
312 case M98090_REG_DRC_TIMING
:
313 case M98090_REG_DRC_COMPRESSOR
:
314 case M98090_REG_DRC_EXPANDER
:
315 case M98090_REG_DRC_GAIN
:
316 case M98090_REG_RCV_LOUTL_MIXER
:
317 case M98090_REG_RCV_LOUTL_CONTROL
:
318 case M98090_REG_RCV_LOUTL_VOLUME
:
319 case M98090_REG_LOUTR_MIXER
:
320 case M98090_REG_LOUTR_CONTROL
:
321 case M98090_REG_LOUTR_VOLUME
:
322 case M98090_REG_JACK_DETECT
:
323 case M98090_REG_INPUT_ENABLE
:
324 case M98090_REG_OUTPUT_ENABLE
:
325 case M98090_REG_LEVEL_CONTROL
:
326 case M98090_REG_DSP_FILTER_ENABLE
:
327 case M98090_REG_BIAS_CONTROL
:
328 case M98090_REG_DAC_CONTROL
:
329 case M98090_REG_ADC_CONTROL
:
330 case M98090_REG_DEVICE_SHUTDOWN
:
331 case M98090_REG_EQUALIZER_BASE
... M98090_REG_EQUALIZER_BASE
+ 0x68:
332 case M98090_REG_RECORD_BIQUAD_BASE
... M98090_REG_RECORD_BIQUAD_BASE
+ 0x0E:
333 case M98090_REG_DMIC3_VOLUME
:
334 case M98090_REG_DMIC4_VOLUME
:
335 case M98090_REG_DMIC34_BQ_PREATTEN
:
336 case M98090_REG_RECORD_TDM_SLOT
:
337 case M98090_REG_SAMPLE_RATE
:
338 case M98090_REG_DMIC34_BIQUAD_BASE
... M98090_REG_DMIC34_BIQUAD_BASE
+ 0x0E:
339 case M98090_REG_REVISION_ID
:
346 static int max98090_reset(struct max98090_priv
*max98090
)
350 /* Reset the codec by writing to this write-only reset register */
351 ret
= regmap_write(max98090
->regmap
, M98090_REG_SOFTWARE_RESET
,
352 M98090_SWRESET_MASK
);
354 dev_err(max98090
->codec
->dev
,
355 "Failed to reset codec: %d\n", ret
);
363 static const unsigned int max98090_micboost_tlv
[] = {
364 TLV_DB_RANGE_HEAD(2),
365 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
366 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
369 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv
, 0, 100, 0);
371 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv
,
374 static const unsigned int max98090_line_tlv
[] = {
375 TLV_DB_RANGE_HEAD(2),
376 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
377 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
380 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv
, 0, 600, 0);
381 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv
, -1200, 100, 0);
383 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv
, 0, 600, 0);
384 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv
, -1500, 100, 0);
386 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv
, -6050, 200, 0);
388 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv
, -1500, 100, 0);
389 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv
, 0, 100, 0);
390 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv
, -3100, 100, 0);
391 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv
, -6600, 100, 0);
393 static const unsigned int max98090_mixout_tlv
[] = {
394 TLV_DB_RANGE_HEAD(2),
395 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
396 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
399 static const unsigned int max98090_hp_tlv
[] = {
400 TLV_DB_RANGE_HEAD(5),
401 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
402 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
403 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
404 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
405 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
408 static const unsigned int max98090_spk_tlv
[] = {
409 TLV_DB_RANGE_HEAD(5),
410 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
411 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
412 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
413 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
414 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
417 static const unsigned int max98090_rcv_lout_tlv
[] = {
418 TLV_DB_RANGE_HEAD(5),
419 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
420 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
421 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
422 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
423 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
426 static int max98090_get_enab_tlv(struct snd_kcontrol
*kcontrol
,
427 struct snd_ctl_elem_value
*ucontrol
)
429 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
430 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
431 struct soc_mixer_control
*mc
=
432 (struct soc_mixer_control
*)kcontrol
->private_value
;
433 unsigned int mask
= (1 << fls(mc
->max
)) - 1;
434 unsigned int val
= snd_soc_read(codec
, mc
->reg
);
435 unsigned int *select
;
438 case M98090_REG_MIC1_INPUT_LEVEL
:
439 select
= &(max98090
->pa1en
);
441 case M98090_REG_MIC2_INPUT_LEVEL
:
442 select
= &(max98090
->pa2en
);
444 case M98090_REG_ADC_SIDETONE
:
445 select
= &(max98090
->sidetone
);
451 val
= (val
>> mc
->shift
) & mask
;
454 /* If on, return the volume */
458 /* If off, return last stored value */
462 ucontrol
->value
.integer
.value
[0] = val
;
466 static int max98090_put_enab_tlv(struct snd_kcontrol
*kcontrol
,
467 struct snd_ctl_elem_value
*ucontrol
)
469 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
470 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
471 struct soc_mixer_control
*mc
=
472 (struct soc_mixer_control
*)kcontrol
->private_value
;
473 unsigned int mask
= (1 << fls(mc
->max
)) - 1;
474 unsigned int sel
= ucontrol
->value
.integer
.value
[0];
475 unsigned int val
= snd_soc_read(codec
, mc
->reg
);
476 unsigned int *select
;
479 case M98090_REG_MIC1_INPUT_LEVEL
:
480 select
= &(max98090
->pa1en
);
482 case M98090_REG_MIC2_INPUT_LEVEL
:
483 select
= &(max98090
->pa2en
);
485 case M98090_REG_ADC_SIDETONE
:
486 select
= &(max98090
->sidetone
);
492 val
= (val
>> mc
->shift
) & mask
;
496 /* Setting a volume is only valid if it is already On */
500 /* Write what was already there */
504 snd_soc_update_bits(codec
, mc
->reg
,
511 static const char *max98090_perf_pwr_text
[] =
512 { "High Performance", "Low Power" };
513 static const char *max98090_pwr_perf_text
[] =
514 { "Low Power", "High Performance" };
516 static const struct soc_enum max98090_vcmbandgap_enum
=
517 SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL
, M98090_VCM_MODE_SHIFT
,
518 ARRAY_SIZE(max98090_pwr_perf_text
), max98090_pwr_perf_text
);
520 static const char *max98090_osr128_text
[] = { "64*fs", "128*fs" };
522 static const struct soc_enum max98090_osr128_enum
=
523 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL
, M98090_OSR128_SHIFT
,
524 ARRAY_SIZE(max98090_osr128_text
), max98090_osr128_text
);
526 static const char *max98090_mode_text
[] = { "Voice", "Music" };
528 static const struct soc_enum max98090_mode_enum
=
529 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG
, M98090_MODE_SHIFT
,
530 ARRAY_SIZE(max98090_mode_text
), max98090_mode_text
);
532 static const struct soc_enum max98090_filter_dmic34mode_enum
=
533 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG
,
534 M98090_FLT_DMIC34MODE_SHIFT
,
535 ARRAY_SIZE(max98090_mode_text
), max98090_mode_text
);
537 static const char *max98090_drcatk_text
[] =
538 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
540 static const struct soc_enum max98090_drcatk_enum
=
541 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING
, M98090_DRCATK_SHIFT
,
542 ARRAY_SIZE(max98090_drcatk_text
), max98090_drcatk_text
);
544 static const char *max98090_drcrls_text
[] =
545 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
547 static const struct soc_enum max98090_drcrls_enum
=
548 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING
, M98090_DRCRLS_SHIFT
,
549 ARRAY_SIZE(max98090_drcrls_text
), max98090_drcrls_text
);
551 static const char *max98090_alccmp_text
[] =
552 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
554 static const struct soc_enum max98090_alccmp_enum
=
555 SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR
, M98090_DRCCMP_SHIFT
,
556 ARRAY_SIZE(max98090_alccmp_text
), max98090_alccmp_text
);
558 static const char *max98090_drcexp_text
[] = { "1:1", "2:1", "3:1" };
560 static const struct soc_enum max98090_drcexp_enum
=
561 SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER
, M98090_DRCEXP_SHIFT
,
562 ARRAY_SIZE(max98090_drcexp_text
), max98090_drcexp_text
);
564 static const struct soc_enum max98090_dac_perfmode_enum
=
565 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL
, M98090_PERFMODE_SHIFT
,
566 ARRAY_SIZE(max98090_perf_pwr_text
), max98090_perf_pwr_text
);
568 static const struct soc_enum max98090_dachp_enum
=
569 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL
, M98090_DACHP_SHIFT
,
570 ARRAY_SIZE(max98090_pwr_perf_text
), max98090_pwr_perf_text
);
572 static const struct soc_enum max98090_adchp_enum
=
573 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL
, M98090_ADCHP_SHIFT
,
574 ARRAY_SIZE(max98090_pwr_perf_text
), max98090_pwr_perf_text
);
576 static const struct snd_kcontrol_new max98090_snd_controls
[] = {
577 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum
),
579 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG
,
580 M98090_DMIC_COMP_SHIFT
, M98090_DMIC_COMP_NUM
- 1, 0),
582 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
583 M98090_REG_MIC1_INPUT_LEVEL
, M98090_MIC_PA1EN_SHIFT
,
584 M98090_MIC_PA1EN_NUM
- 1, 0, max98090_get_enab_tlv
,
585 max98090_put_enab_tlv
, max98090_micboost_tlv
),
587 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
588 M98090_REG_MIC2_INPUT_LEVEL
, M98090_MIC_PA2EN_SHIFT
,
589 M98090_MIC_PA2EN_NUM
- 1, 0, max98090_get_enab_tlv
,
590 max98090_put_enab_tlv
, max98090_micboost_tlv
),
592 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL
,
593 M98090_MIC_PGAM1_SHIFT
, M98090_MIC_PGAM1_NUM
- 1, 1,
596 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL
,
597 M98090_MIC_PGAM2_SHIFT
, M98090_MIC_PGAM2_NUM
- 1, 1,
600 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
601 M98090_REG_LINE_INPUT_LEVEL
, M98090_MIXG135_SHIFT
, 0,
602 M98090_MIXG135_NUM
- 1, 1, max98090_line_single_ended_tlv
),
604 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
605 M98090_REG_LINE_INPUT_LEVEL
, M98090_MIXG246_SHIFT
, 0,
606 M98090_MIXG246_NUM
- 1, 1, max98090_line_single_ended_tlv
),
608 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL
,
609 M98090_LINAPGA_SHIFT
, 0, M98090_LINAPGA_NUM
- 1, 1,
612 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL
,
613 M98090_LINBPGA_SHIFT
, 0, M98090_LINBPGA_NUM
- 1, 1,
616 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE
,
617 M98090_EXTBUFA_SHIFT
, M98090_EXTBUFA_NUM
- 1, 0),
618 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE
,
619 M98090_EXTBUFB_SHIFT
, M98090_EXTBUFB_NUM
- 1, 0),
621 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL
,
622 M98090_AVLG_SHIFT
, M98090_AVLG_NUM
- 1, 0,
624 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL
,
625 M98090_AVRG_SHIFT
, M98090_AVLG_NUM
- 1, 0,
628 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL
,
629 M98090_AVL_SHIFT
, M98090_AVL_NUM
- 1, 1,
631 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL
,
632 M98090_AVR_SHIFT
, M98090_AVR_NUM
- 1, 1,
635 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum
),
636 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL
,
637 M98090_ADCDITHER_SHIFT
, M98090_ADCDITHER_NUM
- 1, 0),
638 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum
),
640 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION
,
641 M98090_DMONO_SHIFT
, M98090_DMONO_NUM
- 1, 0),
642 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION
,
643 M98090_SDIEN_SHIFT
, M98090_SDIEN_NUM
- 1, 0),
644 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION
,
645 M98090_SDOEN_SHIFT
, M98090_SDOEN_NUM
- 1, 0),
646 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION
,
647 M98090_HIZOFF_SHIFT
, M98090_HIZOFF_NUM
- 1, 1),
648 SOC_ENUM("Filter Mode", max98090_mode_enum
),
649 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG
,
650 M98090_AHPF_SHIFT
, M98090_AHPF_NUM
- 1, 0),
651 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG
,
652 M98090_DHPF_SHIFT
, M98090_DHPF_NUM
- 1, 0),
653 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL
,
654 M98090_AVBQ_SHIFT
, M98090_AVBQ_NUM
- 1, 1, max98090_dv_tlv
),
655 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
656 M98090_REG_ADC_SIDETONE
, M98090_DVST_SHIFT
,
657 M98090_DVST_NUM
- 1, 1, max98090_get_enab_tlv
,
658 max98090_put_enab_tlv
, max98090_micboost_tlv
),
659 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL
,
660 M98090_DVG_SHIFT
, M98090_DVG_NUM
- 1, 0,
662 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL
,
663 M98090_DV_SHIFT
, M98090_DV_NUM
- 1, 1,
665 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE
, 105),
666 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE
,
667 M98090_EQ3BANDEN_SHIFT
, M98090_EQ3BANDEN_NUM
- 1, 0),
668 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE
,
669 M98090_EQ5BANDEN_SHIFT
, M98090_EQ5BANDEN_NUM
- 1, 0),
670 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE
,
671 M98090_EQ7BANDEN_SHIFT
, M98090_EQ7BANDEN_NUM
- 1, 0),
672 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ
,
673 M98090_EQCLPN_SHIFT
, M98090_EQCLPN_NUM
- 1,
675 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ
,
676 M98090_DVEQ_SHIFT
, M98090_DVEQ_NUM
- 1, 1,
679 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING
,
680 M98090_DRCEN_SHIFT
, M98090_DRCEN_NUM
- 1, 0),
681 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum
),
682 SOC_ENUM("ALC Release Time", max98090_drcrls_enum
),
683 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN
,
684 M98090_DRCG_SHIFT
, M98090_DRCG_NUM
- 1, 0,
685 max98090_alcmakeup_tlv
),
686 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum
),
687 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum
),
688 SOC_SINGLE_TLV("ALC Compression Threshold Volume",
689 M98090_REG_DRC_COMPRESSOR
, M98090_DRCTHC_SHIFT
,
690 M98090_DRCTHC_NUM
- 1, 1, max98090_alccomp_tlv
),
691 SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
692 M98090_REG_DRC_EXPANDER
, M98090_DRCTHE_SHIFT
,
693 M98090_DRCTHE_NUM
- 1, 1, max98090_drcexp_tlv
),
695 SOC_ENUM("DAC HP Playback Performance Mode",
696 max98090_dac_perfmode_enum
),
697 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum
),
699 SOC_SINGLE_TLV("Headphone Left Mixer Volume",
700 M98090_REG_HP_CONTROL
, M98090_MIXHPLG_SHIFT
,
701 M98090_MIXHPLG_NUM
- 1, 1, max98090_mixout_tlv
),
702 SOC_SINGLE_TLV("Headphone Right Mixer Volume",
703 M98090_REG_HP_CONTROL
, M98090_MIXHPRG_SHIFT
,
704 M98090_MIXHPRG_NUM
- 1, 1, max98090_mixout_tlv
),
706 SOC_SINGLE_TLV("Speaker Left Mixer Volume",
707 M98090_REG_SPK_CONTROL
, M98090_MIXSPLG_SHIFT
,
708 M98090_MIXSPLG_NUM
- 1, 1, max98090_mixout_tlv
),
709 SOC_SINGLE_TLV("Speaker Right Mixer Volume",
710 M98090_REG_SPK_CONTROL
, M98090_MIXSPRG_SHIFT
,
711 M98090_MIXSPRG_NUM
- 1, 1, max98090_mixout_tlv
),
713 SOC_SINGLE_TLV("Receiver Left Mixer Volume",
714 M98090_REG_RCV_LOUTL_CONTROL
, M98090_MIXRCVLG_SHIFT
,
715 M98090_MIXRCVLG_NUM
- 1, 1, max98090_mixout_tlv
),
716 SOC_SINGLE_TLV("Receiver Right Mixer Volume",
717 M98090_REG_LOUTR_CONTROL
, M98090_MIXRCVRG_SHIFT
,
718 M98090_MIXRCVRG_NUM
- 1, 1, max98090_mixout_tlv
),
720 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME
,
721 M98090_REG_RIGHT_HP_VOLUME
, M98090_HPVOLL_SHIFT
,
722 M98090_HPVOLL_NUM
- 1, 0, max98090_hp_tlv
),
724 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
725 M98090_REG_LEFT_SPK_VOLUME
, M98090_REG_RIGHT_SPK_VOLUME
,
726 M98090_SPVOLL_SHIFT
, 24, M98090_SPVOLL_NUM
- 1 + 24,
727 0, max98090_spk_tlv
),
729 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME
,
730 M98090_REG_LOUTR_VOLUME
, M98090_RCVLVOL_SHIFT
,
731 M98090_RCVLVOL_NUM
- 1, 0, max98090_rcv_lout_tlv
),
733 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME
,
734 M98090_HPLM_SHIFT
, 1, 1),
735 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME
,
736 M98090_HPRM_SHIFT
, 1, 1),
738 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME
,
739 M98090_SPLM_SHIFT
, 1, 1),
740 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME
,
741 M98090_SPRM_SHIFT
, 1, 1),
743 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME
,
744 M98090_RCVLM_SHIFT
, 1, 1),
745 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME
,
746 M98090_RCVRM_SHIFT
, 1, 1),
748 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL
,
749 M98090_ZDENN_SHIFT
, M98090_ZDENN_NUM
- 1, 1),
750 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL
,
751 M98090_VS2ENN_SHIFT
, M98090_VS2ENN_NUM
- 1, 1),
752 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL
,
753 M98090_VSENN_SHIFT
, M98090_VSENN_NUM
- 1, 1),
755 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE
, 15),
756 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE
,
757 M98090_ADCBQEN_SHIFT
, M98090_ADCBQEN_NUM
- 1, 0),
760 static const struct snd_kcontrol_new max98091_snd_controls
[] = {
762 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE
,
763 M98090_DMIC34_ZEROPAD_SHIFT
,
764 M98090_DMIC34_ZEROPAD_NUM
- 1, 0),
766 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum
),
767 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG
,
768 M98090_FLT_DMIC34HPF_SHIFT
,
769 M98090_FLT_DMIC34HPF_NUM
- 1, 0),
771 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME
,
772 M98090_DMIC_AV3G_SHIFT
, M98090_DMIC_AV3G_NUM
- 1, 0,
774 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME
,
775 M98090_DMIC_AV4G_SHIFT
, M98090_DMIC_AV4G_NUM
- 1, 0,
778 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME
,
779 M98090_DMIC_AV3_SHIFT
, M98090_DMIC_AV3_NUM
- 1, 1,
781 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME
,
782 M98090_DMIC_AV4_SHIFT
, M98090_DMIC_AV4_NUM
- 1, 1,
785 SND_SOC_BYTES("DMIC34 Biquad Coefficients",
786 M98090_REG_DMIC34_BIQUAD_BASE
, 15),
787 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE
,
788 M98090_DMIC34BQEN_SHIFT
, M98090_DMIC34BQEN_NUM
- 1, 0),
790 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
791 M98090_REG_DMIC34_BQ_PREATTEN
, M98090_AV34BQ_SHIFT
,
792 M98090_AV34BQ_NUM
- 1, 1, max98090_dv_tlv
),
795 static int max98090_micinput_event(struct snd_soc_dapm_widget
*w
,
796 struct snd_kcontrol
*kcontrol
, int event
)
798 struct snd_soc_codec
*codec
= w
->codec
;
799 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
801 unsigned int val
= snd_soc_read(codec
, w
->reg
);
803 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
)
804 val
= (val
& M98090_MIC_PA1EN_MASK
) >> M98090_MIC_PA1EN_SHIFT
;
806 val
= (val
& M98090_MIC_PA2EN_MASK
) >> M98090_MIC_PA2EN_SHIFT
;
810 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
) {
811 max98090
->pa1en
= val
- 1; /* Update for volatile */
813 max98090
->pa2en
= val
- 1; /* Update for volatile */
818 case SND_SOC_DAPM_POST_PMU
:
819 /* If turning on, set to most recently selected volume */
820 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
)
821 val
= max98090
->pa1en
+ 1;
823 val
= max98090
->pa2en
+ 1;
825 case SND_SOC_DAPM_POST_PMD
:
826 /* If turning off, turn off */
833 if (w
->reg
== M98090_REG_MIC1_INPUT_LEVEL
)
834 snd_soc_update_bits(codec
, w
->reg
, M98090_MIC_PA1EN_MASK
,
835 val
<< M98090_MIC_PA1EN_SHIFT
);
837 snd_soc_update_bits(codec
, w
->reg
, M98090_MIC_PA2EN_MASK
,
838 val
<< M98090_MIC_PA2EN_SHIFT
);
843 static const char *mic1_mux_text
[] = { "IN12", "IN56" };
845 static const struct soc_enum mic1_mux_enum
=
846 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE
, M98090_EXTMIC1_SHIFT
,
847 ARRAY_SIZE(mic1_mux_text
), mic1_mux_text
);
849 static const struct snd_kcontrol_new max98090_mic1_mux
=
850 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum
);
852 static const char *mic2_mux_text
[] = { "IN34", "IN56" };
854 static const struct soc_enum mic2_mux_enum
=
855 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE
, M98090_EXTMIC2_SHIFT
,
856 ARRAY_SIZE(mic2_mux_text
), mic2_mux_text
);
858 static const struct snd_kcontrol_new max98090_mic2_mux
=
859 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum
);
861 static const char *max98090_micpre_text
[] = { "Off", "On" };
863 static const struct soc_enum max98090_pa1en_enum
=
864 SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL
, M98090_MIC_PA1EN_SHIFT
,
865 ARRAY_SIZE(max98090_micpre_text
), max98090_micpre_text
);
867 static const struct soc_enum max98090_pa2en_enum
=
868 SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL
, M98090_MIC_PA2EN_SHIFT
,
869 ARRAY_SIZE(max98090_micpre_text
), max98090_micpre_text
);
871 /* LINEA mixer switch */
872 static const struct snd_kcontrol_new max98090_linea_mixer_controls
[] = {
873 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG
,
874 M98090_IN1SEEN_SHIFT
, 1, 0),
875 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG
,
876 M98090_IN3SEEN_SHIFT
, 1, 0),
877 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG
,
878 M98090_IN5SEEN_SHIFT
, 1, 0),
879 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG
,
880 M98090_IN34DIFF_SHIFT
, 1, 0),
883 /* LINEB mixer switch */
884 static const struct snd_kcontrol_new max98090_lineb_mixer_controls
[] = {
885 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG
,
886 M98090_IN2SEEN_SHIFT
, 1, 0),
887 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG
,
888 M98090_IN4SEEN_SHIFT
, 1, 0),
889 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG
,
890 M98090_IN6SEEN_SHIFT
, 1, 0),
891 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG
,
892 M98090_IN56DIFF_SHIFT
, 1, 0),
895 /* Left ADC mixer switch */
896 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls
[] = {
897 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER
,
898 M98090_MIXADL_IN12DIFF_SHIFT
, 1, 0),
899 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER
,
900 M98090_MIXADL_IN34DIFF_SHIFT
, 1, 0),
901 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER
,
902 M98090_MIXADL_IN65DIFF_SHIFT
, 1, 0),
903 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER
,
904 M98090_MIXADL_LINEA_SHIFT
, 1, 0),
905 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER
,
906 M98090_MIXADL_LINEB_SHIFT
, 1, 0),
907 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER
,
908 M98090_MIXADL_MIC1_SHIFT
, 1, 0),
909 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER
,
910 M98090_MIXADL_MIC2_SHIFT
, 1, 0),
913 /* Right ADC mixer switch */
914 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls
[] = {
915 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER
,
916 M98090_MIXADR_IN12DIFF_SHIFT
, 1, 0),
917 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER
,
918 M98090_MIXADR_IN34DIFF_SHIFT
, 1, 0),
919 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER
,
920 M98090_MIXADR_IN65DIFF_SHIFT
, 1, 0),
921 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER
,
922 M98090_MIXADR_LINEA_SHIFT
, 1, 0),
923 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER
,
924 M98090_MIXADR_LINEB_SHIFT
, 1, 0),
925 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER
,
926 M98090_MIXADR_MIC1_SHIFT
, 1, 0),
927 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER
,
928 M98090_MIXADR_MIC2_SHIFT
, 1, 0),
931 static const char *lten_mux_text
[] = { "Normal", "Loopthrough" };
933 static const struct soc_enum ltenl_mux_enum
=
934 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION
, M98090_LTEN_SHIFT
,
935 ARRAY_SIZE(lten_mux_text
), lten_mux_text
);
937 static const struct soc_enum ltenr_mux_enum
=
938 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION
, M98090_LTEN_SHIFT
,
939 ARRAY_SIZE(lten_mux_text
), lten_mux_text
);
941 static const struct snd_kcontrol_new max98090_ltenl_mux
=
942 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum
);
944 static const struct snd_kcontrol_new max98090_ltenr_mux
=
945 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum
);
947 static const char *lben_mux_text
[] = { "Normal", "Loopback" };
949 static const struct soc_enum lbenl_mux_enum
=
950 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION
, M98090_LBEN_SHIFT
,
951 ARRAY_SIZE(lben_mux_text
), lben_mux_text
);
953 static const struct soc_enum lbenr_mux_enum
=
954 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION
, M98090_LBEN_SHIFT
,
955 ARRAY_SIZE(lben_mux_text
), lben_mux_text
);
957 static const struct snd_kcontrol_new max98090_lbenl_mux
=
958 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum
);
960 static const struct snd_kcontrol_new max98090_lbenr_mux
=
961 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum
);
963 static const char *stenl_mux_text
[] = { "Normal", "Sidetone Left" };
965 static const char *stenr_mux_text
[] = { "Normal", "Sidetone Right" };
967 static const struct soc_enum stenl_mux_enum
=
968 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE
, M98090_DSTSL_SHIFT
,
969 ARRAY_SIZE(stenl_mux_text
), stenl_mux_text
);
971 static const struct soc_enum stenr_mux_enum
=
972 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE
, M98090_DSTSR_SHIFT
,
973 ARRAY_SIZE(stenr_mux_text
), stenr_mux_text
);
975 static const struct snd_kcontrol_new max98090_stenl_mux
=
976 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum
);
978 static const struct snd_kcontrol_new max98090_stenr_mux
=
979 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum
);
981 /* Left speaker mixer switch */
983 snd_kcontrol_new max98090_left_speaker_mixer_controls
[] = {
984 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER
,
985 M98090_MIXSPL_DACL_SHIFT
, 1, 0),
986 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER
,
987 M98090_MIXSPL_DACR_SHIFT
, 1, 0),
988 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER
,
989 M98090_MIXSPL_LINEA_SHIFT
, 1, 0),
990 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER
,
991 M98090_MIXSPL_LINEB_SHIFT
, 1, 0),
992 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER
,
993 M98090_MIXSPL_MIC1_SHIFT
, 1, 0),
994 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER
,
995 M98090_MIXSPL_MIC2_SHIFT
, 1, 0),
998 /* Right speaker mixer switch */
1000 snd_kcontrol_new max98090_right_speaker_mixer_controls
[] = {
1001 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER
,
1002 M98090_MIXSPR_DACL_SHIFT
, 1, 0),
1003 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER
,
1004 M98090_MIXSPR_DACR_SHIFT
, 1, 0),
1005 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER
,
1006 M98090_MIXSPR_LINEA_SHIFT
, 1, 0),
1007 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER
,
1008 M98090_MIXSPR_LINEB_SHIFT
, 1, 0),
1009 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER
,
1010 M98090_MIXSPR_MIC1_SHIFT
, 1, 0),
1011 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER
,
1012 M98090_MIXSPR_MIC2_SHIFT
, 1, 0),
1015 /* Left headphone mixer switch */
1016 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls
[] = {
1017 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER
,
1018 M98090_MIXHPL_DACL_SHIFT
, 1, 0),
1019 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER
,
1020 M98090_MIXHPL_DACR_SHIFT
, 1, 0),
1021 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER
,
1022 M98090_MIXHPL_LINEA_SHIFT
, 1, 0),
1023 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER
,
1024 M98090_MIXHPL_LINEB_SHIFT
, 1, 0),
1025 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER
,
1026 M98090_MIXHPL_MIC1_SHIFT
, 1, 0),
1027 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER
,
1028 M98090_MIXHPL_MIC2_SHIFT
, 1, 0),
1031 /* Right headphone mixer switch */
1032 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls
[] = {
1033 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER
,
1034 M98090_MIXHPR_DACL_SHIFT
, 1, 0),
1035 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER
,
1036 M98090_MIXHPR_DACR_SHIFT
, 1, 0),
1037 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER
,
1038 M98090_MIXHPR_LINEA_SHIFT
, 1, 0),
1039 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER
,
1040 M98090_MIXHPR_LINEB_SHIFT
, 1, 0),
1041 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER
,
1042 M98090_MIXHPR_MIC1_SHIFT
, 1, 0),
1043 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER
,
1044 M98090_MIXHPR_MIC2_SHIFT
, 1, 0),
1047 /* Left receiver mixer switch */
1048 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls
[] = {
1049 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER
,
1050 M98090_MIXRCVL_DACL_SHIFT
, 1, 0),
1051 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER
,
1052 M98090_MIXRCVL_DACR_SHIFT
, 1, 0),
1053 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER
,
1054 M98090_MIXRCVL_LINEA_SHIFT
, 1, 0),
1055 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER
,
1056 M98090_MIXRCVL_LINEB_SHIFT
, 1, 0),
1057 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER
,
1058 M98090_MIXRCVL_MIC1_SHIFT
, 1, 0),
1059 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER
,
1060 M98090_MIXRCVL_MIC2_SHIFT
, 1, 0),
1063 /* Right receiver mixer switch */
1064 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls
[] = {
1065 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER
,
1066 M98090_MIXRCVR_DACL_SHIFT
, 1, 0),
1067 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER
,
1068 M98090_MIXRCVR_DACR_SHIFT
, 1, 0),
1069 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER
,
1070 M98090_MIXRCVR_LINEA_SHIFT
, 1, 0),
1071 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER
,
1072 M98090_MIXRCVR_LINEB_SHIFT
, 1, 0),
1073 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER
,
1074 M98090_MIXRCVR_MIC1_SHIFT
, 1, 0),
1075 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER
,
1076 M98090_MIXRCVR_MIC2_SHIFT
, 1, 0),
1079 static const char *linmod_mux_text
[] = { "Left Only", "Left and Right" };
1081 static const struct soc_enum linmod_mux_enum
=
1082 SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER
, M98090_LINMOD_SHIFT
,
1083 ARRAY_SIZE(linmod_mux_text
), linmod_mux_text
);
1085 static const struct snd_kcontrol_new max98090_linmod_mux
=
1086 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum
);
1088 static const char *mixhpsel_mux_text
[] = { "DAC Only", "HP Mixer" };
1091 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1093 static const struct soc_enum mixhplsel_mux_enum
=
1094 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL
, M98090_MIXHPLSEL_SHIFT
,
1095 ARRAY_SIZE(mixhpsel_mux_text
), mixhpsel_mux_text
);
1097 static const struct snd_kcontrol_new max98090_mixhplsel_mux
=
1098 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum
);
1100 static const struct soc_enum mixhprsel_mux_enum
=
1101 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL
, M98090_MIXHPRSEL_SHIFT
,
1102 ARRAY_SIZE(mixhpsel_mux_text
), mixhpsel_mux_text
);
1104 static const struct snd_kcontrol_new max98090_mixhprsel_mux
=
1105 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum
);
1107 static const struct snd_soc_dapm_widget max98090_dapm_widgets
[] = {
1109 SND_SOC_DAPM_INPUT("MIC1"),
1110 SND_SOC_DAPM_INPUT("MIC2"),
1111 SND_SOC_DAPM_INPUT("DMICL"),
1112 SND_SOC_DAPM_INPUT("DMICR"),
1113 SND_SOC_DAPM_INPUT("IN1"),
1114 SND_SOC_DAPM_INPUT("IN2"),
1115 SND_SOC_DAPM_INPUT("IN3"),
1116 SND_SOC_DAPM_INPUT("IN4"),
1117 SND_SOC_DAPM_INPUT("IN5"),
1118 SND_SOC_DAPM_INPUT("IN6"),
1119 SND_SOC_DAPM_INPUT("IN12"),
1120 SND_SOC_DAPM_INPUT("IN34"),
1121 SND_SOC_DAPM_INPUT("IN56"),
1123 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE
,
1124 M98090_MBEN_SHIFT
, 0, NULL
, 0),
1125 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN
,
1126 M98090_SHDNN_SHIFT
, 0, NULL
, 0),
1127 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION
,
1128 M98090_SDIEN_SHIFT
, 0, NULL
, 0),
1129 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION
,
1130 M98090_SDOEN_SHIFT
, 0, NULL
, 0),
1131 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1132 M98090_DIGMICL_SHIFT
, 0, NULL
, 0),
1133 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1134 M98090_DIGMICR_SHIFT
, 0, NULL
, 0),
1135 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG
,
1136 M98090_AHPF_SHIFT
, 0, NULL
, 0),
1139 * Note: Sysclk and misc power supplies are taken care of by SHDN
1142 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM
,
1143 0, 0, &max98090_mic1_mux
),
1145 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM
,
1146 0, 0, &max98090_mic2_mux
),
1148 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL
,
1149 M98090_MIC_PA1EN_SHIFT
, 0, NULL
, 0, max98090_micinput_event
,
1150 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1152 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL
,
1153 M98090_MIC_PA2EN_SHIFT
, 0, NULL
, 0, max98090_micinput_event
,
1154 SND_SOC_DAPM_POST_PMU
| SND_SOC_DAPM_POST_PMD
),
1156 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM
, 0, 0,
1157 &max98090_linea_mixer_controls
[0],
1158 ARRAY_SIZE(max98090_linea_mixer_controls
)),
1160 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM
, 0, 0,
1161 &max98090_lineb_mixer_controls
[0],
1162 ARRAY_SIZE(max98090_lineb_mixer_controls
)),
1164 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE
,
1165 M98090_LINEAEN_SHIFT
, 0, NULL
, 0),
1166 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE
,
1167 M98090_LINEBEN_SHIFT
, 0, NULL
, 0),
1169 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM
, 0, 0,
1170 &max98090_left_adc_mixer_controls
[0],
1171 ARRAY_SIZE(max98090_left_adc_mixer_controls
)),
1173 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM
, 0, 0,
1174 &max98090_right_adc_mixer_controls
[0],
1175 ARRAY_SIZE(max98090_right_adc_mixer_controls
)),
1177 SND_SOC_DAPM_ADC("ADCL", NULL
, M98090_REG_INPUT_ENABLE
,
1178 M98090_ADLEN_SHIFT
, 0),
1179 SND_SOC_DAPM_ADC("ADCR", NULL
, M98090_REG_INPUT_ENABLE
,
1180 M98090_ADREN_SHIFT
, 0),
1182 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1183 SND_SOC_NOPM
, 0, 0),
1184 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1185 SND_SOC_NOPM
, 0, 0),
1187 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM
,
1188 0, 0, &max98090_lbenl_mux
),
1190 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM
,
1191 0, 0, &max98090_lbenr_mux
),
1193 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM
,
1194 0, 0, &max98090_ltenl_mux
),
1196 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM
,
1197 0, 0, &max98090_ltenr_mux
),
1199 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM
,
1200 0, 0, &max98090_stenl_mux
),
1202 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM
,
1203 0, 0, &max98090_stenr_mux
),
1205 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM
, 0, 0),
1206 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM
, 0, 0),
1208 SND_SOC_DAPM_DAC("DACL", NULL
, M98090_REG_OUTPUT_ENABLE
,
1209 M98090_DALEN_SHIFT
, 0),
1210 SND_SOC_DAPM_DAC("DACR", NULL
, M98090_REG_OUTPUT_ENABLE
,
1211 M98090_DAREN_SHIFT
, 0),
1213 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM
, 0, 0,
1214 &max98090_left_hp_mixer_controls
[0],
1215 ARRAY_SIZE(max98090_left_hp_mixer_controls
)),
1217 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM
, 0, 0,
1218 &max98090_right_hp_mixer_controls
[0],
1219 ARRAY_SIZE(max98090_right_hp_mixer_controls
)),
1221 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM
, 0, 0,
1222 &max98090_left_speaker_mixer_controls
[0],
1223 ARRAY_SIZE(max98090_left_speaker_mixer_controls
)),
1225 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM
, 0, 0,
1226 &max98090_right_speaker_mixer_controls
[0],
1227 ARRAY_SIZE(max98090_right_speaker_mixer_controls
)),
1229 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM
, 0, 0,
1230 &max98090_left_rcv_mixer_controls
[0],
1231 ARRAY_SIZE(max98090_left_rcv_mixer_controls
)),
1233 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM
, 0, 0,
1234 &max98090_right_rcv_mixer_controls
[0],
1235 ARRAY_SIZE(max98090_right_rcv_mixer_controls
)),
1237 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER
,
1238 M98090_LINMOD_SHIFT
, 0, &max98090_linmod_mux
),
1240 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL
,
1241 M98090_MIXHPLSEL_SHIFT
, 0, &max98090_mixhplsel_mux
),
1243 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL
,
1244 M98090_MIXHPRSEL_SHIFT
, 0, &max98090_mixhprsel_mux
),
1246 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE
,
1247 M98090_HPLEN_SHIFT
, 0, NULL
, 0),
1248 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE
,
1249 M98090_HPREN_SHIFT
, 0, NULL
, 0),
1251 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE
,
1252 M98090_SPLEN_SHIFT
, 0, NULL
, 0),
1253 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE
,
1254 M98090_SPREN_SHIFT
, 0, NULL
, 0),
1256 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE
,
1257 M98090_RCVLEN_SHIFT
, 0, NULL
, 0),
1258 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE
,
1259 M98090_RCVREN_SHIFT
, 0, NULL
, 0),
1261 SND_SOC_DAPM_OUTPUT("HPL"),
1262 SND_SOC_DAPM_OUTPUT("HPR"),
1263 SND_SOC_DAPM_OUTPUT("SPKL"),
1264 SND_SOC_DAPM_OUTPUT("SPKR"),
1265 SND_SOC_DAPM_OUTPUT("RCVL"),
1266 SND_SOC_DAPM_OUTPUT("RCVR"),
1269 static const struct snd_soc_dapm_widget max98091_dapm_widgets
[] = {
1271 SND_SOC_DAPM_INPUT("DMIC3"),
1272 SND_SOC_DAPM_INPUT("DMIC4"),
1274 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1275 M98090_DIGMIC3_SHIFT
, 0, NULL
, 0),
1276 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE
,
1277 M98090_DIGMIC4_SHIFT
, 0, NULL
, 0),
1280 static const struct snd_soc_dapm_route max98090_dapm_routes
[] = {
1282 {"MIC1 Input", NULL
, "MIC1"},
1283 {"MIC2 Input", NULL
, "MIC2"},
1285 {"DMICL", NULL
, "DMICL_ENA"},
1286 {"DMICR", NULL
, "DMICR_ENA"},
1287 {"DMICL", NULL
, "AHPF"},
1288 {"DMICR", NULL
, "AHPF"},
1290 /* MIC1 input mux */
1291 {"MIC1 Mux", "IN12", "IN12"},
1292 {"MIC1 Mux", "IN56", "IN56"},
1294 /* MIC2 input mux */
1295 {"MIC2 Mux", "IN34", "IN34"},
1296 {"MIC2 Mux", "IN56", "IN56"},
1298 {"MIC1 Input", NULL
, "MIC1 Mux"},
1299 {"MIC2 Input", NULL
, "MIC2 Mux"},
1301 /* Left ADC input mixer */
1302 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1303 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1304 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1305 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1306 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1307 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1308 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1310 /* Right ADC input mixer */
1311 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1312 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1313 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1314 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1315 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1316 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1317 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1319 /* Line A input mixer */
1320 {"LINEA Mixer", "IN1 Switch", "IN1"},
1321 {"LINEA Mixer", "IN3 Switch", "IN3"},
1322 {"LINEA Mixer", "IN5 Switch", "IN5"},
1323 {"LINEA Mixer", "IN34 Switch", "IN34"},
1325 /* Line B input mixer */
1326 {"LINEB Mixer", "IN2 Switch", "IN2"},
1327 {"LINEB Mixer", "IN4 Switch", "IN4"},
1328 {"LINEB Mixer", "IN6 Switch", "IN6"},
1329 {"LINEB Mixer", "IN56 Switch", "IN56"},
1331 {"LINEA Input", NULL
, "LINEA Mixer"},
1332 {"LINEB Input", NULL
, "LINEB Mixer"},
1335 {"ADCL", NULL
, "Left ADC Mixer"},
1336 {"ADCR", NULL
, "Right ADC Mixer"},
1337 {"ADCL", NULL
, "SHDN"},
1338 {"ADCR", NULL
, "SHDN"},
1340 {"LBENL Mux", "Normal", "ADCL"},
1341 {"LBENL Mux", "Normal", "DMICL"},
1342 {"LBENL Mux", "Loopback", "LTENL Mux"},
1343 {"LBENR Mux", "Normal", "ADCR"},
1344 {"LBENR Mux", "Normal", "DMICR"},
1345 {"LBENR Mux", "Loopback", "LTENR Mux"},
1347 {"AIFOUTL", NULL
, "LBENL Mux"},
1348 {"AIFOUTR", NULL
, "LBENR Mux"},
1349 {"AIFOUTL", NULL
, "SHDN"},
1350 {"AIFOUTR", NULL
, "SHDN"},
1351 {"AIFOUTL", NULL
, "SDOEN"},
1352 {"AIFOUTR", NULL
, "SDOEN"},
1354 {"LTENL Mux", "Normal", "AIFINL"},
1355 {"LTENL Mux", "Loopthrough", "LBENL Mux"},
1356 {"LTENR Mux", "Normal", "AIFINR"},
1357 {"LTENR Mux", "Loopthrough", "LBENR Mux"},
1359 {"DACL", NULL
, "LTENL Mux"},
1360 {"DACR", NULL
, "LTENR Mux"},
1362 {"STENL Mux", "Sidetone Left", "ADCL"},
1363 {"STENL Mux", "Sidetone Left", "DMICL"},
1364 {"STENR Mux", "Sidetone Right", "ADCR"},
1365 {"STENR Mux", "Sidetone Right", "DMICR"},
1366 {"DACL", "NULL", "STENL Mux"},
1367 {"DACR", "NULL", "STENL Mux"},
1369 {"AIFINL", NULL
, "SHDN"},
1370 {"AIFINR", NULL
, "SHDN"},
1371 {"AIFINL", NULL
, "SDIEN"},
1372 {"AIFINR", NULL
, "SDIEN"},
1373 {"DACL", NULL
, "SHDN"},
1374 {"DACR", NULL
, "SHDN"},
1376 /* Left headphone output mixer */
1377 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1378 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1379 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1380 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1381 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1382 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1384 /* Right headphone output mixer */
1385 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1386 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1387 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1388 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1389 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1390 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1392 /* Left speaker output mixer */
1393 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1394 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1395 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1396 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1397 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1398 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1400 /* Right speaker output mixer */
1401 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1402 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1403 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1404 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1405 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1406 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1408 /* Left Receiver output mixer */
1409 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1410 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1411 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1412 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1413 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1414 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1416 /* Right Receiver output mixer */
1417 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1418 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1419 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1420 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1421 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1422 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1424 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1427 * Disable this for lowest power if bypassing
1428 * the DAC with an analog signal
1430 {"HP Left Out", NULL
, "DACL"},
1431 {"HP Left Out", NULL
, "MIXHPLSEL Mux"},
1433 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1436 * Disable this for lowest power if bypassing
1437 * the DAC with an analog signal
1439 {"HP Right Out", NULL
, "DACR"},
1440 {"HP Right Out", NULL
, "MIXHPRSEL Mux"},
1442 {"SPK Left Out", NULL
, "Left Speaker Mixer"},
1443 {"SPK Right Out", NULL
, "Right Speaker Mixer"},
1444 {"RCV Left Out", NULL
, "Left Receiver Mixer"},
1446 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1447 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"},
1448 {"RCV Right Out", NULL
, "LINMOD Mux"},
1450 {"HPL", NULL
, "HP Left Out"},
1451 {"HPR", NULL
, "HP Right Out"},
1452 {"SPKL", NULL
, "SPK Left Out"},
1453 {"SPKR", NULL
, "SPK Right Out"},
1454 {"RCVL", NULL
, "RCV Left Out"},
1455 {"RCVR", NULL
, "RCV Right Out"},
1459 static const struct snd_soc_dapm_route max98091_dapm_routes
[] = {
1462 {"DMIC3", NULL
, "DMIC3_ENA"},
1463 {"DMIC4", NULL
, "DMIC4_ENA"},
1464 {"DMIC3", NULL
, "AHPF"},
1465 {"DMIC4", NULL
, "AHPF"},
1469 static int max98090_add_widgets(struct snd_soc_codec
*codec
)
1471 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
1472 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1474 snd_soc_add_codec_controls(codec
, max98090_snd_controls
,
1475 ARRAY_SIZE(max98090_snd_controls
));
1477 if (max98090
->devtype
== MAX98091
) {
1478 snd_soc_add_codec_controls(codec
, max98091_snd_controls
,
1479 ARRAY_SIZE(max98091_snd_controls
));
1482 snd_soc_dapm_new_controls(dapm
, max98090_dapm_widgets
,
1483 ARRAY_SIZE(max98090_dapm_widgets
));
1485 snd_soc_dapm_add_routes(dapm
, max98090_dapm_routes
,
1486 ARRAY_SIZE(max98090_dapm_routes
));
1488 if (max98090
->devtype
== MAX98091
) {
1489 snd_soc_dapm_new_controls(dapm
, max98091_dapm_widgets
,
1490 ARRAY_SIZE(max98091_dapm_widgets
));
1492 snd_soc_dapm_add_routes(dapm
, max98091_dapm_routes
,
1493 ARRAY_SIZE(max98091_dapm_routes
));
1500 static const int pclk_rates
[] = {
1501 12000000, 12000000, 13000000, 13000000,
1502 16000000, 16000000, 19200000, 19200000
1505 static const int lrclk_rates
[] = {
1506 8000, 16000, 8000, 16000,
1507 8000, 16000, 8000, 16000
1510 static const int user_pclk_rates
[] = {
1514 static const int user_lrclk_rates
[] = {
1518 static const unsigned long long ni_value
[] = {
1522 static const unsigned long long mi_value
[] = {
1526 static void max98090_configure_bclk(struct snd_soc_codec
*codec
)
1528 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
1529 unsigned long long ni
;
1532 if (!max98090
->sysclk
) {
1533 dev_err(codec
->dev
, "No SYSCLK configured\n");
1537 if (!max98090
->bclk
|| !max98090
->lrclk
) {
1538 dev_err(codec
->dev
, "No audio clocks configured\n");
1542 /* Skip configuration when operating as slave */
1543 if (!(snd_soc_read(codec
, M98090_REG_MASTER_MODE
) &
1548 /* Check for supported PCLK to LRCLK ratios */
1549 for (i
= 0; i
< ARRAY_SIZE(pclk_rates
); i
++) {
1550 if ((pclk_rates
[i
] == max98090
->sysclk
) &&
1551 (lrclk_rates
[i
] == max98090
->lrclk
)) {
1553 "Found supported PCLK to LRCLK rates 0x%x\n",
1556 snd_soc_update_bits(codec
, M98090_REG_CLOCK_MODE
,
1558 (i
+ 0x8) << M98090_FREQ_SHIFT
);
1559 snd_soc_update_bits(codec
, M98090_REG_CLOCK_MODE
,
1560 M98090_USE_M1_MASK
, 0);
1565 /* Check for user calculated MI and NI ratios */
1566 for (i
= 0; i
< ARRAY_SIZE(user_pclk_rates
); i
++) {
1567 if ((user_pclk_rates
[i
] == max98090
->sysclk
) &&
1568 (user_lrclk_rates
[i
] == max98090
->lrclk
)) {
1570 "Found user supported PCLK to LRCLK rates\n");
1571 dev_dbg(codec
->dev
, "i %d ni %lld mi %lld\n",
1572 i
, ni_value
[i
], mi_value
[i
]);
1574 snd_soc_update_bits(codec
, M98090_REG_CLOCK_MODE
,
1575 M98090_FREQ_MASK
, 0);
1576 snd_soc_update_bits(codec
, M98090_REG_CLOCK_MODE
,
1578 1 << M98090_USE_M1_SHIFT
);
1580 snd_soc_write(codec
, M98090_REG_CLOCK_RATIO_NI_MSB
,
1581 (ni_value
[i
] >> 8) & 0x7F);
1582 snd_soc_write(codec
, M98090_REG_CLOCK_RATIO_NI_LSB
,
1583 ni_value
[i
] & 0xFF);
1584 snd_soc_write(codec
, M98090_REG_CLOCK_RATIO_MI_MSB
,
1585 (mi_value
[i
] >> 8) & 0x7F);
1586 snd_soc_write(codec
, M98090_REG_CLOCK_RATIO_MI_LSB
,
1587 mi_value
[i
] & 0xFF);
1594 * Calculate based on MI = 65536 (not as good as either method above)
1596 snd_soc_update_bits(codec
, M98090_REG_CLOCK_MODE
,
1597 M98090_FREQ_MASK
, 0);
1598 snd_soc_update_bits(codec
, M98090_REG_CLOCK_MODE
,
1599 M98090_USE_M1_MASK
, 0);
1602 * Configure NI when operating as master
1603 * Note: There is a small, but significant audio quality improvement
1604 * by calculating ni and mi.
1606 ni
= 65536ULL * (max98090
->lrclk
< 50000 ? 96ULL : 48ULL)
1607 * (unsigned long long int)max98090
->lrclk
;
1608 do_div(ni
, (unsigned long long int)max98090
->sysclk
);
1609 dev_info(codec
->dev
, "No better method found\n");
1610 dev_info(codec
->dev
, "Calculating ni %lld with mi 65536\n", ni
);
1611 snd_soc_write(codec
, M98090_REG_CLOCK_RATIO_NI_MSB
,
1613 snd_soc_write(codec
, M98090_REG_CLOCK_RATIO_NI_LSB
, ni
& 0xFF);
1616 static int max98090_dai_set_fmt(struct snd_soc_dai
*codec_dai
,
1619 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1620 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
1621 struct max98090_cdata
*cdata
;
1624 max98090
->dai_fmt
= fmt
;
1625 cdata
= &max98090
->dai
[0];
1627 if (fmt
!= cdata
->fmt
) {
1631 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
1632 case SND_SOC_DAIFMT_CBS_CFS
:
1633 /* Set to slave mode PLL - MAS mode off */
1634 snd_soc_write(codec
,
1635 M98090_REG_CLOCK_RATIO_NI_MSB
, 0x00);
1636 snd_soc_write(codec
,
1637 M98090_REG_CLOCK_RATIO_NI_LSB
, 0x00);
1638 snd_soc_update_bits(codec
, M98090_REG_CLOCK_MODE
,
1639 M98090_USE_M1_MASK
, 0);
1641 case SND_SOC_DAIFMT_CBM_CFM
:
1642 /* Set to master mode */
1643 if (max98090
->tdm_slots
== 4) {
1645 regval
|= M98090_MAS_MASK
|
1647 } else if (max98090
->tdm_slots
== 3) {
1649 regval
|= M98090_MAS_MASK
|
1652 /* Few TDM slots, or No TDM */
1653 regval
|= M98090_MAS_MASK
|
1657 case SND_SOC_DAIFMT_CBS_CFM
:
1658 case SND_SOC_DAIFMT_CBM_CFS
:
1660 dev_err(codec
->dev
, "DAI clock mode unsupported");
1663 snd_soc_write(codec
, M98090_REG_MASTER_MODE
, regval
);
1666 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
1667 case SND_SOC_DAIFMT_I2S
:
1668 regval
|= M98090_DLY_MASK
;
1670 case SND_SOC_DAIFMT_LEFT_J
:
1672 case SND_SOC_DAIFMT_RIGHT_J
:
1673 regval
|= M98090_RJ_MASK
;
1675 case SND_SOC_DAIFMT_DSP_A
:
1676 /* Not supported mode */
1678 dev_err(codec
->dev
, "DAI format unsupported");
1682 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
1683 case SND_SOC_DAIFMT_NB_NF
:
1685 case SND_SOC_DAIFMT_NB_IF
:
1686 regval
|= M98090_WCI_MASK
;
1688 case SND_SOC_DAIFMT_IB_NF
:
1689 regval
|= M98090_BCI_MASK
;
1691 case SND_SOC_DAIFMT_IB_IF
:
1692 regval
|= M98090_BCI_MASK
|M98090_WCI_MASK
;
1695 dev_err(codec
->dev
, "DAI invert mode unsupported");
1700 * This accommodates an inverted logic in the MAX98090 chip
1701 * for Bit Clock Invert (BCI). The inverted logic is only
1702 * seen for the case of TDM mode. The remaining cases have
1705 if (max98090
->tdm_slots
> 1)
1706 regval
^= M98090_BCI_MASK
;
1708 snd_soc_write(codec
,
1709 M98090_REG_INTERFACE_FORMAT
, regval
);
1715 static int max98090_set_tdm_slot(struct snd_soc_dai
*codec_dai
,
1716 unsigned int tx_mask
, unsigned int rx_mask
, int slots
, int slot_width
)
1718 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1719 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
1720 struct max98090_cdata
*cdata
;
1721 cdata
= &max98090
->dai
[0];
1723 if (slots
< 0 || slots
> 4)
1726 max98090
->tdm_slots
= slots
;
1727 max98090
->tdm_width
= slot_width
;
1729 if (max98090
->tdm_slots
> 1) {
1730 /* SLOTL SLOTR SLOTDLY */
1731 snd_soc_write(codec
, M98090_REG_TDM_FORMAT
,
1732 0 << M98090_TDM_SLOTL_SHIFT
|
1733 1 << M98090_TDM_SLOTR_SHIFT
|
1734 0 << M98090_TDM_SLOTDLY_SHIFT
);
1737 snd_soc_update_bits(codec
, M98090_REG_TDM_CONTROL
,
1743 * Normally advisable to set TDM first, but this permits either order
1746 max98090_dai_set_fmt(codec_dai
, max98090
->dai_fmt
);
1751 static int max98090_set_bias_level(struct snd_soc_codec
*codec
,
1752 enum snd_soc_bias_level level
)
1754 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
1758 case SND_SOC_BIAS_ON
:
1759 if (max98090
->jack_state
== M98090_JACK_STATE_HEADSET
) {
1761 * Set to normal bias level.
1763 snd_soc_update_bits(codec
, M98090_REG_MIC_BIAS_VOLTAGE
,
1764 M98090_MBVSEL_MASK
, M98090_MBVSEL_2V8
);
1768 case SND_SOC_BIAS_PREPARE
:
1771 case SND_SOC_BIAS_STANDBY
:
1772 if (codec
->dapm
.bias_level
== SND_SOC_BIAS_OFF
) {
1773 ret
= regcache_sync(max98090
->regmap
);
1776 "Failed to sync cache: %d\n", ret
);
1782 case SND_SOC_BIAS_OFF
:
1783 /* Set internal pull-up to lowest power mode */
1784 snd_soc_update_bits(codec
, M98090_REG_JACK_DETECT
,
1785 M98090_JDWK_MASK
, M98090_JDWK_MASK
);
1786 regcache_mark_dirty(max98090
->regmap
);
1789 codec
->dapm
.bias_level
= level
;
1793 static const int comp_pclk_rates
[] = {
1794 11289600, 12288000, 12000000, 13000000, 19200000
1797 static const int dmic_micclk
[] = {
1801 static const int comp_lrclk_rates
[] = {
1802 8000, 16000, 32000, 44100, 48000, 96000
1805 static const int dmic_comp
[6][6] = {
1814 static int max98090_dai_hw_params(struct snd_pcm_substream
*substream
,
1815 struct snd_pcm_hw_params
*params
,
1816 struct snd_soc_dai
*dai
)
1818 struct snd_soc_codec
*codec
= dai
->codec
;
1819 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
1820 struct max98090_cdata
*cdata
;
1823 cdata
= &max98090
->dai
[0];
1824 max98090
->bclk
= snd_soc_params_to_bclk(params
);
1825 if (params_channels(params
) == 1)
1826 max98090
->bclk
*= 2;
1828 max98090
->lrclk
= params_rate(params
);
1830 switch (params_format(params
)) {
1831 case SNDRV_PCM_FORMAT_S16_LE
:
1832 snd_soc_update_bits(codec
, M98090_REG_INTERFACE_FORMAT
,
1839 max98090_configure_bclk(codec
);
1841 cdata
->rate
= max98090
->lrclk
;
1843 /* Update filter mode */
1844 if (max98090
->lrclk
< 24000)
1845 snd_soc_update_bits(codec
, M98090_REG_FILTER_CONFIG
,
1846 M98090_MODE_MASK
, 0);
1848 snd_soc_update_bits(codec
, M98090_REG_FILTER_CONFIG
,
1849 M98090_MODE_MASK
, M98090_MODE_MASK
);
1851 /* Update sample rate mode */
1852 if (max98090
->lrclk
< 50000)
1853 snd_soc_update_bits(codec
, M98090_REG_FILTER_CONFIG
,
1854 M98090_DHF_MASK
, 0);
1856 snd_soc_update_bits(codec
, M98090_REG_FILTER_CONFIG
,
1857 M98090_DHF_MASK
, M98090_DHF_MASK
);
1859 /* Check for supported PCLK to LRCLK ratios */
1860 for (j
= 0; j
< ARRAY_SIZE(comp_pclk_rates
); j
++) {
1861 if (comp_pclk_rates
[j
] == max98090
->sysclk
) {
1866 for (i
= 0; i
< ARRAY_SIZE(comp_lrclk_rates
) - 1; i
++) {
1867 if (max98090
->lrclk
<= (comp_lrclk_rates
[i
] +
1868 comp_lrclk_rates
[i
+ 1]) / 2) {
1873 snd_soc_update_bits(codec
, M98090_REG_DIGITAL_MIC_ENABLE
,
1875 dmic_micclk
[j
] << M98090_MICCLK_SHIFT
);
1877 snd_soc_update_bits(codec
, M98090_REG_DIGITAL_MIC_CONFIG
,
1878 M98090_DMIC_COMP_MASK
,
1879 dmic_comp
[j
][i
] << M98090_DMIC_COMP_SHIFT
);
1887 static int max98090_dai_set_sysclk(struct snd_soc_dai
*dai
,
1888 int clk_id
, unsigned int freq
, int dir
)
1890 struct snd_soc_codec
*codec
= dai
->codec
;
1891 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
1893 /* Requested clock frequency is already setup */
1894 if (freq
== max98090
->sysclk
)
1897 /* Setup clocks for slave mode, and using the PLL
1898 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1899 * 0x02 (when master clk is 20MHz to 40MHz)..
1900 * 0x03 (when master clk is 40MHz to 60MHz)..
1902 if ((freq
>= 10000000) && (freq
< 20000000)) {
1903 snd_soc_write(codec
, M98090_REG_SYSTEM_CLOCK
,
1905 } else if ((freq
>= 20000000) && (freq
< 40000000)) {
1906 snd_soc_write(codec
, M98090_REG_SYSTEM_CLOCK
,
1908 } else if ((freq
>= 40000000) && (freq
< 60000000)) {
1909 snd_soc_write(codec
, M98090_REG_SYSTEM_CLOCK
,
1912 dev_err(codec
->dev
, "Invalid master clock frequency\n");
1916 max98090
->sysclk
= freq
;
1918 max98090_configure_bclk(codec
);
1923 static int max98090_dai_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
1925 struct snd_soc_codec
*codec
= codec_dai
->codec
;
1928 regval
= mute
? M98090_DVM_MASK
: 0;
1929 snd_soc_update_bits(codec
, M98090_REG_DAI_PLAYBACK_LEVEL
,
1930 M98090_DVM_MASK
, regval
);
1935 static void max98090_jack_work(struct work_struct
*work
)
1937 struct max98090_priv
*max98090
= container_of(work
,
1938 struct max98090_priv
,
1940 struct snd_soc_codec
*codec
= max98090
->codec
;
1941 struct snd_soc_dapm_context
*dapm
= &codec
->dapm
;
1945 /* Read a second time */
1946 if (max98090
->jack_state
== M98090_JACK_STATE_NO_HEADSET
) {
1948 /* Strong pull up allows mic detection */
1949 snd_soc_update_bits(codec
, M98090_REG_JACK_DETECT
,
1950 M98090_JDWK_MASK
, 0);
1954 reg
= snd_soc_read(codec
, M98090_REG_JACK_STATUS
);
1956 /* Weak pull up allows only insertion detection */
1957 snd_soc_update_bits(codec
, M98090_REG_JACK_DETECT
,
1958 M98090_JDWK_MASK
, M98090_JDWK_MASK
);
1960 reg
= snd_soc_read(codec
, M98090_REG_JACK_STATUS
);
1963 reg
= snd_soc_read(codec
, M98090_REG_JACK_STATUS
);
1965 switch (reg
& (M98090_LSNS_MASK
| M98090_JKSNS_MASK
)) {
1966 case M98090_LSNS_MASK
| M98090_JKSNS_MASK
:
1967 dev_dbg(codec
->dev
, "No Headset Detected\n");
1969 max98090
->jack_state
= M98090_JACK_STATE_NO_HEADSET
;
1976 if (max98090
->jack_state
==
1977 M98090_JACK_STATE_HEADSET
) {
1980 "Headset Button Down Detected\n");
1983 * max98090_headset_button_event(codec)
1984 * could be defined, then called here.
1987 status
|= SND_JACK_HEADSET
;
1988 status
|= SND_JACK_BTN_0
;
1993 /* Line is reported as Headphone */
1994 /* Nokia Headset is reported as Headphone */
1995 /* Mono Headphone is reported as Headphone */
1996 dev_dbg(codec
->dev
, "Headphone Detected\n");
1998 max98090
->jack_state
= M98090_JACK_STATE_HEADPHONE
;
2000 status
|= SND_JACK_HEADPHONE
;
2004 case M98090_JKSNS_MASK
:
2005 dev_dbg(codec
->dev
, "Headset Detected\n");
2007 max98090
->jack_state
= M98090_JACK_STATE_HEADSET
;
2009 status
|= SND_JACK_HEADSET
;
2014 dev_dbg(codec
->dev
, "Unrecognized Jack Status\n");
2018 snd_soc_jack_report(max98090
->jack
, status
,
2019 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
2021 snd_soc_dapm_sync(dapm
);
2024 static irqreturn_t
max98090_interrupt(int irq
, void *data
)
2026 struct snd_soc_codec
*codec
= data
;
2027 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
2030 unsigned int active
;
2032 dev_dbg(codec
->dev
, "***** max98090_interrupt *****\n");
2034 ret
= regmap_read(max98090
->regmap
, M98090_REG_INTERRUPT_S
, &mask
);
2038 "failed to read M98090_REG_INTERRUPT_S: %d\n",
2043 ret
= regmap_read(max98090
->regmap
, M98090_REG_DEVICE_STATUS
, &active
);
2047 "failed to read M98090_REG_DEVICE_STATUS: %d\n",
2052 dev_dbg(codec
->dev
, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2053 active
, mask
, active
& mask
);
2060 if (active
& M98090_CLD_MASK
)
2061 dev_err(codec
->dev
, "M98090_CLD_MASK\n");
2063 if (active
& M98090_SLD_MASK
)
2064 dev_dbg(codec
->dev
, "M98090_SLD_MASK\n");
2066 if (active
& M98090_ULK_MASK
)
2067 dev_err(codec
->dev
, "M98090_ULK_MASK\n");
2069 if (active
& M98090_JDET_MASK
) {
2070 dev_dbg(codec
->dev
, "M98090_JDET_MASK\n");
2072 pm_wakeup_event(codec
->dev
, 100);
2074 schedule_delayed_work(&max98090
->jack_work
,
2075 msecs_to_jiffies(100));
2078 if (active
& M98090_DRCACT_MASK
)
2079 dev_dbg(codec
->dev
, "M98090_DRCACT_MASK\n");
2081 if (active
& M98090_DRCCLP_MASK
)
2082 dev_err(codec
->dev
, "M98090_DRCCLP_MASK\n");
2088 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2090 * @codec: MAX98090 codec
2091 * @jack: jack to report detection events on
2093 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are
2094 * being used to bring out signals to the processor then only platform
2095 * data configuration is needed for MAX98090 and processor GPIOs should
2096 * be configured using snd_soc_jack_add_gpios() instead.
2098 * If no jack is supplied detection will be disabled.
2100 int max98090_mic_detect(struct snd_soc_codec
*codec
,
2101 struct snd_soc_jack
*jack
)
2103 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
2105 dev_dbg(codec
->dev
, "max98090_mic_detect\n");
2107 max98090
->jack
= jack
;
2109 snd_soc_update_bits(codec
, M98090_REG_INTERRUPT_S
,
2111 1 << M98090_IJDET_SHIFT
);
2113 snd_soc_update_bits(codec
, M98090_REG_INTERRUPT_S
,
2118 /* Send an initial empty report */
2119 snd_soc_jack_report(max98090
->jack
, 0,
2120 SND_JACK_HEADSET
| SND_JACK_BTN_0
);
2122 schedule_delayed_work(&max98090
->jack_work
,
2123 msecs_to_jiffies(100));
2127 EXPORT_SYMBOL_GPL(max98090_mic_detect
);
2129 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2130 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2132 static struct snd_soc_dai_ops max98090_dai_ops
= {
2133 .set_sysclk
= max98090_dai_set_sysclk
,
2134 .set_fmt
= max98090_dai_set_fmt
,
2135 .set_tdm_slot
= max98090_set_tdm_slot
,
2136 .hw_params
= max98090_dai_hw_params
,
2137 .digital_mute
= max98090_dai_digital_mute
,
2140 static struct snd_soc_dai_driver max98090_dai
[] = {
2144 .stream_name
= "HiFi Playback",
2147 .rates
= MAX98090_RATES
,
2148 .formats
= MAX98090_FORMATS
,
2151 .stream_name
= "HiFi Capture",
2154 .rates
= MAX98090_RATES
,
2155 .formats
= MAX98090_FORMATS
,
2157 .ops
= &max98090_dai_ops
,
2161 static void max98090_handle_pdata(struct snd_soc_codec
*codec
)
2163 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
2164 struct max98090_pdata
*pdata
= max98090
->pdata
;
2167 dev_err(codec
->dev
, "No platform data\n");
2173 static int max98090_probe(struct snd_soc_codec
*codec
)
2175 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
2176 struct max98090_cdata
*cdata
;
2179 dev_dbg(codec
->dev
, "max98090_probe\n");
2181 max98090
->codec
= codec
;
2183 codec
->control_data
= max98090
->regmap
;
2185 ret
= snd_soc_codec_set_cache_io(codec
, 8, 8, SND_SOC_REGMAP
);
2187 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
2191 /* Reset the codec, the DSP core, and disable all interrupts */
2192 max98090_reset(max98090
);
2194 /* Initialize private data */
2196 max98090
->sysclk
= (unsigned)-1;
2198 cdata
= &max98090
->dai
[0];
2199 cdata
->rate
= (unsigned)-1;
2200 cdata
->fmt
= (unsigned)-1;
2202 max98090
->lin_state
= 0;
2203 max98090
->pa1en
= 0;
2204 max98090
->pa2en
= 0;
2205 max98090
->extmic_mux
= 0;
2207 ret
= snd_soc_read(codec
, M98090_REG_REVISION_ID
);
2209 dev_err(codec
->dev
, "Failed to read device revision: %d\n",
2214 if ((ret
>= M98090_REVA
) && (ret
<= M98090_REVA
+ 0x0f)) {
2215 max98090
->devtype
= MAX98090
;
2216 dev_info(codec
->dev
, "MAX98090 REVID=0x%02x\n", ret
);
2217 } else if ((ret
>= M98091_REVA
) && (ret
<= M98091_REVA
+ 0x0f)) {
2218 max98090
->devtype
= MAX98091
;
2219 dev_info(codec
->dev
, "MAX98091 REVID=0x%02x\n", ret
);
2221 max98090
->devtype
= MAX98090
;
2222 dev_err(codec
->dev
, "Unrecognized revision 0x%02x\n", ret
);
2225 max98090
->jack_state
= M98090_JACK_STATE_NO_HEADSET
;
2227 INIT_DELAYED_WORK(&max98090
->jack_work
, max98090_jack_work
);
2229 /* Enable jack detection */
2230 snd_soc_write(codec
, M98090_REG_JACK_DETECT
,
2231 M98090_JDETEN_MASK
| M98090_JDEB_25MS
);
2233 /* Register for interrupts */
2234 dev_dbg(codec
->dev
, "irq = %d\n", max98090
->irq
);
2236 ret
= request_threaded_irq(max98090
->irq
, NULL
,
2237 max98090_interrupt
, IRQF_TRIGGER_FALLING
| IRQF_ONESHOT
,
2238 "max98090_interrupt", codec
);
2240 dev_err(codec
->dev
, "request_irq failed: %d\n",
2245 * Clear any old interrupts.
2246 * An old interrupt ocurring prior to installing the ISR
2247 * can keep a new interrupt from generating a trigger.
2249 snd_soc_read(codec
, M98090_REG_DEVICE_STATUS
);
2251 /* High Performance is default */
2252 snd_soc_update_bits(codec
, M98090_REG_DAC_CONTROL
,
2254 1 << M98090_DACHP_SHIFT
);
2255 snd_soc_update_bits(codec
, M98090_REG_DAC_CONTROL
,
2256 M98090_PERFMODE_MASK
,
2257 0 << M98090_PERFMODE_SHIFT
);
2258 snd_soc_update_bits(codec
, M98090_REG_ADC_CONTROL
,
2260 1 << M98090_ADCHP_SHIFT
);
2262 /* Turn on VCM bandgap reference */
2263 snd_soc_write(codec
, M98090_REG_BIAS_CONTROL
,
2264 M98090_VCM_MODE_MASK
);
2266 max98090_handle_pdata(codec
);
2268 max98090_add_widgets(codec
);
2274 static int max98090_remove(struct snd_soc_codec
*codec
)
2276 struct max98090_priv
*max98090
= snd_soc_codec_get_drvdata(codec
);
2278 cancel_delayed_work_sync(&max98090
->jack_work
);
2283 static struct snd_soc_codec_driver soc_codec_dev_max98090
= {
2284 .probe
= max98090_probe
,
2285 .remove
= max98090_remove
,
2286 .set_bias_level
= max98090_set_bias_level
,
2289 static const struct regmap_config max98090_regmap
= {
2293 .max_register
= MAX98090_MAX_REGISTER
,
2294 .reg_defaults
= max98090_reg
,
2295 .num_reg_defaults
= ARRAY_SIZE(max98090_reg
),
2296 .volatile_reg
= max98090_volatile_register
,
2297 .readable_reg
= max98090_readable_register
,
2298 .cache_type
= REGCACHE_RBTREE
,
2301 static int max98090_i2c_probe(struct i2c_client
*i2c
,
2302 const struct i2c_device_id
*id
)
2304 struct max98090_priv
*max98090
;
2307 pr_debug("max98090_i2c_probe\n");
2309 max98090
= devm_kzalloc(&i2c
->dev
, sizeof(struct max98090_priv
),
2311 if (max98090
== NULL
)
2314 max98090
->devtype
= id
->driver_data
;
2315 i2c_set_clientdata(i2c
, max98090
);
2316 max98090
->control_data
= i2c
;
2317 max98090
->pdata
= i2c
->dev
.platform_data
;
2318 max98090
->irq
= i2c
->irq
;
2320 max98090
->regmap
= devm_regmap_init_i2c(i2c
, &max98090_regmap
);
2321 if (IS_ERR(max98090
->regmap
)) {
2322 ret
= PTR_ERR(max98090
->regmap
);
2323 dev_err(&i2c
->dev
, "Failed to allocate regmap: %d\n", ret
);
2327 ret
= snd_soc_register_codec(&i2c
->dev
,
2328 &soc_codec_dev_max98090
, max98090_dai
,
2329 ARRAY_SIZE(max98090_dai
));
2334 static int max98090_i2c_remove(struct i2c_client
*client
)
2336 snd_soc_unregister_codec(&client
->dev
);
2340 static int max98090_runtime_resume(struct device
*dev
)
2342 struct max98090_priv
*max98090
= dev_get_drvdata(dev
);
2344 regcache_cache_only(max98090
->regmap
, false);
2346 regcache_sync(max98090
->regmap
);
2351 static int max98090_runtime_suspend(struct device
*dev
)
2353 struct max98090_priv
*max98090
= dev_get_drvdata(dev
);
2355 regcache_cache_only(max98090
->regmap
, true);
2360 static const struct dev_pm_ops max98090_pm
= {
2361 SET_RUNTIME_PM_OPS(max98090_runtime_suspend
,
2362 max98090_runtime_resume
, NULL
)
2365 static const struct i2c_device_id max98090_i2c_id
[] = {
2366 { "max98090", MAX98090
},
2369 MODULE_DEVICE_TABLE(i2c
, max98090_i2c_id
);
2371 static struct i2c_driver max98090_i2c_driver
= {
2374 .owner
= THIS_MODULE
,
2377 .probe
= max98090_i2c_probe
,
2378 .remove
= max98090_i2c_remove
,
2379 .id_table
= max98090_i2c_id
,
2382 module_i2c_driver(max98090_i2c_driver
);
2384 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2385 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2386 MODULE_LICENSE("GPL");