drivers/usb/host/xhci.h

   1
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  * for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software Foundation,
  21  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #ifndef __LINUX_XHCI_HCD_H
  25 #define __LINUX_XHCI_HCD_H
  26
  27 #include <linux/usb.h>
  28 #include <linux/timer.h>
  29 #include <linux/kernel.h>
  30 #include <linux/usb/hcd.h>
  31
  32 /* Code sharing between pci-quirks and xhci hcd */
  33 #include        "xhci-ext-caps.h"
  34 #include "pci-quirks.h"
  35
  36
  37 /* xHCI PCI Configuration Registers */
  38 #define XHCI_SBRN_OFFSET        (0x60)
  39
  40 /* Max number of USB devices for any host controller - limit in section 6.1 */
  41 #define MAX_HC_SLOTS            256
  42 /* Section 5.3.3 - MaxPorts */
  43 #define MAX_HC_PORTS            127
  44
  45 /*
  46  * xHCI register interface.
  47  * This corresponds to the eXtensible Host Controller Interface (xHCI)
  48  * Revision 0.95 specification
  49  */
  50
  51 /**
  52  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
  53  * @hc_capbase:         length of the capabilities register and HC version number
  54  * @hcs_params1:        HCSPARAMS1 - Structural Parameters 1
  55  * @hcs_params2:        HCSPARAMS2 - Structural Parameters 2
  56  * @hcs_params3:        HCSPARAMS3 - Structural Parameters 3
  57  * @hcc_params:         HCCPARAMS - Capability Parameters
  58  * @db_off:             DBOFF - Doorbell array offset
  59  * @run_regs_off:       RTSOFF - Runtime register space offset
  60  */
  61 struct xhci_cap_regs {
  62         __le32  hc_capbase;
  63         __le32  hcs_params1;
  64         __le32  hcs_params2;
  65         __le32  hcs_params3;
  66         __le32  hcc_params;
  67         __le32  db_off;
  68         __le32  run_regs_off;
  69         /* Reserved up to (CAPLENGTH - 0x1C) */
  70 };
  71
  72 /* hc_capbase bitmasks */
  73 /* bits 7:0 - how long is the Capabilities register */
  74 #define HC_LENGTH(p)            XHCI_HC_LENGTH(p)
  75 /* bits 31:16   */
  76 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)
  77
  78 /* HCSPARAMS1 - hcs_params1 - bitmasks */
  79 /* bits 0:7, Max Device Slots */
  80 #define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
  81 #define HCS_SLOTS_MASK          0xff
  82 /* bits 8:18, Max Interrupters */
  83 #define HCS_MAX_INTRS(p)        (((p) >> 8) & 0x7ff)
  84 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
  85 #define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
  86
  87 /* HCSPARAMS2 - hcs_params2 - bitmasks */
  88 /* bits 0:3, frames or uframes that SW needs to queue transactions
  89  * ahead of the HW to meet periodic deadlines */
  90 #define HCS_IST(p)              (((p) >> 0) & 0xf)
  91 /* bits 4:7, max number of Event Ring segments */
  92 #define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
  93 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
  94 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
  95 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
  96 #define HCS_MAX_SCRATCHPAD(p)   ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
  97
  98 /* HCSPARAMS3 - hcs_params3 - bitmasks */
  99 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
 100 #define HCS_U1_LATENCY(p)       (((p) >> 0) & 0xff)
 101 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
 102 #define HCS_U2_LATENCY(p)       (((p) >> 16) & 0xffff)
 103
 104 /* HCCPARAMS - hcc_params - bitmasks */
 105 /* true: HC can use 64-bit address pointers */
 106 #define HCC_64BIT_ADDR(p)       ((p) & (1 << 0))
 107 /* true: HC can do bandwidth negotiation */
 108 #define HCC_BANDWIDTH_NEG(p)    ((p) & (1 << 1))
 109 /* true: HC uses 64-byte Device Context structures
 110  * FIXME 64-byte context structures aren't supported yet.
 111  */
 112 #define HCC_64BYTE_CONTEXT(p)   ((p) & (1 << 2))
 113 /* true: HC has port power switches */
 114 #define HCC_PPC(p)              ((p) & (1 << 3))
 115 /* true: HC has port indicators */
 116 #define HCS_INDICATOR(p)        ((p) & (1 << 4))
 117 /* true: HC has Light HC Reset Capability */
 118 #define HCC_LIGHT_RESET(p)      ((p) & (1 << 5))
 119 /* true: HC supports latency tolerance messaging */
 120 #define HCC_LTC(p)              ((p) & (1 << 6))
 121 /* true: no secondary Stream ID Support */
 122 #define HCC_NSS(p)              ((p) & (1 << 7))
 123 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
 124 #define HCC_MAX_PSA(p)          (1 << ((((p) >> 12) & 0xf) + 1))
 125 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
 126 #define HCC_EXT_CAPS(p)         XHCI_HCC_EXT_CAPS(p)
 127
 128 /* db_off bitmask - bits 0:1 reserved */
 129 #define DBOFF_MASK      (~0x3)
 130
 131 /* run_regs_off bitmask - bits 0:4 reserved */
 132 #define RTSOFF_MASK     (~0x1f)
 133
 134
 135 /* Number of registers per port */
 136 #define NUM_PORT_REGS   4
 137
 138 /**
 139  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
 140  * @command:            USBCMD - xHC command register
 141  * @status:             USBSTS - xHC status register
 142  * @page_size:          This indicates the page size that the host controller
 143  *                      supports.  If bit n is set, the HC supports a page size
 144  *                      of 2^(n+12), up to a 128MB page size.
 145  *                      4K is the minimum page size.
 146  * @cmd_ring:           CRP - 64-bit Command Ring Pointer
 147  * @dcbaa_ptr:          DCBAAP - 64-bit Device Context Base Address Array Pointer
 148  * @config_reg:         CONFIG - Configure Register
 149  * @port_status_base:   PORTSCn - base address for Port Status and Control
 150  *                      Each port has a Port Status and Control register,
 151  *                      followed by a Port Power Management Status and Control
 152  *                      register, a Port Link Info register, and a reserved
 153  *                      register.
 154  * @port_power_base:    PORTPMSCn - base address for
 155  *                      Port Power Management Status and Control
 156  * @port_link_base:     PORTLIn - base address for Port Link Info (current
 157  *                      Link PM state and control) for USB 2.1 and USB 3.0
 158  *                      devices.
 159  */
 160 struct xhci_op_regs {
 161         __le32  command;
 162         __le32  status;
 163         __le32  page_size;
 164         __le32  reserved1;
 165         __le32  reserved2;
 166         __le32  dev_notification;
 167         __le64  cmd_ring;
 168         /* rsvd: offset 0x20-2F */
 169         __le32  reserved3[4];
 170         __le64  dcbaa_ptr;
 171         __le32  config_reg;
 172         /* rsvd: offset 0x3C-3FF */
 173         __le32  reserved4[241];
 174         /* port 1 registers, which serve as a base address for other ports */
 175         __le32  port_status_base;
 176         __le32  port_power_base;
 177         __le32  port_link_base;
 178         __le32  reserved5;
 179         /* registers for ports 2-255 */
 180         __le32  reserved6[NUM_PORT_REGS*254];
 181 };
 182
 183 /* USBCMD - USB command - command bitmasks */
 184 /* start/stop HC execution - do not write unless HC is halted*/
 185 #define CMD_RUN         XHCI_CMD_RUN
 186 /* Reset HC - resets internal HC state machine and all registers (except
 187  * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
 188  * The xHCI driver must reinitialize the xHC after setting this bit.
 189  */
 190 #define CMD_RESET       (1 << 1)
 191 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
 192 #define CMD_EIE         XHCI_CMD_EIE
 193 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
 194 #define CMD_HSEIE       XHCI_CMD_HSEIE
 195 /* bits 4:6 are reserved (and should be preserved on writes). */
 196 /* light reset (port status stays unchanged) - reset completed when this is 0 */
 197 #define CMD_LRESET      (1 << 7)
 198 /* host controller save/restore state. */
 199 #define CMD_CSS         (1 << 8)
 200 #define CMD_CRS         (1 << 9)
 201 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
 202 #define CMD_EWE         XHCI_CMD_EWE
 203 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
 204  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
 205  * '0' means the xHC can power it off if all ports are in the disconnect,
 206  * disabled, or powered-off state.
 207  */
 208 #define CMD_PM_INDEX    (1 << 11)
 209 /* bits 12:31 are reserved (and should be preserved on writes). */
 210
 211 /* IMAN - Interrupt Management Register */
 212 #define IMAN_IE         (1 << 1)
 213 #define IMAN_IP         (1 << 0)
 214
 215 /* USBSTS - USB status - status bitmasks */
 216 /* HC not running - set to 1 when run/stop bit is cleared. */
 217 #define STS_HALT        XHCI_STS_HALT
 218 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
 219 #define STS_FATAL       (1 << 2)
 220 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
 221 #define STS_EINT        (1 << 3)
 222 /* port change detect */
 223 #define STS_PORT        (1 << 4)
 224 /* bits 5:7 reserved and zeroed */
 225 /* save state status - '1' means xHC is saving state */
 226 #define STS_SAVE        (1 << 8)
 227 /* restore state status - '1' means xHC is restoring state */
 228 #define STS_RESTORE     (1 << 9)
 229 /* true: save or restore error */
 230 #define STS_SRE         (1 << 10)
 231 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
 232 #define STS_CNR         XHCI_STS_CNR
 233 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
 234 #define STS_HCE         (1 << 12)
 235 /* bits 13:31 reserved and should be preserved */
 236
 237 /*
 238  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
 239  * Generate a device notification event when the HC sees a transaction with a
 240  * notification type that matches a bit set in this bit field.
 241  */
 242 #define DEV_NOTE_MASK           (0xffff)
 243 #define ENABLE_DEV_NOTE(x)      (1 << (x))
 244 /* Most of the device notification types should only be used for debug.
 245  * SW does need to pay attention to function wake notifications.
 246  */
 247 #define DEV_NOTE_FWAKE          ENABLE_DEV_NOTE(1)
 248
 249 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
 250 /* bit 0 is the command ring cycle state */
 251 /* stop ring operation after completion of the currently executing command */
 252 #define CMD_RING_PAUSE          (1 << 1)
 253 /* stop ring immediately - abort the currently executing command */
 254 #define CMD_RING_ABORT          (1 << 2)
 255 /* true: command ring is running */
 256 #define CMD_RING_RUNNING        (1 << 3)
 257 /* bits 4:5 reserved and should be preserved */
 258 /* Command Ring pointer - bit mask for the lower 32 bits. */
 259 #define CMD_RING_RSVD_BITS      (0x3f)
 260
 261 /* CONFIG - Configure Register - config_reg bitmasks */
 262 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
 263 #define MAX_DEVS(p)     ((p) & 0xff)
 264 /* bits 8:31 - reserved and should be preserved */
 265
 266 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
 267 /* true: device connected */
 268 #define PORT_CONNECT    (1 << 0)
 269 /* true: port enabled */
 270 #define PORT_PE         (1 << 1)
 271 /* bit 2 reserved and zeroed */
 272 /* true: port has an over-current condition */
 273 #define PORT_OC         (1 << 3)
 274 /* true: port reset signaling asserted */
 275 #define PORT_RESET      (1 << 4)
 276 /* Port Link State - bits 5:8
 277  * A read gives the current link PM state of the port,
 278  * a write with Link State Write Strobe set sets the link state.
 279  */
 280 #define PORT_PLS_MASK   (0xf << 5)
 281 #define XDEV_U0         (0x0 << 5)
 282 #define XDEV_U2         (0x2 << 5)
 283 #define XDEV_U3         (0x3 << 5)
 284 #define XDEV_INACTIVE   (0x6 << 5)
 285 #define XDEV_RESUME     (0xf << 5)
 286 /* true: port has power (see HCC_PPC) */
 287 #define PORT_POWER      (1 << 9)
 288 /* bits 10:13 indicate device speed:
 289  * 0 - undefined speed - port hasn't be initialized by a reset yet
 290  * 1 - full speed
 291  * 2 - low speed
 292  * 3 - high speed
 293  * 4 - super speed
 294  * 5-15 reserved
 295  */
 296 #define DEV_SPEED_MASK          (0xf << 10)
 297 #define XDEV_FS                 (0x1 << 10)
 298 #define XDEV_LS                 (0x2 << 10)
 299 #define XDEV_HS                 (0x3 << 10)
 300 #define XDEV_SS                 (0x4 << 10)
 301 #define DEV_UNDEFSPEED(p)       (((p) & DEV_SPEED_MASK) == (0x0<<10))
 302 #define DEV_FULLSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_FS)
 303 #define DEV_LOWSPEED(p)         (((p) & DEV_SPEED_MASK) == XDEV_LS)
 304 #define DEV_HIGHSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_HS)
 305 #define DEV_SUPERSPEED(p)       (((p) & DEV_SPEED_MASK) == XDEV_SS)
 306 /* Bits 20:23 in the Slot Context are the speed for the device */
 307 #define SLOT_SPEED_FS           (XDEV_FS << 10)
 308 #define SLOT_SPEED_LS           (XDEV_LS << 10)
 309 #define SLOT_SPEED_HS           (XDEV_HS << 10)
 310 #define SLOT_SPEED_SS           (XDEV_SS << 10)
 311 /* Port Indicator Control */
 312 #define PORT_LED_OFF    (0 << 14)
 313 #define PORT_LED_AMBER  (1 << 14)
 314 #define PORT_LED_GREEN  (2 << 14)
 315 #define PORT_LED_MASK   (3 << 14)
 316 /* Port Link State Write Strobe - set this when changing link state */
 317 #define PORT_LINK_STROBE        (1 << 16)
 318 /* true: connect status change */
 319 #define PORT_CSC        (1 << 17)
 320 /* true: port enable change */
 321 #define PORT_PEC        (1 << 18)
 322 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
 323  * into an enabled state, and the device into the default state.  A "warm" reset
 324  * also resets the link, forcing the device through the link training sequence.
 325  * SW can also look at the Port Reset register to see when warm reset is done.
 326  */
 327 #define PORT_WRC        (1 << 19)
 328 /* true: over-current change */
 329 #define PORT_OCC        (1 << 20)
 330 /* true: reset change - 1 to 0 transition of PORT_RESET */
 331 #define PORT_RC         (1 << 21)
 332 /* port link status change - set on some port link state transitions:
 333  *  Transition                          Reason
 334  *  ------------------------------------------------------------------------------
 335  *  - U3 to Resume                      Wakeup signaling from a device
 336  *  - Resume to Recovery to U0          USB 3.0 device resume
 337  *  - Resume to U0                      USB 2.0 device resume
 338  *  - U3 to Recovery to U0              Software resume of USB 3.0 device complete
 339  *  - U3 to U0                          Software resume of USB 2.0 device complete
 340  *  - U2 to U0                          L1 resume of USB 2.1 device complete
 341  *  - U0 to U0 (???)                    L1 entry rejection by USB 2.1 device
 342  *  - U0 to disabled                    L1 entry error with USB 2.1 device
 343  *  - Any state to inactive             Error on USB 3.0 port
 344  */
 345 #define PORT_PLC        (1 << 22)
 346 /* port configure error change - port failed to configure its link partner */
 347 #define PORT_CEC        (1 << 23)
 348 /* Cold Attach Status - xHC can set this bit to report device attached during
 349  * Sx state. Warm port reset should be perfomed to clear this bit and move port
 350  * to connected state.
 351  */
 352 #define PORT_CAS        (1 << 24)
 353 /* wake on connect (enable) */
 354 #define PORT_WKCONN_E   (1 << 25)
 355 /* wake on disconnect (enable) */
 356 #define PORT_WKDISC_E   (1 << 26)
 357 /* wake on over-current (enable) */
 358 #define PORT_WKOC_E     (1 << 27)
 359 /* bits 28:29 reserved */
 360 /* true: device is removable - for USB 3.0 roothub emulation */
 361 #define PORT_DEV_REMOVE (1 << 30)
 362 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
 363 #define PORT_WR         (1 << 31)
 364
 365 /* We mark duplicate entries with -1 */
 366 #define DUPLICATE_ENTRY ((u8)(-1))
 367
 368 /* Port Power Management Status and Control - port_power_base bitmasks */
 369 /* Inactivity timer value for transitions into U1, in microseconds.
 370  * Timeout can be up to 127us.  0xFF means an infinite timeout.
 371  */
 372 #define PORT_U1_TIMEOUT(p)      ((p) & 0xff)
 373 #define PORT_U1_TIMEOUT_MASK    0xff
 374 /* Inactivity timer value for transitions into U2 */
 375 #define PORT_U2_TIMEOUT(p)      (((p) & 0xff) << 8)
 376 #define PORT_U2_TIMEOUT_MASK    (0xff << 8)
 377 /* Bits 24:31 for port testing */
 378
 379 /* USB2 Protocol PORTSPMSC */
 380 #define PORT_L1S_MASK           7
 381 #define PORT_L1S_SUCCESS        1
 382 #define PORT_RWE                (1 << 3)
 383 #define PORT_HIRD(p)            (((p) & 0xf) << 4)
 384 #define PORT_HIRD_MASK          (0xf << 4)
 385 #define PORT_L1DS(p)            (((p) & 0xff) << 8)
 386 #define PORT_HLE                (1 << 16)
 387
 388 /**
 389  * struct xhci_intr_reg - Interrupt Register Set
 390  * @irq_pending:        IMAN - Interrupt Management Register.  Used to enable
 391  *                      interrupts and check for pending interrupts.
 392  * @irq_control:        IMOD - Interrupt Moderation Register.
 393  *                      Used to throttle interrupts.
 394  * @erst_size:          Number of segments in the Event Ring Segment Table (ERST).
 395  * @erst_base:          ERST base address.
 396  * @erst_dequeue:       Event ring dequeue pointer.
 397  *
 398  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
 399  * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
 400  * multiple segments of the same size.  The HC places events on the ring and
 401  * "updates the Cycle bit in the TRBs to indicate to software the current
 402  * position of the Enqueue Pointer." The HCD (Linux) processes those events and
 403  * updates the dequeue pointer.
 404  */
 405 struct xhci_intr_reg {
 406         __le32  irq_pending;
 407         __le32  irq_control;
 408         __le32  erst_size;
 409         __le32  rsvd;
 410         __le64  erst_base;
 411         __le64  erst_dequeue;
 412 };
 413
 414 /* irq_pending bitmasks */
 415 #define ER_IRQ_PENDING(p)       ((p) & 0x1)
 416 /* bits 2:31 need to be preserved */
 417 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
 418 #define ER_IRQ_CLEAR(p)         ((p) & 0xfffffffe)
 419 #define ER_IRQ_ENABLE(p)        ((ER_IRQ_CLEAR(p)) | 0x2)
 420 #define ER_IRQ_DISABLE(p)       ((ER_IRQ_CLEAR(p)) & ~(0x2))
 421
 422 /* irq_control bitmasks */
 423 /* Minimum interval between interrupts (in 250ns intervals).  The interval
 424  * between interrupts will be longer if there are no events on the event ring.
 425  * Default is 4000 (1 ms).
 426  */
 427 #define ER_IRQ_INTERVAL_MASK    (0xffff)
 428 /* Counter used to count down the time to the next interrupt - HW use only */
 429 #define ER_IRQ_COUNTER_MASK     (0xffff << 16)
 430
 431 /* erst_size bitmasks */
 432 /* Preserve bits 16:31 of erst_size */
 433 #define ERST_SIZE_MASK          (0xffff << 16)
 434
 435 /* erst_dequeue bitmasks */
 436 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
 437  * where the current dequeue pointer lies.  This is an optional HW hint.
 438  */
 439 #define ERST_DESI_MASK          (0x7)
 440 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
 441  * a work queue (or delayed service routine)?
 442  */
 443 #define ERST_EHB                (1 << 3)
 444 #define ERST_PTR_MASK           (0xf)
 445
 446 /**
 447  * struct xhci_run_regs
 448  * @microframe_index:
 449  *              MFINDEX - current microframe number
 450  *
 451  * Section 5.5 Host Controller Runtime Registers:
 452  * "Software should read and write these registers using only Dword (32 bit)
 453  * or larger accesses"
 454  */
 455 struct xhci_run_regs {
 456         __le32                  microframe_index;
 457         __le32                  rsvd[7];
 458         struct xhci_intr_reg    ir_set[128];
 459 };
 460
 461 /**
 462  * struct doorbell_array
 463  *
 464  * Bits  0 -  7: Endpoint target
 465  * Bits  8 - 15: RsvdZ
 466  * Bits 16 - 31: Stream ID
 467  *
 468  * Section 5.6
 469  */
 470 struct xhci_doorbell_array {
 471         __le32  doorbell[256];
 472 };
 473
 474 #define DB_VALUE(ep, stream)    ((((ep) + 1) & 0xff) | ((stream) << 16))
 475 #define DB_VALUE_HOST           0x00000000
 476
 477 /**
 478  * struct xhci_protocol_caps
 479  * @revision:           major revision, minor revision, capability ID,
 480  *                      and next capability pointer.
 481  * @name_string:        Four ASCII characters to say which spec this xHC
 482  *                      follows, typically "USB ".
 483  * @port_info:          Port offset, count, and protocol-defined information.
 484  */
 485 struct xhci_protocol_caps {
 486         u32     revision;
 487         u32     name_string;
 488         u32     port_info;
 489 };
 490
 491 #define XHCI_EXT_PORT_MAJOR(x)  (((x) >> 24) & 0xff)
 492 #define XHCI_EXT_PORT_OFF(x)    ((x) & 0xff)
 493 #define XHCI_EXT_PORT_COUNT(x)  (((x) >> 8) & 0xff)
 494
 495 /**
 496  * struct xhci_container_ctx
 497  * @type: Type of context.  Used to calculated offsets to contained contexts.
 498  * @size: Size of the context data
 499  * @bytes: The raw context data given to HW
 500  * @dma: dma address of the bytes
 501  *
 502  * Represents either a Device or Input context.  Holds a pointer to the raw
 503  * memory used for the context (bytes) and dma address of it (dma).
 504  */
 505 struct xhci_container_ctx {
 506         unsigned type;
 507 #define XHCI_CTX_TYPE_DEVICE  0x1
 508 #define XHCI_CTX_TYPE_INPUT   0x2
 509
 510         int size;
 511
 512         u8 *bytes;
 513         dma_addr_t dma;
 514 };
 515
 516 /**
 517  * struct xhci_slot_ctx
 518  * @dev_info:   Route string, device speed, hub info, and last valid endpoint
 519  * @dev_info2:  Max exit latency for device number, root hub port number
 520  * @tt_info:    tt_info is used to construct split transaction tokens
 521  * @dev_state:  slot state and device address
 522  *
 523  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
 524  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 525  * reserved at the end of the slot context for HC internal use.
 526  */
 527 struct xhci_slot_ctx {
 528         __le32  dev_info;
 529         __le32  dev_info2;
 530         __le32  tt_info;
 531         __le32  dev_state;
 532         /* offset 0x10 to 0x1f reserved for HC internal use */
 533         __le32  reserved[4];
 534 };
 535
 536 /* dev_info bitmasks */
 537 /* Route String - 0:19 */
 538 #define ROUTE_STRING_MASK       (0xfffff)
 539 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
 540 #define DEV_SPEED       (0xf << 20)
 541 /* bit 24 reserved */
 542 /* Is this LS/FS device connected through a HS hub? - bit 25 */
 543 #define DEV_MTT         (0x1 << 25)
 544 /* Set if the device is a hub - bit 26 */
 545 #define DEV_HUB         (0x1 << 26)
 546 /* Index of the last valid endpoint context in this device context - 27:31 */
 547 #define LAST_CTX_MASK   (0x1f << 27)
 548 #define LAST_CTX(p)     ((p) << 27)
 549 #define LAST_CTX_TO_EP_NUM(p)   (((p) >> 27) - 1)
 550 #define SLOT_FLAG       (1 << 0)
 551 #define EP0_FLAG        (1 << 1)
 552
 553 /* dev_info2 bitmasks */
 554 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
 555 #define MAX_EXIT        (0xffff)
 556 /* Root hub port number that is needed to access the USB device */
 557 #define ROOT_HUB_PORT(p)        (((p) & 0xff) << 16)
 558 #define DEVINFO_TO_ROOT_HUB_PORT(p)     (((p) >> 16) & 0xff)
 559 /* Maximum number of ports under a hub device */
 560 #define XHCI_MAX_PORTS(p)       (((p) & 0xff) << 24)
 561
 562 /* tt_info bitmasks */
 563 /*
 564  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
 565  * The Slot ID of the hub that isolates the high speed signaling from
 566  * this low or full-speed device.  '0' if attached to root hub port.
 567  */
 568 #define TT_SLOT         (0xff)
 569 /*
 570  * The number of the downstream facing port of the high-speed hub
 571  * '0' if the device is not low or full speed.
 572  */
 573 #define TT_PORT         (0xff << 8)
 574 #define TT_THINK_TIME(p)        (((p) & 0x3) << 16)
 575
 576 /* dev_state bitmasks */
 577 /* USB device address - assigned by the HC */
 578 #define DEV_ADDR_MASK   (0xff)
 579 /* bits 8:26 reserved */
 580 /* Slot state */
 581 #define SLOT_STATE      (0x1f << 27)
 582 #define GET_SLOT_STATE(p)       (((p) & (0x1f << 27)) >> 27)
 583
 584 #define SLOT_STATE_DISABLED     0
 585 #define SLOT_STATE_ENABLED      SLOT_STATE_DISABLED
 586 #define SLOT_STATE_DEFAULT      1
 587 #define SLOT_STATE_ADDRESSED    2
 588 #define SLOT_STATE_CONFIGURED   3
 589
 590 /**
 591  * struct xhci_ep_ctx
 592  * @ep_info:    endpoint state, streams, mult, and interval information.
 593  * @ep_info2:   information on endpoint type, max packet size, max burst size,
 594  *              error count, and whether the HC will force an event for all
 595  *              transactions.
 596  * @deq:        64-bit ring dequeue pointer address.  If the endpoint only
 597  *              defines one stream, this points to the endpoint transfer ring.
 598  *              Otherwise, it points to a stream context array, which has a
 599  *              ring pointer for each flow.
 600  * @tx_info:
 601  *              Average TRB lengths for the endpoint ring and
 602  *              max payload within an Endpoint Service Interval Time (ESIT).
 603  *
 604  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
 605  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 606  * reserved at the end of the endpoint context for HC internal use.
 607  */
 608 struct xhci_ep_ctx {
 609         __le32  ep_info;
 610         __le32  ep_info2;
 611         __le64  deq;
 612         __le32  tx_info;
 613         /* offset 0x14 - 0x1f reserved for HC internal use */
 614         __le32  reserved[3];
 615 };
 616
 617 /* ep_info bitmasks */
 618 /*
 619  * Endpoint State - bits 0:2
 620  * 0 - disabled
 621  * 1 - running
 622  * 2 - halted due to halt condition - ok to manipulate endpoint ring
 623  * 3 - stopped
 624  * 4 - TRB error
 625  * 5-7 - reserved
 626  */
 627 #define EP_STATE_MASK           (0xf)
 628 #define EP_STATE_DISABLED       0
 629 #define EP_STATE_RUNNING        1
 630 #define EP_STATE_HALTED         2
 631 #define EP_STATE_STOPPED        3
 632 #define EP_STATE_ERROR          4
 633 /* Mult - Max number of burtst within an interval, in EP companion desc. */
 634 #define EP_MULT(p)              (((p) & 0x3) << 8)
 635 #define CTX_TO_EP_MULT(p)       (((p) >> 8) & 0x3)
 636 /* bits 10:14 are Max Primary Streams */
 637 /* bit 15 is Linear Stream Array */
 638 /* Interval - period between requests to an endpoint - 125u increments. */
 639 #define EP_INTERVAL(p)          (((p) & 0xff) << 16)
 640 #define EP_INTERVAL_TO_UFRAMES(p)               (1 << (((p) >> 16) & 0xff))
 641 #define CTX_TO_EP_INTERVAL(p)   (((p) >> 16) & 0xff)
 642 #define EP_MAXPSTREAMS_MASK     (0x1f << 10)
 643 #define EP_MAXPSTREAMS(p)       (((p) << 10) & EP_MAXPSTREAMS_MASK)
 644 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
 645 #define EP_HAS_LSA              (1 << 15)
 646
 647 /* ep_info2 bitmasks */
 648 /*
 649  * Force Event - generate transfer events for all TRBs for this endpoint
 650  * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
 651  */
 652 #define FORCE_EVENT     (0x1)
 653 #define ERROR_COUNT(p)  (((p) & 0x3) << 1)
 654 #define CTX_TO_EP_TYPE(p)       (((p) >> 3) & 0x7)
 655 #define EP_TYPE(p)      ((p) << 3)
 656 #define ISOC_OUT_EP     1
 657 #define BULK_OUT_EP     2
 658 #define INT_OUT_EP      3
 659 #define CTRL_EP         4
 660 #define ISOC_IN_EP      5
 661 #define BULK_IN_EP      6
 662 #define INT_IN_EP       7
 663 /* bit 6 reserved */
 664 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 665 #define MAX_BURST(p)    (((p)&0xff) << 8)
 666 #define CTX_TO_MAX_BURST(p)     (((p) >> 8) & 0xff)
 667 #define MAX_PACKET(p)   (((p)&0xffff) << 16)
 668 #define MAX_PACKET_MASK         (0xffff << 16)
 669 #define MAX_PACKET_DECODED(p)   (((p) >> 16) & 0xffff)
 670
 671 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
 672  * USB2.0 spec 9.6.6.
 673  */
 674 #define GET_MAX_PACKET(p)       ((p) & 0x7ff)
 675
 676 /* tx_info bitmasks */
 677 #define AVG_TRB_LENGTH_FOR_EP(p)        ((p) & 0xffff)
 678 #define MAX_ESIT_PAYLOAD_FOR_EP(p)      (((p) & 0xffff) << 16)
 679 #define CTX_TO_MAX_ESIT_PAYLOAD(p)      (((p) >> 16) & 0xffff)
 680
 681 /* deq bitmasks */
 682 #define EP_CTX_CYCLE_MASK               (1 << 0)
 683
 684 #ifdef CONFIG_MTK_XHCI
 685 /* mtk scheduler bitmasks */
 686 #define BPKTS(p)        ((p) & 0x3f)
 687 #define BCSCOUNT(p)     (((p) & 0x7) << 8)
 688 #define BBM(p)          ((p) << 11)
 689 #define BOFFSET(p)      ((p) & 0x3fff)
 690 #define BREPEAT(p)      (((p) & 0x7fff) << 16)
 691 #endif
 692
 693 /**
 694  * struct xhci_input_control_context
 695  * Input control context; see section 6.2.5.
 696  *
 697  * @drop_context:       set the bit of the endpoint context you want to disable
 698  * @add_context:        set the bit of the endpoint context you want to enable
 699  */
 700 struct xhci_input_control_ctx {
 701         __le32  drop_flags;
 702         __le32  add_flags;
 703         __le32  rsvd2[6];
 704 };
 705
 706 #define EP_IS_ADDED(ctrl_ctx, i) \
 707         (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
 708 #define EP_IS_DROPPED(ctrl_ctx, i)       \
 709         (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
 710
 711 /* Represents everything that is needed to issue a command on the command ring.
 712  * It's useful to pre-allocate these for commands that cannot fail due to
 713  * out-of-memory errors, like freeing streams.
 714  */
 715 struct xhci_command {
 716         /* Input context for changing device state */
 717         struct xhci_container_ctx       *in_ctx;
 718         u32                             status;
 719         /* If completion is null, no one is waiting on this command
 720          * and the structure can be freed after the command completes.
 721          */
 722         struct completion               *completion;
 723         union xhci_trb                  *command_trb;
 724         struct list_head                cmd_list;
 725 };
 726
 727 /* drop context bitmasks */
 728 #define DROP_EP(x)      (0x1 << x)
 729 /* add context bitmasks */
 730 #define ADD_EP(x)       (0x1 << x)
 731
 732 struct xhci_stream_ctx {
 733         /* 64-bit stream ring address, cycle state, and stream type */
 734         __le64  stream_ring;
 735         /* offset 0x14 - 0x1f reserved for HC internal use */
 736         __le32  reserved[2];
 737 };
 738
 739 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
 740 #define SCT_FOR_CTX(p)          (((p) << 1) & 0x7)
 741 /* Secondary stream array type, dequeue pointer is to a transfer ring */
 742 #define SCT_SEC_TR              0
 743 /* Primary stream array type, dequeue pointer is to a transfer ring */
 744 #define SCT_PRI_TR              1
 745 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
 746 #define SCT_SSA_8               2
 747 #define SCT_SSA_16              3
 748 #define SCT_SSA_32              4
 749 #define SCT_SSA_64              5
 750 #define SCT_SSA_128             6
 751 #define SCT_SSA_256             7
 752
 753 /* Assume no secondary streams for now */
 754 struct xhci_stream_info {
 755         struct xhci_ring                **stream_rings;
 756         /* Number of streams, including stream 0 (which drivers can't use) */
 757         unsigned int                    num_streams;
 758         /* The stream context array may be bigger than
 759          * the number of streams the driver asked for
 760          */
 761         struct xhci_stream_ctx          *stream_ctx_array;
 762         unsigned int                    num_stream_ctxs;
 763         dma_addr_t                      ctx_array_dma;
 764         /* For mapping physical TRB addresses to segments in stream rings */
 765         struct radix_tree_root          trb_address_map;
 766         struct xhci_command             *free_streams_command;
 767 };
 768
 769 #define SMALL_STREAM_ARRAY_SIZE         256
 770 #define MEDIUM_STREAM_ARRAY_SIZE        1024
 771
 772 /* Some Intel xHCI host controllers need software to keep track of the bus
 773  * bandwidth.  Keep track of endpoint info here.  Each root port is allocated
 774  * the full bus bandwidth.  We must also treat TTs (including each port under a
 775  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
 776  * (DMI) also limits the total bandwidth (across all domains) that can be used.
 777  */
 778 struct xhci_bw_info {
 779         /* ep_interval is zero-based */
 780         unsigned int            ep_interval;
 781         /* mult and num_packets are one-based */
 782         unsigned int            mult;
 783         unsigned int            num_packets;
 784         unsigned int            max_packet_size;
 785         unsigned int            max_esit_payload;
 786         unsigned int            type;
 787 };
 788
 789 /* "Block" sizes in bytes the hardware uses for different device speeds.
 790  * The logic in this part of the hardware limits the number of bits the hardware
 791  * can use, so must represent bandwidth in a less precise manner to mimic what
 792  * the scheduler hardware computes.
 793  */
 794 #define FS_BLOCK        1
 795 #define HS_BLOCK        4
 796 #define SS_BLOCK        16
 797 #define DMI_BLOCK       32
 798
 799 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
 800  * with each byte transferred.  SuperSpeed devices have an initial overhead to
 801  * set up bursts.  These are in blocks, see above.  LS overhead has already been
 802  * translated into FS blocks.
 803  */
 804 #define DMI_OVERHEAD 8
 805 #define DMI_OVERHEAD_BURST 4
 806 #define SS_OVERHEAD 8
 807 #define SS_OVERHEAD_BURST 32
 808 #define HS_OVERHEAD 26
 809 #define FS_OVERHEAD 20
 810 #define LS_OVERHEAD 128
 811 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
 812  * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
 813  * of overhead associated with split transfers crossing microframe boundaries.
 814  * 31 blocks is pure protocol overhead.
 815  */
 816 #define TT_HS_OVERHEAD (31 + 94)
 817 #define TT_DMI_OVERHEAD (25 + 12)
 818
 819 /* Bandwidth limits in blocks */
 820 #define FS_BW_LIMIT             1285
 821 #define TT_BW_LIMIT             1320
 822 #define HS_BW_LIMIT             1607
 823 #define SS_BW_LIMIT_IN          3906
 824 #define DMI_BW_LIMIT_IN         3906
 825 #define SS_BW_LIMIT_OUT         3906
 826 #define DMI_BW_LIMIT_OUT        3906
 827
 828 /* Percentage of bus bandwidth reserved for non-periodic transfers */
 829 #define FS_BW_RESERVED          10
 830 #define HS_BW_RESERVED          20
 831 #define SS_BW_RESERVED          10
 832
 833 struct xhci_virt_ep {
 834         struct xhci_ring                *ring;
 835         /* Related to endpoints that are configured to use stream IDs only */
 836         struct xhci_stream_info         *stream_info;
 837         /* Temporary storage in case the configure endpoint command fails and we
 838          * have to restore the device state to the previous state
 839          */
 840         struct xhci_ring                *new_ring;
 841         unsigned int                    ep_state;
 842 #define SET_DEQ_PENDING         (1 << 0)
 843 #define EP_HALTED               (1 << 1)        /* For stall handling */
 844 #define EP_HALT_PENDING         (1 << 2)        /* For URB cancellation */
 845 /* Transitioning the endpoint to using streams, don't enqueue URBs */
 846 #define EP_GETTING_STREAMS      (1 << 3)
 847 #define EP_HAS_STREAMS          (1 << 4)
 848 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
 849 #define EP_GETTING_NO_STREAMS   (1 << 5)
 850         /* ----  Related to URB cancellation ---- */
 851         struct list_head        cancelled_td_list;
 852         /* The TRB that was last reported in a stopped endpoint ring */
 853         union xhci_trb          *stopped_trb;
 854         struct xhci_td          *stopped_td;
 855         unsigned int            stopped_stream;
 856         /* Watchdog timer for stop endpoint command to cancel URBs */
 857         struct timer_list       stop_cmd_timer;
 858         int                     stop_cmds_pending;
 859         struct xhci_hcd         *xhci;
 860         /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
 861          * command.  We'll need to update the ring's dequeue segment and dequeue
 862          * pointer after the command completes.
 863          */
 864         struct xhci_segment     *queued_deq_seg;
 865         union xhci_trb          *queued_deq_ptr;
 866         /*
 867          * Sometimes the xHC can not process isochronous endpoint ring quickly
 868          * enough, and it will miss some isoc tds on the ring and generate
 869          * a Missed Service Error Event.
 870          * Set skip flag when receive a Missed Service Error Event and
 871          * process the missed tds on the endpoint ring.
 872          */
 873         bool                    skip;
 874         /* Bandwidth checking storage */
 875         struct xhci_bw_info     bw_info;
 876         struct list_head        bw_endpoint_list;
 877 };
 878
 879 enum xhci_overhead_type {
 880         LS_OVERHEAD_TYPE = 0,
 881         FS_OVERHEAD_TYPE,
 882         HS_OVERHEAD_TYPE,
 883 };
 884
 885 struct xhci_interval_bw {
 886         unsigned int            num_packets;
 887         /* Sorted by max packet size.
 888          * Head of the list is the greatest max packet size.
 889          */
 890         struct list_head        endpoints;
 891         /* How many endpoints of each speed are present. */
 892         unsigned int            overhead[3];
 893 };
 894
 895 #define XHCI_MAX_INTERVAL       16
 896
 897 struct xhci_interval_bw_table {
 898         unsigned int            interval0_esit_payload;
 899         struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
 900         /* Includes reserved bandwidth for async endpoints */
 901         unsigned int            bw_used;
 902         unsigned int            ss_bw_in;
 903         unsigned int            ss_bw_out;
 904 };
 905
 906
 907 struct xhci_virt_device {
 908         struct usb_device               *udev;
 909         /*
 910          * Commands to the hardware are passed an "input context" that
 911          * tells the hardware what to change in its data structures.
 912          * The hardware will return changes in an "output context" that
 913          * software must allocate for the hardware.  We need to keep
 914          * track of input and output contexts separately because
 915          * these commands might fail and we don't trust the hardware.
 916          */
 917         struct xhci_container_ctx       *out_ctx;
 918         /* Used for addressing devices and configuration changes */
 919         struct xhci_container_ctx       *in_ctx;
 920         /* Rings saved to ensure old alt settings can be re-instated */
 921         struct xhci_ring                **ring_cache;
 922         int                             num_rings_cached;
 923         /* Store xHC assigned device address */
 924         int                             address;
 925 #define XHCI_MAX_RINGS_CACHED   31
 926         struct xhci_virt_ep             eps[31];
 927         struct completion               cmd_completion;
 928         /* Status of the last command issued for this device */
 929         u32                             cmd_status;
 930         struct list_head                cmd_list;
 931         u8                              fake_port;
 932         u8                              real_port;
 933         struct xhci_interval_bw_table   *bw_table;
 934         struct xhci_tt_bw_info          *tt_info;
 935         /* The current max exit latency for the enabled USB3 link states. */
 936         u16                             current_mel;
 937 };
 938
 939 /*
 940  * For each roothub, keep track of the bandwidth information for each periodic
 941  * interval.
 942  *
 943  * If a high speed hub is attached to the roothub, each TT associated with that
 944  * hub is a separate bandwidth domain.  The interval information for the
 945  * endpoints on the devices under that TT will appear in the TT structure.
 946  */
 947 struct xhci_root_port_bw_info {
 948         struct list_head                tts;
 949         unsigned int                    num_active_tts;
 950         struct xhci_interval_bw_table   bw_table;
 951 };
 952
 953 struct xhci_tt_bw_info {
 954         struct list_head                tt_list;
 955         int                             slot_id;
 956         int                             ttport;
 957         struct xhci_interval_bw_table   bw_table;
 958         int                             active_eps;
 959 };
 960
 961
 962 /**
 963  * struct xhci_device_context_array
 964  * @dev_context_ptr     array of 64-bit DMA addresses for device contexts
 965  */
 966 struct xhci_device_context_array {
 967         /* 64-bit device addresses; we only write 32-bit addresses */
 968         __le64                  dev_context_ptrs[MAX_HC_SLOTS];
 969         /* private xHCD pointers */
 970         dma_addr_t      dma;
 971 };
 972 /* TODO: write function to set the 64-bit device DMA address */
 973 /*
 974  * TODO: change this to be dynamically sized at HC mem init time since the HC
 975  * might not be able to handle the maximum number of devices possible.
 976  */
 977
 978
 979 struct xhci_transfer_event {
 980         /* 64-bit buffer address, or immediate data */
 981         __le64  buffer;
 982         __le32  transfer_len;
 983         /* This field is interpreted differently based on the type of TRB */
 984         __le32  flags;
 985 };
 986
 987 /* Transfer event TRB length bit mask */
 988 /* bits 0:23 */
 989 #define EVENT_TRB_LEN(p)                ((p) & 0xffffff)
 990
 991 /** Transfer Event bit fields **/
 992 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
 993
 994 /* Completion Code - only applicable for some types of TRBs */
 995 #define COMP_CODE_MASK          (0xff << 24)
 996 #define GET_COMP_CODE(p)        (((p) & COMP_CODE_MASK) >> 24)
 997 #define COMP_SUCCESS    1
 998 /* Data Buffer Error */
 999 #define COMP_DB_ERR     2
1000 /* Babble Detected Error */
1001 #define COMP_BABBLE     3
1002 /* USB Transaction Error */
1003 #define COMP_TX_ERR     4
1004 /* TRB Error - some TRB field is invalid */
1005 #define COMP_TRB_ERR    5
1006 /* Stall Error - USB device is stalled */
1007 #define COMP_STALL      6
1008 /* Resource Error - HC doesn't have memory for that device configuration */
1009 #define COMP_ENOMEM     7
1010 /* Bandwidth Error - not enough room in schedule for this dev config */
1011 #define COMP_BW_ERR     8
1012 /* No Slots Available Error - HC ran out of device slots */
1013 #define COMP_ENOSLOTS   9
1014 /* Invalid Stream Type Error */
1015 #define COMP_STREAM_ERR 10
1016 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1017 #define COMP_EBADSLT    11
1018 /* Endpoint Not Enabled Error */
1019 #define COMP_EBADEP     12
1020 /* Short Packet */
1021 #define COMP_SHORT_TX   13
1022 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1023 #define COMP_UNDERRUN   14
1024 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1025 #define COMP_OVERRUN    15
1026 /* Virtual Function Event Ring Full Error */
1027 #define COMP_VF_FULL    16
1028 /* Parameter Error - Context parameter is invalid */
1029 #define COMP_EINVAL     17
1030 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1031 #define COMP_BW_OVER    18
1032 /* Context State Error - illegal context state transition requested */
1033 #define COMP_CTX_STATE  19
1034 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1035 #define COMP_PING_ERR   20
1036 /* Event Ring is full */
1037 #define COMP_ER_FULL    21
1038 /* Incompatible Device Error */
1039 #define COMP_DEV_ERR    22
1040 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1041 #define COMP_MISSED_INT 23
1042 /* Successfully stopped command ring */
1043 #define COMP_CMD_STOP   24
1044 /* Successfully aborted current command and stopped command ring */
1045 #define COMP_CMD_ABORT  25
1046 /* Stopped - transfer was terminated by a stop endpoint command */
1047 #define COMP_STOP       26
1048 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1049 #define COMP_STOP_INVAL 27
1050 /* Control Abort Error - Debug Capability - control pipe aborted */
1051 #define COMP_DBG_ABORT  28
1052 /* Max Exit Latency Too Large Error */
1053 #define COMP_MEL_ERR    29
1054 /* TRB type 30 reserved */
1055 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1056 #define COMP_BUFF_OVER  31
1057 /* Event Lost Error - xHC has an "internal event overrun condition" */
1058 #define COMP_ISSUES     32
1059 /* Undefined Error - reported when other error codes don't apply */
1060 #define COMP_UNKNOWN    33
1061 /* Invalid Stream ID Error */
1062 #define COMP_STRID_ERR  34
1063 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1064 #define COMP_2ND_BW_ERR 35
1065 /* Split Transaction Error */
1066 #define COMP_SPLIT_ERR  36
1067
1068 struct xhci_link_trb {
1069         /* 64-bit segment pointer*/
1070         __le64 segment_ptr;
1071         __le32 intr_target;
1072         __le32 control;
1073 };
1074
1075 /* control bitfields */
1076 #define LINK_TOGGLE     (0x1<<1)
1077
1078 /* Command completion event TRB */
1079 struct xhci_event_cmd {
1080         /* Pointer to command TRB, or the value passed by the event data trb */
1081         __le64 cmd_trb;
1082         __le32 status;
1083         __le32 flags;
1084 };
1085
1086 /* flags bitmasks */
1087 /* bits 16:23 are the virtual function ID */
1088 /* bits 24:31 are the slot ID */
1089 #define TRB_TO_SLOT_ID(p)       (((p) & (0xff<<24)) >> 24)
1090 #define SLOT_ID_FOR_TRB(p)      (((p) & 0xff) << 24)
1091
1092 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1093 #define TRB_TO_EP_INDEX(p)              ((((p) & (0x1f << 16)) >> 16) - 1)
1094 #define EP_ID_FOR_TRB(p)                ((((p) + 1) & 0x1f) << 16)
1095
1096 #define SUSPEND_PORT_FOR_TRB(p)         (((p) & 1) << 23)
1097 #define TRB_TO_SUSPEND_PORT(p)          (((p) & (1 << 23)) >> 23)
1098 #define LAST_EP_INDEX                   30
1099
1100 /* Set TR Dequeue Pointer command TRB fields */
1101 #define TRB_TO_STREAM_ID(p)             ((((p) & (0xffff << 16)) >> 16))
1102 #define STREAM_ID_FOR_TRB(p)            ((((p)) & 0xffff) << 16)
1103
1104
1105 /* Port Status Change Event TRB fields */
1106 /* Port ID - bits 31:24 */
1107 #define GET_PORT_ID(p)          (((p) & (0xff << 24)) >> 24)
1108
1109 /* Normal TRB fields */
1110 /* transfer_len bitmasks - bits 0:16 */
1111 #define TRB_LEN(p)              ((p) & 0x1ffff)
1112 /* Interrupter Target - which MSI-X vector to target the completion event at */
1113 #define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
1114 #define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
1115 #define TRB_TBC(p)              (((p) & 0x3) << 7)
1116 #define TRB_TLBPC(p)            (((p) & 0xf) << 16)
1117
1118 /* Cycle bit - indicates TRB ownership by HC or HCD */
1119 #define TRB_CYCLE               (1<<0)
1120 /*
1121  * Force next event data TRB to be evaluated before task switch.
1122  * Used to pass OS data back after a TD completes.
1123  */
1124 #define TRB_ENT                 (1<<1)
1125 /* Interrupt on short packet */
1126 #define TRB_ISP                 (1<<2)
1127 /* Set PCIe no snoop attribute */
1128 #define TRB_NO_SNOOP            (1<<3)
1129 /* Chain multiple TRBs into a TD */
1130 #define TRB_CHAIN               (1<<4)
1131 /* Interrupt on completion */
1132 #define TRB_IOC                 (1<<5)
1133 /* The buffer pointer contains immediate data */
1134 #define TRB_IDT                 (1<<6)
1135
1136 /* Block Event Interrupt */
1137 #define TRB_BEI                 (1<<9)
1138
1139 /* Control transfer TRB specific fields */
1140 #define TRB_DIR_IN              (1<<16)
1141 #define TRB_TX_TYPE(p)          ((p) << 16)
1142 #define TRB_DATA_OUT            2
1143 #define TRB_DATA_IN             3
1144
1145 /* Isochronous TRB specific fields */
1146 #define TRB_SIA                 (1<<31)
1147
1148 struct xhci_generic_trb {
1149         __le32 field[4];
1150 };
1151
1152 union xhci_trb {
1153         struct xhci_link_trb            link;
1154         struct xhci_transfer_event      trans_event;
1155         struct xhci_event_cmd           event_cmd;
1156         struct xhci_generic_trb         generic;
1157 };
1158
1159 /* TRB bit mask */
1160 #define TRB_TYPE_BITMASK        (0xfc00)
1161 #define TRB_TYPE(p)             ((p) << 10)
1162 #define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1163 /* TRB type IDs */
1164 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1165 #define TRB_NORMAL              1
1166 /* setup stage for control transfers */
1167 #define TRB_SETUP               2
1168 /* data stage for control transfers */
1169 #define TRB_DATA                3
1170 /* status stage for control transfers */
1171 #define TRB_STATUS              4
1172 /* isoc transfers */
1173 #define TRB_ISOC                5
1174 /* TRB for linking ring segments */
1175 #define TRB_LINK                6
1176 #define TRB_EVENT_DATA          7
1177 /* Transfer Ring No-op (not for the command ring) */
1178 #define TRB_TR_NOOP             8
1179 /* Command TRBs */
1180 /* Enable Slot Command */
1181 #define TRB_ENABLE_SLOT         9
1182 /* Disable Slot Command */
1183 #define TRB_DISABLE_SLOT        10
1184 /* Address Device Command */
1185 #define TRB_ADDR_DEV            11
1186 /* Configure Endpoint Command */
1187 #define TRB_CONFIG_EP           12
1188 /* Evaluate Context Command */
1189 #define TRB_EVAL_CONTEXT        13
1190 /* Reset Endpoint Command */
1191 #define TRB_RESET_EP            14
1192 /* Stop Transfer Ring Command */
1193 #define TRB_STOP_RING           15
1194 /* Set Transfer Ring Dequeue Pointer Command */
1195 #define TRB_SET_DEQ             16
1196 /* Reset Device Command */
1197 #define TRB_RESET_DEV           17
1198 /* Force Event Command (opt) */
1199 #define TRB_FORCE_EVENT         18
1200 /* Negotiate Bandwidth Command (opt) */
1201 #define TRB_NEG_BANDWIDTH       19
1202 /* Set Latency Tolerance Value Command (opt) */
1203 #define TRB_SET_LT              20
1204 /* Get port bandwidth Command */
1205 #define TRB_GET_BW              21
1206 /* Force Header Command - generate a transaction or link management packet */
1207 #define TRB_FORCE_HEADER        22
1208 /* No-op Command - not for transfer rings */
1209 #define TRB_CMD_NOOP            23
1210 /* TRB IDs 24-31 reserved */
1211 /* Event TRBS */
1212 /* Transfer Event */
1213 #define TRB_TRANSFER            32
1214 /* Command Completion Event */
1215 #define TRB_COMPLETION          33
1216 /* Port Status Change Event */
1217 #define TRB_PORT_STATUS         34
1218 /* Bandwidth Request Event (opt) */
1219 #define TRB_BANDWIDTH_EVENT     35
1220 /* Doorbell Event (opt) */
1221 #define TRB_DOORBELL            36
1222 /* Host Controller Event */
1223 #define TRB_HC_EVENT            37
1224 /* Device Notification Event - device sent function wake notification */
1225 #define TRB_DEV_NOTE            38
1226 /* MFINDEX Wrap Event - microframe counter wrapped */
1227 #define TRB_MFINDEX_WRAP        39
1228 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1229
1230 /* Nec vendor-specific command completion event. */
1231 #define TRB_NEC_CMD_COMP        48
1232 /* Get NEC firmware revision. */
1233 #define TRB_NEC_GET_FW          49
1234
1235 #define TRB_TYPE_LINK(x)        (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1236 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1237 #define TRB_TYPE_LINK_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1238                                  cpu_to_le32(TRB_TYPE(TRB_LINK)))
1239 #define TRB_TYPE_NOOP_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1240                                  cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1241
1242 #define NEC_FW_MINOR(p)         (((p) >> 0) & 0xff)
1243 #define NEC_FW_MAJOR(p)         (((p) >> 8) & 0xff)
1244
1245 /*
1246  * TRBS_PER_SEGMENT must be a multiple of 4,
1247  * since the command ring is 64-byte aligned.
1248  * It must also be greater than 16.
1249  */
1250 #define TRBS_PER_SEGMENT        256
1251 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1252 #define MAX_RSVD_CMD_TRBS       (TRBS_PER_SEGMENT - 3)
1253 #define TRB_SEGMENT_SIZE        (TRBS_PER_SEGMENT*16)
1254 #define TRB_SEGMENT_SHIFT       (ilog2(TRB_SEGMENT_SIZE))
1255 /* TRB buffer pointers can't cross 64KB boundaries */
1256 #define TRB_MAX_BUFF_SHIFT              16
1257 #define TRB_MAX_BUFF_SIZE       (1 << TRB_MAX_BUFF_SHIFT)
1258
1259 struct xhci_segment {
1260         union xhci_trb          *trbs;
1261         /* private to HCD */
1262         struct xhci_segment     *next;
1263         dma_addr_t              dma;
1264 };
1265
1266 struct xhci_td {
1267         struct list_head        td_list;
1268         struct list_head        cancelled_td_list;
1269         struct urb              *urb;
1270         struct xhci_segment     *start_seg;
1271         union xhci_trb          *first_trb;
1272         union xhci_trb          *last_trb;
1273         /* actual_length of the URB has already been set */
1274         bool                    urb_length_set;
1275 };
1276
1277 /* xHCI command default timeout value */
1278 #define XHCI_CMD_DEFAULT_TIMEOUT        (5 * HZ)
1279
1280 /* command descriptor */
1281 struct xhci_cd {
1282         struct list_head        cancel_cmd_list;
1283         struct xhci_command     *command;
1284         union xhci_trb          *cmd_trb;
1285 };
1286
1287 struct xhci_dequeue_state {
1288         struct xhci_segment *new_deq_seg;
1289         union xhci_trb *new_deq_ptr;
1290         int new_cycle_state;
1291 };
1292
1293 enum xhci_ring_type {
1294         TYPE_CTRL = 0,
1295         TYPE_ISOC,
1296         TYPE_BULK,
1297         TYPE_INTR,
1298         TYPE_STREAM,
1299         TYPE_COMMAND,
1300         TYPE_EVENT,
1301 };
1302
1303 struct xhci_ring {
1304         struct xhci_segment     *first_seg;
1305         struct xhci_segment     *last_seg;
1306         union  xhci_trb         *enqueue;
1307         struct xhci_segment     *enq_seg;
1308         unsigned int            enq_updates;
1309         union  xhci_trb         *dequeue;
1310         struct xhci_segment     *deq_seg;
1311         unsigned int            deq_updates;
1312         struct list_head        td_list;
1313         /*
1314          * Write the cycle state into the TRB cycle field to give ownership of
1315          * the TRB to the host controller (if we are the producer), or to check
1316          * if we own the TRB (if we are the consumer).  See section 4.9.1.
1317          */
1318         u32                     cycle_state;
1319         unsigned int            stream_id;
1320         unsigned int            num_segs;
1321         unsigned int            num_trbs_free;
1322         unsigned int            num_trbs_free_temp;
1323         enum xhci_ring_type     type;
1324         bool                    last_td_was_short;
1325 };
1326
1327 struct xhci_erst_entry {
1328         /* 64-bit event ring segment address */
1329         __le64  seg_addr;
1330         __le32  seg_size;
1331         /* Set to zero */
1332         __le32  rsvd;
1333 };
1334
1335 struct xhci_erst {
1336         struct xhci_erst_entry  *entries;
1337         unsigned int            num_entries;
1338         /* xhci->event_ring keeps track of segment dma addresses */
1339         dma_addr_t              erst_dma_addr;
1340         /* Num entries the ERST can contain */
1341         unsigned int            erst_size;
1342 };
1343
1344 struct xhci_scratchpad {
1345         u64 *sp_array;
1346         dma_addr_t sp_dma;
1347         void **sp_buffers;
1348         dma_addr_t *sp_dma_buffers;
1349 };
1350
1351 struct urb_priv {
1352         int     length;
1353         int     td_cnt;
1354         struct  xhci_td *td[0];
1355 };
1356
1357 /*
1358  * Each segment table entry is 4*32bits long.  1K seems like an ok size:
1359  * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1360  * meaning 64 ring segments.
1361  * Initial allocated size of the ERST, in number of entries */
1362 #define ERST_NUM_SEGS   1
1363 /* Initial allocated size of the ERST, in number of entries */
1364 #define ERST_SIZE       64
1365 /* Initial number of event segment rings allocated */
1366 #define ERST_ENTRIES    1
1367 /* Poll every 60 seconds */
1368 #define POLL_TIMEOUT    60
1369 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1370 #define XHCI_STOP_EP_CMD_TIMEOUT        5
1371 /* XXX: Make these module parameters */
1372
1373 struct s3_save {
1374         u32     command;
1375         u32     dev_nt;
1376         u64     dcbaa_ptr;
1377         u32     config_reg;
1378         u32     irq_pending;
1379         u32     irq_control;
1380         u32     erst_size;
1381         u64     erst_base;
1382         u64     erst_dequeue;
1383 };
1384
1385 /* Use for lpm */
1386 struct dev_info {
1387         u32                     dev_id;
1388         struct  list_head       list;
1389 };
1390
1391 struct xhci_bus_state {
1392         unsigned long           bus_suspended;
1393         unsigned long           next_statechange;
1394
1395         /* Port suspend arrays are indexed by the portnum of the fake roothub */
1396         /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1397         u32                     port_c_suspend;
1398         u32                     suspended_ports;
1399         u32                     port_remote_wakeup;
1400         unsigned long           resume_done[USB_MAXCHILDREN];
1401         /* which ports have started to resume */
1402         unsigned long           resuming_ports;
1403 };
1404
1405 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1406 {
1407         if (hcd->speed == HCD_USB3)
1408                 return 0;
1409         else
1410                 return 1;
1411 }
1412
1413 /* There is one xhci_hcd structure per controller */
1414 struct xhci_hcd {
1415         struct usb_hcd *main_hcd;
1416         struct usb_hcd *shared_hcd;
1417         /* glue to PCI and HCD framework */
1418         struct xhci_cap_regs __iomem *cap_regs;
1419         struct xhci_op_regs __iomem *op_regs;
1420         struct xhci_run_regs __iomem *run_regs;
1421         struct xhci_doorbell_array __iomem *dba;
1422         /* Our HCD's current interrupter register set */
1423         struct  xhci_intr_reg __iomem *ir_set;
1424
1425         #ifdef CONFIG_MTK_XHCI
1426         unsigned long base_regs;
1427         unsigned long sif_regs;
1428         unsigned long sif2_regs;
1429         #endif
1430
1431         /* Cached register copies of read-only HC data */
1432         __u32           hcs_params1;
1433         __u32           hcs_params2;
1434         __u32           hcs_params3;
1435         __u32           hcc_params;
1436
1437         spinlock_t      lock;
1438
1439         /* packed release number */
1440         u8              sbrn;
1441         u16             hci_version;
1442         u8              max_slots;
1443         u8              max_interrupters;
1444         u8              max_ports;
1445         u8              isoc_threshold;
1446         int             event_ring_max;
1447         int             addr_64;
1448         /* 4KB min, 128MB max */
1449         int             page_size;
1450         /* Valid values are 12 to 20, inclusive */
1451         int             page_shift;
1452         /* msi-x vectors */
1453         int             msix_count;
1454         struct msix_entry       *msix_entries;
1455         /* data structures */
1456         struct xhci_device_context_array *dcbaa;
1457         struct xhci_ring        *cmd_ring;
1458         unsigned int            cmd_ring_state;
1459 #define CMD_RING_STATE_RUNNING         (1 << 0)
1460 #define CMD_RING_STATE_ABORTED         (1 << 1)
1461 #define CMD_RING_STATE_STOPPED         (1 << 2)
1462         struct list_head        cancel_cmd_list;
1463         unsigned int            cmd_ring_reserved_trbs;
1464         struct xhci_ring        *event_ring;
1465         struct xhci_erst        erst;
1466         /* Scratchpad */
1467         struct xhci_scratchpad  *scratchpad;
1468         /* Store LPM test failed devices' information */
1469         struct list_head        lpm_failed_devs;
1470
1471         /* slot enabling and address device helpers */
1472         struct completion       addr_dev;
1473         int slot_id;
1474         /* For USB 3.0 LPM enable/disable. */
1475         struct xhci_command             *lpm_command;
1476         /* Internal mirror of the HW's dcbaa */
1477         struct xhci_virt_device *devs[MAX_HC_SLOTS];
1478         /* For keeping track of bandwidth domains per roothub. */
1479         struct xhci_root_port_bw_info   *rh_bw;
1480
1481         /* DMA pools */
1482         struct dma_pool *device_pool;
1483         struct dma_pool *segment_pool;
1484         struct dma_pool *small_streams_pool;
1485         struct dma_pool *medium_streams_pool;
1486
1487 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1488         /* Poll the rings - for debugging */
1489         struct timer_list       event_ring_timer;
1490         int                     zombie;
1491 #endif
1492         /* Host controller watchdog timer structures */
1493         unsigned int            xhc_state;
1494
1495         u32                     command;
1496         struct s3_save          s3;
1497 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1498  *
1499  * xHC interrupts have been disabled and a watchdog timer will (or has already)
1500  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1501  * that sees this status (other than the timer that set it) should stop touching
1502  * hardware immediately.  Interrupt handlers should return immediately when
1503  * they see this status (any time they drop and re-acquire xhci->lock).
1504  * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1505  * putting the TD on the canceled list, etc.
1506  *
1507  * There are no reports of xHCI host controllers that display this issue.
1508  */
1509 #define XHCI_STATE_DYING        (1 << 0)
1510 #define XHCI_STATE_HALTED       (1 << 1)
1511         /* Statistics */
1512         int                     error_bitmask;
1513         unsigned int            quirks;
1514 #define XHCI_LINK_TRB_QUIRK     (1 << 0)
1515 #define XHCI_RESET_EP_QUIRK     (1 << 1)
1516 #define XHCI_NEC_HOST           (1 << 2)
1517 #ifndef CONFIG_MTK_XHCI
1518 #define XHCI_AMD_PLL_FIX        (1 << 3)
1519 #endif
1520 #define XHCI_SPURIOUS_SUCCESS   (1 << 4)
1521 /*
1522  * Certain Intel host controllers have a limit to the number of endpoint
1523  * contexts they can handle.  Ideally, they would signal that they can't handle
1524  * anymore endpoint contexts by returning a Resource Error for the Configure
1525  * Endpoint command, but they don't.  Instead they expect software to keep track
1526  * of the number of active endpoints for them, across configure endpoint
1527  * commands, reset device commands, disable slot commands, and address device
1528  * commands.
1529  */
1530 #define XHCI_EP_LIMIT_QUIRK     (1 << 5)
1531 #define XHCI_BROKEN_MSI         (1 << 6)
1532 #define XHCI_RESET_ON_RESUME    (1 << 7)
1533 #define XHCI_SW_BW_CHECKING     (1 << 8)
1534 #ifndef CONFIG_MTK_XHCI
1535 #define XHCI_AMD_0x96_HOST      (1 << 9)
1536 #endif
1537 #define XHCI_TRUST_TX_LENGTH    (1 << 10)
1538 #define XHCI_LPM_SUPPORT        (1 << 11)
1539 #define XHCI_INTEL_HOST         (1 << 12)
1540 #define XHCI_SPURIOUS_REBOOT    (1 << 13)
1541 #define XHCI_COMP_MODE_QUIRK    (1 << 14)
1542 #define XHCI_AVOID_BEI          (1 << 15)
1543 #define XHCI_PLAT               (1 << 16)
1544         unsigned int            num_active_eps;
1545         unsigned int            limit_active_eps;
1546         /* There are two roothubs to keep track of bus suspend info for */
1547         struct xhci_bus_state   bus_state[2];
1548         /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1549         u8                      *port_array;
1550         /* Array of pointers to USB 3.0 PORTSC registers */
1551         __le32 __iomem          **usb3_ports;
1552         unsigned int            num_usb3_ports;
1553         /* Array of pointers to USB 2.0 PORTSC registers */
1554         __le32 __iomem          **usb2_ports;
1555         unsigned int            num_usb2_ports;
1556         /* support xHCI 0.96 spec USB2 software LPM */
1557         unsigned                sw_lpm_support:1;
1558         /* support xHCI 1.0 spec USB2 hardware LPM */
1559         unsigned                hw_lpm_support:1;
1560         /* Compliance Mode Recovery Data */
1561         struct timer_list       comp_mode_recovery_timer;
1562         u32                     port_status_u0;
1563 /* Compliance Mode Timer Triggered every 2 seconds */
1564 #define COMP_MODE_RCVRY_MSECS 2000
1565 };
1566
1567 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1568 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1569 {
1570         return *((struct xhci_hcd **) (hcd->hcd_priv));
1571 }
1572
1573 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1574 {
1575         return xhci->main_hcd;
1576 }
1577
1578 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1579 #define XHCI_DEBUG      1
1580 #else
1581 #define XHCI_DEBUG      0
1582 #endif
1583
1584 #define xhci_dbg(xhci, fmt, args...) \
1585         do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1586 #define xhci_info(xhci, fmt, args...) \
1587         do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1588 #define xhci_err(xhci, fmt, args...) \
1589         dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1590 #define xhci_warn(xhci, fmt, args...) \
1591         dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1592 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1593         dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1594
1595 /* TODO: copied from ehci.h - can be refactored? */
1596 /* xHCI spec says all registers are little endian */
1597 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1598                 void __iomem *regs)
1599 {
1600         return readl(regs);
1601 }
1602 static inline void xhci_writel(struct xhci_hcd *xhci,
1603                 const unsigned int val, void __iomem *regs)
1604 {
1605         writel(val, regs);
1606 }
1607
1608 /*
1609  * Registers should always be accessed with double word or quad word accesses.
1610  *
1611  * Some xHCI implementations may support 64-bit address pointers.  Registers
1612  * with 64-bit address pointers should be written to with dword accesses by
1613  * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1614  * xHCI implementations that do not support 64-bit address pointers will ignore
1615  * the high dword, and write order is irrelevant.
1616  */
1617 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1618                 __le64 __iomem *regs)
1619 {
1620         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1621         u64 val_lo = readl(ptr);
1622         u64 val_hi = readl(ptr + 1);
1623         return val_lo + (val_hi << 32);
1624 }
1625 static inline void xhci_write_64(struct xhci_hcd *xhci,
1626                                  const u64 val, __le64 __iomem *regs)
1627 {
1628         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1629         u32 val_lo = lower_32_bits(val);
1630         u32 val_hi = upper_32_bits(val);
1631
1632         writel(val_lo, ptr);
1633         writel(val_hi, ptr + 1);
1634 }
1635
1636 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1637 {
1638         return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1639 }
1640
1641 /* xHCI debugging */
1642 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1643 void xhci_print_registers(struct xhci_hcd *xhci);
1644 void xhci_dbg_regs(struct xhci_hcd *xhci);
1645 void xhci_print_run_regs(struct xhci_hcd *xhci);
1646 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1647 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1648 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1649 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1650 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1651 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1652 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1653 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1654 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1655                 struct xhci_container_ctx *ctx);
1656 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1657                 unsigned int slot_id, unsigned int ep_index,
1658                 struct xhci_virt_ep *ep);
1659
1660 /* xHCI memory management */
1661 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1662 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1663 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1664 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1665 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1666 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1667                 struct usb_device *udev);
1668 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1669 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1670 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1671 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1672 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1673 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1674                 struct xhci_bw_info *ep_bw,
1675                 struct xhci_interval_bw_table *bw_table,
1676                 struct usb_device *udev,
1677                 struct xhci_virt_ep *virt_ep,
1678                 struct xhci_tt_bw_info *tt_info);
1679 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1680                 struct xhci_virt_device *virt_dev,
1681                 int old_active_eps);
1682 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1683 void xhci_update_bw_info(struct xhci_hcd *xhci,
1684                 struct xhci_container_ctx *in_ctx,
1685                 struct xhci_input_control_ctx *ctrl_ctx,
1686                 struct xhci_virt_device *virt_dev);
1687 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1688                 struct xhci_container_ctx *in_ctx,
1689                 struct xhci_container_ctx *out_ctx,
1690                 unsigned int ep_index);
1691 void xhci_slot_copy(struct xhci_hcd *xhci,
1692                 struct xhci_container_ctx *in_ctx,
1693                 struct xhci_container_ctx *out_ctx);
1694 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1695                 struct usb_device *udev, struct usb_host_endpoint *ep,
1696                 gfp_t mem_flags);
1697 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1698 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1699                                 unsigned int num_trbs, gfp_t flags);
1700 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1701                 struct xhci_virt_device *virt_dev,
1702                 unsigned int ep_index);
1703 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1704                 unsigned int num_stream_ctxs,
1705                 unsigned int num_streams, gfp_t flags);
1706 void xhci_free_stream_info(struct xhci_hcd *xhci,
1707                 struct xhci_stream_info *stream_info);
1708 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1709                 struct xhci_ep_ctx *ep_ctx,
1710                 struct xhci_stream_info *stream_info);
1711 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1712                 struct xhci_ep_ctx *ep_ctx,
1713                 struct xhci_virt_ep *ep);
1714 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1715         struct xhci_virt_device *virt_dev, bool drop_control_ep);
1716 struct xhci_ring *xhci_dma_to_transfer_ring(
1717                 struct xhci_virt_ep *ep,
1718                 u64 address);
1719 struct xhci_ring *xhci_stream_id_to_ring(
1720                 struct xhci_virt_device *dev,
1721                 unsigned int ep_index,
1722                 unsigned int stream_id);
1723 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1724                 bool allocate_in_ctx, bool allocate_completion,
1725                 gfp_t mem_flags);
1726 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1727 void xhci_free_command(struct xhci_hcd *xhci,
1728                 struct xhci_command *command);
1729
1730 #ifdef CONFIG_PCI
1731 /* xHCI PCI glue */
1732 int xhci_register_pci(void);
1733 void xhci_unregister_pci(void);
1734 #else
1735 static inline int xhci_register_pci(void) { return 0; }
1736 static inline void xhci_unregister_pci(void) {}
1737 #endif
1738
1739 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1740         || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1741 int xhci_register_plat(void);
1742 void xhci_unregister_plat(void);
1743 #else
1744 static inline int xhci_register_plat(void)
1745 { return 0; }
1746 static inline void xhci_unregister_plat(void)
1747 {  }
1748 #endif
1749
1750 /* xHCI host controller glue */
1751 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1752 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1753                 u32 mask, u32 done, int usec);
1754 void xhci_quiesce(struct xhci_hcd *xhci);
1755 int xhci_halt(struct xhci_hcd *xhci);
1756 int xhci_reset(struct xhci_hcd *xhci);
1757 int xhci_init(struct usb_hcd *hcd);
1758 int xhci_run(struct usb_hcd *hcd);
1759 void xhci_stop(struct usb_hcd *hcd);
1760 void xhci_shutdown(struct usb_hcd *hcd);
1761 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1762
1763 #ifdef  CONFIG_PM
1764 int xhci_suspend(struct xhci_hcd *xhci);
1765 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1766 #else
1767 #define xhci_suspend    NULL
1768 #define xhci_resume     NULL
1769 #endif
1770
1771 int xhci_get_frame(struct usb_hcd *hcd);
1772 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1773 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1774 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1775 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1776 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1777                 struct xhci_virt_device *virt_dev,
1778                 struct usb_device *hdev,
1779                 struct usb_tt *tt, gfp_t mem_flags);
1780 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1781                 struct usb_host_endpoint **eps, unsigned int num_eps,
1782                 unsigned int num_streams, gfp_t mem_flags);
1783 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1784                 struct usb_host_endpoint **eps, unsigned int num_eps,
1785                 gfp_t mem_flags);
1786 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1787 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1788 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1789                                 struct usb_device *udev, int enable);
1790 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1791                         struct usb_tt *tt, gfp_t mem_flags);
1792 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1793 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1794 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1795 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1796 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1797 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1798 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1799 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1800
1801 /* xHCI ring, segment, TRB, and TD functions */
1802 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1803 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1804                 union xhci_trb *start_trb, union xhci_trb *end_trb,
1805                 dma_addr_t suspect_dma);
1806 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1807 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1808 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1809 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1810                 u32 slot_id);
1811 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1812                 u32 field1, u32 field2, u32 field3, u32 field4);
1813 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1814                 unsigned int ep_index, int suspend);
1815 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1816                 int slot_id, unsigned int ep_index);
1817 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1818                 int slot_id, unsigned int ep_index);
1819 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1820                 int slot_id, unsigned int ep_index);
1821 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1822                 struct urb *urb, int slot_id, unsigned int ep_index);
1823 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1824                 u32 slot_id, bool command_must_succeed);
1825 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1826                 u32 slot_id, bool command_must_succeed);
1827 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1828                 unsigned int ep_index);
1829 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1830 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1831                 unsigned int slot_id, unsigned int ep_index,
1832                 unsigned int stream_id, struct xhci_td *cur_td,
1833                 struct xhci_dequeue_state *state);
1834 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1835                 unsigned int slot_id, unsigned int ep_index,
1836                 unsigned int stream_id,
1837                 struct xhci_dequeue_state *deq_state);
1838 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1839                 struct usb_device *udev, unsigned int ep_index);
1840 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1841                 unsigned int slot_id, unsigned int ep_index,
1842                 struct xhci_dequeue_state *deq_state);
1843 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1844 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1845                 union xhci_trb *cmd_trb);
1846 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1847                 unsigned int ep_index, unsigned int stream_id);
1848 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring);
1849
1850 /* xHCI roothub code */
1851 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1852                                 int port_id, u32 link_state);
1853 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1854                         struct usb_device *udev, enum usb3_link_state state);
1855 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1856                         struct usb_device *udev, enum usb3_link_state state);
1857 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1858                                 int port_id, u32 port_bit);
1859 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1860                 char *buf, u16 wLength);
1861 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1862 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1863
1864 #ifdef CONFIG_PM
1865 int xhci_bus_suspend(struct usb_hcd *hcd);
1866 int xhci_bus_resume(struct usb_hcd *hcd);
1867 #else
1868 #define xhci_bus_suspend        NULL
1869 #define xhci_bus_resume         NULL
1870 #endif  /* CONFIG_PM */
1871
1872 u32 xhci_port_state_to_neutral(u32 state);
1873 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1874                 u16 port);
1875 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1876
1877 /* xHCI contexts */
1878 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1879 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1880 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1881
1882 /* xHCI quirks */
1883 bool xhci_compliance_mode_recovery_timer_quirk_check(void);
1884
1885 #endif /* __LINUX_XHCI_HCD_H */