2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
119 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
121 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
122 return TRB_TYPE_LINK_LE32(link
->control
);
125 union xhci_trb
*xhci_find_next_enqueue(struct xhci_ring
*ring
)
127 /* Enqueue pointer can be left pointing to the link TRB,
128 * we must handle that
130 if (TRB_TYPE_LINK_LE32(ring
->enqueue
->link
.control
))
131 return ring
->enq_seg
->next
->trbs
;
132 return ring
->enqueue
;
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd
*xhci
,
140 struct xhci_ring
*ring
,
141 struct xhci_segment
**seg
,
142 union xhci_trb
**trb
)
144 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
146 *trb
= ((*seg
)->trbs
);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
158 unsigned long long addr
;
163 * If this is not event ring, and the dequeue pointer
164 * is not on a link TRB, there is one more usable TRB
166 if (ring
->type
!= TYPE_EVENT
&&
167 !last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
))
168 ring
->num_trbs_free
++;
172 * Update the dequeue pointer further if that was a link TRB or
173 * we're at the end of an event ring segment (which doesn't have
176 if (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
)) {
177 if (ring
->type
== TYPE_EVENT
&&
178 last_trb_on_last_seg(xhci
, ring
,
179 ring
->deq_seg
, ring
->dequeue
)) {
180 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
182 ring
->deq_seg
= ring
->deq_seg
->next
;
183 ring
->dequeue
= ring
->deq_seg
->trbs
;
187 } while (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
));
189 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
193 * See Cycle bit rules. SW is the consumer for the event ring only.
194 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
196 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
197 * chain bit is set), then set the chain bit in all the following link TRBs.
198 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
199 * have their chain bit cleared (so that each Link TRB is a separate TD).
201 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
202 * set, but other sections talk about dealing with the chain bit set. This was
203 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
204 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
206 * @more_trbs_coming: Will you enqueue more TRBs before calling
207 * prepare_transfer()?
209 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
210 bool more_trbs_coming
)
213 union xhci_trb
*next
;
214 unsigned long long addr
;
216 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
217 /* If this is not event ring, there is one less usable TRB */
218 if (ring
->type
!= TYPE_EVENT
&&
219 !last_trb(xhci
, ring
, ring
->enq_seg
, ring
->enqueue
))
220 ring
->num_trbs_free
--;
221 next
= ++(ring
->enqueue
);
224 /* Update the dequeue pointer further if that was a link TRB or we're at
225 * the end of an event ring segment (which doesn't have link TRBS)
227 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
228 if (ring
->type
!= TYPE_EVENT
) {
230 * If the caller doesn't plan on enqueueing more
231 * TDs before ringing the doorbell, then we
232 * don't want to give the link TRB to the
233 * hardware just yet. We'll give the link TRB
234 * back in prepare_ring() just before we enqueue
235 * the TD at the top of the ring.
237 if (!chain
&& !more_trbs_coming
)
240 /* If we're not dealing with 0.95 hardware or
241 * isoc rings on AMD 0.96 host,
242 * carry over the chain bit of the previous TRB
243 * (which may mean the chain bit is cleared).
245 #ifdef CONFIG_MTK_XHCI
246 if (!xhci_link_trb_quirk(xhci
)) {
248 if (!(ring
->type
== TYPE_ISOC
&&
249 (xhci
->quirks
& XHCI_AMD_0x96_HOST
))
250 && !xhci_link_trb_quirk(xhci
)) {
252 next
->link
.control
&=
253 cpu_to_le32(~TRB_CHAIN
);
254 next
->link
.control
|=
257 /* Give this link TRB to the hardware */
259 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
261 /* Toggle the cycle bit after the last ring segment. */
262 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
263 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
266 ring
->enq_seg
= ring
->enq_seg
->next
;
267 ring
->enqueue
= ring
->enq_seg
->trbs
;
268 next
= ring
->enqueue
;
270 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
274 * Check to see if there's room to enqueue num_trbs on the ring and make sure
275 * enqueue pointer will not advance into dequeue segment. See rules above.
277 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
278 unsigned int num_trbs
)
280 #ifndef CONFIG_MTK_XHCI
281 int num_trbs_in_deq_seg
;
284 if (ring
->num_trbs_free
< num_trbs
)
287 #ifndef CONFIG_MTK_XHCI
288 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
289 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
290 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
298 /* Ring the host controller doorbell after placing a command on the ring */
299 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
301 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
304 xhci_dbg(xhci
, "// Ding dong!\n");
305 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
306 /* Flush PCI posted writes */
307 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
310 static int xhci_abort_cmd_ring(struct xhci_hcd
*xhci
)
315 xhci_dbg(xhci
, "Abort command ring\n");
317 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
)) {
318 xhci_dbg(xhci
, "The command ring isn't running, "
319 "Have the command ring been stopped?\n");
323 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
324 if (!(temp_64
& CMD_RING_RUNNING
)) {
325 xhci_dbg(xhci
, "Command ring had been stopped\n");
328 xhci
->cmd_ring_state
= CMD_RING_STATE_ABORTED
;
329 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
330 &xhci
->op_regs
->cmd_ring
);
332 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
333 * time the completion od all xHCI commands, including
334 * the Command Abort operation. If software doesn't see
335 * CRR negated in a timely manner (e.g. longer than 5
336 * seconds), then it should assume that the there are
337 * larger problems with the xHC and assert HCRST.
339 ret
= xhci_handshake(xhci
, &xhci
->op_regs
->cmd_ring
,
340 CMD_RING_RUNNING
, 0, 5 * 1000 * 1000);
342 xhci_err(xhci
, "Stopped the command ring failed, "
343 "maybe the host is dead\n");
344 xhci
->xhc_state
|= XHCI_STATE_DYING
;
353 static int xhci_queue_cd(struct xhci_hcd
*xhci
,
354 struct xhci_command
*command
,
355 union xhci_trb
*cmd_trb
)
358 cd
= kzalloc(sizeof(struct xhci_cd
), GFP_ATOMIC
);
361 INIT_LIST_HEAD(&cd
->cancel_cmd_list
);
363 cd
->command
= command
;
364 cd
->cmd_trb
= cmd_trb
;
365 list_add_tail(&cd
->cancel_cmd_list
, &xhci
->cancel_cmd_list
);
371 * Cancel the command which has issue.
373 * Some commands may hang due to waiting for acknowledgement from
374 * usb device. It is outside of the xHC's ability to control and
375 * will cause the command ring is blocked. When it occurs software
376 * should intervene to recover the command ring.
377 * See Section 4.6.1.1 and 4.6.1.2
379 int xhci_cancel_cmd(struct xhci_hcd
*xhci
, struct xhci_command
*command
,
380 union xhci_trb
*cmd_trb
)
385 spin_lock_irqsave(&xhci
->lock
, flags
);
387 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
388 xhci_warn(xhci
, "Abort the command ring,"
389 " but the xHCI is dead.\n");
394 /* queue the cmd desriptor to cancel_cmd_list */
395 retval
= xhci_queue_cd(xhci
, command
, cmd_trb
);
397 xhci_warn(xhci
, "Queuing command descriptor failed.\n");
401 /* abort command ring */
402 retval
= xhci_abort_cmd_ring(xhci
);
404 xhci_err(xhci
, "Abort command ring failed\n");
405 if (unlikely(retval
== -ESHUTDOWN
)) {
406 spin_unlock_irqrestore(&xhci
->lock
, flags
);
407 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
408 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
414 spin_unlock_irqrestore(&xhci
->lock
, flags
);
418 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
419 unsigned int slot_id
,
420 unsigned int ep_index
,
421 unsigned int stream_id
)
423 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
424 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
425 unsigned int ep_state
= ep
->ep_state
;
427 /* Don't ring the doorbell for this endpoint if there are pending
428 * cancellations because we don't want to interrupt processing.
429 * We don't want to restart any stream rings if there's a set dequeue
430 * pointer command pending because the device can choose to start any
431 * stream once the endpoint is on the HW schedule.
432 * FIXME - check all the stream rings for pending cancellations.
434 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
435 (ep_state
& EP_HALTED
))
437 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
438 /* The CPU has better things to do at this point than wait for a
439 * write-posting flush. It'll get there soon enough.
443 /* Ring the doorbell for any rings with pending URBs */
444 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
445 unsigned int slot_id
,
446 unsigned int ep_index
)
448 unsigned int stream_id
;
449 struct xhci_virt_ep
*ep
;
451 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
453 /* A ring has pending URBs if its TD list is not empty */
454 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
455 if (ep
->ring
&& !(list_empty(&ep
->ring
->td_list
)))
456 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
460 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
462 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
463 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
464 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
470 * Find the segment that trb is in. Start searching in start_seg.
471 * If we must move past a segment that has a link TRB with a toggle cycle state
472 * bit set, then we will toggle the value pointed at by cycle_state.
474 static struct xhci_segment
*find_trb_seg(
475 struct xhci_segment
*start_seg
,
476 union xhci_trb
*trb
, int *cycle_state
)
478 struct xhci_segment
*cur_seg
= start_seg
;
479 struct xhci_generic_trb
*generic_trb
;
481 while (cur_seg
->trbs
> trb
||
482 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
483 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
484 if (generic_trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
))
486 cur_seg
= cur_seg
->next
;
487 if (cur_seg
== start_seg
)
488 /* Looped over the entire list. Oops! */
495 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
496 unsigned int slot_id
, unsigned int ep_index
,
497 unsigned int stream_id
)
499 struct xhci_virt_ep
*ep
;
501 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
502 /* Common case: no streams */
503 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
506 if (stream_id
== 0) {
508 "WARN: Slot ID %u, ep index %u has streams, "
509 "but URB has no stream ID.\n",
514 if (stream_id
< ep
->stream_info
->num_streams
)
515 return ep
->stream_info
->stream_rings
[stream_id
];
518 "WARN: Slot ID %u, ep index %u has "
519 "stream IDs 1 to %u allocated, "
520 "but stream ID %u is requested.\n",
522 ep
->stream_info
->num_streams
- 1,
527 /* Get the right ring for the given URB.
528 * If the endpoint supports streams, boundary check the URB's stream ID.
529 * If the endpoint doesn't support streams, return the singular endpoint ring.
531 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
534 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
535 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
539 * Move the xHC's endpoint ring dequeue pointer past cur_td.
540 * Record the new state of the xHC's endpoint ring dequeue segment,
541 * dequeue pointer, and new consumer cycle state in state.
542 * Update our internal representation of the ring's dequeue pointer.
544 * We do this in three jumps:
545 * - First we update our new ring state to be the same as when the xHC stopped.
546 * - Then we traverse the ring to find the segment that contains
547 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
548 * any link TRBs with the toggle cycle bit set.
549 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
550 * if we've moved it past a link TRB with the toggle cycle bit set.
552 * Some of the uses of xhci_generic_trb are grotty, but if they're done
553 * with correct __le32 accesses they should work fine. Only users of this are
556 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
557 unsigned int slot_id
, unsigned int ep_index
,
558 unsigned int stream_id
, struct xhci_td
*cur_td
,
559 struct xhci_dequeue_state
*state
)
561 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
562 struct xhci_ring
*ep_ring
;
563 struct xhci_generic_trb
*trb
;
564 struct xhci_ep_ctx
*ep_ctx
;
567 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
568 ep_index
, stream_id
);
570 xhci_warn(xhci
, "WARN can't find new dequeue state "
571 "for invalid stream ID %u.\n",
575 state
->new_cycle_state
= 0;
576 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
577 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
578 dev
->eps
[ep_index
].stopped_trb
,
579 &state
->new_cycle_state
);
580 if (!state
->new_deq_seg
) {
585 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
586 xhci_dbg(xhci
, "Finding endpoint context\n");
587 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
588 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
590 state
->new_deq_ptr
= cur_td
->last_trb
;
591 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
592 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
594 &state
->new_cycle_state
);
595 if (!state
->new_deq_seg
) {
600 trb
= &state
->new_deq_ptr
->generic
;
601 if (TRB_TYPE_LINK_LE32(trb
->field
[3]) &&
602 (trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
)))
603 state
->new_cycle_state
^= 0x1;
604 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
607 * If there is only one segment in a ring, find_trb_seg()'s while loop
608 * will not run, and it will return before it has a chance to see if it
609 * needs to toggle the cycle bit. It can't tell if the stalled transfer
610 * ended just before the link TRB on a one-segment ring, or if the TD
611 * wrapped around the top of the ring, because it doesn't have the TD in
612 * question. Look for the one-segment case where stalled TRB's address
613 * is greater than the new dequeue pointer address.
615 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
616 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
617 state
->new_cycle_state
^= 0x1;
618 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
620 /* Don't update the ring cycle state for the producer (us). */
621 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
623 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
624 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
625 (unsigned long long) addr
);
628 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
629 * (The last TRB actually points to the ring enqueue pointer, which is not part
630 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
632 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
633 struct xhci_td
*cur_td
, bool flip_cycle
)
635 struct xhci_segment
*cur_seg
;
636 union xhci_trb
*cur_trb
;
638 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
640 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
641 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
642 /* Unchain any chained Link TRBs, but
643 * leave the pointers intact.
645 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
646 /* Flip the cycle bit (link TRBs can't be the first
650 cur_trb
->generic
.field
[3] ^=
651 cpu_to_le32(TRB_CYCLE
);
652 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
653 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
654 "in seg %p (0x%llx dma)\n",
656 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
658 (unsigned long long)cur_seg
->dma
);
660 cur_trb
->generic
.field
[0] = 0;
661 cur_trb
->generic
.field
[1] = 0;
662 cur_trb
->generic
.field
[2] = 0;
663 /* Preserve only the cycle bit of this TRB */
664 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
665 /* Flip the cycle bit except on the first or last TRB */
666 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
667 cur_trb
!= cur_td
->last_trb
)
668 cur_trb
->generic
.field
[3] ^=
669 cpu_to_le32(TRB_CYCLE
);
670 cur_trb
->generic
.field
[3] |= cpu_to_le32(
671 TRB_TYPE(TRB_TR_NOOP
));
672 xhci_dbg(xhci
, "TRB to noop at offset 0x%llx\n",
674 xhci_trb_virt_to_dma(cur_seg
, cur_trb
));
676 if (cur_trb
== cur_td
->last_trb
)
681 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
682 unsigned int ep_index
, unsigned int stream_id
,
683 struct xhci_segment
*deq_seg
,
684 union xhci_trb
*deq_ptr
, u32 cycle_state
);
686 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
687 unsigned int slot_id
, unsigned int ep_index
,
688 unsigned int stream_id
,
689 struct xhci_dequeue_state
*deq_state
)
691 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
693 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
694 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
695 deq_state
->new_deq_seg
,
696 (unsigned long long)deq_state
->new_deq_seg
->dma
,
697 deq_state
->new_deq_ptr
,
698 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
699 deq_state
->new_cycle_state
);
700 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
701 deq_state
->new_deq_seg
,
702 deq_state
->new_deq_ptr
,
703 (u32
) deq_state
->new_cycle_state
);
704 /* Stop the TD queueing code from ringing the doorbell until
705 * this command completes. The HC won't set the dequeue pointer
706 * if the ring is running, and ringing the doorbell starts the
709 ep
->ep_state
|= SET_DEQ_PENDING
;
712 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
713 struct xhci_virt_ep
*ep
)
715 ep
->ep_state
&= ~EP_HALT_PENDING
;
716 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
717 * timer is running on another CPU, we don't decrement stop_cmds_pending
718 * (since we didn't successfully stop the watchdog timer).
720 if (del_timer(&ep
->stop_cmd_timer
))
721 ep
->stop_cmds_pending
--;
724 /* Must be called with xhci->lock held in interrupt context */
725 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
726 struct xhci_td
*cur_td
, int status
, char *adjective
)
730 struct urb_priv
*urb_priv
;
733 urb_priv
= urb
->hcpriv
;
735 hcd
= bus_to_hcd(urb
->dev
->bus
);
737 /* Only giveback urb when this is the last td in urb */
738 if (urb_priv
->td_cnt
== urb_priv
->length
) {
739 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
740 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
741 #ifndef CONFIG_MTK_XHCI
742 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
743 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
744 usb_amd_quirk_pll_enable();
748 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
750 spin_unlock(&xhci
->lock
);
751 usb_hcd_giveback_urb(hcd
, urb
, status
);
752 xhci_urb_free_priv(xhci
, urb_priv
);
753 spin_lock(&xhci
->lock
);
758 * When we get a command completion for a Stop Endpoint Command, we need to
759 * unlink any cancelled TDs from the ring. There are two ways to do that:
761 * 1. If the HW was in the middle of processing the TD that needs to be
762 * cancelled, then we must move the ring's dequeue pointer past the last TRB
763 * in the TD with a Set Dequeue Pointer Command.
764 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
765 * bit cleared) so that the HW will skip over them.
767 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
768 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
770 unsigned int slot_id
;
771 unsigned int ep_index
;
772 struct xhci_virt_device
*virt_dev
;
773 struct xhci_ring
*ep_ring
;
774 struct xhci_virt_ep
*ep
;
775 struct list_head
*entry
;
776 struct xhci_td
*cur_td
= NULL
;
777 struct xhci_td
*last_unlinked_td
;
779 struct xhci_dequeue_state deq_state
;
781 if (unlikely(TRB_TO_SUSPEND_PORT(
782 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
783 slot_id
= TRB_TO_SLOT_ID(
784 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
785 virt_dev
= xhci
->devs
[slot_id
];
787 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
790 xhci_warn(xhci
, "Stop endpoint command "
791 "completion for disabled slot %u\n",
796 memset(&deq_state
, 0, sizeof(deq_state
));
797 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
798 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
799 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
801 if (list_empty(&ep
->cancelled_td_list
)) {
802 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
803 ep
->stopped_td
= NULL
;
804 ep
->stopped_trb
= NULL
;
805 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
809 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
810 * We have the xHCI lock, so nothing can modify this list until we drop
811 * it. We're also in the event handler, so we can't get re-interrupted
812 * if another Stop Endpoint command completes
814 list_for_each(entry
, &ep
->cancelled_td_list
) {
815 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
816 xhci_dbg(xhci
, "Removing canceled TD starting at 0x%llx (dma).\n",
817 (unsigned long long)xhci_trb_virt_to_dma(
818 cur_td
->start_seg
, cur_td
->first_trb
));
819 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
821 /* This shouldn't happen unless a driver is mucking
822 * with the stream ID after submission. This will
823 * leave the TD on the hardware ring, and the hardware
824 * will try to execute it, and may access a buffer
825 * that has already been freed. In the best case, the
826 * hardware will execute it, and the event handler will
827 * ignore the completion event for that TD, since it was
828 * removed from the td_list for that endpoint. In
829 * short, don't muck with the stream ID after
832 xhci_warn(xhci
, "WARN Cancelled URB %p "
833 "has invalid stream ID %u.\n",
835 cur_td
->urb
->stream_id
);
836 goto remove_finished_td
;
839 * If we stopped on the TD we need to cancel, then we have to
840 * move the xHC endpoint ring dequeue pointer past this TD.
842 if (cur_td
== ep
->stopped_td
)
843 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
844 cur_td
->urb
->stream_id
,
847 td_to_noop(xhci
, ep_ring
, cur_td
, false);
850 * The event handler won't see a completion for this TD anymore,
851 * so remove it from the endpoint ring's TD list. Keep it in
852 * the cancelled TD list for URB completion later.
854 list_del_init(&cur_td
->td_list
);
856 last_unlinked_td
= cur_td
;
857 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
859 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
860 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
861 xhci_queue_new_dequeue_state(xhci
,
863 ep
->stopped_td
->urb
->stream_id
,
865 xhci_ring_cmd_db(xhci
);
867 /* Otherwise ring the doorbell(s) to restart queued transfers */
868 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
871 /* Clear stopped_td and stopped_trb if endpoint is not halted */
872 if (!(ep
->ep_state
& EP_HALTED
)) {
873 ep
->stopped_td
= NULL
;
874 ep
->stopped_trb
= NULL
;
878 * Drop the lock and complete the URBs in the cancelled TD list.
879 * New TDs to be cancelled might be added to the end of the list before
880 * we can complete all the URBs for the TDs we already unlinked.
881 * So stop when we've completed the URB for the last TD we unlinked.
884 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
885 struct xhci_td
, cancelled_td_list
);
886 list_del_init(&cur_td
->cancelled_td_list
);
888 /* Clean up the cancelled URB */
889 /* Doesn't matter what we pass for status, since the core will
890 * just overwrite it (because the URB has been unlinked).
892 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
894 /* Stop processing the cancelled list if the watchdog timer is
897 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
899 } while (cur_td
!= last_unlinked_td
);
901 /* Return to the event handler with xhci->lock re-acquired */
904 /* Watchdog timer function for when a stop endpoint command fails to complete.
905 * In this case, we assume the host controller is broken or dying or dead. The
906 * host may still be completing some other events, so we have to be careful to
907 * let the event ring handler and the URB dequeueing/enqueueing functions know
908 * through xhci->state.
910 * The timer may also fire if the host takes a very long time to respond to the
911 * command, and the stop endpoint command completion handler cannot delete the
912 * timer before the timer function is called. Another endpoint cancellation may
913 * sneak in before the timer function can grab the lock, and that may queue
914 * another stop endpoint command and add the timer back. So we cannot use a
915 * simple flag to say whether there is a pending stop endpoint command for a
916 * particular endpoint.
918 * Instead we use a combination of that flag and a counter for the number of
919 * pending stop endpoint commands. If the timer is the tail end of the last
920 * stop endpoint command, and the endpoint's command is still pending, we assume
923 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
925 struct xhci_hcd
*xhci
;
926 struct xhci_virt_ep
*ep
;
927 struct xhci_virt_ep
*temp_ep
;
928 struct xhci_ring
*ring
;
929 struct xhci_td
*cur_td
;
933 ep
= (struct xhci_virt_ep
*) arg
;
936 spin_lock_irqsave(&xhci
->lock
, flags
);
938 ep
->stop_cmds_pending
--;
939 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
940 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
941 "xHCI as DYING, exiting.\n");
942 spin_unlock_irqrestore(&xhci
->lock
, flags
);
945 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
946 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
948 spin_unlock_irqrestore(&xhci
->lock
, flags
);
952 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
953 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
954 /* Oops, HC is dead or dying or at least not responding to the stop
957 xhci
->xhc_state
|= XHCI_STATE_DYING
;
958 /* Disable interrupts from the host controller and start halting it */
960 spin_unlock_irqrestore(&xhci
->lock
, flags
);
962 ret
= xhci_halt(xhci
);
964 spin_lock_irqsave(&xhci
->lock
, flags
);
966 /* This is bad; the host is not responding to commands and it's
967 * not allowing itself to be halted. At least interrupts are
968 * disabled. If we call usb_hc_died(), it will attempt to
969 * disconnect all device drivers under this host. Those
970 * disconnect() methods will wait for all URBs to be unlinked,
971 * so we must complete them.
973 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
974 xhci_warn(xhci
, "Completing active URBs anyway.\n");
975 /* We could turn all TDs on the rings to no-ops. This won't
976 * help if the host has cached part of the ring, and is slow if
977 * we want to preserve the cycle bit. Skip it and hope the host
978 * doesn't touch the memory.
981 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
984 for (j
= 0; j
< 31; j
++) {
985 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
986 ring
= temp_ep
->ring
;
989 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
990 "ep index %u\n", i
, j
);
991 while (!list_empty(&ring
->td_list
)) {
992 cur_td
= list_first_entry(&ring
->td_list
,
995 list_del_init(&cur_td
->td_list
);
996 if (!list_empty(&cur_td
->cancelled_td_list
))
997 list_del_init(&cur_td
->cancelled_td_list
);
998 xhci_giveback_urb_in_irq(xhci
, cur_td
,
999 -ESHUTDOWN
, "killed");
1001 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
1002 cur_td
= list_first_entry(
1003 &temp_ep
->cancelled_td_list
,
1006 list_del_init(&cur_td
->cancelled_td_list
);
1007 xhci_giveback_urb_in_irq(xhci
, cur_td
,
1008 -ESHUTDOWN
, "killed");
1012 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1013 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
1014 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
1015 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
1019 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
1020 struct xhci_virt_device
*dev
,
1021 struct xhci_ring
*ep_ring
,
1022 unsigned int ep_index
)
1024 union xhci_trb
*dequeue_temp
;
1025 int num_trbs_free_temp
;
1026 bool revert
= false;
1028 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
1029 dequeue_temp
= ep_ring
->dequeue
;
1031 /* If we get two back-to-back stalls, and the first stalled transfer
1032 * ends just before a link TRB, the dequeue pointer will be left on
1033 * the link TRB by the code in the while loop. So we have to update
1034 * the dequeue pointer one segment further, or we'll jump off
1035 * the segment into la-la-land.
1037 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
, ep_ring
->dequeue
)) {
1038 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1039 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1042 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
1043 /* We have more usable TRBs */
1044 ep_ring
->num_trbs_free
++;
1046 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
,
1047 ep_ring
->dequeue
)) {
1048 if (ep_ring
->dequeue
==
1049 dev
->eps
[ep_index
].queued_deq_ptr
)
1051 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1052 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1054 if (ep_ring
->dequeue
== dequeue_temp
) {
1061 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
1062 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
1067 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1068 * we need to clear the set deq pending flag in the endpoint ring state, so that
1069 * the TD queueing code can ring the doorbell again. We also need to ring the
1070 * endpoint doorbell to restart the ring, but only if there aren't more
1071 * cancellations pending.
1073 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
1074 struct xhci_event_cmd
*event
,
1075 union xhci_trb
*trb
)
1077 unsigned int slot_id
;
1078 unsigned int ep_index
;
1079 unsigned int stream_id
;
1080 struct xhci_ring
*ep_ring
;
1081 struct xhci_virt_device
*dev
;
1082 struct xhci_ep_ctx
*ep_ctx
;
1083 struct xhci_slot_ctx
*slot_ctx
;
1085 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1086 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1087 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
1088 dev
= xhci
->devs
[slot_id
];
1090 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
1092 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
1093 "freed stream ID %u\n",
1095 /* XXX: Harmless??? */
1096 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1100 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
1101 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
1103 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
1104 unsigned int ep_state
;
1105 unsigned int slot_state
;
1107 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
1109 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
1110 "of stream ID configuration\n");
1112 case COMP_CTX_STATE
:
1113 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
1114 "to incorrect slot or ep state.\n");
1115 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
1116 ep_state
&= EP_STATE_MASK
;
1117 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
1118 slot_state
= GET_SLOT_STATE(slot_state
);
1119 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
1120 slot_state
, ep_state
);
1123 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
1124 "slot %u was not enabled.\n", slot_id
);
1127 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
1128 "completion code of %u.\n",
1129 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1132 /* OK what do we do now? The endpoint state is hosed, and we
1133 * should never get to this point if the synchronization between
1134 * queueing, and endpoint state are correct. This might happen
1135 * if the device gets disconnected after we've finished
1136 * cancelling URBs, which might not be an error...
1139 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1140 le64_to_cpu(ep_ctx
->deq
));
1141 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
1142 dev
->eps
[ep_index
].queued_deq_ptr
) ==
1143 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
1144 /* Update the ring's dequeue segment and dequeue pointer
1145 * to reflect the new position.
1147 update_ring_for_set_deq_completion(xhci
, dev
,
1150 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
1151 "Ptr command & xHCI internal state.\n");
1152 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1153 dev
->eps
[ep_index
].queued_deq_seg
,
1154 dev
->eps
[ep_index
].queued_deq_ptr
);
1158 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1159 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1160 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1161 /* Restart any rings with pending URBs */
1162 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1165 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1166 struct xhci_event_cmd
*event
,
1167 union xhci_trb
*trb
)
1170 unsigned int ep_index
;
1172 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1173 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1174 /* This command will only fail if the endpoint wasn't halted,
1175 * but we don't care.
1177 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1178 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1180 /* HW with the reset endpoint quirk needs to have a configure endpoint
1181 * command complete before the endpoint can be used. Queue that here
1182 * because the HW can't handle two commands being queued in a row.
1184 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1185 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1186 xhci_queue_configure_endpoint(xhci
,
1187 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1189 xhci_ring_cmd_db(xhci
);
1191 /* Clear our internal halted state */
1192 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1196 /* Complete the command and detele it from the devcie's command queue.
1198 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1199 struct xhci_command
*command
, u32 status
)
1201 command
->status
= status
;
1202 list_del(&command
->cmd_list
);
1203 if (command
->completion
)
1204 complete(command
->completion
);
1206 xhci_free_command(xhci
, command
);
1210 /* Check to see if a command in the device's command queue matches this one.
1211 * Signal the completion or free the command, and return 1. Return 0 if the
1212 * completed command isn't at the head of the command list.
1214 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1215 struct xhci_virt_device
*virt_dev
,
1216 struct xhci_event_cmd
*event
)
1218 struct xhci_command
*command
;
1220 if (list_empty(&virt_dev
->cmd_list
))
1223 command
= list_entry(virt_dev
->cmd_list
.next
,
1224 struct xhci_command
, cmd_list
);
1225 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1228 xhci_complete_cmd_in_cmd_wait_list(xhci
, command
,
1229 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1234 * Finding the command trb need to be cancelled and modifying it to
1235 * NO OP command. And if the command is in device's command wait
1236 * list, finishing and freeing it.
1238 * If we can't find the command trb, we think it had already been
1241 static void xhci_cmd_to_noop(struct xhci_hcd
*xhci
, struct xhci_cd
*cur_cd
)
1243 struct xhci_segment
*cur_seg
;
1244 union xhci_trb
*cmd_trb
;
1247 if (xhci
->cmd_ring
->dequeue
== xhci
->cmd_ring
->enqueue
)
1250 /* find the current segment of command ring */
1251 cur_seg
= find_trb_seg(xhci
->cmd_ring
->first_seg
,
1252 xhci
->cmd_ring
->dequeue
, &cycle_state
);
1255 xhci_warn(xhci
, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1256 xhci
->cmd_ring
->dequeue
,
1257 (unsigned long long)
1258 xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1259 xhci
->cmd_ring
->dequeue
));
1260 xhci_debug_ring(xhci
, xhci
->cmd_ring
);
1261 xhci_dbg_ring_ptrs(xhci
, xhci
->cmd_ring
);
1265 /* find the command trb matched by cd from command ring */
1266 for (cmd_trb
= xhci
->cmd_ring
->dequeue
;
1267 cmd_trb
!= xhci
->cmd_ring
->enqueue
;
1268 next_trb(xhci
, xhci
->cmd_ring
, &cur_seg
, &cmd_trb
)) {
1269 /* If the trb is link trb, continue */
1270 if (TRB_TYPE_LINK_LE32(cmd_trb
->generic
.field
[3]))
1273 if (cur_cd
->cmd_trb
== cmd_trb
) {
1275 /* If the command in device's command list, we should
1276 * finish it and free the command structure.
1278 if (cur_cd
->command
)
1279 xhci_complete_cmd_in_cmd_wait_list(xhci
,
1280 cur_cd
->command
, COMP_CMD_STOP
);
1282 /* get cycle state from the origin command trb */
1283 cycle_state
= le32_to_cpu(cmd_trb
->generic
.field
[3])
1286 /* modify the command trb to NO OP command */
1287 cmd_trb
->generic
.field
[0] = 0;
1288 cmd_trb
->generic
.field
[1] = 0;
1289 cmd_trb
->generic
.field
[2] = 0;
1290 cmd_trb
->generic
.field
[3] = cpu_to_le32(
1291 TRB_TYPE(TRB_CMD_NOOP
) | cycle_state
);
1297 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd
*xhci
)
1299 struct xhci_cd
*cur_cd
, *next_cd
;
1301 if (list_empty(&xhci
->cancel_cmd_list
))
1304 list_for_each_entry_safe(cur_cd
, next_cd
,
1305 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1306 xhci_cmd_to_noop(xhci
, cur_cd
);
1307 list_del(&cur_cd
->cancel_cmd_list
);
1313 * traversing the cancel_cmd_list. If the command descriptor according
1314 * to cmd_trb is found, the function free it and return 1, otherwise
1317 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd
*xhci
,
1318 union xhci_trb
*cmd_trb
)
1320 struct xhci_cd
*cur_cd
, *next_cd
;
1322 if (list_empty(&xhci
->cancel_cmd_list
))
1325 list_for_each_entry_safe(cur_cd
, next_cd
,
1326 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1327 if (cur_cd
->cmd_trb
== cmd_trb
) {
1328 if (cur_cd
->command
)
1329 xhci_complete_cmd_in_cmd_wait_list(xhci
,
1330 cur_cd
->command
, COMP_CMD_STOP
);
1331 list_del(&cur_cd
->cancel_cmd_list
);
1341 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1342 * trb pointed by the command ring dequeue pointer is the trb we want to
1343 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1344 * traverse the cancel_cmd_list to trun the all of the commands according
1345 * to command descriptor to NO-OP trb.
1347 static int handle_stopped_cmd_ring(struct xhci_hcd
*xhci
,
1348 int cmd_trb_comp_code
)
1350 int cur_trb_is_good
= 0;
1352 /* Searching the cmd trb pointed by the command ring dequeue
1353 * pointer in command descriptor list. If it is found, free it.
1355 cur_trb_is_good
= xhci_search_cmd_trb_in_cd_list(xhci
,
1356 xhci
->cmd_ring
->dequeue
);
1358 if (cmd_trb_comp_code
== COMP_CMD_ABORT
)
1359 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
1360 else if (cmd_trb_comp_code
== COMP_CMD_STOP
) {
1361 /* traversing the cancel_cmd_list and canceling
1362 * the command according to command descriptor
1364 xhci_cancel_cmd_in_cd_list(xhci
);
1366 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
1368 * ring command ring doorbell again to restart the
1371 if (xhci
->cmd_ring
->dequeue
!= xhci
->cmd_ring
->enqueue
)
1372 xhci_ring_cmd_db(xhci
);
1374 return cur_trb_is_good
;
1377 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1378 struct xhci_event_cmd
*event
)
1380 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1382 dma_addr_t cmd_dequeue_dma
;
1383 struct xhci_input_control_ctx
*ctrl_ctx
;
1384 struct xhci_virt_device
*virt_dev
;
1385 unsigned int ep_index
;
1386 struct xhci_ring
*ep_ring
;
1387 unsigned int ep_state
;
1389 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1390 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1391 xhci
->cmd_ring
->dequeue
);
1392 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1393 if (cmd_dequeue_dma
== 0) {
1394 xhci
->error_bitmask
|= 1 << 4;
1397 /* Does the DMA address match our internal dequeue pointer address? */
1398 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1399 xhci
->error_bitmask
|= 1 << 5;
1403 if ((GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_CMD_ABORT
) ||
1404 (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_CMD_STOP
)) {
1405 /* If the return value is 0, we think the trb pointed by
1406 * command ring dequeue pointer is a good trb. The good
1407 * trb means we don't want to cancel the trb, but it have
1408 * been stopped by host. So we should handle it normally.
1409 * Otherwise, driver should invoke inc_deq() and return.
1411 if (handle_stopped_cmd_ring(xhci
,
1412 GET_COMP_CODE(le32_to_cpu(event
->status
)))) {
1413 inc_deq(xhci
, xhci
->cmd_ring
);
1416 /* There is no command to handle if we get a stop event when the
1417 * command ring is empty, event->cmd_trb points to the next
1420 if (xhci
->cmd_ring
->dequeue
== xhci
->cmd_ring
->enqueue
)
1424 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1425 & TRB_TYPE_BITMASK
) {
1426 case TRB_TYPE(TRB_ENABLE_SLOT
):
1427 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1428 xhci
->slot_id
= slot_id
;
1431 complete(&xhci
->addr_dev
);
1433 case TRB_TYPE(TRB_DISABLE_SLOT
):
1434 if (xhci
->devs
[slot_id
]) {
1435 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1436 /* Delete default control endpoint resources */
1437 xhci_free_device_endpoint_resources(xhci
,
1438 xhci
->devs
[slot_id
], true);
1439 xhci_free_virt_device(xhci
, slot_id
);
1442 case TRB_TYPE(TRB_CONFIG_EP
):
1443 virt_dev
= xhci
->devs
[slot_id
];
1444 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1447 * Configure endpoint commands can come from the USB core
1448 * configuration or alt setting changes, or because the HW
1449 * needed an extra configure endpoint command after a reset
1450 * endpoint command or streams were being configured.
1451 * If the command was for a halted endpoint, the xHCI driver
1452 * is not waiting on the configure endpoint command.
1454 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1456 /* Input ctx add_flags are the endpoint index plus one */
1457 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1458 /* A usb_set_interface() call directly after clearing a halted
1459 * condition may race on this quirky hardware. Not worth
1460 * worrying about, since this is prototype hardware. Not sure
1461 * if this will work for streams, but streams support was
1462 * untested on this prototype.
1464 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1465 ep_index
!= (unsigned int) -1 &&
1466 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1467 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1468 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1469 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1470 if (!(ep_state
& EP_HALTED
))
1471 goto bandwidth_change
;
1472 xhci_dbg(xhci
, "Completed config ep cmd - "
1473 "last ep index = %d, state = %d\n",
1474 ep_index
, ep_state
);
1475 /* Clear internal halted state and restart ring(s) */
1476 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1478 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1482 xhci_dbg(xhci
, "Completed config ep cmd\n");
1483 xhci
->devs
[slot_id
]->cmd_status
=
1484 GET_COMP_CODE(le32_to_cpu(event
->status
));
1485 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1487 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1488 virt_dev
= xhci
->devs
[slot_id
];
1489 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1491 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1492 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1494 case TRB_TYPE(TRB_ADDR_DEV
):
1495 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1496 complete(&xhci
->addr_dev
);
1498 case TRB_TYPE(TRB_STOP_RING
):
1499 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1501 case TRB_TYPE(TRB_SET_DEQ
):
1502 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1504 case TRB_TYPE(TRB_CMD_NOOP
):
1506 case TRB_TYPE(TRB_RESET_EP
):
1507 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1509 case TRB_TYPE(TRB_RESET_DEV
):
1510 xhci_dbg(xhci
, "Completed reset device command.\n");
1511 slot_id
= TRB_TO_SLOT_ID(
1512 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1513 virt_dev
= xhci
->devs
[slot_id
];
1515 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1517 xhci_warn(xhci
, "Reset device command completion "
1518 "for disabled slot %u\n", slot_id
);
1520 case TRB_TYPE(TRB_NEC_GET_FW
):
1521 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1522 xhci
->error_bitmask
|= 1 << 6;
1525 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1526 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1527 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1530 /* Skip over unknown commands on the event ring */
1531 xhci
->error_bitmask
|= 1 << 6;
1534 inc_deq(xhci
, xhci
->cmd_ring
);
1537 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1538 union xhci_trb
*event
)
1542 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1543 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1544 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1545 handle_cmd_completion(xhci
, &event
->event_cmd
);
1548 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1549 * port registers -- USB 3.0 and USB 2.0).
1551 * Returns a zero-based port number, which is suitable for indexing into each of
1552 * the split roothubs' port arrays and bus state arrays.
1553 * Add one to it in order to call xhci_find_slot_id_by_port.
1555 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1556 struct xhci_hcd
*xhci
, u32 port_id
)
1559 unsigned int num_similar_speed_ports
= 0;
1561 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1562 * and usb2_ports are 0-based indexes. Count the number of similar
1563 * speed ports, up to 1 port before this port.
1565 for (i
= 0; i
< (port_id
- 1); i
++) {
1566 u8 port_speed
= xhci
->port_array
[i
];
1569 * Skip ports that don't have known speeds, or have duplicate
1570 * Extended Capabilities port speed entries.
1572 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1576 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1577 * 1.1 ports are under the USB 2.0 hub. If the port speed
1578 * matches the device speed, it's a similar speed port.
1580 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1581 num_similar_speed_ports
++;
1583 return num_similar_speed_ports
;
1586 static void handle_device_notification(struct xhci_hcd
*xhci
,
1587 union xhci_trb
*event
)
1590 struct usb_device
*udev
;
1592 slot_id
= TRB_TO_SLOT_ID(event
->generic
.field
[3]);
1593 if (!xhci
->devs
[slot_id
]) {
1594 xhci_warn(xhci
, "Device Notification event for "
1595 "unused slot %u\n", slot_id
);
1599 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1601 udev
= xhci
->devs
[slot_id
]->udev
;
1602 if (udev
&& udev
->parent
)
1603 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1606 static void handle_port_status(struct xhci_hcd
*xhci
,
1607 union xhci_trb
*event
)
1609 struct usb_hcd
*hcd
;
1614 unsigned int faked_port_index
;
1616 struct xhci_bus_state
*bus_state
;
1617 __le32 __iomem
**port_array
;
1618 bool bogus_port_status
= false;
1620 /* Port status change events always have a successful completion code */
1621 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1622 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1623 xhci
->error_bitmask
|= 1 << 8;
1625 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1626 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1628 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1629 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1630 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1631 inc_deq(xhci
, xhci
->event_ring
);
1635 /* Figure out which usb_hcd this port is attached to:
1636 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1638 major_revision
= xhci
->port_array
[port_id
- 1];
1640 /* Find the right roothub. */
1641 hcd
= xhci_to_hcd(xhci
);
1642 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1643 hcd
= xhci
->shared_hcd
;
1645 if (major_revision
== 0) {
1646 xhci_warn(xhci
, "Event for port %u not in "
1647 "Extended Capabilities, ignoring.\n",
1649 bogus_port_status
= true;
1652 if (major_revision
== DUPLICATE_ENTRY
) {
1653 xhci_warn(xhci
, "Event for port %u duplicated in"
1654 "Extended Capabilities, ignoring.\n",
1656 bogus_port_status
= true;
1661 * Hardware port IDs reported by a Port Status Change Event include USB
1662 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1663 * resume event, but we first need to translate the hardware port ID
1664 * into the index into the ports on the correct split roothub, and the
1665 * correct bus_state structure.
1667 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1668 if (hcd
->speed
== HCD_USB3
)
1669 port_array
= xhci
->usb3_ports
;
1671 port_array
= xhci
->usb2_ports
;
1672 /* Find the faked port hub number */
1673 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1676 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1677 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1678 xhci_dbg(xhci
, "resume root hub\n");
1679 usb_hcd_resume_root_hub(hcd
);
1682 if (hcd
->speed
== HCD_USB3
&& (temp
& PORT_PLS_MASK
) == XDEV_INACTIVE
)
1683 bus_state
->port_remote_wakeup
&= ~(1 << faked_port_index
);
1685 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1686 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1688 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1689 if (!(temp1
& CMD_RUN
)) {
1690 xhci_warn(xhci
, "xHC is not running.\n");
1694 if (DEV_SUPERSPEED(temp
)) {
1695 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1696 /* Set a flag to say the port signaled remote wakeup,
1697 * so we can tell the difference between the end of
1698 * device and host initiated resume.
1700 bus_state
->port_remote_wakeup
|= 1 << faked_port_index
;
1701 xhci_test_and_clear_bit(xhci
, port_array
,
1702 faked_port_index
, PORT_PLC
);
1703 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1705 /* Need to wait until the next link state change
1706 * indicates the device is actually in U0.
1708 bogus_port_status
= true;
1711 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1712 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1713 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
1714 set_bit(faked_port_index
, &bus_state
->resuming_ports
);
1715 mod_timer(&hcd
->rh_timer
,
1716 bus_state
->resume_done
[faked_port_index
]);
1717 /* Do the rest in GetPortStatus */
1721 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_U0
&&
1722 DEV_SUPERSPEED(temp
)) {
1723 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1724 /* We've just brought the device into U0 through either the
1725 * Resume state after a device remote wakeup, or through the
1726 * U3Exit state after a host-initiated resume. If it's a device
1727 * initiated remote wake, don't pass up the link state change,
1728 * so the roothub behavior is consistent with external
1729 * USB 3.0 hub behavior.
1731 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1732 faked_port_index
+ 1);
1733 if (slot_id
&& xhci
->devs
[slot_id
])
1734 xhci_ring_device(xhci
, slot_id
);
1735 if (bus_state
->port_remote_wakeup
& (1 << faked_port_index
)) {
1736 bus_state
->port_remote_wakeup
&=
1737 ~(1 << faked_port_index
);
1738 xhci_test_and_clear_bit(xhci
, port_array
,
1739 faked_port_index
, PORT_PLC
);
1740 usb_wakeup_notification(hcd
->self
.root_hub
,
1741 faked_port_index
+ 1);
1742 bogus_port_status
= true;
1747 if (hcd
->speed
!= HCD_USB3
)
1748 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1752 /* Update event ring dequeue pointer before dropping the lock */
1753 inc_deq(xhci
, xhci
->event_ring
);
1755 /* Don't make the USB core poll the roothub if we got a bad port status
1756 * change event. Besides, at that point we can't tell which roothub
1757 * (USB 2.0 or USB 3.0) to kick.
1759 if (bogus_port_status
)
1763 * xHCI port-status-change events occur when the "or" of all the
1764 * status-change bits in the portsc register changes from 0 to 1.
1765 * New status changes won't cause an event if any other change
1766 * bits are still set. When an event occurs, switch over to
1767 * polling to avoid losing status changes.
1769 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1770 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1771 spin_unlock(&xhci
->lock
);
1772 /* Pass this up to the core */
1773 usb_hcd_poll_rh_status(hcd
);
1774 spin_lock(&xhci
->lock
);
1778 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1779 * at end_trb, which may be in another segment. If the suspect DMA address is a
1780 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1783 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1784 union xhci_trb
*start_trb
,
1785 union xhci_trb
*end_trb
,
1786 dma_addr_t suspect_dma
)
1788 dma_addr_t start_dma
;
1789 dma_addr_t end_seg_dma
;
1790 dma_addr_t end_trb_dma
;
1791 struct xhci_segment
*cur_seg
;
1793 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1794 cur_seg
= start_seg
;
1799 /* We may get an event for a Link TRB in the middle of a TD */
1800 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1801 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1802 /* If the end TRB isn't in this segment, this is set to 0 */
1803 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1805 if (end_trb_dma
> 0) {
1806 /* The end TRB is in this segment, so suspect should be here */
1807 if (start_dma
<= end_trb_dma
) {
1808 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1811 /* Case for one segment with
1812 * a TD wrapped around to the top
1814 if ((suspect_dma
>= start_dma
&&
1815 suspect_dma
<= end_seg_dma
) ||
1816 (suspect_dma
>= cur_seg
->dma
&&
1817 suspect_dma
<= end_trb_dma
))
1822 /* Might still be somewhere in this segment */
1823 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1826 cur_seg
= cur_seg
->next
;
1827 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1828 } while (cur_seg
!= start_seg
);
1833 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1834 unsigned int slot_id
, unsigned int ep_index
,
1835 unsigned int stream_id
,
1836 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1838 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1839 ep
->ep_state
|= EP_HALTED
;
1840 ep
->stopped_td
= td
;
1841 ep
->stopped_trb
= event_trb
;
1842 ep
->stopped_stream
= stream_id
;
1844 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1845 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1847 ep
->stopped_td
= NULL
;
1848 ep
->stopped_trb
= NULL
;
1849 ep
->stopped_stream
= 0;
1851 xhci_ring_cmd_db(xhci
);
1854 /* Check if an error has halted the endpoint ring. The class driver will
1855 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1856 * However, a babble and other errors also halt the endpoint ring, and the class
1857 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1858 * Ring Dequeue Pointer command manually.
1860 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1861 struct xhci_ep_ctx
*ep_ctx
,
1862 unsigned int trb_comp_code
)
1864 /* TRB completion codes that may require a manual halt cleanup */
1865 if (trb_comp_code
== COMP_TX_ERR
||
1866 trb_comp_code
== COMP_BABBLE
||
1867 trb_comp_code
== COMP_SPLIT_ERR
)
1868 /* The 0.96 spec says a babbling control endpoint
1869 * is not halted. The 0.96 spec says it is. Some HW
1870 * claims to be 0.95 compliant, but it halts the control
1871 * endpoint anyway. Check if a babble halted the
1874 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1875 cpu_to_le32(EP_STATE_HALTED
))
1881 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1883 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1884 /* Vendor defined "informational" completion code,
1885 * treat as not-an-error.
1887 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1889 xhci_dbg(xhci
, "Treating code as success.\n");
1896 * Finish the td processing, remove the td from td list;
1897 * Return 1 if the urb can be given back.
1899 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1900 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1901 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1903 struct xhci_virt_device
*xdev
;
1904 struct xhci_ring
*ep_ring
;
1905 unsigned int slot_id
;
1907 struct urb
*urb
= NULL
;
1908 struct xhci_ep_ctx
*ep_ctx
;
1910 struct urb_priv
*urb_priv
;
1913 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1914 xdev
= xhci
->devs
[slot_id
];
1915 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1916 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1917 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1918 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1923 if (trb_comp_code
== COMP_STOP_INVAL
||
1924 trb_comp_code
== COMP_STOP
) {
1925 /* The Endpoint Stop Command completion will take care of any
1926 * stopped TDs. A stopped TD may be restarted, so don't update
1927 * the ring dequeue pointer or take this TD off any lists yet.
1929 ep
->stopped_td
= td
;
1930 ep
->stopped_trb
= event_trb
;
1933 if (trb_comp_code
== COMP_STALL
) {
1934 /* The transfer is completed from the driver's
1935 * perspective, but we need to issue a set dequeue
1936 * command for this stalled endpoint to move the dequeue
1937 * pointer past the TD. We can't do that here because
1938 * the halt condition must be cleared first. Let the
1939 * USB class driver clear the stall later.
1941 ep
->stopped_td
= td
;
1942 ep
->stopped_trb
= event_trb
;
1943 ep
->stopped_stream
= ep_ring
->stream_id
;
1944 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1945 ep_ctx
, trb_comp_code
)) {
1946 /* Other types of errors halt the endpoint, but the
1947 * class driver doesn't call usb_reset_endpoint() unless
1948 * the error is -EPIPE. Clear the halted status in the
1949 * xHCI hardware manually.
1951 xhci_cleanup_halted_endpoint(xhci
,
1952 slot_id
, ep_index
, ep_ring
->stream_id
,
1955 /* Update ring dequeue pointer */
1956 while (ep_ring
->dequeue
!= td
->last_trb
)
1957 inc_deq(xhci
, ep_ring
);
1958 inc_deq(xhci
, ep_ring
);
1962 /* Clean up the endpoint's TD list */
1964 urb_priv
= urb
->hcpriv
;
1966 /* Do one last check of the actual transfer length.
1967 * If the host controller said we transferred more data than
1968 * the buffer length, urb->actual_length will be a very big
1969 * number (since it's unsigned). Play it safe and say we didn't
1970 * transfer anything.
1972 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1973 xhci_warn(xhci
, "URB transfer length is wrong, "
1974 "xHC issue? req. len = %u, "
1976 urb
->transfer_buffer_length
,
1977 urb
->actual_length
);
1978 urb
->actual_length
= 0;
1979 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1980 *status
= -EREMOTEIO
;
1984 list_del_init(&td
->td_list
);
1985 /* Was this TD slated to be cancelled but completed anyway? */
1986 if (!list_empty(&td
->cancelled_td_list
))
1987 list_del_init(&td
->cancelled_td_list
);
1990 /* Giveback the urb when all the tds are completed */
1991 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1993 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1994 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1995 #ifndef CONFIG_MTK_XHCI
1996 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1998 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1999 usb_amd_quirk_pll_enable();
2010 * Process control tds, update urb status and actual_length.
2012 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2013 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2014 struct xhci_virt_ep
*ep
, int *status
)
2016 struct xhci_virt_device
*xdev
;
2017 struct xhci_ring
*ep_ring
;
2018 unsigned int slot_id
;
2020 struct xhci_ep_ctx
*ep_ctx
;
2023 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2024 xdev
= xhci
->devs
[slot_id
];
2025 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2026 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2027 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2028 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2030 switch (trb_comp_code
) {
2032 if (event_trb
== ep_ring
->dequeue
) {
2033 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
2034 "without IOC set??\n");
2035 *status
= -ESHUTDOWN
;
2036 } else if (event_trb
!= td
->last_trb
) {
2037 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
2038 "without IOC set??\n");
2039 *status
= -ESHUTDOWN
;
2045 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2046 *status
= -EREMOTEIO
;
2050 case COMP_STOP_INVAL
:
2052 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2054 if (!xhci_requires_manual_halt_cleanup(xhci
,
2055 ep_ctx
, trb_comp_code
))
2057 xhci_dbg(xhci
, "TRB error code %u, "
2058 "halted endpoint index = %u\n",
2059 trb_comp_code
, ep_index
);
2060 /* else fall through */
2062 /* Did we transfer part of the data (middle) phase? */
2063 if (event_trb
!= ep_ring
->dequeue
&&
2064 event_trb
!= td
->last_trb
)
2065 td
->urb
->actual_length
=
2066 td
->urb
->transfer_buffer_length
-
2067 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2069 td
->urb
->actual_length
= 0;
2071 xhci_cleanup_halted_endpoint(xhci
,
2072 slot_id
, ep_index
, 0, td
, event_trb
);
2073 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
2076 * Did we transfer any data, despite the errors that might have
2077 * happened? I.e. did we get past the setup stage?
2079 if (event_trb
!= ep_ring
->dequeue
) {
2080 /* The event was for the status stage */
2081 if (event_trb
== td
->last_trb
) {
2082 if (td
->urb_length_set
) {
2083 /* Don't overwrite a previously set error code
2085 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
2086 (td
->urb
->transfer_flags
2087 & URB_SHORT_NOT_OK
))
2088 /* Did we already see a short data
2090 *status
= -EREMOTEIO
;
2092 td
->urb
->actual_length
=
2093 td
->urb
->transfer_buffer_length
;
2097 * Maybe the event was for the data stage? If so, update
2098 * already the actual_length of the URB and flag it as
2099 * set, so that it is not overwritten in the event for
2102 td
->urb_length_set
= true;
2103 td
->urb
->actual_length
=
2104 td
->urb
->transfer_buffer_length
-
2105 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2106 xhci_dbg(xhci
, "Waiting for status "
2112 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2116 * Process isochronous tds, update urb packet status and actual_length.
2118 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2119 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2120 struct xhci_virt_ep
*ep
, int *status
)
2122 struct xhci_ring
*ep_ring
;
2123 struct urb_priv
*urb_priv
;
2126 union xhci_trb
*cur_trb
;
2127 struct xhci_segment
*cur_seg
;
2128 struct usb_iso_packet_descriptor
*frame
;
2130 bool skip_td
= false;
2132 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2133 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2134 urb_priv
= td
->urb
->hcpriv
;
2135 idx
= urb_priv
->td_cnt
;
2136 frame
= &td
->urb
->iso_frame_desc
[idx
];
2138 /* handle completion code */
2139 switch (trb_comp_code
) {
2141 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0) {
2145 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2146 trb_comp_code
= COMP_SHORT_TX
;
2148 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
2152 frame
->status
= -ECOMM
;
2155 case COMP_BUFF_OVER
:
2157 frame
->status
= -EOVERFLOW
;
2162 frame
->status
= -EPROTO
;
2166 frame
->status
= -EPROTO
;
2167 if (event_trb
!= td
->last_trb
)
2172 case COMP_STOP_INVAL
:
2179 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
2180 frame
->actual_length
= frame
->length
;
2181 td
->urb
->actual_length
+= frame
->length
;
2183 for (cur_trb
= ep_ring
->dequeue
,
2184 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
2185 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2186 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2187 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2188 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2190 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2191 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2193 if (trb_comp_code
!= COMP_STOP_INVAL
) {
2194 frame
->actual_length
= len
;
2195 td
->urb
->actual_length
+= len
;
2199 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2202 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2203 struct xhci_transfer_event
*event
,
2204 struct xhci_virt_ep
*ep
, int *status
)
2206 struct xhci_ring
*ep_ring
;
2207 struct urb_priv
*urb_priv
;
2208 struct usb_iso_packet_descriptor
*frame
;
2211 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2212 urb_priv
= td
->urb
->hcpriv
;
2213 idx
= urb_priv
->td_cnt
;
2214 frame
= &td
->urb
->iso_frame_desc
[idx
];
2216 /* The transfer is partly done. */
2217 frame
->status
= -EXDEV
;
2219 /* calc actual length */
2220 frame
->actual_length
= 0;
2222 /* Update ring dequeue pointer */
2223 while (ep_ring
->dequeue
!= td
->last_trb
)
2224 inc_deq(xhci
, ep_ring
);
2225 inc_deq(xhci
, ep_ring
);
2227 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
2231 * Process bulk and interrupt tds, update urb status and actual_length.
2233 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2234 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2235 struct xhci_virt_ep
*ep
, int *status
)
2237 struct xhci_ring
*ep_ring
;
2238 union xhci_trb
*cur_trb
;
2239 struct xhci_segment
*cur_seg
;
2242 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2243 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2245 switch (trb_comp_code
) {
2247 /* Double check that the HW transferred everything. */
2248 if (event_trb
!= td
->last_trb
||
2249 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2250 xhci_warn(xhci
, "WARN Successful completion "
2252 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2253 *status
= -EREMOTEIO
;
2256 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2257 trb_comp_code
= COMP_SHORT_TX
;
2263 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2264 *status
= -EREMOTEIO
;
2269 /* Others already handled above */
2272 if (trb_comp_code
== COMP_SHORT_TX
)
2273 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
2274 "%d bytes untransferred\n",
2275 td
->urb
->ep
->desc
.bEndpointAddress
,
2276 td
->urb
->transfer_buffer_length
,
2277 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2278 /* Fast path - was this the last TRB in the TD for this URB? */
2279 if (event_trb
== td
->last_trb
) {
2280 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2281 td
->urb
->actual_length
=
2282 td
->urb
->transfer_buffer_length
-
2283 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2284 if (td
->urb
->transfer_buffer_length
<
2285 td
->urb
->actual_length
) {
2286 xhci_warn(xhci
, "HC gave bad length "
2287 "of %d bytes left\n",
2288 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2289 td
->urb
->actual_length
= 0;
2290 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2291 *status
= -EREMOTEIO
;
2295 /* Don't overwrite a previously set error code */
2296 if (*status
== -EINPROGRESS
) {
2297 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2298 *status
= -EREMOTEIO
;
2303 td
->urb
->actual_length
=
2304 td
->urb
->transfer_buffer_length
;
2305 /* Ignore a short packet completion if the
2306 * untransferred length was zero.
2308 if (*status
== -EREMOTEIO
)
2312 /* Slow path - walk the list, starting from the dequeue
2313 * pointer, to get the actual length transferred.
2315 td
->urb
->actual_length
= 0;
2316 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
2317 cur_trb
!= event_trb
;
2318 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2319 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2320 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2321 td
->urb
->actual_length
+=
2322 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2324 /* If the ring didn't stop on a Link or No-op TRB, add
2325 * in the actual bytes transferred from the Normal TRB
2327 if (trb_comp_code
!= COMP_STOP_INVAL
)
2328 td
->urb
->actual_length
+=
2329 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2330 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2333 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2337 * If this function returns an error condition, it means it got a Transfer
2338 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2339 * At this point, the host controller is probably hosed and should be reset.
2341 static int handle_tx_event(struct xhci_hcd
*xhci
,
2342 struct xhci_transfer_event
*event
)
2343 __releases(&xhci
->lock
)
2344 __acquires(&xhci
->lock
)
2346 struct xhci_virt_device
*xdev
;
2347 struct xhci_virt_ep
*ep
;
2348 struct xhci_ring
*ep_ring
;
2349 unsigned int slot_id
;
2351 struct xhci_td
*td
= NULL
;
2352 dma_addr_t event_dma
;
2353 struct xhci_segment
*event_seg
;
2354 union xhci_trb
*event_trb
;
2355 struct urb
*urb
= NULL
;
2356 int status
= -EINPROGRESS
;
2357 struct urb_priv
*urb_priv
;
2358 struct xhci_ep_ctx
*ep_ctx
;
2359 struct list_head
*tmp
;
2364 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2365 xdev
= xhci
->devs
[slot_id
];
2367 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
2368 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2369 (unsigned long long) xhci_trb_virt_to_dma(
2370 xhci
->event_ring
->deq_seg
,
2371 xhci
->event_ring
->dequeue
),
2372 lower_32_bits(le64_to_cpu(event
->buffer
)),
2373 upper_32_bits(le64_to_cpu(event
->buffer
)),
2374 le32_to_cpu(event
->transfer_len
),
2375 le32_to_cpu(event
->flags
));
2376 xhci_dbg(xhci
, "Event ring:\n");
2377 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2381 /* Endpoint ID is 1 based, our index is zero based */
2382 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2383 ep
= &xdev
->eps
[ep_index
];
2384 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2385 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2387 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
2388 EP_STATE_DISABLED
) {
2389 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
2390 "or incorrect stream ring\n");
2391 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2392 (unsigned long long) xhci_trb_virt_to_dma(
2393 xhci
->event_ring
->deq_seg
,
2394 xhci
->event_ring
->dequeue
),
2395 lower_32_bits(le64_to_cpu(event
->buffer
)),
2396 upper_32_bits(le64_to_cpu(event
->buffer
)),
2397 le32_to_cpu(event
->transfer_len
),
2398 le32_to_cpu(event
->flags
));
2399 xhci_dbg(xhci
, "Event ring:\n");
2400 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2404 /* Count current td numbers if ep->skip is set */
2406 list_for_each(tmp
, &ep_ring
->td_list
)
2410 event_dma
= le64_to_cpu(event
->buffer
);
2411 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2412 /* Look for common error cases */
2413 switch (trb_comp_code
) {
2414 /* Skip codes that require special handling depending on
2418 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2420 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2421 trb_comp_code
= COMP_SHORT_TX
;
2423 xhci_warn_ratelimited(xhci
,
2424 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2428 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
2430 case COMP_STOP_INVAL
:
2431 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
2434 xhci_dbg(xhci
, "Stalled endpoint\n");
2435 ep
->ep_state
|= EP_HALTED
;
2439 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
2442 case COMP_SPLIT_ERR
:
2444 xhci_dbg(xhci
, "Transfer error on endpoint\n");
2448 xhci_dbg(xhci
, "Babble error on endpoint\n");
2449 status
= -EOVERFLOW
;
2452 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2456 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2458 case COMP_BUFF_OVER
:
2459 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2463 * When the Isoch ring is empty, the xHC will generate
2464 * a Ring Overrun Event for IN Isoch endpoint or Ring
2465 * Underrun Event for OUT Isoch endpoint.
2467 xhci_dbg(xhci
, "underrun event on endpoint\n");
2468 if (!list_empty(&ep_ring
->td_list
))
2469 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2470 "still with TDs queued?\n",
2471 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2475 xhci_dbg(xhci
, "overrun event on endpoint\n");
2476 if (!list_empty(&ep_ring
->td_list
))
2477 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2478 "still with TDs queued?\n",
2479 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2483 xhci_warn(xhci
, "WARN: detect an incompatible device");
2486 case COMP_MISSED_INT
:
2488 * When encounter missed service error, one or more isoc tds
2489 * may be missed by xHC.
2490 * Set skip flag of the ep_ring; Complete the missed tds as
2491 * short transfer when process the ep_ring next time.
2494 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2497 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2501 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2507 /* This TRB should be in the TD at the head of this ring's
2510 if (list_empty(&ep_ring
->td_list
)) {
2512 * A stopped endpoint may generate an extra completion
2513 * event if the device was suspended. Don't print
2516 if (!(trb_comp_code
== COMP_STOP
||
2517 trb_comp_code
== COMP_STOP_INVAL
)) {
2518 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2519 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2521 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2522 (le32_to_cpu(event
->flags
) &
2523 TRB_TYPE_BITMASK
)>>10);
2524 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2528 xhci_dbg(xhci
, "td_list is empty while skip "
2529 "flag set. Clear skip flag.\n");
2535 /* We've skipped all the TDs on the ep ring when ep->skip set */
2536 if (ep
->skip
&& td_num
== 0) {
2538 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2539 "Clear skip flag.\n");
2544 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2548 /* Is this a TRB in the currently executing TD? */
2549 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2550 td
->last_trb
, event_dma
);
2553 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2554 * is not in the current TD pointed by ep_ring->dequeue because
2555 * that the hardware dequeue pointer still at the previous TRB
2556 * of the current TD. The previous TRB maybe a Link TD or the
2557 * last TRB of the previous TD. The command completion handle
2558 * will take care the rest.
2560 if (!event_seg
&& (trb_comp_code
== COMP_STOP
||
2561 trb_comp_code
== COMP_STOP_INVAL
)) {
2568 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2569 /* Some host controllers give a spurious
2570 * successful event after a short transfer.
2573 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2574 ep_ring
->last_td_was_short
) {
2575 ep_ring
->last_td_was_short
= false;
2579 /* HC is busted, give up! */
2581 "ERROR Transfer event TRB DMA ptr not "
2582 "part of current TD\n");
2586 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2589 if (trb_comp_code
== COMP_SHORT_TX
)
2590 ep_ring
->last_td_was_short
= true;
2592 ep_ring
->last_td_was_short
= false;
2595 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2599 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2600 sizeof(*event_trb
)];
2602 * No-op TRB should not trigger interrupts.
2603 * If event_trb is a no-op TRB, it means the
2604 * corresponding TD has been cancelled. Just ignore
2607 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2609 "event_trb is a no-op TRB. Skip it\n");
2613 /* Now update the urb's actual_length and give back to
2616 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2617 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2619 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2620 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2623 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2628 * Do not update event ring dequeue pointer if ep->skip is set.
2629 * Will roll back to continue process missed tds.
2631 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2632 inc_deq(xhci
, xhci
->event_ring
);
2637 urb_priv
= urb
->hcpriv
;
2638 /* Leave the TD around for the reset endpoint function
2639 * to use(but only if it's not a control endpoint,
2640 * since we already queued the Set TR dequeue pointer
2641 * command for stalled control endpoints).
2643 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2644 (trb_comp_code
!= COMP_STALL
&&
2645 trb_comp_code
!= COMP_BABBLE
))
2646 xhci_urb_free_priv(xhci
, urb_priv
);
2650 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2651 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2652 (urb
->transfer_flags
&
2653 URB_SHORT_NOT_OK
)) ||
2655 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2656 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2657 "expected = %d, status = %d\n",
2658 urb
, urb
->actual_length
,
2659 urb
->transfer_buffer_length
,
2661 spin_unlock(&xhci
->lock
);
2662 /* EHCI, UHCI, and OHCI always unconditionally set the
2663 * urb->status of an isochronous endpoint to 0.
2665 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2667 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2668 spin_lock(&xhci
->lock
);
2672 * If ep->skip is set, it means there are missed tds on the
2673 * endpoint ring need to take care of.
2674 * Process them as short transfer until reach the td pointed by
2677 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2683 * This function handles all OS-owned events on the event ring. It may drop
2684 * xhci->lock between event processing (e.g. to pass up port status changes).
2685 * Returns >0 for "possibly more events to process" (caller should call again),
2686 * otherwise 0 if done. In future, <0 returns should indicate error code.
2688 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2690 union xhci_trb
*event
;
2691 int update_ptrs
= 1;
2694 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2695 xhci
->error_bitmask
|= 1 << 1;
2699 event
= xhci
->event_ring
->dequeue
;
2700 /* Does the HC or OS own the TRB? */
2701 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2702 xhci
->event_ring
->cycle_state
) {
2703 xhci
->error_bitmask
|= 1 << 2;
2708 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2709 * speculative reads of the event's flags/data below.
2712 /* FIXME: Handle more event types. */
2713 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2714 case TRB_TYPE(TRB_COMPLETION
):
2715 handle_cmd_completion(xhci
, &event
->event_cmd
);
2717 case TRB_TYPE(TRB_PORT_STATUS
):
2718 handle_port_status(xhci
, event
);
2721 case TRB_TYPE(TRB_TRANSFER
):
2722 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2724 xhci
->error_bitmask
|= 1 << 9;
2728 case TRB_TYPE(TRB_DEV_NOTE
):
2729 handle_device_notification(xhci
, event
);
2732 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2734 handle_vendor_event(xhci
, event
);
2736 xhci
->error_bitmask
|= 1 << 3;
2738 /* Any of the above functions may drop and re-acquire the lock, so check
2739 * to make sure a watchdog timer didn't mark the host as non-responsive.
2741 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2742 xhci_dbg(xhci
, "xHCI host dying, returning from "
2743 "event handler.\n");
2748 /* Update SW event ring dequeue pointer */
2749 inc_deq(xhci
, xhci
->event_ring
);
2751 /* Are there more items on the event ring? Caller will call us again to
2758 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2759 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2760 * indicators of an event TRB error, but we check the status *first* to be safe.
2762 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2764 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2767 union xhci_trb
*event_ring_deq
;
2770 spin_lock(&xhci
->lock
);
2771 /* Check if the xHC generated the interrupt, or the irq is shared */
2772 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2773 if (status
== 0xffffffff)
2776 if (!(status
& STS_EINT
)) {
2777 spin_unlock(&xhci
->lock
);
2780 if (status
& STS_FATAL
) {
2781 xhci_warn(xhci
, "WARNING: Host System Error\n");
2784 spin_unlock(&xhci
->lock
);
2789 * Clear the op reg interrupt status first,
2790 * so we can receive interrupts from other MSI-X interrupters.
2791 * Write 1 to clear the interrupt status.
2794 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2795 /* FIXME when MSI-X is supported and there are multiple vectors */
2796 /* Clear the MSI-X event interrupt status */
2800 /* Acknowledge the PCI interrupt */
2801 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2802 irq_pending
|= IMAN_IP
;
2803 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2806 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2807 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2808 "Shouldn't IRQs be disabled?\n");
2809 /* Clear the event handler busy flag (RW1C);
2810 * the event ring should be empty.
2812 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2813 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2814 &xhci
->ir_set
->erst_dequeue
);
2815 spin_unlock(&xhci
->lock
);
2820 event_ring_deq
= xhci
->event_ring
->dequeue
;
2821 /* FIXME this should be a delayed service routine
2822 * that clears the EHB.
2824 while (xhci_handle_event(xhci
) > 0) {}
2826 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2827 /* If necessary, update the HW's version of the event ring deq ptr. */
2828 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2829 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2830 xhci
->event_ring
->dequeue
);
2832 xhci_warn(xhci
, "WARN something wrong with SW event "
2833 "ring dequeue ptr.\n");
2834 /* Update HC event ring dequeue pointer */
2835 temp_64
&= ERST_PTR_MASK
;
2836 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2839 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2840 temp_64
|= ERST_EHB
;
2841 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2843 spin_unlock(&xhci
->lock
);
2848 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2850 return xhci_irq(hcd
);
2853 /**** Endpoint Ring Operations ****/
2856 * Generic function for queueing a TRB on a ring.
2857 * The caller must have checked to make sure there's room on the ring.
2859 * @more_trbs_coming: Will you enqueue more TRBs before calling
2860 * prepare_transfer()?
2862 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2863 bool more_trbs_coming
,
2864 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2866 struct xhci_generic_trb
*trb
;
2868 trb
= &ring
->enqueue
->generic
;
2869 trb
->field
[0] = cpu_to_le32(field1
);
2870 trb
->field
[1] = cpu_to_le32(field2
);
2871 trb
->field
[2] = cpu_to_le32(field3
);
2872 trb
->field
[3] = cpu_to_le32(field4
);
2873 inc_enq(xhci
, ring
, more_trbs_coming
);
2877 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2878 * FIXME allocate segments if the ring is full.
2880 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2881 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2883 unsigned int num_trbs_needed
;
2885 /* Make sure the endpoint has been added to xHC schedule */
2887 case EP_STATE_DISABLED
:
2889 * USB core changed config/interfaces without notifying us,
2890 * or hardware is reporting the wrong state.
2892 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2894 case EP_STATE_ERROR
:
2895 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2896 /* FIXME event handling code for error needs to clear it */
2897 /* XXX not sure if this should be -ENOENT or not */
2899 case EP_STATE_HALTED
:
2900 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2901 case EP_STATE_STOPPED
:
2902 case EP_STATE_RUNNING
:
2905 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2907 * FIXME issue Configure Endpoint command to try to get the HC
2908 * back into a known state.
2914 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
2917 if (ep_ring
== xhci
->cmd_ring
) {
2918 xhci_err(xhci
, "Do not support expand command ring\n");
2922 xhci_dbg(xhci
, "ERROR no room on ep ring, "
2923 "try ring expansion\n");
2924 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
2925 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
2927 xhci_err(xhci
, "Ring expansion failed\n");
2932 if (enqueue_is_link_trb(ep_ring
)) {
2933 struct xhci_ring
*ring
= ep_ring
;
2934 union xhci_trb
*next
;
2936 next
= ring
->enqueue
;
2938 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2939 /* If we're not dealing with 0.95 hardware or isoc rings
2940 * on AMD 0.96 host, clear the chain bit.
2942 #ifndef CONFIG_MTK_XHCI
2943 if (!xhci_link_trb_quirk(xhci
) &&
2944 !(ring
->type
== TYPE_ISOC
&&
2945 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2946 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2948 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2950 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2953 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2955 /* Toggle the cycle bit after the last ring segment. */
2956 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2957 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2959 ring
->enq_seg
= ring
->enq_seg
->next
;
2960 ring
->enqueue
= ring
->enq_seg
->trbs
;
2961 next
= ring
->enqueue
;
2968 static int prepare_transfer(struct xhci_hcd
*xhci
,
2969 struct xhci_virt_device
*xdev
,
2970 unsigned int ep_index
,
2971 unsigned int stream_id
,
2972 unsigned int num_trbs
,
2974 unsigned int td_index
,
2978 struct urb_priv
*urb_priv
;
2980 struct xhci_ring
*ep_ring
;
2981 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2983 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2985 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2990 ret
= prepare_ring(xhci
, ep_ring
,
2991 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2992 num_trbs
, mem_flags
);
2996 urb_priv
= urb
->hcpriv
;
2997 td
= urb_priv
->td
[td_index
];
2999 INIT_LIST_HEAD(&td
->td_list
);
3000 INIT_LIST_HEAD(&td
->cancelled_td_list
);
3002 if (td_index
== 0) {
3003 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3009 /* Add this TD to the tail of the endpoint ring's TD list */
3010 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
3011 td
->start_seg
= ep_ring
->enq_seg
;
3012 td
->first_trb
= ep_ring
->enqueue
;
3014 urb_priv
->td
[td_index
] = td
;
3019 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
3021 int num_sgs
, num_trbs
, running_total
, temp
, i
;
3022 struct scatterlist
*sg
;
3025 num_sgs
= urb
->num_mapped_sgs
;
3026 temp
= urb
->transfer_buffer_length
;
3029 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
3030 unsigned int len
= sg_dma_len(sg
);
3032 /* Scatter gather list entries may cross 64KB boundaries */
3033 running_total
= TRB_MAX_BUFF_SIZE
-
3034 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
3035 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3036 if (running_total
!= 0)
3039 /* How many more 64KB chunks to transfer, how many more TRBs? */
3040 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
3042 running_total
+= TRB_MAX_BUFF_SIZE
;
3044 len
= min_t(int, len
, temp
);
3052 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
3055 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
3056 "TRBs, %d left\n", __func__
,
3057 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
3058 if (running_total
!= urb
->transfer_buffer_length
)
3059 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
3060 "queued %#x (%d), asked for %#x (%d)\n",
3062 urb
->ep
->desc
.bEndpointAddress
,
3063 running_total
, running_total
,
3064 urb
->transfer_buffer_length
,
3065 urb
->transfer_buffer_length
);
3068 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
3069 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
3070 struct xhci_generic_trb
*start_trb
)
3073 * Pass all the TRBs to the hardware at once and make sure this write
3078 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
3080 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
3081 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
3085 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3086 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3087 * (comprised of sg list entries) can take several service intervals to
3090 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3091 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3093 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
3094 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
3098 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3099 ep_interval
= urb
->interval
;
3100 /* Convert to microframes */
3101 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3102 urb
->dev
->speed
== USB_SPEED_FULL
)
3104 /* FIXME change this to a warning and a suggestion to use the new API
3105 * to set the polling interval (once the API is added).
3107 if (xhci_interval
!= ep_interval
) {
3108 if (printk_ratelimit())
3109 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3110 " (%d microframe%s) than xHCI "
3111 "(%d microframe%s)\n",
3113 ep_interval
== 1 ? "" : "s",
3115 xhci_interval
== 1 ? "" : "s");
3116 urb
->interval
= xhci_interval
;
3117 /* Convert back to frames for LS/FS devices */
3118 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3119 urb
->dev
->speed
== USB_SPEED_FULL
)
3122 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3126 * The TD size is the number of bytes remaining in the TD (including this TRB),
3127 * right shifted by 10.
3128 * It must fit in bits 21:17, so it can't be bigger than 31.
3130 #ifdef CONFIG_MTK_XHCI
3131 static u32
xhci_td_remainder(unsigned int td_transfer_size
, unsigned int td_running_total
3132 , unsigned int maxp
, unsigned trb_buffer_length
)
3135 int remainder
, td_packet_count
, packet_transferred
;
3137 //0 for the last TRB
3138 //FIXME: need to workaround if there is ZLP in this TD
3139 if (td_running_total
+ trb_buffer_length
== td_transfer_size
)
3142 //FIXME: need to take care of high-bandwidth (MAX_ESIT)
3143 packet_transferred
= (td_running_total
/*+ trb_buffer_length*/) / maxp
;
3144 td_packet_count
= DIV_ROUND_UP(td_transfer_size
, maxp
);
3145 remainder
= td_packet_count
- packet_transferred
;
3147 if (remainder
> max
)
3150 return remainder
<< 17;
3153 static u32
xhci_td_remainder(unsigned int remainder
)
3155 u32 max
= (1 << (21 - 17 + 1)) - 1;
3157 if ((remainder
>> 10) >= max
)
3160 return (remainder
>> 10) << 17;
3165 #ifndef CONFIG_MTK_XHCI
3167 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3168 * packets remaining in the TD (*not* including this TRB).
3170 * Total TD packet count = total_packet_count =
3171 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3173 * Packets transferred up to and including this TRB = packets_transferred =
3174 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3176 * TD size = total_packet_count - packets_transferred
3178 * It must fit in bits 21:17, so it can't be bigger than 31.
3179 * The last TRB in a TD must have the TD size set to zero.
3181 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
3182 unsigned int total_packet_count
, struct urb
*urb
,
3183 unsigned int num_trbs_left
)
3185 int packets_transferred
;
3187 /* One TRB with a zero-length data packet. */
3188 if (num_trbs_left
== 0 || (running_total
== 0 && trb_buff_len
== 0))
3191 /* All the TRB queueing functions don't count the current TRB in
3194 packets_transferred
= (running_total
+ trb_buff_len
) /
3195 GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3197 if ((total_packet_count
- packets_transferred
) > 31)
3199 return (total_packet_count
- packets_transferred
) << 17;
3203 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3204 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3206 struct xhci_ring
*ep_ring
;
3207 unsigned int num_trbs
;
3208 struct urb_priv
*urb_priv
;
3210 struct scatterlist
*sg
;
3212 int trb_buff_len
, this_sg_len
, running_total
;
3213 unsigned int total_packet_count
;
3216 bool more_trbs_coming
;
3218 struct xhci_generic_trb
*start_trb
;
3221 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3225 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
3226 num_sgs
= urb
->num_mapped_sgs
;
3227 total_packet_count
= DIV_ROUND_UP(urb
->transfer_buffer_length
,
3228 usb_endpoint_maxp(&urb
->ep
->desc
));
3230 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3231 ep_index
, urb
->stream_id
,
3232 num_trbs
, urb
, 0, mem_flags
);
3233 if (trb_buff_len
< 0)
3234 return trb_buff_len
;
3236 urb_priv
= urb
->hcpriv
;
3237 td
= urb_priv
->td
[0];
3240 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3241 * until we've finished creating all the other TRBs. The ring's cycle
3242 * state may change as we enqueue the other TRBs, so save it too.
3244 start_trb
= &ep_ring
->enqueue
->generic
;
3245 start_cycle
= ep_ring
->cycle_state
;
3249 * How much data is in the first TRB?
3251 * There are three forces at work for TRB buffer pointers and lengths:
3252 * 1. We don't want to walk off the end of this sg-list entry buffer.
3253 * 2. The transfer length that the driver requested may be smaller than
3254 * the amount of memory allocated for this scatter-gather list.
3255 * 3. TRBs buffers can't cross 64KB boundaries.
3258 addr
= (u64
) sg_dma_address(sg
);
3259 this_sg_len
= sg_dma_len(sg
);
3260 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3261 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
3262 if (trb_buff_len
> urb
->transfer_buffer_length
)
3263 trb_buff_len
= urb
->transfer_buffer_length
;
3266 /* Queue the first TRB, even if it's zero-length */
3269 u32 length_field
= 0;
3272 /* Don't change the cycle bit of the first TRB until later */
3275 if (start_cycle
== 0)
3278 field
|= ep_ring
->cycle_state
;
3280 /* Chain all the TRBs together; clear the chain bit in the last
3281 * TRB to indicate it's the last TRB in the chain.
3286 /* FIXME - add check for ZERO_PACKET flag before this */
3287 td
->last_trb
= ep_ring
->enqueue
;
3291 /* Only set interrupt on short packet for IN endpoints */
3292 if (usb_urb_dir_in(urb
))
3295 if (TRB_MAX_BUFF_SIZE
-
3296 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
3297 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3298 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
3299 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
3300 (unsigned int) addr
+ trb_buff_len
);
3303 /* Set the TRB length, TD size, and interrupter fields. */
3304 #ifdef CONFIG_MTK_XHCI
3306 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
,
3307 running_total
, urb
->ep
->desc
.wMaxPacketSize
, trb_buff_len
);
3310 /* Set the TRB length, TD size, and interrupter fields. */
3311 if (xhci
->hci_version
< 0x100) {
3312 remainder
= xhci_td_remainder(
3313 urb
->transfer_buffer_length
-
3316 remainder
= xhci_v1_0_td_remainder(running_total
,
3317 trb_buff_len
, total_packet_count
, urb
,
3322 length_field
= TRB_LEN(trb_buff_len
) |
3327 more_trbs_coming
= true;
3329 more_trbs_coming
= false;
3330 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3331 lower_32_bits(addr
),
3332 upper_32_bits(addr
),
3334 field
| TRB_TYPE(TRB_NORMAL
));
3336 running_total
+= trb_buff_len
;
3338 /* Calculate length for next transfer --
3339 * Are we done queueing all the TRBs for this sg entry?
3341 this_sg_len
-= trb_buff_len
;
3342 if (this_sg_len
== 0) {
3347 addr
= (u64
) sg_dma_address(sg
);
3348 this_sg_len
= sg_dma_len(sg
);
3350 addr
+= trb_buff_len
;
3353 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3354 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3355 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
3356 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
3358 urb
->transfer_buffer_length
- running_total
;
3359 } while (running_total
< urb
->transfer_buffer_length
);
3361 check_trb_math(urb
, num_trbs
, running_total
);
3362 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3363 start_cycle
, start_trb
);
3367 /* This is very similar to what ehci-q.c qtd_fill() does */
3368 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3369 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3371 struct xhci_ring
*ep_ring
;
3372 struct urb_priv
*urb_priv
;
3375 struct xhci_generic_trb
*start_trb
;
3377 bool more_trbs_coming
;
3379 u32 field
, length_field
;
3380 #ifdef CONFIG_MTK_XHCI
3381 int max_packet
= USB_SPEED_HIGH
;
3383 int running_total
, trb_buff_len
, ret
;
3384 unsigned int total_packet_count
;
3388 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3390 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3395 /* How much data is (potentially) left before the 64KB boundary? */
3396 running_total
= TRB_MAX_BUFF_SIZE
-
3397 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3398 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3400 /* If there's some data on this 64KB chunk, or we have to send a
3401 * zero-length transfer, we need at least one TRB
3403 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
3405 /* How many more 64KB chunks to transfer, how many more TRBs? */
3406 while (running_total
< urb
->transfer_buffer_length
) {
3408 running_total
+= TRB_MAX_BUFF_SIZE
;
3410 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3412 #ifdef CONFIG_MTK_XHCI
3413 switch(urb
->dev
->speed
){
3414 case USB_SPEED_SUPER
:
3415 max_packet
= urb
->ep
->desc
.wMaxPacketSize
;
3417 case USB_SPEED_HIGH
:
3418 case USB_SPEED_FULL
:
3421 max_packet
= urb
->ep
->desc
.wMaxPacketSize
& 0x7ff;
3424 if((urb
->transfer_flags
& URB_ZERO_PACKET
)
3425 && ((urb
->transfer_buffer_length
% max_packet
) == 0)){
3430 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3431 ep_index
, urb
->stream_id
,
3432 num_trbs
, urb
, 0, mem_flags
);
3436 urb_priv
= urb
->hcpriv
;
3437 td
= urb_priv
->td
[0];
3440 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3441 * until we've finished creating all the other TRBs. The ring's cycle
3442 * state may change as we enqueue the other TRBs, so save it too.
3444 start_trb
= &ep_ring
->enqueue
->generic
;
3445 start_cycle
= ep_ring
->cycle_state
;
3448 total_packet_count
= DIV_ROUND_UP(urb
->transfer_buffer_length
,
3449 usb_endpoint_maxp(&urb
->ep
->desc
));
3450 /* How much data is in the first TRB? */
3451 addr
= (u64
) urb
->transfer_dma
;
3452 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3453 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3454 if (trb_buff_len
> urb
->transfer_buffer_length
)
3455 trb_buff_len
= urb
->transfer_buffer_length
;
3459 /* Queue the first TRB, even if it's zero-length */
3464 /* Don't change the cycle bit of the first TRB until later */
3467 if (start_cycle
== 0)
3470 field
|= ep_ring
->cycle_state
;
3472 /* Chain all the TRBs together; clear the chain bit in the last
3473 * TRB to indicate it's the last TRB in the chain.
3478 /* FIXME - add check for ZERO_PACKET flag before this */
3479 td
->last_trb
= ep_ring
->enqueue
;
3483 /* Only set interrupt on short packet for IN endpoints */
3484 if (usb_urb_dir_in(urb
))
3486 #ifdef CONFIG_MTK_XHCI
3487 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
, running_total
, max_packet
, trb_buff_len
);
3489 /* Set the TRB length, TD size, and interrupter fields. */
3490 if (xhci
->hci_version
< 0x100) {
3491 remainder
= xhci_td_remainder(
3492 urb
->transfer_buffer_length
-
3495 remainder
= xhci_v1_0_td_remainder(running_total
,
3496 trb_buff_len
, total_packet_count
, urb
,
3500 length_field
= TRB_LEN(trb_buff_len
) |
3505 more_trbs_coming
= true;
3507 more_trbs_coming
= false;
3508 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3509 lower_32_bits(addr
),
3510 upper_32_bits(addr
),
3512 field
| TRB_TYPE(TRB_NORMAL
));
3514 running_total
+= trb_buff_len
;
3516 /* Calculate length for next transfer */
3517 addr
+= trb_buff_len
;
3518 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
3519 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
3520 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
3521 } while (running_total
< urb
->transfer_buffer_length
);
3523 check_trb_math(urb
, num_trbs
, running_total
);
3524 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3525 start_cycle
, start_trb
);
3529 /* Caller must have locked xhci->lock */
3530 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3531 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3533 struct xhci_ring
*ep_ring
;
3536 struct usb_ctrlrequest
*setup
;
3537 struct xhci_generic_trb
*start_trb
;
3539 u32 field
, length_field
;
3540 struct urb_priv
*urb_priv
;
3543 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3548 * Need to copy setup packet into setup TRB, so we can't use the setup
3551 if (!urb
->setup_packet
)
3554 /* 1 TRB for setup, 1 for status */
3557 * Don't need to check if we need additional event data and normal TRBs,
3558 * since data in control transfers will never get bigger than 16MB
3559 * XXX: can we get a buffer that crosses 64KB boundaries?
3561 if (urb
->transfer_buffer_length
> 0)
3563 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3564 ep_index
, urb
->stream_id
,
3565 num_trbs
, urb
, 0, mem_flags
);
3569 urb_priv
= urb
->hcpriv
;
3570 td
= urb_priv
->td
[0];
3573 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3574 * until we've finished creating all the other TRBs. The ring's cycle
3575 * state may change as we enqueue the other TRBs, so save it too.
3577 start_trb
= &ep_ring
->enqueue
->generic
;
3578 start_cycle
= ep_ring
->cycle_state
;
3580 /* Queue setup TRB - see section 6.4.1.2.1 */
3581 /* FIXME better way to translate setup_packet into two u32 fields? */
3582 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3584 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3585 if (start_cycle
== 0)
3588 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3589 #ifdef CONFIG_MTK_XHCI
3592 if (xhci
->hci_version
== 0x100) {
3594 if (urb
->transfer_buffer_length
> 0) {
3595 if (setup
->bRequestType
& USB_DIR_IN
)
3596 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3598 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3602 queue_trb(xhci
, ep_ring
, true,
3603 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3604 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3605 TRB_LEN(8) | TRB_INTR_TARGET(0),
3606 /* Immediate data in pointer */
3609 /* If there's data, queue data TRBs */
3610 /* Only set interrupt on short packet for IN endpoints */
3611 if (usb_urb_dir_in(urb
))
3612 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3614 field
= TRB_TYPE(TRB_DATA
);
3616 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3617 #ifdef CONFIG_MTK_XHCI
3618 //CC: MTK style, no scatter-gather for control transfer
3621 xhci_td_remainder(urb
->transfer_buffer_length
) |
3624 if (urb
->transfer_buffer_length
> 0) {
3625 if (setup
->bRequestType
& USB_DIR_IN
)
3626 field
|= TRB_DIR_IN
;
3627 queue_trb(xhci
, ep_ring
, true,
3628 lower_32_bits(urb
->transfer_dma
),
3629 upper_32_bits(urb
->transfer_dma
),
3631 field
| ep_ring
->cycle_state
);
3634 /* Save the DMA address of the last TRB in the TD */
3635 td
->last_trb
= ep_ring
->enqueue
;
3637 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3638 /* If the device sent data, the status stage is an OUT transfer */
3639 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3643 queue_trb(xhci
, ep_ring
, false,
3647 /* Event on completion */
3648 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3650 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3651 start_cycle
, start_trb
);
3655 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3656 struct urb
*urb
, int i
)
3661 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3662 td_len
= urb
->iso_frame_desc
[i
].length
;
3664 num_trbs
= DIV_ROUND_UP(td_len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3673 * The transfer burst count field of the isochronous TRB defines the number of
3674 * bursts that are required to move all packets in this TD. Only SuperSpeed
3675 * devices can burst up to bMaxBurst number of packets per service interval.
3676 * This field is zero based, meaning a value of zero in the field means one
3677 * burst. Basically, for everything but SuperSpeed devices, this field will be
3678 * zero. Only xHCI 1.0 host controllers support this field.
3680 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3681 struct usb_device
*udev
,
3682 struct urb
*urb
, unsigned int total_packet_count
)
3684 unsigned int max_burst
;
3686 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3689 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3690 return DIV_ROUND_UP(total_packet_count
, max_burst
+ 1) - 1;
3694 * Returns the number of packets in the last "burst" of packets. This field is
3695 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3696 * the last burst packet count is equal to the total number of packets in the
3697 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3698 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3699 * contain 1 to (bMaxBurst + 1) packets.
3701 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3702 struct usb_device
*udev
,
3703 struct urb
*urb
, unsigned int total_packet_count
)
3705 unsigned int max_burst
;
3706 unsigned int residue
;
3708 if (xhci
->hci_version
< 0x100)
3711 switch (udev
->speed
) {
3712 case USB_SPEED_SUPER
:
3713 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3714 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3715 residue
= total_packet_count
% (max_burst
+ 1);
3716 /* If residue is zero, the last burst contains (max_burst + 1)
3717 * number of packets, but the TLBPC field is zero-based.
3723 if (total_packet_count
== 0)
3725 return total_packet_count
- 1;
3729 /* This is for isoc transfer */
3730 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3731 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3733 struct xhci_ring
*ep_ring
;
3734 struct urb_priv
*urb_priv
;
3736 int num_tds
, trbs_per_td
;
3737 struct xhci_generic_trb
*start_trb
;
3740 u32 field
, length_field
;
3741 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3742 u64 start_addr
, addr
;
3744 bool more_trbs_coming
;
3745 #ifdef CONFIG_MTK_XHCI
3746 int max_packet
= USB_SPEED_HIGH
;
3749 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3751 num_tds
= urb
->number_of_packets
;
3753 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3757 start_addr
= (u64
) urb
->transfer_dma
;
3758 start_trb
= &ep_ring
->enqueue
->generic
;
3759 start_cycle
= ep_ring
->cycle_state
;
3761 #ifdef CONFIG_MTK_XHCI
3762 switch(urb
->dev
->speed
){
3763 case USB_SPEED_SUPER
:
3764 max_packet
= urb
->ep
->desc
.wMaxPacketSize
;
3766 case USB_SPEED_HIGH
:
3767 case USB_SPEED_FULL
:
3770 max_packet
= urb
->ep
->desc
.wMaxPacketSize
& 0x7ff;
3774 urb_priv
= urb
->hcpriv
;
3775 /* Queue the first TRB, even if it's zero-length */
3776 for (i
= 0; i
< num_tds
; i
++) {
3777 unsigned int total_packet_count
;
3778 unsigned int burst_count
;
3779 unsigned int residue
;
3783 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3784 td_len
= urb
->iso_frame_desc
[i
].length
;
3785 td_remain_len
= td_len
;
3786 total_packet_count
= DIV_ROUND_UP(td_len
,
3788 usb_endpoint_maxp(&urb
->ep
->desc
)));
3789 /* A zero-length transfer still involves at least one packet. */
3790 if (total_packet_count
== 0)
3791 total_packet_count
++;
3792 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3793 total_packet_count
);
3794 residue
= xhci_get_last_burst_packet_count(xhci
,
3795 urb
->dev
, urb
, total_packet_count
);
3797 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3799 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3800 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3807 td
= urb_priv
->td
[i
];
3808 for (j
= 0; j
< trbs_per_td
; j
++) {
3813 field
= TRB_TBC(burst_count
) |
3815 /* Queue the isoc TRB */
3816 field
|= TRB_TYPE(TRB_ISOC
);
3817 /* Assume URB_ISO_ASAP is set */
3820 if (start_cycle
== 0)
3823 field
|= ep_ring
->cycle_state
;
3826 /* Queue other normal TRBs */
3827 field
|= TRB_TYPE(TRB_NORMAL
);
3828 field
|= ep_ring
->cycle_state
;
3831 /* Only set interrupt on short packet for IN EPs */
3832 if (usb_urb_dir_in(urb
))
3835 /* Chain all the TRBs together; clear the chain bit in
3836 * the last TRB to indicate it's the last TRB in the
3839 if (j
< trbs_per_td
- 1) {
3841 more_trbs_coming
= true;
3843 td
->last_trb
= ep_ring
->enqueue
;
3845 if (xhci
->hci_version
== 0x100 &&
3848 /* Set BEI bit except for the last td */
3849 if (i
< num_tds
- 1)
3852 more_trbs_coming
= false;
3855 /* Calculate TRB length */
3856 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3857 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3858 if (trb_buff_len
> td_remain_len
)
3859 trb_buff_len
= td_remain_len
;
3861 /* Set the TRB length, TD size, & interrupter fields. */
3862 #ifdef CONFIG_MTK_XHCI
3863 remainder
= xhci_td_remainder(urb
->transfer_buffer_length
, running_total
, max_packet
, trb_buff_len
);
3865 if (xhci
->hci_version
< 0x100) {
3866 remainder
= xhci_td_remainder(
3867 td_len
- running_total
);
3869 remainder
= xhci_v1_0_td_remainder(
3870 running_total
, trb_buff_len
,
3871 total_packet_count
, urb
,
3872 (trbs_per_td
- j
- 1));
3875 length_field
= TRB_LEN(trb_buff_len
) |
3879 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3880 lower_32_bits(addr
),
3881 upper_32_bits(addr
),
3884 running_total
+= trb_buff_len
;
3886 addr
+= trb_buff_len
;
3887 td_remain_len
-= trb_buff_len
;
3890 /* Check TD length */
3891 if (running_total
!= td_len
) {
3892 xhci_err(xhci
, "ISOC TD length unmatch\n");
3897 #ifndef CONFIG_MTK_XHCI
3898 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3899 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3900 usb_amd_quirk_pll_disable();
3903 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3905 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3906 start_cycle
, start_trb
);
3909 /* Clean up a partially enqueued isoc transfer. */
3911 for (i
--; i
>= 0; i
--)
3912 list_del_init(&urb_priv
->td
[i
]->td_list
);
3914 /* Use the first TD as a temporary variable to turn the TDs we've queued
3915 * into No-ops with a software-owned cycle bit. That way the hardware
3916 * won't accidentally start executing bogus TDs when we partially
3917 * overwrite them. td->first_trb and td->start_seg are already set.
3919 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3920 /* Every TRB except the first & last will have its cycle bit flipped. */
3921 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3923 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3924 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3925 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3926 ep_ring
->cycle_state
= start_cycle
;
3927 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
3928 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3933 * Check transfer ring to guarantee there is enough room for the urb.
3934 * Update ISO URB start_frame and interval.
3935 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3936 * update the urb->start_frame by now.
3937 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3939 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3940 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3942 struct xhci_virt_device
*xdev
;
3943 struct xhci_ring
*ep_ring
;
3944 struct xhci_ep_ctx
*ep_ctx
;
3948 int num_tds
, num_trbs
, i
;
3951 xdev
= xhci
->devs
[slot_id
];
3952 ep_ring
= xdev
->eps
[ep_index
].ring
;
3953 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3956 num_tds
= urb
->number_of_packets
;
3957 for (i
= 0; i
< num_tds
; i
++)
3958 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3960 /* Check the ring to guarantee there is enough room for the whole urb.
3961 * Do not insert any td of the urb to the ring if the check failed.
3963 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3964 num_trbs
, mem_flags
);
3968 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3969 start_frame
&= 0x3fff;
3971 urb
->start_frame
= start_frame
;
3972 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3973 urb
->dev
->speed
== USB_SPEED_FULL
)
3974 urb
->start_frame
>>= 3;
3976 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3977 ep_interval
= urb
->interval
;
3978 /* Convert to microframes */
3979 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3980 urb
->dev
->speed
== USB_SPEED_FULL
)
3982 /* FIXME change this to a warning and a suggestion to use the new API
3983 * to set the polling interval (once the API is added).
3985 if (xhci_interval
!= ep_interval
) {
3986 if (printk_ratelimit())
3987 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3988 " (%d microframe%s) than xHCI "
3989 "(%d microframe%s)\n",
3991 ep_interval
== 1 ? "" : "s",
3993 xhci_interval
== 1 ? "" : "s");
3994 urb
->interval
= xhci_interval
;
3995 /* Convert back to frames for LS/FS devices */
3996 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3997 urb
->dev
->speed
== USB_SPEED_FULL
)
4000 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
4002 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
4005 /**** Command Ring Operations ****/
4007 /* Generic function for queueing a command TRB on the command ring.
4008 * Check to make sure there's room on the command ring for one command TRB.
4009 * Also check that there's room reserved for commands that must not fail.
4010 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
4011 * then only check for the number of reserved spots.
4012 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
4013 * because the command event handler may want to resubmit a failed command.
4015 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
4016 u32 field3
, u32 field4
, bool command_must_succeed
)
4018 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
4021 if (!command_must_succeed
)
4024 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
4025 reserved_trbs
, GFP_ATOMIC
);
4027 xhci_err(xhci
, "ERR: No room for command on command ring\n");
4028 if (command_must_succeed
)
4029 xhci_err(xhci
, "ERR: Reserved TRB counting for "
4030 "unfailable commands failed.\n");
4033 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
4034 field4
| xhci
->cmd_ring
->cycle_state
);
4038 /* Queue a slot enable or disable request on the command ring */
4039 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
4041 return queue_command(xhci
, 0, 0, 0,
4042 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
4045 /* Queue an address device command TRB */
4046 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
4049 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
4050 upper_32_bits(in_ctx_ptr
), 0,
4051 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
4055 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
4056 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
4058 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
4061 /* Queue a reset device command TRB */
4062 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
4064 return queue_command(xhci
, 0, 0, 0,
4065 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
4069 /* Queue a configure endpoint command TRB */
4070 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
4071 u32 slot_id
, bool command_must_succeed
)
4073 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
4074 upper_32_bits(in_ctx_ptr
), 0,
4075 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
4076 command_must_succeed
);
4079 /* Queue an evaluate context command TRB */
4080 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
4081 u32 slot_id
, bool command_must_succeed
)
4083 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
4084 upper_32_bits(in_ctx_ptr
), 0,
4085 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
4086 command_must_succeed
);
4090 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
4091 * activity on an endpoint that is about to be suspended.
4093 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
4094 unsigned int ep_index
, int suspend
)
4096 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4097 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4098 u32 type
= TRB_TYPE(TRB_STOP_RING
);
4099 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
4101 return queue_command(xhci
, 0, 0, 0,
4102 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
4105 /* Set Transfer Ring Dequeue Pointer command.
4106 * This should not be used for endpoints that have streams enabled.
4108 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
4109 unsigned int ep_index
, unsigned int stream_id
,
4110 struct xhci_segment
*deq_seg
,
4111 union xhci_trb
*deq_ptr
, u32 cycle_state
)
4114 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4115 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4116 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
4117 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
4118 struct xhci_virt_ep
*ep
;
4120 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
4122 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4123 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
4127 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
4128 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
4129 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4130 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
4133 ep
->queued_deq_seg
= deq_seg
;
4134 ep
->queued_deq_ptr
= deq_ptr
;
4135 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
4136 upper_32_bits(addr
), trb_stream_id
,
4137 trb_slot_id
| trb_ep_index
| type
, false);
4140 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
4141 unsigned int ep_index
)
4143 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4144 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4145 u32 type
= TRB_TYPE(TRB_RESET_EP
);
4147 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,