2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/hardirq.h>
11 #include <linux/init.h>
12 #include <linux/highmem.h>
13 #include <linux/kernel.h>
14 #include <linux/linkage.h>
15 #include <linux/preempt.h>
16 #include <linux/sched.h>
17 #include <linux/smp.h>
19 #include <linux/module.h>
20 #include <linux/bitops.h>
22 #include <asm/bcache.h>
23 #include <asm/bootinfo.h>
24 #include <asm/cache.h>
25 #include <asm/cacheops.h>
27 #include <asm/cpu-features.h>
30 #include <asm/pgtable.h>
31 #include <asm/r4kcache.h>
32 #include <asm/sections.h>
33 #include <asm/mmu_context.h>
35 #include <asm/cacheflush.h> /* for run_uncached() */
36 #include <asm/traps.h>
37 #include <asm/dma-coherence.h>
40 * Special Variant of smp_call_function for use by cache functions:
43 * o collapses to normal function call on UP kernels
44 * o collapses to normal function call on systems with a single shared
46 * o doesn't disable interrupts on the local CPU
48 static inline void r4k_on_each_cpu(void (*func
) (void *info
), void *info
)
52 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
53 smp_call_function(func
, info
, 1);
59 #if defined(CONFIG_MIPS_CMP)
60 #define cpu_has_safe_index_cacheops 0
62 #define cpu_has_safe_index_cacheops 1
68 static unsigned long icache_size __read_mostly
;
69 static unsigned long dcache_size __read_mostly
;
70 static unsigned long scache_size __read_mostly
;
73 * Dummy cache handling routines for machines without boardcaches
75 static void cache_noop(void) {}
77 static struct bcache_ops no_sc_ops
= {
78 .bc_enable
= (void *)cache_noop
,
79 .bc_disable
= (void *)cache_noop
,
80 .bc_wback_inv
= (void *)cache_noop
,
81 .bc_inv
= (void *)cache_noop
84 struct bcache_ops
*bcops
= &no_sc_ops
;
86 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
87 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
89 #define R4600_HIT_CACHEOP_WAR_IMPL \
91 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
92 *(volatile unsigned long *)CKSEG1; \
93 if (R4600_V1_HIT_CACHEOP_WAR) \
94 __asm__ __volatile__("nop;nop;nop;nop"); \
97 static void (*r4k_blast_dcache_page
)(unsigned long addr
);
99 static inline void r4k_blast_dcache_page_dc32(unsigned long addr
)
101 R4600_HIT_CACHEOP_WAR_IMPL
;
102 blast_dcache32_page(addr
);
105 static inline void r4k_blast_dcache_page_dc64(unsigned long addr
)
107 R4600_HIT_CACHEOP_WAR_IMPL
;
108 blast_dcache64_page(addr
);
111 static void __cpuinit
r4k_blast_dcache_page_setup(void)
113 unsigned long dc_lsize
= cpu_dcache_line_size();
116 r4k_blast_dcache_page
= (void *)cache_noop
;
117 else if (dc_lsize
== 16)
118 r4k_blast_dcache_page
= blast_dcache16_page
;
119 else if (dc_lsize
== 32)
120 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc32
;
121 else if (dc_lsize
== 64)
122 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc64
;
125 static void (* r4k_blast_dcache_page_indexed
)(unsigned long addr
);
127 static void __cpuinit
r4k_blast_dcache_page_indexed_setup(void)
129 unsigned long dc_lsize
= cpu_dcache_line_size();
132 r4k_blast_dcache_page_indexed
= (void *)cache_noop
;
133 else if (dc_lsize
== 16)
134 r4k_blast_dcache_page_indexed
= blast_dcache16_page_indexed
;
135 else if (dc_lsize
== 32)
136 r4k_blast_dcache_page_indexed
= blast_dcache32_page_indexed
;
137 else if (dc_lsize
== 64)
138 r4k_blast_dcache_page_indexed
= blast_dcache64_page_indexed
;
141 void (* r4k_blast_dcache
)(void);
142 EXPORT_SYMBOL(r4k_blast_dcache
);
144 static void __cpuinit
r4k_blast_dcache_setup(void)
146 unsigned long dc_lsize
= cpu_dcache_line_size();
149 r4k_blast_dcache
= (void *)cache_noop
;
150 else if (dc_lsize
== 16)
151 r4k_blast_dcache
= blast_dcache16
;
152 else if (dc_lsize
== 32)
153 r4k_blast_dcache
= blast_dcache32
;
154 else if (dc_lsize
== 64)
155 r4k_blast_dcache
= blast_dcache64
;
158 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
159 #define JUMP_TO_ALIGN(order) \
160 __asm__ __volatile__( \
162 ".align\t" #order "\n\t" \
165 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
166 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
168 static inline void blast_r4600_v1_icache32(void)
172 local_irq_save(flags
);
174 local_irq_restore(flags
);
177 static inline void tx49_blast_icache32(void)
179 unsigned long start
= INDEX_BASE
;
180 unsigned long end
= start
+ current_cpu_data
.icache
.waysize
;
181 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
182 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
183 current_cpu_data
.icache
.waybit
;
184 unsigned long ws
, addr
;
186 CACHE32_UNROLL32_ALIGN2
;
187 /* I'm in even chunk. blast odd chunks */
188 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
189 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
190 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
191 CACHE32_UNROLL32_ALIGN
;
192 /* I'm in odd chunk. blast even chunks */
193 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
194 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
195 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
198 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page
)
202 local_irq_save(flags
);
203 blast_icache32_page_indexed(page
);
204 local_irq_restore(flags
);
207 static inline void tx49_blast_icache32_page_indexed(unsigned long page
)
209 unsigned long indexmask
= current_cpu_data
.icache
.waysize
- 1;
210 unsigned long start
= INDEX_BASE
+ (page
& indexmask
);
211 unsigned long end
= start
+ PAGE_SIZE
;
212 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
213 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
214 current_cpu_data
.icache
.waybit
;
215 unsigned long ws
, addr
;
217 CACHE32_UNROLL32_ALIGN2
;
218 /* I'm in even chunk. blast odd chunks */
219 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
220 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
221 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
222 CACHE32_UNROLL32_ALIGN
;
223 /* I'm in odd chunk. blast even chunks */
224 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
225 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
226 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
229 static void (* r4k_blast_icache_page
)(unsigned long addr
);
231 static void __cpuinit
r4k_blast_icache_page_setup(void)
233 unsigned long ic_lsize
= cpu_icache_line_size();
236 r4k_blast_icache_page
= (void *)cache_noop
;
237 else if (ic_lsize
== 16)
238 r4k_blast_icache_page
= blast_icache16_page
;
239 else if (ic_lsize
== 32)
240 r4k_blast_icache_page
= blast_icache32_page
;
241 else if (ic_lsize
== 64)
242 r4k_blast_icache_page
= blast_icache64_page
;
246 static void (* r4k_blast_icache_page_indexed
)(unsigned long addr
);
248 static void __cpuinit
r4k_blast_icache_page_indexed_setup(void)
250 unsigned long ic_lsize
= cpu_icache_line_size();
253 r4k_blast_icache_page_indexed
= (void *)cache_noop
;
254 else if (ic_lsize
== 16)
255 r4k_blast_icache_page_indexed
= blast_icache16_page_indexed
;
256 else if (ic_lsize
== 32) {
257 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
258 r4k_blast_icache_page_indexed
=
259 blast_icache32_r4600_v1_page_indexed
;
260 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
261 r4k_blast_icache_page_indexed
=
262 tx49_blast_icache32_page_indexed
;
264 r4k_blast_icache_page_indexed
=
265 blast_icache32_page_indexed
;
266 } else if (ic_lsize
== 64)
267 r4k_blast_icache_page_indexed
= blast_icache64_page_indexed
;
270 void (* r4k_blast_icache
)(void);
271 EXPORT_SYMBOL(r4k_blast_icache
);
273 static void __cpuinit
r4k_blast_icache_setup(void)
275 unsigned long ic_lsize
= cpu_icache_line_size();
278 r4k_blast_icache
= (void *)cache_noop
;
279 else if (ic_lsize
== 16)
280 r4k_blast_icache
= blast_icache16
;
281 else if (ic_lsize
== 32) {
282 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
283 r4k_blast_icache
= blast_r4600_v1_icache32
;
284 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
285 r4k_blast_icache
= tx49_blast_icache32
;
287 r4k_blast_icache
= blast_icache32
;
288 } else if (ic_lsize
== 64)
289 r4k_blast_icache
= blast_icache64
;
292 static void (* r4k_blast_scache_page
)(unsigned long addr
);
294 static void __cpuinit
r4k_blast_scache_page_setup(void)
296 unsigned long sc_lsize
= cpu_scache_line_size();
298 if (scache_size
== 0)
299 r4k_blast_scache_page
= (void *)cache_noop
;
300 else if (sc_lsize
== 16)
301 r4k_blast_scache_page
= blast_scache16_page
;
302 else if (sc_lsize
== 32)
303 r4k_blast_scache_page
= blast_scache32_page
;
304 else if (sc_lsize
== 64)
305 r4k_blast_scache_page
= blast_scache64_page
;
306 else if (sc_lsize
== 128)
307 r4k_blast_scache_page
= blast_scache128_page
;
310 static void (* r4k_blast_scache_page_indexed
)(unsigned long addr
);
312 static void __cpuinit
r4k_blast_scache_page_indexed_setup(void)
314 unsigned long sc_lsize
= cpu_scache_line_size();
316 if (scache_size
== 0)
317 r4k_blast_scache_page_indexed
= (void *)cache_noop
;
318 else if (sc_lsize
== 16)
319 r4k_blast_scache_page_indexed
= blast_scache16_page_indexed
;
320 else if (sc_lsize
== 32)
321 r4k_blast_scache_page_indexed
= blast_scache32_page_indexed
;
322 else if (sc_lsize
== 64)
323 r4k_blast_scache_page_indexed
= blast_scache64_page_indexed
;
324 else if (sc_lsize
== 128)
325 r4k_blast_scache_page_indexed
= blast_scache128_page_indexed
;
328 static void (* r4k_blast_scache
)(void);
330 static void __cpuinit
r4k_blast_scache_setup(void)
332 unsigned long sc_lsize
= cpu_scache_line_size();
334 if (scache_size
== 0)
335 r4k_blast_scache
= (void *)cache_noop
;
336 else if (sc_lsize
== 16)
337 r4k_blast_scache
= blast_scache16
;
338 else if (sc_lsize
== 32)
339 r4k_blast_scache
= blast_scache32
;
340 else if (sc_lsize
== 64)
341 r4k_blast_scache
= blast_scache64
;
342 else if (sc_lsize
== 128)
343 r4k_blast_scache
= blast_scache128
;
346 static inline void local_r4k___flush_cache_all(void * args
)
348 #if defined(CONFIG_CPU_LOONGSON2)
355 switch (current_cpu_type()) {
367 static void r4k___flush_cache_all(void)
369 r4k_on_each_cpu(local_r4k___flush_cache_all
, NULL
);
372 static inline int has_valid_asid(const struct mm_struct
*mm
)
374 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
377 for_each_online_cpu(i
)
378 if (cpu_context(i
, mm
))
383 return cpu_context(smp_processor_id(), mm
);
387 static void r4k__flush_cache_vmap(void)
392 static void r4k__flush_cache_vunmap(void)
397 static inline void local_r4k_flush_cache_range(void * args
)
399 struct vm_area_struct
*vma
= args
;
400 int exec
= vma
->vm_flags
& VM_EXEC
;
402 if (!(has_valid_asid(vma
->vm_mm
)))
410 static void r4k_flush_cache_range(struct vm_area_struct
*vma
,
411 unsigned long start
, unsigned long end
)
413 int exec
= vma
->vm_flags
& VM_EXEC
;
415 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
))
416 r4k_on_each_cpu(local_r4k_flush_cache_range
, vma
);
419 static inline void local_r4k_flush_cache_mm(void * args
)
421 struct mm_struct
*mm
= args
;
423 if (!has_valid_asid(mm
))
427 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
428 * only flush the primary caches but R10000 and R12000 behave sane ...
429 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
430 * caches, so we can bail out early.
432 if (current_cpu_type() == CPU_R4000SC
||
433 current_cpu_type() == CPU_R4000MC
||
434 current_cpu_type() == CPU_R4400SC
||
435 current_cpu_type() == CPU_R4400MC
) {
443 static void r4k_flush_cache_mm(struct mm_struct
*mm
)
445 if (!cpu_has_dc_aliases
)
448 r4k_on_each_cpu(local_r4k_flush_cache_mm
, mm
);
451 struct flush_cache_page_args
{
452 struct vm_area_struct
*vma
;
457 static inline void local_r4k_flush_cache_page(void *args
)
459 struct flush_cache_page_args
*fcp_args
= args
;
460 struct vm_area_struct
*vma
= fcp_args
->vma
;
461 unsigned long addr
= fcp_args
->addr
;
462 struct page
*page
= pfn_to_page(fcp_args
->pfn
);
463 int exec
= vma
->vm_flags
& VM_EXEC
;
464 struct mm_struct
*mm
= vma
->vm_mm
;
465 int map_coherent
= 0;
473 * If ownes no valid ASID yet, cannot possibly have gotten
474 * this page into the cache.
476 if (!has_valid_asid(mm
))
480 pgdp
= pgd_offset(mm
, addr
);
481 pudp
= pud_offset(pgdp
, addr
);
482 pmdp
= pmd_offset(pudp
, addr
);
483 ptep
= pte_offset(pmdp
, addr
);
486 * If the page isn't marked valid, the page cannot possibly be
489 if (!(pte_present(*ptep
)))
492 if ((mm
== current
->active_mm
) && (pte_val(*ptep
) & _PAGE_VALID
))
496 * Use kmap_coherent or kmap_atomic to do flushes for
497 * another ASID than the current one.
499 map_coherent
= (cpu_has_dc_aliases
&&
500 page_mapped(page
) && !Page_dcache_dirty(page
));
502 vaddr
= kmap_coherent(page
, addr
);
504 vaddr
= kmap_atomic(page
);
505 addr
= (unsigned long)vaddr
;
508 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
509 r4k_blast_dcache_page(addr
);
510 if (exec
&& !cpu_icache_snoops_remote_store
)
511 r4k_blast_scache_page(addr
);
514 if (vaddr
&& cpu_has_vtag_icache
&& mm
== current
->active_mm
) {
515 int cpu
= smp_processor_id();
517 if (cpu_context(cpu
, mm
) != 0)
518 drop_mmu_context(mm
, cpu
);
520 r4k_blast_icache_page(addr
);
527 kunmap_atomic(vaddr
);
531 static void r4k_flush_cache_page(struct vm_area_struct
*vma
,
532 unsigned long addr
, unsigned long pfn
)
534 struct flush_cache_page_args args
;
540 r4k_on_each_cpu(local_r4k_flush_cache_page
, &args
);
543 static inline void local_r4k_flush_data_cache_page(void * addr
)
545 r4k_blast_dcache_page((unsigned long) addr
);
548 static void r4k_flush_data_cache_page(unsigned long addr
)
551 local_r4k_flush_data_cache_page((void *)addr
);
553 r4k_on_each_cpu(local_r4k_flush_data_cache_page
, (void *) addr
);
556 struct flush_icache_range_args
{
561 static inline void local_r4k_flush_icache_range(unsigned long start
, unsigned long end
)
563 if (!cpu_has_ic_fills_f_dc
) {
564 if (end
- start
>= dcache_size
) {
567 R4600_HIT_CACHEOP_WAR_IMPL
;
568 protected_blast_dcache_range(start
, end
);
572 if (end
- start
> icache_size
)
575 protected_blast_icache_range(start
, end
);
578 static inline void local_r4k_flush_icache_range_ipi(void *args
)
580 struct flush_icache_range_args
*fir_args
= args
;
581 unsigned long start
= fir_args
->start
;
582 unsigned long end
= fir_args
->end
;
584 local_r4k_flush_icache_range(start
, end
);
587 static void r4k_flush_icache_range(unsigned long start
, unsigned long end
)
589 struct flush_icache_range_args args
;
594 r4k_on_each_cpu(local_r4k_flush_icache_range_ipi
, &args
);
595 instruction_hazard();
598 #ifdef CONFIG_DMA_NONCOHERENT
600 static void r4k_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
602 /* Catch bad driver code */
606 if (cpu_has_inclusive_pcaches
) {
607 if (size
>= scache_size
)
610 blast_scache_range(addr
, addr
+ size
);
616 * Either no secondary cache or the available caches don't have the
617 * subset property so we have to flush the primary caches
620 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
) {
623 R4600_HIT_CACHEOP_WAR_IMPL
;
624 blast_dcache_range(addr
, addr
+ size
);
628 bc_wback_inv(addr
, size
);
632 static void r4k_dma_cache_inv(unsigned long addr
, unsigned long size
)
634 /* Catch bad driver code */
638 if (cpu_has_inclusive_pcaches
) {
639 if (size
>= scache_size
)
643 * There is no clearly documented alignment requirement
644 * for the cache instruction on MIPS processors and
645 * some processors, among them the RM5200 and RM7000
646 * QED processors will throw an address error for cache
647 * hit ops with insufficient alignment. Solved by
648 * aligning the address to cache line size.
650 blast_inv_scache_range(addr
, addr
+ size
);
656 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
) {
659 R4600_HIT_CACHEOP_WAR_IMPL
;
660 blast_inv_dcache_range(addr
, addr
+ size
);
667 #endif /* CONFIG_DMA_NONCOHERENT */
670 * While we're protected against bad userland addresses we don't care
671 * very much about what happens in that case. Usually a segmentation
672 * fault will dump the process later on anyway ...
674 static void local_r4k_flush_cache_sigtramp(void * arg
)
676 unsigned long ic_lsize
= cpu_icache_line_size();
677 unsigned long dc_lsize
= cpu_dcache_line_size();
678 unsigned long sc_lsize
= cpu_scache_line_size();
679 unsigned long addr
= (unsigned long) arg
;
681 R4600_HIT_CACHEOP_WAR_IMPL
;
683 protected_writeback_dcache_line(addr
& ~(dc_lsize
- 1));
684 if (!cpu_icache_snoops_remote_store
&& scache_size
)
685 protected_writeback_scache_line(addr
& ~(sc_lsize
- 1));
687 protected_flush_icache_line(addr
& ~(ic_lsize
- 1));
688 if (MIPS4K_ICACHE_REFILL_WAR
) {
689 __asm__
__volatile__ (
704 : "i" (Hit_Invalidate_I
));
706 if (MIPS_CACHE_SYNC_WAR
)
707 __asm__
__volatile__ ("sync");
710 static void r4k_flush_cache_sigtramp(unsigned long addr
)
712 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp
, (void *) addr
);
715 static void r4k_flush_icache_all(void)
717 if (cpu_has_vtag_icache
)
721 struct flush_kernel_vmap_range_args
{
726 static inline void local_r4k_flush_kernel_vmap_range(void *args
)
728 struct flush_kernel_vmap_range_args
*vmra
= args
;
729 unsigned long vaddr
= vmra
->vaddr
;
730 int size
= vmra
->size
;
733 * Aliases only affect the primary caches so don't bother with
734 * S-caches or T-caches.
736 if (cpu_has_safe_index_cacheops
&& size
>= dcache_size
)
739 R4600_HIT_CACHEOP_WAR_IMPL
;
740 blast_dcache_range(vaddr
, vaddr
+ size
);
744 static void r4k_flush_kernel_vmap_range(unsigned long vaddr
, int size
)
746 struct flush_kernel_vmap_range_args args
;
748 args
.vaddr
= (unsigned long) vaddr
;
751 r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range
, &args
);
754 static inline void rm7k_erratum31(void)
756 const unsigned long ic_lsize
= 32;
759 /* RM7000 erratum #31. The icache is screwed at startup. */
763 for (addr
= INDEX_BASE
; addr
<= INDEX_BASE
+ 4096; addr
+= ic_lsize
) {
764 __asm__
__volatile__ (
768 "cache\t%1, 0(%0)\n\t"
769 "cache\t%1, 0x1000(%0)\n\t"
770 "cache\t%1, 0x2000(%0)\n\t"
771 "cache\t%1, 0x3000(%0)\n\t"
772 "cache\t%2, 0(%0)\n\t"
773 "cache\t%2, 0x1000(%0)\n\t"
774 "cache\t%2, 0x2000(%0)\n\t"
775 "cache\t%2, 0x3000(%0)\n\t"
776 "cache\t%1, 0(%0)\n\t"
777 "cache\t%1, 0x1000(%0)\n\t"
778 "cache\t%1, 0x2000(%0)\n\t"
779 "cache\t%1, 0x3000(%0)\n\t"
782 : "r" (addr
), "i" (Index_Store_Tag_I
), "i" (Fill
));
786 static inline void alias_74k_erratum(struct cpuinfo_mips
*c
)
789 * Early versions of the 74K do not update the cache tags on a
790 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
791 * aliases. In this case it is better to treat the cache as always
794 if ((c
->processor_id
& 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
795 c
->dcache
.flags
|= MIPS_CACHE_VTAG
;
796 if ((c
->processor_id
& 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
797 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND
);
798 if (((c
->processor_id
& 0xff00) == PRID_IMP_1074K
) &&
799 ((c
->processor_id
& 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
800 c
->dcache
.flags
|= MIPS_CACHE_VTAG
;
801 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND
);
805 static char *way_string
[] __cpuinitdata
= { NULL
, "direct mapped", "2-way",
806 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
809 static void __cpuinit
probe_pcache(void)
811 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
812 unsigned int config
= read_c0_config();
813 unsigned int prid
= read_c0_prid();
814 unsigned long config1
;
817 switch (c
->cputype
) {
818 case CPU_R4600
: /* QED style two way caches? */
822 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
823 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
825 c
->icache
.waybit
= __ffs(icache_size
/2);
827 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
828 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
830 c
->dcache
.waybit
= __ffs(dcache_size
/2);
832 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
837 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
838 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
842 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
843 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
845 c
->dcache
.waybit
= 0;
847 c
->options
|= MIPS_CPU_CACHE_CDEX_P
| MIPS_CPU_PREFETCH
;
851 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
852 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
856 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
857 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
859 c
->dcache
.waybit
= 0;
861 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
862 c
->options
|= MIPS_CPU_PREFETCH
;
872 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
873 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
875 c
->icache
.waybit
= 0; /* doesn't matter */
877 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
878 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
880 c
->dcache
.waybit
= 0; /* does not matter */
882 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
888 icache_size
= 1 << (12 + ((config
& R10K_CONF_IC
) >> 29));
889 c
->icache
.linesz
= 64;
891 c
->icache
.waybit
= 0;
893 dcache_size
= 1 << (12 + ((config
& R10K_CONF_DC
) >> 26));
894 c
->dcache
.linesz
= 32;
896 c
->dcache
.waybit
= 0;
898 c
->options
|= MIPS_CPU_PREFETCH
;
902 write_c0_config(config
& ~VR41_CONF_P4K
);
904 /* Workaround for cache instruction bug of VR4131 */
905 if (c
->processor_id
== 0x0c80U
|| c
->processor_id
== 0x0c81U
||
906 c
->processor_id
== 0x0c82U
) {
907 config
|= 0x00400000U
;
908 if (c
->processor_id
== 0x0c80U
)
909 config
|= VR41_CONF_BP
;
910 write_c0_config(config
);
912 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
914 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
915 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
917 c
->icache
.waybit
= __ffs(icache_size
/2);
919 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
920 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
922 c
->dcache
.waybit
= __ffs(dcache_size
/2);
931 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
932 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
934 c
->icache
.waybit
= 0; /* doesn't matter */
936 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
937 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
939 c
->dcache
.waybit
= 0; /* does not matter */
941 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
947 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
948 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
950 c
->icache
.waybit
= __ffs(icache_size
/ c
->icache
.ways
);
952 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
953 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
955 c
->dcache
.waybit
= __ffs(dcache_size
/ c
->dcache
.ways
);
957 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
958 c
->options
|= MIPS_CPU_PREFETCH
;
962 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
963 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
968 c
->icache
.waybit
= 0;
970 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
971 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
976 c
->dcache
.waybit
= 0;
980 if (!(config
& MIPS_CONF_M
))
981 panic("Don't know how to probe P-caches on this cpu.");
984 * So we seem to be a MIPS32 or MIPS64 CPU
985 * So let's probe the I-cache ...
987 config1
= read_c0_config1();
989 if ((lsize
= ((config1
>> 19) & 7)))
990 c
->icache
.linesz
= 2 << lsize
;
992 c
->icache
.linesz
= lsize
;
993 c
->icache
.sets
= 32 << (((config1
>> 22) + 1) & 7);
994 c
->icache
.ways
= 1 + ((config1
>> 16) & 7);
996 icache_size
= c
->icache
.sets
*
999 c
->icache
.waybit
= __ffs(icache_size
/c
->icache
.ways
);
1001 if (config
& 0x8) /* VI bit */
1002 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
1005 * Now probe the MIPS32 / MIPS64 data cache.
1007 c
->dcache
.flags
= 0;
1009 if ((lsize
= ((config1
>> 10) & 7)))
1010 c
->dcache
.linesz
= 2 << lsize
;
1012 c
->dcache
.linesz
= lsize
;
1013 c
->dcache
.sets
= 32 << (((config1
>> 13) + 1) & 7);
1014 c
->dcache
.ways
= 1 + ((config1
>> 7) & 7);
1016 dcache_size
= c
->dcache
.sets
*
1019 c
->dcache
.waybit
= __ffs(dcache_size
/c
->dcache
.ways
);
1021 c
->options
|= MIPS_CPU_PREFETCH
;
1026 * Processor configuration sanity check for the R4000SC erratum
1027 * #5. With page sizes larger than 32kB there is no possibility
1028 * to get a VCE exception anymore so we don't care about this
1029 * misconfiguration. The case is rather theoretical anyway;
1030 * presumably no vendor is shipping his hardware in the "bad"
1033 if ((prid
& 0xff00) == PRID_IMP_R4000
&& (prid
& 0xff) < 0x40 &&
1034 !(config
& CONF_SC
) && c
->icache
.linesz
!= 16 &&
1035 PAGE_SIZE
<= 0x8000)
1036 panic("Improper R4000SC processor configuration detected");
1038 /* compute a couple of other cache variables */
1039 c
->icache
.waysize
= icache_size
/ c
->icache
.ways
;
1040 c
->dcache
.waysize
= dcache_size
/ c
->dcache
.ways
;
1042 c
->icache
.sets
= c
->icache
.linesz
?
1043 icache_size
/ (c
->icache
.linesz
* c
->icache
.ways
) : 0;
1044 c
->dcache
.sets
= c
->dcache
.linesz
?
1045 dcache_size
/ (c
->dcache
.linesz
* c
->dcache
.ways
) : 0;
1048 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
1049 * 2-way virtually indexed so normally would suffer from aliases. So
1050 * normally they'd suffer from aliases but magic in the hardware deals
1051 * with that for us so we don't need to take care ourselves.
1053 switch (c
->cputype
) {
1059 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
1073 if (c
->cputype
== CPU_74K
)
1074 alias_74k_erratum(c
);
1075 if ((read_c0_config7() & (1 << 16))) {
1076 /* effectively physically indexed dcache,
1077 thus no virtual aliases. */
1078 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
1082 if (c
->dcache
.waysize
> PAGE_SIZE
)
1083 c
->dcache
.flags
|= MIPS_CACHE_ALIASES
;
1086 switch (c
->cputype
) {
1089 * Some older 20Kc chips doesn't have the 'VI' bit in
1090 * the config register.
1092 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
1096 c
->icache
.flags
|= MIPS_CACHE_IC_F_DC
;
1100 #ifdef CONFIG_CPU_LOONGSON2
1102 * LOONGSON2 has 4 way icache, but when using indexed cache op,
1103 * one op will act on all 4 ways
1108 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1110 c
->icache
.flags
& MIPS_CACHE_VTAG
? "VIVT" : "VIPT",
1111 way_string
[c
->icache
.ways
], c
->icache
.linesz
);
1113 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1114 dcache_size
>> 10, way_string
[c
->dcache
.ways
],
1115 (c
->dcache
.flags
& MIPS_CACHE_PINDEX
) ? "PIPT" : "VIPT",
1116 (c
->dcache
.flags
& MIPS_CACHE_ALIASES
) ?
1117 "cache aliases" : "no aliases",
1122 * If you even _breathe_ on this function, look at the gcc output and make sure
1123 * it does not pop things on and off the stack for the cache sizing loop that
1124 * executes in KSEG1 space or else you will crash and burn badly. You have
1127 static int __cpuinit
probe_scache(void)
1129 unsigned long flags
, addr
, begin
, end
, pow2
;
1130 unsigned int config
= read_c0_config();
1131 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1133 if (config
& CONF_SC
)
1136 begin
= (unsigned long) &_stext
;
1137 begin
&= ~((4 * 1024 * 1024) - 1);
1138 end
= begin
+ (4 * 1024 * 1024);
1141 * This is such a bitch, you'd think they would make it easy to do
1142 * this. Away you daemons of stupidity!
1144 local_irq_save(flags
);
1146 /* Fill each size-multiple cache line with a valid tag. */
1148 for (addr
= begin
; addr
< end
; addr
= (begin
+ pow2
)) {
1149 unsigned long *p
= (unsigned long *) addr
;
1150 __asm__
__volatile__("nop" : : "r" (*p
)); /* whee... */
1154 /* Load first line with zero (therefore invalid) tag. */
1157 __asm__
__volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1158 cache_op(Index_Store_Tag_I
, begin
);
1159 cache_op(Index_Store_Tag_D
, begin
);
1160 cache_op(Index_Store_Tag_SD
, begin
);
1162 /* Now search for the wrap around point. */
1163 pow2
= (128 * 1024);
1164 for (addr
= begin
+ (128 * 1024); addr
< end
; addr
= begin
+ pow2
) {
1165 cache_op(Index_Load_Tag_SD
, addr
);
1166 __asm__
__volatile__("nop; nop; nop; nop;"); /* hazard... */
1167 if (!read_c0_taglo())
1171 local_irq_restore(flags
);
1175 c
->scache
.linesz
= 16 << ((config
& R4K_CONF_SB
) >> 22);
1177 c
->dcache
.waybit
= 0; /* does not matter */
1182 #if defined(CONFIG_CPU_LOONGSON2)
1183 static void __init
loongson2_sc_init(void)
1185 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1187 scache_size
= 512*1024;
1188 c
->scache
.linesz
= 32;
1190 c
->scache
.waybit
= 0;
1191 c
->scache
.waysize
= scache_size
/ (c
->scache
.ways
);
1192 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1193 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1194 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1196 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1200 extern int r5k_sc_init(void);
1201 extern int rm7k_sc_init(void);
1202 extern int mips_sc_init(void);
1204 static void __cpuinit
setup_scache(void)
1206 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1207 unsigned int config
= read_c0_config();
1211 * Do the probing thing on R4000SC and R4400SC processors. Other
1212 * processors don't have a S-cache that would be relevant to the
1213 * Linux memory management.
1215 switch (c
->cputype
) {
1220 sc_present
= run_uncached(probe_scache
);
1222 c
->options
|= MIPS_CPU_CACHE_CDEX_S
;
1228 scache_size
= 0x80000 << ((config
& R10K_CONF_SS
) >> 16);
1229 c
->scache
.linesz
= 64 << ((config
>> 13) & 1);
1231 c
->scache
.waybit
= 0;
1237 #ifdef CONFIG_R5000_CPU_SCACHE
1243 #ifdef CONFIG_RM7000_CPU_SCACHE
1248 #if defined(CONFIG_CPU_LOONGSON2)
1250 loongson2_sc_init();
1254 /* don't need to worry about L2, fully coherent */
1258 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M32R2
|
1259 MIPS_CPU_ISA_M64R1
| MIPS_CPU_ISA_M64R2
)) {
1260 #ifdef CONFIG_MIPS_CPU_SCACHE
1261 if (mips_sc_init ()) {
1262 scache_size
= c
->scache
.ways
* c
->scache
.sets
* c
->scache
.linesz
;
1263 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1265 way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1268 if (!(c
->scache
.flags
& MIPS_CACHE_NOT_PRESENT
))
1269 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1279 /* compute a couple of other cache variables */
1280 c
->scache
.waysize
= scache_size
/ c
->scache
.ways
;
1282 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1284 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1285 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1287 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1290 void au1x00_fixup_config_od(void)
1293 * c0_config.od (bit 19) was write only (and read as 0)
1294 * on the early revisions of Alchemy SOCs. It disables the bus
1295 * transaction overlapping and needs to be set to fix various errata.
1297 switch (read_c0_prid()) {
1298 case 0x00030100: /* Au1000 DA */
1299 case 0x00030201: /* Au1000 HA */
1300 case 0x00030202: /* Au1000 HB */
1301 case 0x01030200: /* Au1500 AB */
1303 * Au1100 errata actually keeps silence about this bit, so we set it
1304 * just in case for those revisions that require it to be set according
1305 * to the (now gone) cpu table.
1307 case 0x02030200: /* Au1100 AB */
1308 case 0x02030201: /* Au1100 BA */
1309 case 0x02030202: /* Au1100 BC */
1310 set_c0_config(1 << 19);
1315 /* CP0 hazard avoidance. */
1316 #define NXP_BARRIER() \
1317 __asm__ __volatile__( \
1318 ".set noreorder\n\t" \
1319 "nop; nop; nop; nop; nop; nop;\n\t" \
1322 static void nxp_pr4450_fixup_config(void)
1324 unsigned long config0
;
1326 config0
= read_c0_config();
1328 /* clear all three cache coherency fields */
1329 config0
&= ~(0x7 | (7 << 25) | (7 << 28));
1330 config0
|= (((_page_cachable_default
>> _CACHE_SHIFT
) << 0) |
1331 ((_page_cachable_default
>> _CACHE_SHIFT
) << 25) |
1332 ((_page_cachable_default
>> _CACHE_SHIFT
) << 28));
1333 write_c0_config(config0
);
1337 static int __cpuinitdata cca
= -1;
1339 static int __init
cca_setup(char *str
)
1341 get_option(&str
, &cca
);
1346 early_param("cca", cca_setup
);
1348 static void __cpuinit
coherency_setup(void)
1350 if (cca
< 0 || cca
> 7)
1351 cca
= read_c0_config() & CONF_CM_CMASK
;
1352 _page_cachable_default
= cca
<< _CACHE_SHIFT
;
1354 pr_debug("Using cache attribute %d\n", cca
);
1355 change_c0_config(CONF_CM_CMASK
, cca
);
1358 * c0_status.cu=0 specifies that updates by the sc instruction use
1359 * the coherency mode specified by the TLB; 1 means cachable
1360 * coherent update on write will be used. Not all processors have
1361 * this bit and; some wire it to zero, others like Toshiba had the
1362 * silly idea of putting something else there ...
1364 switch (current_cpu_type()) {
1371 clear_c0_config(CONF_CU
);
1374 * We need to catch the early Alchemy SOCs with
1375 * the write-only co_config.od bit and set it back to one on:
1376 * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
1379 au1x00_fixup_config_od();
1382 case PRID_IMP_PR4450
:
1383 nxp_pr4450_fixup_config();
1388 static void __cpuinit
r4k_cache_error_setup(void)
1390 extern char __weak except_vec2_generic
;
1391 extern char __weak except_vec2_sb1
;
1392 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1394 switch (c
->cputype
) {
1397 set_uncached_handler(0x100, &except_vec2_sb1
, 0x80);
1401 set_uncached_handler(0x100, &except_vec2_generic
, 0x80);
1406 void __cpuinit
r4k_cache_init(void)
1408 extern void build_clear_page(void);
1409 extern void build_copy_page(void);
1410 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1415 r4k_blast_dcache_page_setup();
1416 r4k_blast_dcache_page_indexed_setup();
1417 r4k_blast_dcache_setup();
1418 r4k_blast_icache_page_setup();
1419 r4k_blast_icache_page_indexed_setup();
1420 r4k_blast_icache_setup();
1421 r4k_blast_scache_page_setup();
1422 r4k_blast_scache_page_indexed_setup();
1423 r4k_blast_scache_setup();
1426 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1427 * This code supports virtually indexed processors and will be
1428 * unnecessarily inefficient on physically indexed processors.
1430 if (c
->dcache
.linesz
)
1431 shm_align_mask
= max_t( unsigned long,
1432 c
->dcache
.sets
* c
->dcache
.linesz
- 1,
1435 shm_align_mask
= PAGE_SIZE
-1;
1437 __flush_cache_vmap
= r4k__flush_cache_vmap
;
1438 __flush_cache_vunmap
= r4k__flush_cache_vunmap
;
1440 flush_cache_all
= cache_noop
;
1441 __flush_cache_all
= r4k___flush_cache_all
;
1442 flush_cache_mm
= r4k_flush_cache_mm
;
1443 flush_cache_page
= r4k_flush_cache_page
;
1444 flush_cache_range
= r4k_flush_cache_range
;
1446 __flush_kernel_vmap_range
= r4k_flush_kernel_vmap_range
;
1448 flush_cache_sigtramp
= r4k_flush_cache_sigtramp
;
1449 flush_icache_all
= r4k_flush_icache_all
;
1450 local_flush_data_cache_page
= local_r4k_flush_data_cache_page
;
1451 flush_data_cache_page
= r4k_flush_data_cache_page
;
1452 flush_icache_range
= r4k_flush_icache_range
;
1453 local_flush_icache_range
= local_r4k_flush_icache_range
;
1455 #if defined(CONFIG_DMA_NONCOHERENT)
1457 _dma_cache_wback_inv
= (void *)cache_noop
;
1458 _dma_cache_wback
= (void *)cache_noop
;
1459 _dma_cache_inv
= (void *)cache_noop
;
1461 _dma_cache_wback_inv
= r4k_dma_cache_wback_inv
;
1462 _dma_cache_wback
= r4k_dma_cache_wback_inv
;
1463 _dma_cache_inv
= r4k_dma_cache_inv
;
1471 * We want to run CMP kernels on core with and without coherent
1472 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1473 * or not to flush caches.
1475 local_r4k___flush_cache_all(NULL
);
1478 board_cache_error_setup
= r4k_cache_error_setup
;