arch/arm64/kernel/swp_emulate.c

   1 /*
   2  *  Derived from from linux/arch/arm/kernel/swp_emulate.c
   3  *
   4  *  Copyright (C) 2009 ARM Limited
   5  *  Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  Implements emulation of the SWP/SWPB instructions using load-exclusive and
  12  *  store-exclusive for processors that have them disabled (or future ones that
  13  *  might not implement them).
  14  *
  15  *  Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
  16  *  Where: Rt  = destination
  17  *         Rt2 = source
  18  *         Rn  = address
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/sched.h>
  26 #include <linux/syscalls.h>
  27 #include <linux/perf_event.h>
  28
  29 #include <asm/opcodes.h>
  30 #include <asm/traps.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/system_misc.h>
  33 #include <linux/debugfs.h>
  34
  35 /*
  36  * Error-checking SWP macros implemented using ldrex{b}/strex{b}
  37  */
  38
  39 static int swpb(u8 in, u8 *out, u8 *addr)
  40 {
  41         u8 _out;
  42         int res;
  43         int err;
  44
  45         do {
  46                 __asm__ __volatile__(
  47                 "0:     ldxrb   %w1, %4\n"
  48                 "1:     stxrb   %w0, %w3, %4\n"
  49                 "       mov     %w2, #0\n"
  50                 "2:\n"
  51                 "       .section         .fixup,\"ax\"\n"
  52                 "       .align          2\n"
  53                 "3:     mov     %w2, %5\n"
  54                 "       b       2b\n"
  55                 "       .previous\n"
  56                 "       .section         __ex_table,\"a\"\n"
  57                 "       .align          3\n"
  58                 "       .quad           0b, 3b\n"
  59                 "       .quad           1b, 3b\n"
  60                 "       .previous"
  61                 : "=&r" (res), "=r" (_out), "=r" (err)
  62                 : "r" (in), "Q" (*addr), "i" (-EFAULT)
  63                 : "cc", "memory");
  64         } while (err == 0 && res != 0);
  65
  66         if (err == 0)
  67                 *out = _out;
  68         return err;
  69 }
  70
  71 static int swp(u32 in, u32 *out, u32 *addr)
  72 {
  73         u32 _out;
  74         int res;
  75         int err = 0;
  76
  77         do {
  78                 __asm__ __volatile__(
  79                 "0:     ldxr    %w1, %4\n"
  80                 "1:     stxr    %w0, %w3, %4\n"
  81                 "       mov     %w2, #0\n"
  82                 "2:\n"
  83                 "       .section         .fixup,\"ax\"\n"
  84                 "       .align          2\n"
  85                 "3:     mov     %w2, %5\n"
  86                 "       b       2b\n"
  87                 "       .previous\n"
  88                 "       .section         __ex_table,\"a\"\n"
  89                 "       .align          3\n"
  90                 "       .quad           0b, 3b\n"
  91                 "       .quad           1b, 3b\n"
  92                 "       .previous"
  93                 : "=&r" (res), "=r" (_out), "=r" (err)
  94                 : "r" (in), "Q" (*addr), "i" (-EFAULT)
  95                 : "cc", "memory");
  96         } while (err == 0 && res != 0);
  97
  98         if (err == 0)
  99                 *out = _out;
 100         return err;
 101 }
 102 /*
 103  * Macros/defines for extracting register numbers from instruction.
 104  */
 105 #define EXTRACT_REG_NUM(instruction, offset) \
 106         (((instruction) & (0xf << (offset))) >> (offset))
 107 #define RN_OFFSET  16
 108 #define RT_OFFSET  12
 109 #define RT2_OFFSET  0
 110 /*
 111  * Bit 22 of the instruction encoding distinguishes between
 112  * the SWP and SWPB variants (bit set means SWPB).
 113  */
 114 #define TYPE_SWPB (1 << 22)
 115
 116 static pid_t previous_pid;
 117
 118 u64 swpb_count = 0;
 119 u64 swp_count = 0;
 120
 121 /*
 122  * swp_handler logs the id of calling process, dissects the instruction, sanity
 123  * checks the memory location, calls emulate_swpX for the actual operation and
 124  * deals with fixup/error handling before returning
 125  */
 126 static int swp_handler(struct pt_regs *regs, unsigned int instr)
 127 {
 128         u32 destreg, data, type;
 129         uintptr_t address;
 130         unsigned int res = 0;
 131         int err;
 132         u32 temp32;
 133         u8 temp8;
 134
 135         perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->pc);
 136
 137         res = arm_check_condition(instr, regs->pstate);
 138         switch (res) {
 139         case ARM_OPCODE_CONDTEST_PASS:
 140                 break;
 141         case ARM_OPCODE_CONDTEST_FAIL:
 142                 /* Condition failed - return to next instruction */
 143                 regs->pc += 4;
 144                 return 0;
 145         case ARM_OPCODE_CONDTEST_UNCOND:
 146                 /* If unconditional encoding - not a SWP, undef */
 147                 return -EFAULT;
 148         default:
 149                 return -EINVAL;
 150         }
 151
 152         if (current->pid != previous_pid) {
 153                 pr_warn("\"%s\" (%ld) uses obsolete SWP{B} instruction\n",
 154                          current->comm, (unsigned long)current->pid);
 155                 previous_pid = current->pid;
 156         }
 157
 158         address = regs->regs[EXTRACT_REG_NUM(instr, RN_OFFSET)] & 0xffffffff;
 159         data = regs->regs[EXTRACT_REG_NUM(instr, RT2_OFFSET)];
 160         destreg = EXTRACT_REG_NUM(instr, RT_OFFSET);
 161
 162         type = instr & TYPE_SWPB;
 163
 164         /* Check access in reasonable access range for both SWP and SWPB */
 165         if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
 166                 pr_debug("SWP{B} emulation: access to %p not allowed!\n",
 167                          (void *)address);
 168                 res = -EFAULT;
 169         }
 170         if (type == TYPE_SWPB) {
 171                 err = swpb((u8) data, &temp8, (u8 *) address);
 172                 if (err)
 173                         return err;
 174                 regs->regs[destreg] = temp8;
 175                 regs->pc += 4;
 176                 swpb_count++;
 177         } else if (address & 0x3) {
 178                 /* SWP to unaligned address not permitted */
 179                 pr_debug("SWP instruction on unaligned pointer!\n");
 180                 return -EFAULT;
 181         } else {
 182                 err = swp((u32) data, &temp32, (u32 *) address);
 183                 if (err)
 184                         return err;
 185                 regs->regs[destreg] = temp32;
 186                 regs->pc += 4;
 187                 swp_count++;
 188         }
 189
 190         return 0;
 191 }
 192
 193 /*
 194  * Only emulate SWP/SWPB executed in ARM state/User mode.
 195  * The kernel must be SWP free and SWP{B} does not exist in Thumb/ThumbEE.
 196  */
 197 static struct undef_hook swp_hook = {
 198         .instr_mask     = 0x0fb00ff0,
 199         .instr_val      = 0x01000090,
 200         .pstate_mask    = COMPAT_PSR_MODE_MASK | COMPAT_PSR_T_BIT,
 201         .pstate_val     = COMPAT_PSR_MODE_USR,
 202         .fn             = swp_handler
 203 };
 204
 205 /*
 206  * Register handler and create status file in /proc/cpu
 207  * Invoked as late_initcall, since not needed before init spawned.
 208  */
 209 static int __init swp_emulation_init(void)
 210 {
 211         struct dentry *dir;
 212         dir = debugfs_create_dir("swp_emulate", NULL);
 213         debugfs_create_u64("swp_count", S_IRUGO | S_IWUSR, dir, &swp_count);
 214         debugfs_create_u64("swpb_count", S_IRUGO | S_IWUSR, dir, &swpb_count);
 215
 216         pr_notice("Registering SWP/SWPB emulation handler\n");
 217         register_undef_hook(&swp_hook);
 218
 219
 220         return 0;
 221 }
 222
 223 late_initcall(swp_emulation_init);