arch/arm64/kernel/setup.c

   1 /*
   2  * Based on arch/arm/kernel/setup.c
   3  *
   4  * Copyright (C) 1995-2001 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <linux/export.h>
  21 #include <linux/kernel.h>
  22 #include <linux/stddef.h>
  23 #include <linux/ioport.h>
  24 #include <linux/delay.h>
  25 #include <linux/utsname.h>
  26 #include <linux/initrd.h>
  27 #include <linux/console.h>
  28 #include <linux/bootmem.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/screen_info.h>
  31 #include <linux/init.h>
  32 #include <linux/kexec.h>
  33 #include <linux/crash_dump.h>
  34 #include <linux/root_dev.h>
  35 #include <linux/clk-provider.h>
  36 #include <linux/cpu.h>
  37 #include <linux/interrupt.h>
  38 #include <linux/smp.h>
  39 #include <linux/fs.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/memblock.h>
  42 #include <linux/of_fdt.h>
  43 #include <linux/of_platform.h>
  44
  45 #include <asm/cputype.h>
  46 #include <asm/elf.h>
  47 #include <asm/cputable.h>
  48 #include <asm/cpu_ops.h>
  49 #include <asm/sections.h>
  50 #include <asm/setup.h>
  51 #include <asm/smp_plat.h>
  52 #include <asm/cacheflush.h>
  53 #include <asm/tlbflush.h>
  54 #include <asm/traps.h>
  55 #include <asm/memblock.h>
  56 #include <asm/psci.h>
  57
  58 unsigned int processor_id;
  59 EXPORT_SYMBOL(processor_id);
  60
  61 unsigned long elf_hwcap __read_mostly;
  62 EXPORT_SYMBOL_GPL(elf_hwcap);
  63
  64 #ifdef CONFIG_COMPAT
  65 #define COMPAT_ELF_HWCAP_DEFAULT        \
  66                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  67                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  68                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  69                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  70                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
  71 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  72 unsigned int compat_elf_hwcap2 __read_mostly;
  73 #endif
  74
  75 static const char *cpu_name;
  76 static const char *machine_name;
  77 phys_addr_t __fdt_pointer __initdata;
  78
  79 /*
  80  * Standard memory resources
  81  */
  82 static struct resource mem_res[] = {
  83         {
  84                 .name = "Kernel code",
  85                 .start = 0,
  86                 .end = 0,
  87                 .flags = IORESOURCE_MEM
  88         },
  89         {
  90                 .name = "Kernel data",
  91                 .start = 0,
  92                 .end = 0,
  93                 .flags = IORESOURCE_MEM
  94         }
  95 };
  96
  97 #define kernel_code mem_res[0]
  98 #define kernel_data mem_res[1]
  99
 100 void __init early_print(const char *str, ...)
 101 {
 102         char buf[256];
 103         va_list ap;
 104
 105         va_start(ap, str);
 106         vsnprintf(buf, sizeof(buf), str, ap);
 107         va_end(ap);
 108
 109         printk("%s", buf);
 110 }
 111
 112 void __init smp_setup_processor_id(void)
 113 {
 114         /*
 115          * clear __my_cpu_offset on boot CPU to avoid hang caused by
 116          * using percpu variable early, for example, lockdep will
 117          * access percpu variable inside lock_release
 118          */
 119         set_my_cpu_offset(0);
 120 }
 121
 122 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
 123 {
 124         return phys_id == cpu_logical_map(cpu);
 125 }
 126
 127 struct mpidr_hash mpidr_hash;
 128 #ifdef CONFIG_SMP
 129 /**
 130  * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
 131  *                        level in order to build a linear index from an
 132  *                        MPIDR value. Resulting algorithm is a collision
 133  *                        free hash carried out through shifting and ORing
 134  */
 135 static void __init smp_build_mpidr_hash(void)
 136 {
 137         u32 i, affinity, fs[4], bits[4], ls;
 138         u64 mask = 0;
 139         /*
 140          * Pre-scan the list of MPIDRS and filter out bits that do
 141          * not contribute to affinity levels, ie they never toggle.
 142          */
 143         for_each_possible_cpu(i)
 144                 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
 145         pr_debug("mask of set bits %#llx\n", mask);
 146         /*
 147          * Find and stash the last and first bit set at all affinity levels to
 148          * check how many bits are required to represent them.
 149          */
 150         for (i = 0; i < 4; i++) {
 151                 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
 152                 /*
 153                  * Find the MSB bit and LSB bits position
 154                  * to determine how many bits are required
 155                  * to express the affinity level.
 156                  */
 157                 ls = fls(affinity);
 158                 fs[i] = affinity ? ffs(affinity) - 1 : 0;
 159                 bits[i] = ls - fs[i];
 160         }
 161         /*
 162          * An index can be created from the MPIDR_EL1 by isolating the
 163          * significant bits at each affinity level and by shifting
 164          * them in order to compress the 32 bits values space to a
 165          * compressed set of values. This is equivalent to hashing
 166          * the MPIDR_EL1 through shifting and ORing. It is a collision free
 167          * hash though not minimal since some levels might contain a number
 168          * of CPUs that is not an exact power of 2 and their bit
 169          * representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
 170          */
 171         mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
 172         mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
 173         mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
 174                                                 (bits[1] + bits[0]);
 175         mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
 176                                   fs[3] - (bits[2] + bits[1] + bits[0]);
 177         mpidr_hash.mask = mask;
 178         mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
 179         pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
 180                 mpidr_hash.shift_aff[0],
 181                 mpidr_hash.shift_aff[1],
 182                 mpidr_hash.shift_aff[2],
 183                 mpidr_hash.shift_aff[3],
 184                 mpidr_hash.mask,
 185                 mpidr_hash.bits);
 186         /*
 187          * 4x is an arbitrary value used to warn on a hash table much bigger
 188          * than expected on most systems.
 189          */
 190         if (mpidr_hash_size() > 4 * num_possible_cpus())
 191                 pr_warn("Large number of MPIDR hash buckets detected\n");
 192         __flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
 193 }
 194 #endif
 195
 196 static void __init setup_processor(void)
 197 {
 198         struct cpu_info *cpu_info;
 199         u64 features, block;
 200
 201         cpu_info = lookup_processor_type(read_cpuid_id());
 202         if (!cpu_info) {
 203                 printk("CPU configuration botched (ID %08x), unable to continue.\n",
 204                        read_cpuid_id());
 205                 while (1);
 206         }
 207
 208         cpu_name = cpu_info->cpu_name;
 209
 210         printk("CPU: %s [%08x] revision %d\n",
 211                cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
 212
 213         sprintf(init_utsname()->machine, "aarch64");
 214         elf_hwcap = 0;
 215
 216         /*
 217          * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
 218          * The blocks we test below represent incremental functionality
 219          * for non-negative values. Negative values are reserved.
 220          */
 221         features = read_cpuid(ID_AA64ISAR0_EL1);
 222         block = (features >> 4) & 0xf;
 223         if (!(block & 0x8)) {
 224                 switch (block) {
 225                 default:
 226                 case 2:
 227                         elf_hwcap |= HWCAP_PMULL;
 228                 case 1:
 229                         elf_hwcap |= HWCAP_AES;
 230                 case 0:
 231                         break;
 232                 }
 233         }
 234
 235         block = (features >> 8) & 0xf;
 236         if (block && !(block & 0x8))
 237                 elf_hwcap |= HWCAP_SHA1;
 238
 239         block = (features >> 12) & 0xf;
 240         if (block && !(block & 0x8))
 241                 elf_hwcap |= HWCAP_SHA2;
 242
 243         block = (features >> 16) & 0xf;
 244         if (block && !(block & 0x8))
 245                 elf_hwcap |= HWCAP_CRC32;
 246 }
 247
 248 static void __init setup_machine_fdt(phys_addr_t dt_phys)
 249 {
 250         struct boot_param_header *devtree;
 251         unsigned long dt_root;
 252
 253         /* Check we have a non-NULL DT pointer */
 254         if (!dt_phys) {
 255                 early_print("\n"
 256                         "Error: NULL or invalid device tree blob\n"
 257                         "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
 258                         "\nPlease check your bootloader.\n");
 259
 260                 while (true)
 261                         cpu_relax();
 262
 263         }
 264
 265         devtree = phys_to_virt(dt_phys);
 266
 267         /* Check device tree validity */
 268         if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) {
 269                 early_print("\n"
 270                         "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
 271                         "Expected 0x%x, found 0x%x\n"
 272                         "\nPlease check your bootloader.\n",
 273                         dt_phys, devtree, OF_DT_HEADER,
 274                         be32_to_cpu(devtree->magic));
 275
 276                 while (true)
 277                         cpu_relax();
 278         }
 279
 280         initial_boot_params = devtree;
 281         dt_root = of_get_flat_dt_root();
 282
 283         machine_name = of_get_flat_dt_prop(dt_root, "model", NULL);
 284         if (!machine_name)
 285                 machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL);
 286         if (!machine_name)
 287                 machine_name = "<unknown>";
 288         pr_info("Machine: %s\n", machine_name);
 289
 290         /* Retrieve various information from the /chosen node */
 291         of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
 292         /* Initialize {size,address}-cells info */
 293         of_scan_flat_dt(early_init_dt_scan_root, NULL);
 294         /* Setup memory, calling early_init_dt_add_memory_arch */
 295         of_scan_flat_dt(early_init_dt_scan_memory, NULL);
 296 }
 297
 298 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 299 {
 300         base &= PAGE_MASK;
 301         size &= PAGE_MASK;
 302         if (base + size < PHYS_OFFSET) {
 303                 pr_warning("Ignoring memory block 0x%llx - 0x%llx\n",
 304                            base, base + size);
 305                 return;
 306         }
 307         if (base < PHYS_OFFSET) {
 308                 pr_warning("Ignoring memory range 0x%llx - 0x%llx\n",
 309                            base, PHYS_OFFSET);
 310                 size -= PHYS_OFFSET - base;
 311                 base = PHYS_OFFSET;
 312         }
 313         memblock_add(base, size);
 314 }
 315
 316 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 317 {
 318         return __va(memblock_alloc(size, align));
 319 }
 320
 321 /*
 322  * Limit the memory size that was specified via FDT.
 323  */
 324 static int __init early_mem(char *p)
 325 {
 326         phys_addr_t limit;
 327
 328         if (!p)
 329                 return 1;
 330
 331         limit = memparse(p, &p) & PAGE_MASK;
 332         pr_notice("Memory limited to %lldMB\n", limit >> 20);
 333
 334         memblock_enforce_memory_limit(limit);
 335
 336         return 0;
 337 }
 338 early_param("mem", early_mem);
 339
 340 static void __init request_standard_resources(void)
 341 {
 342         struct memblock_region *region;
 343         struct resource *res;
 344
 345         kernel_code.start   = virt_to_phys(_text);
 346         kernel_code.end     = virt_to_phys(_etext - 1);
 347         kernel_data.start   = virt_to_phys(_sdata);
 348         kernel_data.end     = virt_to_phys(_end - 1);
 349
 350         for_each_memblock(memory, region) {
 351                 res = alloc_bootmem_low(sizeof(*res));
 352                 res->name  = "System RAM";
 353                 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
 354                 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
 355                 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
 356
 357                 request_resource(&iomem_resource, res);
 358
 359                 if (kernel_code.start >= res->start &&
 360                     kernel_code.end <= res->end)
 361                         request_resource(res, &kernel_code);
 362                 if (kernel_data.start >= res->start &&
 363                     kernel_data.end <= res->end)
 364                         request_resource(res, &kernel_data);
 365         }
 366 }
 367
 368 u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
 369
 370 void __init setup_arch(char **cmdline_p)
 371 {
 372         setup_processor();
 373
 374         setup_machine_fdt(__fdt_pointer);
 375
 376         init_mm.start_code = (unsigned long) _text;
 377         init_mm.end_code   = (unsigned long) _etext;
 378         init_mm.end_data   = (unsigned long) _edata;
 379         init_mm.brk        = (unsigned long) _end;
 380
 381         *cmdline_p = boot_command_line;
 382
 383         parse_early_param();
 384
 385         arm64_memblock_init();
 386
 387         paging_init();
 388         request_standard_resources();
 389
 390         unflatten_device_tree();
 391
 392         psci_init();
 393
 394         cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
 395         cpu_read_bootcpu_ops();
 396 #ifdef CONFIG_SMP
 397         smp_init_cpus();
 398         smp_build_mpidr_hash();
 399 #endif
 400
 401 #ifdef CONFIG_VT
 402 #if defined(CONFIG_VGA_CONSOLE)
 403         conswitchp = &vga_con;
 404 #elif defined(CONFIG_DUMMY_CONSOLE)
 405         conswitchp = &dummy_con;
 406 #endif
 407 #endif
 408
 409 }
 410
 411 static int __init arm64_device_init(void)
 412 {
 413         of_clk_init(NULL);
 414         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 415         return 0;
 416 }
 417 arch_initcall_sync(arm64_device_init);
 418
 419 static DEFINE_PER_CPU(struct cpu, cpu_data);
 420
 421 static int __init topology_init(void)
 422 {
 423         int i;
 424
 425         for_each_possible_cpu(i) {
 426                 struct cpu *cpu = &per_cpu(cpu_data, i);
 427                 cpu->hotpluggable = 1;
 428                 register_cpu(cpu, i);
 429         }
 430
 431         return 0;
 432 }
 433 subsys_initcall(topology_init);
 434
 435 static const char *hwcap_str[] = {
 436         "fp",
 437         "asimd",
 438         "evtstrm",
 439         "aes",
 440         "pmull",
 441         "sha1",
 442         "sha2",
 443         "crc32",
 444         NULL
 445 };
 446
 447 static int c_show(struct seq_file *m, void *v)
 448 {
 449         int i;
 450
 451         seq_printf(m, "Processor\t: %s rev %d (%s)\n",
 452                    cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
 453
 454         for_each_online_cpu(i) {
 455                 /*
 456                  * glibc reads /proc/cpuinfo to determine the number of
 457                  * online processors, looking for lines beginning with
 458                  * "processor".  Give glibc what it expects.
 459                  */
 460 #ifdef CONFIG_SMP
 461                 seq_printf(m, "processor\t: %d\n", i);
 462 #endif
 463                 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n\n",
 464                            loops_per_jiffy / (500000UL/HZ),
 465                            loops_per_jiffy / (5000UL/HZ) % 100);
 466         }
 467
 468         /* dump out the processor features */
 469         seq_puts(m, "Features\t: ");
 470
 471         for (i = 0; hwcap_str[i]; i++)
 472                 if (elf_hwcap & (1 << i))
 473                         seq_printf(m, "%s ", hwcap_str[i]);
 474 #ifdef CONFIG_ARMV7_COMPAT_CPUINFO
 475         if (is_compat_task()) {
 476                 /* Print out the non-optional ARMv8 HW capabilities */
 477                 seq_printf(m, "wp half thumb fastmult vfp edsp neon vfpv3 tlsi ");
 478                 seq_printf(m, "vfpv4 idiva idivt ");
 479         }
 480 #endif
 481
 482         seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
 483         seq_printf(m, "CPU architecture: %s\n",
 484 #if IS_ENABLED(CONFIG_ARMV7_COMPAT_CPUINFO)
 485                         is_compat_task() ? "8" :
 486 #endif
 487                         "AArch64");
 488         seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
 489         seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
 490         seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
 491
 492         seq_puts(m, "\n");
 493
 494         seq_printf(m, "Hardware\t: %s\n", machine_name);
 495
 496         return 0;
 497 }
 498
 499 static void *c_start(struct seq_file *m, loff_t *pos)
 500 {
 501         return *pos < 1 ? (void *)1 : NULL;
 502 }
 503
 504 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 505 {
 506         ++*pos;
 507         return NULL;
 508 }
 509
 510 static void c_stop(struct seq_file *m, void *v)
 511 {
 512 }
 513
 514 const struct seq_operations cpuinfo_op = {
 515         .start  = c_start,
 516         .next   = c_next,
 517         .stop   = c_stop,
 518         .show   = c_show
 519 };