arch/arm64/kernel/head.S

   1 /*
   2  * Low-level CPU initialisation
   3  * Based on arch/arm/kernel/head.S
   4  *
   5  * Copyright (C) 1994-2002 Russell King
   6  * Copyright (C) 2003-2012 ARM Ltd.
   7  * Authors:     Catalin Marinas <catalin.marinas@arm.com>
   8  *              Will Deacon <will.deacon@arm.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include <linux/linkage.h>
  24 #include <linux/init.h>
  25
  26 #include <asm/assembler.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/asm-offsets.h>
  29 #include <asm/cputype.h>
  30 #include <asm/memory.h>
  31 #include <asm/thread_info.h>
  32 #include <asm/pgtable-hwdef.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/page.h>
  35 #include <asm/virt.h>
  36
  37 /*
  38  * swapper_pg_dir is the virtual address of the initial page table. We place
  39  * the page tables 3 * PAGE_SIZE below KERNEL_RAM_VADDR. The idmap_pg_dir has
  40  * 2 pages and is placed below swapper_pg_dir.
  41  */
  42 #define KERNEL_RAM_VADDR        (PAGE_OFFSET + TEXT_OFFSET)
  43
  44 #if (KERNEL_RAM_VADDR & 0xfffff) != 0x80000
  45 #error KERNEL_RAM_VADDR must start at 0xXXX80000
  46 #endif
  47
  48 #define SWAPPER_DIR_SIZE        (3 * PAGE_SIZE)
  49 #define IDMAP_DIR_SIZE          (2 * PAGE_SIZE)
  50
  51         .globl  swapper_pg_dir
  52         .equ    swapper_pg_dir, KERNEL_RAM_VADDR - SWAPPER_DIR_SIZE
  53
  54         .globl  idmap_pg_dir
  55         .equ    idmap_pg_dir, swapper_pg_dir - IDMAP_DIR_SIZE
  56
  57         .macro  pgtbl, ttb0, ttb1, phys
  58         add     \ttb1, \phys, #TEXT_OFFSET - SWAPPER_DIR_SIZE
  59         sub     \ttb0, \ttb1, #IDMAP_DIR_SIZE
  60         .endm
  61
  62 #ifdef CONFIG_ARM64_64K_PAGES
  63 #define BLOCK_SHIFT     PAGE_SHIFT
  64 #define BLOCK_SIZE      PAGE_SIZE
  65 #else
  66 #define BLOCK_SHIFT     SECTION_SHIFT
  67 #define BLOCK_SIZE      SECTION_SIZE
  68 #endif
  69
  70 #define KERNEL_START    KERNEL_RAM_VADDR
  71 #define KERNEL_END      _end
  72
  73 /*
  74  * Initial memory map attributes.
  75  */
  76 #ifndef CONFIG_SMP
  77 #define PTE_FLAGS       PTE_TYPE_PAGE | PTE_AF
  78 #define PMD_FLAGS       PMD_TYPE_SECT | PMD_SECT_AF
  79 #else
  80 #define PTE_FLAGS       PTE_TYPE_PAGE | PTE_AF | PTE_SHARED
  81 #define PMD_FLAGS       PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S
  82 #endif
  83
  84 #ifdef CONFIG_ARM64_64K_PAGES
  85 #define MM_MMUFLAGS     PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
  86 #else
  87 #define MM_MMUFLAGS     PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
  88 #endif
  89
  90 /*
  91  * Kernel startup entry point.
  92  * ---------------------------
  93  *
  94  * The requirements are:
  95  *   MMU = off, D-cache = off, I-cache = on or off,
  96  *   x0 = physical address to the FDT blob.
  97  *
  98  * This code is mostly position independent so you call this at
  99  * __pa(PAGE_OFFSET + TEXT_OFFSET).
 100  *
 101  * Note that the callee-saved registers are used for storing variables
 102  * that are useful before the MMU is enabled. The allocations are described
 103  * in the entry routines.
 104  */
 105         __HEAD
 106
 107         /*
 108          * DO NOT MODIFY. Image header expected by Linux boot-loaders.
 109          */
 110         b       stext                           // branch to kernel start, magic
 111         .long   0                               // reserved
 112         .quad   TEXT_OFFSET                     // Image load offset from start of RAM
 113         .quad   0                               // reserved
 114         .quad   0                               // reserved
 115
 116 ENTRY(stext)
 117         mov     x21, x0                         // x21=FDT
 118         bl      __calc_phys_offset              // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET
 119         bl      el2_setup                       // Drop to EL1
 120         mrs     x22, midr_el1                   // x22=cpuid
 121         mov     x0, x22
 122         bl      lookup_processor_type
 123         mov     x23, x0                         // x23=current cpu_table
 124         cbz     x23, __error_p                  // invalid processor (x23=0)?
 125         bl      __vet_fdt
 126         bl      __create_page_tables            // x25=TTBR0, x26=TTBR1
 127         /*
 128          * The following calls CPU specific code in a position independent
 129          * manner. See arch/arm64/mm/proc.S for details. x23 = base of
 130          * cpu_info structure selected by lookup_processor_type above.
 131          * On return, the CPU will be ready for the MMU to be turned on and
 132          * the TCR will have been set.
 133          */
 134         ldr     x27, __switch_data              // address to jump to after
 135                                                 // MMU has been enabled
 136         adr     lr, __enable_mmu                // return (PIC) address
 137         ldr     x12, [x23, #CPU_INFO_SETUP]
 138         add     x12, x12, x28                   // __virt_to_phys
 139         br      x12                             // initialise processor
 140 ENDPROC(stext)
 141
 142 /*
 143  * If we're fortunate enough to boot at EL2, ensure that the world is
 144  * sane before dropping to EL1.
 145  */
 146 ENTRY(el2_setup)
 147         mrs     x0, CurrentEL
 148         cmp     x0, #PSR_MODE_EL2t
 149         ccmp    x0, #PSR_MODE_EL2h, #0x4, ne
 150         ldr     x0, =__boot_cpu_mode            // Compute __boot_cpu_mode
 151         add     x0, x0, x28
 152         b.eq    1f
 153         str     wzr, [x0]                       // Remember we don't have EL2...
 154         ret
 155
 156         /* Hyp configuration. */
 157 1:      ldr     w1, =BOOT_CPU_MODE_EL2
 158         str     w1, [x0, #4]                    // This CPU has EL2
 159         mov     x0, #(1 << 31)                  // 64-bit EL1
 160         msr     hcr_el2, x0
 161
 162         /* Generic timers. */
 163         mrs     x0, cnthctl_el2
 164         orr     x0, x0, #3                      // Enable EL1 physical timers
 165         msr     cnthctl_el2, x0
 166         msr     cntvoff_el2, xzr                // Clear virtual offset
 167
 168         /* Populate ID registers. */
 169         mrs     x0, midr_el1
 170         mrs     x1, mpidr_el1
 171         msr     vpidr_el2, x0
 172         msr     vmpidr_el2, x1
 173
 174         /* sctlr_el1 */
 175         mov     x0, #0x0800                     // Set/clear RES{1,0} bits
 176         movk    x0, #0x30d0, lsl #16
 177         msr     sctlr_el1, x0
 178
 179         /* Coprocessor traps. */
 180         mov     x0, #0x33ff
 181         msr     cptr_el2, x0                    // Disable copro. traps to EL2
 182
 183 #ifdef CONFIG_COMPAT
 184         msr     hstr_el2, xzr                   // Disable CP15 traps to EL2
 185 #endif
 186
 187         /* Stage-2 translation */
 188         msr     vttbr_el2, xzr
 189
 190         /* Hypervisor stub */
 191         adr     x0, __hyp_stub_vectors
 192         msr     vbar_el2, x0
 193
 194         /* spsr */
 195         mov     x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
 196                       PSR_MODE_EL1h)
 197         msr     spsr_el2, x0
 198         msr     elr_el2, lr
 199         eret
 200 ENDPROC(el2_setup)
 201
 202 /*
 203  * We need to find out the CPU boot mode long after boot, so we need to
 204  * store it in a writable variable.
 205  *
 206  * This is not in .bss, because we set it sufficiently early that the boot-time
 207  * zeroing of .bss would clobber it.
 208  */
 209         .pushsection    .data
 210 ENTRY(__boot_cpu_mode)
 211         .long   BOOT_CPU_MODE_EL2
 212         .long   0
 213         .popsection
 214
 215         .align  3
 216 2:      .quad   .
 217         .quad   PAGE_OFFSET
 218
 219 #ifdef CONFIG_SMP
 220         .align  3
 221 1:      .quad   .
 222         .quad   secondary_holding_pen_release
 223
 224
 225 /*FIXME: MTK only*/
 226 CCI400_SI3_SNOOP_CONTROL:
 227 .long 0x10394000
 228 CCI400_STATUS:
 229 .long 0x1039000C
 230 MISCDBG:
 231 .long 0x1020020C
 232         /*
 233          * This provides a "holding pen" for platforms to hold all secondary
 234          * cores are held until we're ready for them to initialise.
 235          */
 236 ENTRY(secondary_holding_pen)
 237         mrs     x0, mpidr_el1
 238         ubfx    x0, x0, #8, #4
 239         cmp     x0, #0
 240         b.eq    cluster0
 241         ldr     w2, MISCDBG
 242         ldr     w1, [x2]
 243         bic     w1, w1, #0x10
 244         str     w1, [x2]
 245         ldr     w2, CCI400_SI3_SNOOP_CONTROL
 246         ldr     w1, [x2]
 247         orr     w1, w1, #0x3
 248         str     w1, [x2]
 249         ldr     w2, CCI400_STATUS
 250         b       3f
 251 0:
 252         dsb     sy
 253 3:
 254         ldr     w1, [x2]
 255         tst     w1, #1
 256         bne     0b
 257
 258 cluster0:
 259         bl      __calc_phys_offset              // x24=phys offset
 260         bl      el2_setup                       // Drop to EL1
 261         mrs     x0, mpidr_el1
 262         ldr     x1, =MPIDR_HWID_BITMASK
 263         and     x0, x0, x1
 264         adr     x1, 1b
 265         ldp     x2, x3, [x1]
 266         sub     x1, x1, x2
 267         add     x3, x3, x1
 268 pen:    ldr     x4, [x3]
 269         cmp     x4, x0
 270         b.eq    secondary_startup
 271         wfe
 272         b       pen
 273 ENDPROC(secondary_holding_pen)
 274
 275         /*
 276          * Secondary entry point that jumps straight into the kernel. Only to
 277          * be used where CPUs are brought online dynamically by the kernel.
 278          */
 279 ENTRY(secondary_entry)
 280         bl      __calc_phys_offset              // x2=phys offset
 281         bl      el2_setup                       // Drop to EL1
 282         b       secondary_startup
 283 ENDPROC(secondary_entry)
 284
 285 ENTRY(secondary_startup)
 286         /*
 287          * Common entry point for secondary CPUs.
 288          */
 289         mrs     x22, midr_el1                   // x22=cpuid
 290         mov     x0, x22
 291         bl      lookup_processor_type
 292         mov     x23, x0                         // x23=current cpu_table
 293         cbz     x23, __error_p                  // invalid processor (x23=0)?
 294
 295         pgtbl   x25, x26, x24                   // x25=TTBR0, x26=TTBR1
 296         ldr     x12, [x23, #CPU_INFO_SETUP]
 297         add     x12, x12, x28                   // __virt_to_phys
 298         blr     x12                             // initialise processor
 299
 300         ldr     x21, =secondary_data
 301         ldr     x27, =__secondary_switched      // address to jump to after enabling the MMU
 302         b       __enable_mmu
 303 ENDPROC(secondary_startup)
 304
 305 ENTRY(__secondary_switched)
 306         ldr     x0, [x21]                       // get secondary_data.stack
 307         mov     sp, x0
 308         mov     x29, #0
 309         b       secondary_start_kernel
 310 ENDPROC(__secondary_switched)
 311 #endif  /* CONFIG_SMP */
 312
 313 /*
 314  * Setup common bits before finally enabling the MMU. Essentially this is just
 315  * loading the page table pointer and vector base registers.
 316  *
 317  * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on
 318  * the MMU.
 319  */
 320 __enable_mmu:
 321         ldr     x5, =vectors
 322         msr     vbar_el1, x5
 323         msr     ttbr0_el1, x25                  // load TTBR0
 324         msr     ttbr1_el1, x26                  // load TTBR1
 325         isb
 326         b       __turn_mmu_on
 327 ENDPROC(__enable_mmu)
 328
 329 /*
 330  * Enable the MMU. This completely changes the structure of the visible memory
 331  * space. You will not be able to trace execution through this.
 332  *
 333  *  x0  = system control register
 334  *  x27 = *virtual* address to jump to upon completion
 335  *
 336  * other registers depend on the function called upon completion
 337  */
 338         .align  6
 339 __turn_mmu_on:
 340         msr     sctlr_el1, x0
 341         isb
 342         br      x27
 343 ENDPROC(__turn_mmu_on)
 344
 345 /*
 346  * Calculate the start of physical memory.
 347  */
 348 ENTRY(__calc_phys_offset)
 349         adr     x0, 1f
 350         ldp     x1, x2, [x0]
 351         sub     x28, x0, x1                     // x28 = PHYS_OFFSET - PAGE_OFFSET
 352         add     x24, x2, x28                    // x24 = PHYS_OFFSET
 353         ret
 354 ENDPROC(__calc_phys_offset)
 355
 356         .align 3
 357 1:      .quad   .
 358         .quad   PAGE_OFFSET
 359
 360 /*
 361  * Macro to populate the PGD for the corresponding block entry in the next
 362  * level (tbl) for the given virtual address.
 363  *
 364  * Preserves:   pgd, tbl, virt
 365  * Corrupts:    tmp1, tmp2
 366  */
 367         .macro  create_pgd_entry, pgd, tbl, virt, tmp1, tmp2
 368         lsr     \tmp1, \virt, #PGDIR_SHIFT
 369         and     \tmp1, \tmp1, #PTRS_PER_PGD - 1 // PGD index
 370         orr     \tmp2, \tbl, #3                 // PGD entry table type
 371         str     \tmp2, [\pgd, \tmp1, lsl #3]
 372         .endm
 373
 374 /*
 375  * Macro to populate block entries in the page table for the start..end
 376  * virtual range (inclusive).
 377  *
 378  * Preserves:   tbl, flags
 379  * Corrupts:    phys, start, end, pstate
 380  */
 381         .macro  create_block_map, tbl, flags, phys, start, end, idmap=0
 382         lsr     \phys, \phys, #BLOCK_SHIFT
 383         .if     \idmap
 384         and     \start, \phys, #PTRS_PER_PTE - 1        // table index
 385         .else
 386         lsr     \start, \start, #BLOCK_SHIFT
 387         and     \start, \start, #PTRS_PER_PTE - 1       // table index
 388         .endif
 389         orr     \phys, \flags, \phys, lsl #BLOCK_SHIFT  // table entry
 390         .ifnc   \start,\end
 391         lsr     \end, \end, #BLOCK_SHIFT
 392         and     \end, \end, #PTRS_PER_PTE - 1           // table end index
 393         .endif
 394 9999:   str     \phys, [\tbl, \start, lsl #3]           // store the entry
 395         .ifnc   \start,\end
 396         add     \start, \start, #1                      // next entry
 397         add     \phys, \phys, #BLOCK_SIZE               // next block
 398         cmp     \start, \end
 399         b.ls    9999b
 400         .endif
 401         .endm
 402
 403 /*
 404  * Setup the initial page tables. We only setup the barest amount which is
 405  * required to get the kernel running. The following sections are required:
 406  *   - identity mapping to enable the MMU (low address, TTBR0)
 407  *   - first few MB of the kernel linear mapping to jump to once the MMU has
 408  *     been enabled, including the FDT blob (TTBR1)
 409  *   - UART mapping if CONFIG_EARLY_PRINTK is enabled (TTBR1)
 410  */
 411 __create_page_tables:
 412         pgtbl   x25, x26, x24                   // idmap_pg_dir and swapper_pg_dir addresses
 413
 414         /*
 415          * Clear the idmap and swapper page tables.
 416          */
 417         mov     x0, x25
 418         add     x6, x26, #SWAPPER_DIR_SIZE
 419 1:      stp     xzr, xzr, [x0], #16
 420         stp     xzr, xzr, [x0], #16
 421         stp     xzr, xzr, [x0], #16
 422         stp     xzr, xzr, [x0], #16
 423         cmp     x0, x6
 424         b.lo    1b
 425
 426         ldr     x7, =MM_MMUFLAGS
 427
 428         /*
 429          * Create the identity mapping.
 430          */
 431         add     x0, x25, #PAGE_SIZE             // section table address
 432         adr     x3, __turn_mmu_on               // virtual/physical address
 433         create_pgd_entry x25, x0, x3, x5, x6
 434         create_block_map x0, x7, x3, x5, x5, idmap=1
 435
 436         /*
 437          * Map the kernel image (starting with PHYS_OFFSET).
 438          */
 439         add     x0, x26, #PAGE_SIZE             // section table address
 440         mov     x5, #PAGE_OFFSET
 441         create_pgd_entry x26, x0, x5, x3, x6
 442         ldr     x6, =KERNEL_END - 1
 443         mov     x3, x24                         // phys offset
 444         create_block_map x0, x7, x3, x5, x6
 445
 446         /*
 447          * Map the FDT blob (maximum 2MB; must be within 512MB of
 448          * PHYS_OFFSET).
 449          */
 450         mov     x3, x21                         // FDT phys address
 451         and     x3, x3, #~((1 << 21) - 1)       // 2MB aligned
 452         mov     x6, #PAGE_OFFSET
 453         sub     x5, x3, x24                     // subtract PHYS_OFFSET
 454         tst     x5, #~((1 << 29) - 1)           // within 512MB?
 455         csel    x21, xzr, x21, ne               // zero the FDT pointer
 456         b.ne    1f
 457         add     x5, x5, x6                      // __va(FDT blob)
 458         add     x6, x5, #1 << 21                // 2MB for the FDT blob
 459         sub     x6, x6, #1                      // inclusive range
 460         create_block_map x0, x7, x3, x5, x6
 461 1:
 462 #ifdef CONFIG_EARLY_PRINTK
 463         /*
 464          * Create the pgd entry for the UART mapping. The full mapping is done
 465          * later based earlyprintk kernel parameter.
 466          */
 467         ldr     x5, =EARLYCON_IOBASE            // UART virtual address
 468         add     x0, x26, #2 * PAGE_SIZE         // section table address
 469         create_pgd_entry x26, x0, x5, x6, x7
 470 #endif
 471         ret
 472 ENDPROC(__create_page_tables)
 473         .ltorg
 474
 475         .align  3
 476         .type   __switch_data, %object
 477 __switch_data:
 478         .quad   __mmap_switched
 479         .quad   __data_loc                      // x4
 480         .quad   _data                           // x5
 481         .quad   __bss_start                     // x6
 482         .quad   _end                            // x7
 483         .quad   processor_id                    // x4
 484         .quad   __fdt_pointer                   // x5
 485         .quad   memstart_addr                   // x6
 486         .quad   init_thread_union + THREAD_START_SP // sp
 487
 488 /*
 489  * The following fragment of code is executed with the MMU on in MMU mode, and
 490  * uses absolute addresses; this is not position independent.
 491  */
 492 __mmap_switched:
 493         adr     x3, __switch_data + 8
 494
 495         ldp     x4, x5, [x3], #16
 496         ldp     x6, x7, [x3], #16
 497         cmp     x4, x5                          // Copy data segment if needed
 498 1:      ccmp    x5, x6, #4, ne
 499         b.eq    2f
 500         ldr     x16, [x4], #8
 501         str     x16, [x5], #8
 502         b       1b
 503 2:
 504 1:      cmp     x6, x7
 505         b.hs    2f
 506         str     xzr, [x6], #8                   // Clear BSS
 507         b       1b
 508 2:
 509         ldp     x4, x5, [x3], #16
 510         ldr     x6, [x3], #8
 511         ldr     x16, [x3]
 512         mov     sp, x16
 513         str     x22, [x4]                       // Save processor ID
 514         str     x21, [x5]                       // Save FDT pointer
 515         str     x24, [x6]                       // Save PHYS_OFFSET
 516         mov     x29, #0
 517         b       start_kernel
 518 ENDPROC(__mmap_switched)
 519
 520 /*
 521  * Exception handling. Something went wrong and we can't proceed. We ought to
 522  * tell the user, but since we don't have any guarantee that we're even
 523  * running on the right architecture, we do virtually nothing.
 524  */
 525 __error_p:
 526 ENDPROC(__error_p)
 527
 528 __error:
 529 1:      nop
 530         b       1b
 531 ENDPROC(__error)
 532
 533 /*
 534  * This function gets the processor ID in w0 and searches the cpu_table[] for
 535  * a match. It returns a pointer to the struct cpu_info it found. The
 536  * cpu_table[] must end with an empty (all zeros) structure.
 537  *
 538  * This routine can be called via C code and it needs to work with the MMU
 539  * both disabled and enabled (the offset is calculated automatically).
 540  */
 541 ENTRY(lookup_processor_type)
 542         adr     x1, __lookup_processor_type_data
 543         ldp     x2, x3, [x1]
 544         sub     x1, x1, x2                      // get offset between VA and PA
 545         add     x3, x3, x1                      // convert VA to PA
 546 1:
 547         ldp     w5, w6, [x3]                    // load cpu_id_val and cpu_id_mask
 548         cbz     w5, 2f                          // end of list?
 549         and     w6, w6, w0
 550         cmp     w5, w6
 551         b.eq    3f
 552         add     x3, x3, #CPU_INFO_SZ
 553         b       1b
 554 2:
 555         mov     x3, #0                          // unknown processor
 556 3:
 557         mov     x0, x3
 558         ret
 559 ENDPROC(lookup_processor_type)
 560
 561         .align  3
 562         .type   __lookup_processor_type_data, %object
 563 __lookup_processor_type_data:
 564         .quad   .
 565         .quad   cpu_table
 566         .size   __lookup_processor_type_data, . - __lookup_processor_type_data
 567
 568 /*
 569  * Determine validity of the x21 FDT pointer.
 570  * The dtb must be 8-byte aligned and live in the first 512M of memory.
 571  */
 572 __vet_fdt:
 573         tst     x21, #0x7
 574         b.ne    1f
 575         cmp     x21, x24
 576         b.lt    1f
 577         mov     x0, #(1 << 29)
 578         add     x0, x0, x24
 579         cmp     x21, x0
 580         b.ge    1f
 581         ret
 582 1:
 583         mov     x21, #0
 584         ret
 585 ENDPROC(__vet_fdt)