arch/arm64/include/asm/io.h

   1 /*
   2  * Based on arch/arm/include/asm/io.h
   3  *
   4  * Copyright (C) 1996-2000 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_IO_H
  20 #define __ASM_IO_H
  21
  22 #ifdef __KERNEL__
  23
  24 #include <linux/types.h>
  25
  26 #include <asm/byteorder.h>
  27 #include <asm/barrier.h>
  28 #include <asm/pgtable.h>
  29
  30 /*
  31  * Generic IO read/write.  These perform native-endian accesses.
  32  */
  33 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  34 {
  35         asm volatile("strb %w0, [%1]" : : "r" (val), "r" (addr));
  36 }
  37
  38 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  39 {
  40         asm volatile("strh %w0, [%1]" : : "r" (val), "r" (addr));
  41 }
  42
  43 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  44 {
  45         asm volatile("str %w0, [%1]" : : "r" (val), "r" (addr));
  46 }
  47
  48 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  49 {
  50         asm volatile("str %0, [%1]" : : "r" (val), "r" (addr));
  51 }
  52
  53 static inline u8 __raw_readb(const volatile void __iomem *addr)
  54 {
  55         u8 val;
  56         asm volatile("ldrb %w0, [%1]" : "=r" (val) : "r" (addr));
  57         return val;
  58 }
  59
  60 static inline u16 __raw_readw(const volatile void __iomem *addr)
  61 {
  62         u16 val;
  63         asm volatile("ldrh %w0, [%1]" : "=r" (val) : "r" (addr));
  64         return val;
  65 }
  66
  67 static inline u32 __raw_readl(const volatile void __iomem *addr)
  68 {
  69         u32 val;
  70         asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
  71         return val;
  72 }
  73
  74 static inline u64 __raw_readq(const volatile void __iomem *addr)
  75 {
  76         u64 val;
  77         asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
  78         return val;
  79 }
  80
  81 /* IO barriers */
  82 #define __iormb()               rmb()
  83 #define __iowmb()               wmb()
  84
  85 #define mmiowb()                do { } while (0)
  86
  87 /*
  88  * Relaxed I/O memory access primitives. These follow the Device memory
  89  * ordering rules but do not guarantee any ordering relative to Normal memory
  90  * accesses.
  91  */
  92 #define readb_relaxed(c)        ({ u8  __v = __raw_readb(c); __v; })
  93 #define readw_relaxed(c)        ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
  94 #define readl_relaxed(c)        ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; })
  95 #define readq_relaxed(c)        ({ u64 __v = le64_to_cpu((__force __le64)__raw_readq(c)); __v; })
  96
  97 #define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
  98 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
  99 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
 100 #define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
 101
 102 /*
 103  * I/O memory access primitives. Reads are ordered relative to any
 104  * following Normal memory access. Writes are ordered relative to any prior
 105  * Normal memory access.
 106  */
 107 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 108 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 109 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 110 #define readq(c)                ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
 111
 112 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed((v),(c)); })
 113 #define writew(v,c)             ({ __iowmb(); writew_relaxed((v),(c)); })
 114 #define writel(v,c)             ({ __iowmb(); writel_relaxed((v),(c)); })
 115 #define writeq(v,c)             ({ __iowmb(); writeq_relaxed((v),(c)); })
 116
 117 /*
 118  *  I/O port access primitives.
 119  */
 120 #define IO_SPACE_LIMIT          0xffff
 121 #define PCI_IOBASE              ((void __iomem *)(MODULES_VADDR - SZ_2M))
 122
 123 #define IOMEM(x)        ((void __force __iomem *)(x))
 124
 125 static inline u8 inb(unsigned long addr)
 126 {
 127         return readb(addr + PCI_IOBASE);
 128 }
 129
 130 static inline u16 inw(unsigned long addr)
 131 {
 132         return readw(addr + PCI_IOBASE);
 133 }
 134
 135 static inline u32 inl(unsigned long addr)
 136 {
 137         return readl(addr + PCI_IOBASE);
 138 }
 139
 140 static inline void outb(u8 b, unsigned long addr)
 141 {
 142         writeb(b, addr + PCI_IOBASE);
 143 }
 144
 145 static inline void outw(u16 b, unsigned long addr)
 146 {
 147         writew(b, addr + PCI_IOBASE);
 148 }
 149
 150 static inline void outl(u32 b, unsigned long addr)
 151 {
 152         writel(b, addr + PCI_IOBASE);
 153 }
 154
 155 #define inb_p(addr)     inb(addr)
 156 #define inw_p(addr)     inw(addr)
 157 #define inl_p(addr)     inl(addr)
 158
 159 #define outb_p(x, addr) outb((x), (addr))
 160 #define outw_p(x, addr) outw((x), (addr))
 161 #define outl_p(x, addr) outl((x), (addr))
 162
 163 static inline void insb(unsigned long addr, void *buffer, int count)
 164 {
 165         u8 *buf = buffer;
 166         while (count--)
 167                 *buf++ = __raw_readb(addr + PCI_IOBASE);
 168 }
 169
 170 static inline void insw(unsigned long addr, void *buffer, int count)
 171 {
 172         u16 *buf = buffer;
 173         while (count--)
 174                 *buf++ = __raw_readw(addr + PCI_IOBASE);
 175 }
 176
 177 static inline void insl(unsigned long addr, void *buffer, int count)
 178 {
 179         u32 *buf = buffer;
 180         while (count--)
 181                 *buf++ = __raw_readl(addr + PCI_IOBASE);
 182 }
 183
 184 static inline void outsb(unsigned long addr, const void *buffer, int count)
 185 {
 186         const u8 *buf = buffer;
 187         while (count--)
 188                 __raw_writeb(*buf++, addr + PCI_IOBASE);
 189 }
 190
 191 static inline void outsw(unsigned long addr, const void *buffer, int count)
 192 {
 193         const u16 *buf = buffer;
 194         while (count--)
 195                 __raw_writew(*buf++, addr + PCI_IOBASE);
 196 }
 197
 198 static inline void outsl(unsigned long addr, const void *buffer, int count)
 199 {
 200         const u32 *buf = buffer;
 201         while (count--)
 202                 __raw_writel(*buf++, addr + PCI_IOBASE);
 203 }
 204
 205 #define insb_p(port,to,len)     insb(port,to,len)
 206 #define insw_p(port,to,len)     insw(port,to,len)
 207 #define insl_p(port,to,len)     insl(port,to,len)
 208
 209 #define outsb_p(port,from,len)  outsb(port,from,len)
 210 #define outsw_p(port,from,len)  outsw(port,from,len)
 211 #define outsl_p(port,from,len)  outsl(port,from,len)
 212
 213 /*
 214  * String version of I/O memory access operations.
 215  */
 216 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
 217 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
 218 extern void __memset_io(volatile void __iomem *, int, size_t);
 219
 220 #define memset_io(c,v,l)        __memset_io((c),(v),(l))
 221 #define memcpy_fromio(a,c,l)    __memcpy_fromio((a),(c),(l))
 222 #define memcpy_toio(c,a,l)      __memcpy_toio((c),(a),(l))
 223
 224 /*
 225  * I/O memory mapping functions.
 226  */
 227 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
 228 extern void __iounmap(volatile void __iomem *addr);
 229
 230 #define PROT_DEFAULT            (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
 231 #define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 232 #define PROT_NORMAL_NC          (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
 233
 234 #define ioremap(addr, size)             __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 235 #define ioremap_nocache(addr, size)     __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 236 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 237 #define iounmap                         __iounmap
 238
 239 #define PROT_SECT_DEFAULT       (PMD_TYPE_SECT | PMD_SECT_AF)
 240 #define PROT_SECT_DEVICE_nGnRE  (PROT_SECT_DEFAULT | PTE_PXN | PTE_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
 241
 242 #define ARCH_HAS_IOREMAP_WC
 243 #include <asm-generic/iomap.h>
 244
 245 /*
 246  * More restrictive address range checking than the default implementation
 247  * (PHYS_OFFSET and PHYS_MASK taken into account).
 248  */
 249 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 250 extern int valid_phys_addr_range(unsigned long addr, size_t size);
 251 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 252
 253 extern int devmem_is_allowed(unsigned long pfn);
 254
 255 /*
 256  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 257  * access
 258  */
 259 #define xlate_dev_mem_ptr(p)    __va(p)
 260
 261 /*
 262  * Convert a virtual cached pointer to an uncached pointer
 263  */
 264 #define xlate_dev_kmem_ptr(p)   p
 265
 266 #endif  /* __KERNEL__ */
 267 #endif  /* __ASM_IO_H */