arch/arm/mm/proc-v7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv7 processor support.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/hwcap.h>
  17 #include <asm/pgtable-hwdef.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/vfpmacros.h>
  20
  21 #include "proc-macros.S"
  22
  23 #ifdef CONFIG_ARM_LPAE
  24 #include "proc-v7-3level.S"
  25 #else
  26 #include "proc-v7-2level.S"
  27 #endif
  28
  29 ENTRY(cpu_v7_proc_init)
  30         mov     pc, lr
  31 ENDPROC(cpu_v7_proc_init)
  32
  33 ENTRY(cpu_v7_proc_fin)
  34         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  35         bic     r0, r0, #0x1000                 @ ...i............
  36         bic     r0, r0, #0x0006                 @ .............ca.
  37         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  38         mov     pc, lr
  39 ENDPROC(cpu_v7_proc_fin)
  40
  41 /*
  42  *      cpu_v7_reset(loc)
  43  *
  44  *      Perform a soft reset of the system.  Put the CPU into the
  45  *      same state as it would be if it had been reset, and branch
  46  *      to what would be the reset vector.
  47  *
  48  *      - loc   - location to jump to for soft reset
  49  *
  50  *      This code must be executed using a flat identity mapping with
  51  *      caches disabled.
  52  */
  53         .align  5
  54         .pushsection    .idmap.text, "ax"
  55 ENTRY(cpu_v7_reset)
  56         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
  57         bic     r1, r1, #0x1                    @ ...............m
  58  THUMB( bic     r1, r1, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
  59         mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
  60         isb
  61         bx      r0
  62 ENDPROC(cpu_v7_reset)
  63         .popsection
  64
  65 /*
  66  *      cpu_v7_do_idle()
  67  *
  68  *      Idle the processor (eg, wait for interrupt).
  69  *
  70  *      IRQs are already disabled.
  71  */
  72 ENTRY(cpu_v7_do_idle)
  73         dsb                                     @ WFI may enter a low-power mode
  74         wfi
  75         mov     pc, lr
  76 ENDPROC(cpu_v7_do_idle)
  77
  78 ENTRY(cpu_v7_dcache_clean_area)
  79         ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
  80         ALT_UP_B(1f)
  81         mov     pc, lr
  82 1:      dcache_line_size r2, r3
  83 #ifdef CONFIG_ARM_ERRATA_824069
  84 2:      mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D entry
  85 #else
  86 2:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  87 #endif
  88         add     r0, r0, r2
  89         subs    r1, r1, r2
  90         bhi     2b
  91         dsb
  92         mov     pc, lr
  93 ENDPROC(cpu_v7_dcache_clean_area)
  94
  95         string  cpu_v7_name, "ARMv7 Processor"
  96         .align
  97
  98 #define A53_IMPLEMENTATION_DEFINED
  99
 100 #if !defined (A53_IMPLEMENTATION_DEFINED)
 101 #define A53_IMPL_SIZE (0)
 102 #else //#if !defined (A53_IMPLEMENTATION_DEFINED)
 103 #define A53_IMPL_SIZE (4)
 104 #endif //#if !defined (A53_IMPLEMENTATION_DEFINED)
 105
 106 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
 107 .globl  cpu_v7_suspend_size
 108 .equ    cpu_v7_suspend_size, 4 * (11 + A53_IMPL_SIZE)
 109
 110 #ifdef CONFIG_ARM_CPU_SUSPEND
 111 ENTRY(cpu_v7_do_suspend)
 112         stmfd   sp!, {r4 - r11, lr}
 113         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 114 @       mrc     p15, 0, r4, c13, c0, 1  @ CONTEXTIDR should be 0, instead of restored.
 115         mrc     p15, 0, r5, c13, c0, 2  @ TPIDRURW
 116         mrc     p15, 0, r6, c13, c0, 3  @ TPIDRURO
 117         mrc     p15, 0, r7, c13, c0, 4  @ TPIDRPRW
 118         stmia   r0!, {r4 - r7}
 119         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
 120 #ifdef CONFIG_ARM_LPAE
 121         mrrc    p15, 1, r5, r7, c2      @ TTB 1
 122 #else
 123         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
 124 #endif
 125         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
 126         mrc     p15, 0, r8, c1, c0, 0   @ Control register
 127         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
 128         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 129         stmia   r0!, {r5 - r11}
 130
 131 #if defined (A53_IMPLEMENTATION_DEFINED)
 132         @@ extention for a53's implementation defined register
 133         MRC     p15, 0, r9, c0, c0, 0   @ MIDR
 134         movw    r10, #0xfff0
 135         movt    r10, #0xff0f
 136         and     r9, r10
 137         movw    r10, #0xD030
 138         movt    r10, #0x410F
 139         teq     r9, r10
 140         bne     1f
 141         MRRC    p15, 0, r4, r5, c15     @ Read CPU Auxiliary Control Register
 142         MRRC    p15, 1, r6, r7, c15     @ Read CPU Extended Control Register
 143         stmia   r0!, {r4 - r7}
 144 #endif //#if defined (A53_IMPLEMENTATION_DEFINED)
 145
 146 1:      ldmfd   sp!, {r4 - r11, pc}
 147 ENDPROC(cpu_v7_do_suspend)
 148
 149         /*** R1 is argument and reserved as TTBR1 **/
 150 ENTRY(cpu_v7_do_resume)
 151         mov     ip, #0
 152         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 153         ldmia   r0!, {r4 - r7}
 154         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 155 @       mcr     p15, 0, r4, c13, c0, 1  @ CONTEXTIDR
 156         mcr     p15, 0, r5, c13, c0, 2  @ TPIDRURW
 157         mcr     p15, 0, r6, c13, c0, 3  @ TPIDRURO
 158         mcr     p15, 0, r7, c13, c0, 4  @ TPIDRPRW
 159         ldmia   r0!, {r5 - r11}
 160         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
 161         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 162 #ifdef CONFIG_ARM_LPAE
 163         mcrr    p15, 0, r1, ip, c2      @ TTB 0
 164         mcrr    p15, 1, r5, r7, c2      @ TTB 1
 165 #else
 166         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 167         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 168         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
 169         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
 170 #endif
 171         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
 172         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
 173         teq     r4, r9                  @ Is it already set?
 174         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
 175         mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 176         /**!! R8 is reserved and keeping CTLR !!  **/
 177         /**!! R8 is reserved and keeping CTLR !!  **/
 178
 179 #if defined (A53_IMPLEMENTATION_DEFINED)
 180         @@ extention for a53's implementation defined register
 181         MRC     p15, 0, r9, c0, c0, 0   @ MIDR
 182         movw    r10, #0xfff0
 183         movt    r10, #0xff0f
 184         and     r9, r10
 185         movw    r10, #0xD030
 186         movt    r10, #0x410F
 187         teq     r9, r10
 188         bne     1f
 189         ldmia   r0!, {r4 - r7}
 190 /*        MCRR  p15, 0, r4, r5, c15     @ Write CPU Auxiliary Control Register   */
 191         MCRR  p15, 1, r6, r7, c15     @ write CPU Extended Control Register
 192 1:      dsb
 193 #endif //#if defined (A53_IMPLEMENTATION_DEFINED)
 194
 195         ldr     r4, =PRRR               @ PRRR
 196         ldr     r5, =NMRR               @ NMRR
 197         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
 198         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
 199         isb
 200         dsb
 201         mov     r0, r8                  @ control register
 202         b       cpu_resume_mmu
 203 ENDPROC(cpu_v7_do_resume)
 204 #endif
 205
 206 #ifdef CONFIG_CPU_PJ4B
 207         globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
 208         globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
 209         globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
 210         globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
 211         globl_equ       cpu_pj4b_reset,         cpu_v7_reset
 212 #ifdef CONFIG_PJ4B_ERRATA_4742
 213 ENTRY(cpu_pj4b_do_idle)
 214         dsb                                     @ WFI may enter a low-power mode
 215         wfi
 216         dsb                                     @barrier
 217         mov     pc, lr
 218 ENDPROC(cpu_pj4b_do_idle)
 219 #else
 220         globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
 221 #endif
 222         globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
 223         globl_equ       cpu_pj4b_do_suspend,    cpu_v7_do_suspend
 224         globl_equ       cpu_pj4b_do_resume,     cpu_v7_do_resume
 225         globl_equ       cpu_pj4b_suspend_size,  cpu_v7_suspend_size
 226
 227 #endif
 228
 229         __CPUINIT
 230
 231 /*
 232  *      __v7_setup
 233  *
 234  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 235  *      on.  Return in r0 the new CP15 C1 control register setting.
 236  *
 237  *      This should be able to cover all ARMv7 cores.
 238  *
 239  *      It is assumed that:
 240  *      - cache type register is implemented
 241  */
 242 __v7_ca5mp_setup:
 243 __v7_ca9mp_setup:
 244         mov     r10, #(1 << 0)                  @ TLB ops broadcasting
 245         b       1f
 246 __v7_ca7mp_setup:
 247 __v7_ca12mp_setup:
 248 __v7_ca15mp_setup:
 249 __v7_ca17mp_setup:
 250         mov     r10, #0
 251 1:
 252 #ifdef CONFIG_VFP_OPT
 253         @ enable CP10 / CP11 access right
 254         ldr     r0, =(0xF << 20)
 255         mcr     p15, 0, r0, c1, c0, 2
 256         orr     r0, r0, #FPEXC_EN               @ user FPEXC has the enable bit set
 257         bic     r0, r0, #FPEXC_EX               @ make sure exceptions are disabled
 258         VFPFMXR FPEXC, r0                       @ enable VFP, disable any pending
 259                                                 @ exceptions, so we can get at the
 260                                                 @ rest of it
 261 #endif
 262 #ifdef CONFIG_SMP
 263         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
 264         ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
 265         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
 266         orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
 267         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
 268         mcreq   p15, 0, r0, c1, c0, 1
 269 #endif
 270         b       __v7_setup
 271
 272 __v7_ca53mp_setup:
 273         mov     r10, #0
 274 #ifdef CONFIG_VFP_OPT
 275         @ enable CP10 / CP11 access right
 276         ldr     r0, =(0xF << 20)
 277         mcr     p15, 0, r0, c1, c0, 2
 278         orr     r0, r0, #FPEXC_EN               @ user FPEXC has the enable bit set
 279         bic     r0, r0, #FPEXC_EX               @ make sure exceptions are disabled
 280         VFPFMXR FPEXC, r0                       @ enable VFP, disable any pending
 281                                                 @ exceptions, so we can get at the
 282                                                 @ rest of it
 283 #endif
 284 #ifdef CONFIG_SMP
 285         ALT_SMP(mrrc     p15, 1, r0, r1, c15)
 286         ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
 287         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
 288         orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
 289         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
 290         mcrreq   p15, 1, r0, r1, c15
 291 #endif
 292         b       __v7_setup
 293
 294 __v7_pj4b_setup:
 295 #ifdef CONFIG_CPU_PJ4B
 296
 297 /* Auxiliary Debug Modes Control 1 Register */
 298 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 299 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
 300 #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
 301 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
 302
 303 /* Auxiliary Debug Modes Control 2 Register */
 304 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
 305 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
 306 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
 307 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
 308 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
 309 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
 310                             PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
 311
 312 /* Auxiliary Functional Modes Control Register 0 */
 313 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
 314 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
 315 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
 316
 317 /* Auxiliary Debug Modes Control 0 Register */
 318 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
 319
 320         /* Auxiliary Debug Modes Control 1 Register */
 321         mrc     p15, 1, r0, c15, c1, 1
 322         orr     r0, r0, #PJ4B_CLEAN_LINE
 323         orr     r0, r0, #PJ4B_BCK_OFF_STREX
 324         orr     r0, r0, #PJ4B_INTER_PARITY
 325         bic     r0, r0, #PJ4B_STATIC_BP
 326         mcr     p15, 1, r0, c15, c1, 1
 327
 328         /* Auxiliary Debug Modes Control 2 Register */
 329         mrc     p15, 1, r0, c15, c1, 2
 330         bic     r0, r0, #PJ4B_FAST_LDR
 331         orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
 332         mcr     p15, 1, r0, c15, c1, 2
 333
 334         /* Auxiliary Functional Modes Control Register 0 */
 335         mrc     p15, 1, r0, c15, c2, 0
 336 #ifdef CONFIG_SMP
 337         orr     r0, r0, #PJ4B_SMP_CFB
 338 #endif
 339         orr     r0, r0, #PJ4B_L1_PAR_CHK
 340         orr     r0, r0, #PJ4B_BROADCAST_CACHE
 341         mcr     p15, 1, r0, c15, c2, 0
 342
 343         /* Auxiliary Debug Modes Control 0 Register */
 344         mrc     p15, 1, r0, c15, c1, 0
 345         orr     r0, r0, #PJ4B_WFI_WFE
 346         mcr     p15, 1, r0, c15, c1, 0
 347
 348 #endif /* CONFIG_CPU_PJ4B */
 349
 350 __v7_setup:
 351         adr     r12, __v7_setup_stack           @ the local stack
 352         stmia   r12, {r0-r5, r7, r9, r11, lr}
 353         bl      v7_flush_dcache_louis
 354         ldmia   r12, {r0-r5, r7, r9, r11, lr}
 355
 356         mrc     p15, 0, r0, c0, c0, 0           @ read main ID register
 357         and     r10, r0, #0xff000000            @ ARM?
 358         teq     r10, #0x41000000
 359         bne     3f
 360         and     r5, r0, #0x00f00000             @ variant
 361         and     r6, r0, #0x0000000f             @ revision
 362         orr     r6, r6, r5, lsr #20-4           @ combine variant and revision
 363         ubfx    r0, r0, #4, #12                 @ primary part number
 364
 365         /* Cortex-A8 Errata */
 366         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
 367         teq     r0, r10
 368         bne     2f
 369 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 370
 371         teq     r5, #0x00100000                 @ only present in r1p*
 372         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
 373         orreq   r10, r10, #(1 << 6)             @ set IBE to 1
 374         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 375 #endif
 376 #ifdef CONFIG_ARM_ERRATA_458693
 377         teq     r6, #0x20                       @ only present in r2p0
 378         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
 379         orreq   r10, r10, #(1 << 5)             @ set L1NEON to 1
 380         orreq   r10, r10, #(1 << 9)             @ set PLDNOP to 1
 381         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 382 #endif
 383 #ifdef CONFIG_ARM_ERRATA_460075
 384         teq     r6, #0x20                       @ only present in r2p0
 385         mrceq   p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
 386         tsteq   r10, #1 << 22
 387         orreq   r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
 388         mcreq   p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
 389 #endif
 390         b       3f
 391
 392         /* Cortex-A9 Errata */
 393 2:      ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
 394         teq     r0, r10
 395         bne     3f
 396 #ifdef CONFIG_ARM_ERRATA_742230
 397         cmp     r6, #0x22                       @ only present up to r2p2
 398         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 399         orrle   r10, r10, #1 << 4               @ set bit #4
 400         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 401 #endif
 402 #ifdef CONFIG_ARM_ERRATA_742231
 403         teq     r6, #0x20                       @ present in r2p0
 404         teqne   r6, #0x21                       @ present in r2p1
 405         teqne   r6, #0x22                       @ present in r2p2
 406         mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 407         orreq   r10, r10, #1 << 12              @ set bit #12
 408         orreq   r10, r10, #1 << 22              @ set bit #22
 409         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 410 #endif
 411 #ifdef CONFIG_ARM_ERRATA_743622
 412         teq     r5, #0x00200000                 @ only present in r2p*
 413         mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 414         orreq   r10, r10, #1 << 6               @ set bit #6
 415         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 416 #endif
 417 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
 418         ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
 419         ALT_UP_B(1f)
 420         mrclt   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 421         orrlt   r10, r10, #1 << 11              @ set bit #11
 422         mcrlt   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 423 1:
 424 #endif
 425
 426 3:      mov     r10, #0
 427         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 428 #ifdef CONFIG_MMU
 429         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 430 #ifdef CONFIG_ARM_ERRATA_831171
 431         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 432 #endif
 433         v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
 434         ldr     r5, =PRRR                       @ PRRR
 435         ldr     r6, =NMRR                       @ NMRR
 436         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
 437         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 438 #endif
 439         dsb                                     @ Complete invalidations
 440 #ifndef CONFIG_ARM_THUMBEE
 441         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
 442         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
 443         teq     r0, #(1 << 12)                  @ check if ThumbEE is present
 444         bne     1f
 445         mov     r5, #0
 446         mcr     p14, 6, r5, c1, c0, 0           @ Initialize TEEHBR to 0
 447         mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
 448         orr     r0, r0, #1                      @ set the 1st bit in order to
 449         mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
 450 1:
 451 #endif
 452         adr     r5, v7_crval
 453         ldmia   r5, {r5, r6}
 454 #ifdef CONFIG_CPU_ENDIAN_BE8
 455         orr     r6, r6, #1 << 25                @ big-endian page tables
 456 #endif
 457 #ifdef CONFIG_SWP_EMULATE
 458         orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
 459         bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
 460 #endif
 461         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 462         bic     r0, r0, r5                      @ clear bits them
 463         orr     r0, r0, r6                      @ set them
 464  THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
 465         mov     pc, lr                          @ return to head.S:__ret
 466 ENDPROC(__v7_setup)
 467
 468         .align  2
 469 __v7_setup_stack:
 470         .space  4 * 11                          @ 11 registers
 471
 472         __INITDATA
 473
 474         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 475         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 476 #ifdef CONFIG_CPU_PJ4B
 477         define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 478 #endif
 479
 480         .section ".rodata"
 481
 482         string  cpu_arch_name, "armv7"
 483         string  cpu_elf_name, "v7"
 484         .align
 485
 486         .section ".proc.info.init", #alloc, #execinstr
 487
 488         /*
 489          * Standard v7 proc info content
 490          */
 491 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
 492         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 493                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 494         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 495                         PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
 496         .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
 497                 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
 498         W(b)    \initfunc
 499         .long   cpu_arch_name
 500         .long   cpu_elf_name
 501         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
 502                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
 503         .long   cpu_v7_name
 504         .long   \proc_fns
 505         .long   v7wbi_tlb_fns
 506         .long   v6_user_fns
 507         .long   v7_cache_fns
 508 .endm
 509
 510 #ifndef CONFIG_ARM_LPAE
 511         /*
 512          * ARM Ltd. Cortex A5 processor.
 513          */
 514         .type   __v7_ca5mp_proc_info, #object
 515 __v7_ca5mp_proc_info:
 516         .long   0x410fc050
 517         .long   0xff0ffff0
 518         __v7_proc __v7_ca5mp_setup
 519         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 520
 521         /*
 522          * ARM Ltd. Cortex A9 processor.
 523          */
 524         .type   __v7_ca9mp_proc_info, #object
 525 __v7_ca9mp_proc_info:
 526         .long   0x410fc090
 527         .long   0xff0ffff0
 528         __v7_proc __v7_ca9mp_setup
 529         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 530
 531 #endif  /* CONFIG_ARM_LPAE */
 532
 533         /*
 534          * Marvell PJ4B processor.
 535          */
 536 #ifdef CONFIG_CPU_PJ4B
 537         .type   __v7_pj4b_proc_info, #object
 538 __v7_pj4b_proc_info:
 539         .long   0x560f5800
 540         .long   0xff0fff00
 541         __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
 542         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 543 #endif
 544
 545         /*
 546          * ARM Ltd. Cortex A7 processor.
 547          */
 548         .type   __v7_ca7mp_proc_info, #object
 549 __v7_ca7mp_proc_info:
 550         .long   0x410fc070
 551         .long   0xff0ffff0
 552         __v7_proc __v7_ca7mp_setup
 553         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 554
 555         /*
 556          * ARM Ltd. Cortex A12 processor.
 557          */
 558         .type   __v7_ca12mp_proc_info, #object
 559 __v7_ca12mp_proc_info:
 560         .long   0x410fc0d0
 561         .long   0xff0ffff0
 562         __v7_proc __v7_ca12mp_setup
 563         .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
 564
 565
 566         /*
 567          * ARM Ltd. Cortex A15 processor.
 568          */
 569         .type   __v7_ca15mp_proc_info, #object
 570 __v7_ca15mp_proc_info:
 571         .long   0x410fc0f0
 572         .long   0xff0ffff0
 573         __v7_proc __v7_ca15mp_setup
 574         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 575
 576         /*
 577          * ARM Ltd. Cortex A17 processor.
 578          */
 579         .type   __v7_ca17mp_proc_info, #object
 580 __v7_ca17mp_proc_info:
 581         .long   0x410fc0e0
 582         .long   0xff0ffff0
 583         __v7_proc __v7_ca17mp_setup
 584         .size   __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
 585
 586         .type   __v7_ca53mp_proc_info, #object
 587 __v7_ca53mp_proc_info:
 588         .long   0x410FD030
 589         .long   0xff0ffff0
 590         __v7_proc __v7_ca53mp_setup
 591         .size   __v7_ca53mp_proc_info, . - __v7_ca53mp_proc_info
 592
 593         /*
 594          * Qualcomm Inc. Krait processors.
 595          */
 596         .type   __krait_proc_info, #object
 597 __krait_proc_info:
 598         .long   0x510f0400              @ Required ID value
 599         .long   0xff0ffc00              @ Mask for ID
 600         /*
 601          * Some Krait processors don't indicate support for SDIV and UDIV
 602          * instructions in the ARM instruction set, even though they actually
 603          * do support them.
 604          */
 605         __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
 606         .size   __krait_proc_info, . - __krait_proc_info
 607
 608         /*
 609          * Match any ARMv7 processor core.
 610          */
 611         .type   __v7_proc_info, #object
 612 __v7_proc_info:
 613         .long   0x000f0000              @ Required ID value
 614         .long   0x000f0000              @ Mask for ID
 615         __v7_proc __v7_setup
 616         .size   __v7_proc_info, . - __v7_proc_info