arch/arm/mm/cache-v7.S

   1 /*
   2  *  linux/arch/arm/mm/cache-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *  Copyright (C) 2005 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  This is the "shell" of the ARMv7 processor support.
  12  */
  13 #include <linux/linkage.h>
  14 #include <linux/init.h>
  15 #include <asm/assembler.h>
  16 #include <asm/errno.h>
  17 #include <asm/unwind.h>
  18
  19 #include "proc-macros.S"
  20
  21 /*
  22  * The secondary kernel init calls v7_flush_dcache_all before it enables
  23  * the L1; however, the L1 comes out of reset in an undefined state, so
  24  * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
  25  * of cache lines with uninitialized data and uninitialized tags to get
  26  * written out to memory, which does really unpleasant things to the main
  27  * processor.  We fix this by performing an invalidate, rather than a
  28  * clean + invalidate, before jumping into the kernel.
  29  *
  30  * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs
  31  * to be called for both secondary cores startup and primary core resume
  32  * procedures.
  33  */
  34 ENTRY(v7_invalidate_l1)
  35        mov     r0, #0
  36        mcr     p15, 2, r0, c0, c0, 0
  37        mrc     p15, 1, r0, c0, c0, 0
  38
  39        ldr     r1, =0x7fff
  40        and     r2, r1, r0, lsr #13
  41
  42        ldr     r1, =0x3ff
  43
  44        and     r3, r1, r0, lsr #3      @ NumWays - 1
  45        add     r2, r2, #1              @ NumSets
  46
  47        and     r0, r0, #0x7
  48        add     r0, r0, #4      @ SetShift
  49
  50        clz     r1, r3          @ WayShift
  51        add     r4, r3, #1      @ NumWays
  52 1:     sub     r2, r2, #1      @ NumSets--
  53        mov     r3, r4          @ Temp = NumWays
  54 2:     subs    r3, r3, #1      @ Temp--
  55        mov     r5, r3, lsl r1
  56        mov     r6, r2, lsl r0
  57        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
  58        mcr     p15, 0, r5, c7, c6, 2
  59        bgt     2b
  60        cmp     r2, #0
  61        bgt     1b
  62        dsb
  63        isb
  64        mov     pc, lr
  65 ENDPROC(v7_invalidate_l1)
  66
  67 /*
  68  *      v7_flush_icache_all()
  69  *
  70  *      Flush the whole I-cache.
  71  *
  72  *      Registers:
  73  *      r0 - set to 0
  74  */
  75 ENTRY(v7_flush_icache_all)
  76         mov     r0, #0
  77         ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)          @ invalidate I-cache inner shareable
  78 #ifdef CONFIG_ARM_ERRATA_831171
  79         ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)          @ invalidate I-cache inner shareable
  80 #endif
  81         ALT_UP(mcr      p15, 0, r0, c7, c5, 0)          @ I+BTB cache invalidate
  82         mov     pc, lr
  83 ENDPROC(v7_flush_icache_all)
  84
  85  /*
  86  *     v7_flush_dcache_louis()
  87  *
  88  *     Flush the D-cache up to the Level of Unification Inner Shareable
  89  *
  90  *     Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
  91  */
  92
  93 ENTRY(v7_flush_dcache_louis)
  94         dmb                                     @ ensure ordering with previous memory accesses
  95         mrc     p15, 1, r0, c0, c0, 1           @ read clidr, r0 = clidr
  96         ALT_SMP(ands    r3, r0, #(7 << 21))     @ extract LoUIS from clidr
  97         ALT_UP(ands     r3, r0, #(7 << 27))     @ extract LoUU from clidr
  98 #ifdef CONFIG_ARM_ERRATA_643719
  99         ALT_SMP(mrceq   p15, 0, r2, c0, c0, 0)  @ read main ID register
 100         ALT_UP(moveq    pc, lr)                 @ LoUU is zero, so nothing to do
 101         ldreq   r1, =0x410fc090                 @ ID of ARM Cortex A9 r0p?
 102         biceq   r2, r2, #0x0000000f             @ clear minor revision number
 103         teqeq   r2, r1                          @ test for errata affected core and if so...
 104         orreqs  r3, #(1 << 21)                  @   fix LoUIS value (and set flags state to 'ne')
 105 #endif
 106         ALT_SMP(mov     r3, r3, lsr #20)        @ r3 = LoUIS * 2
 107         ALT_UP(mov      r3, r3, lsr #26)        @ r3 = LoUU * 2
 108         moveq   pc, lr                          @ return if level == 0
 109         mov     r10, #0                         @ r10 (starting level) = 0
 110         b       flush_levels                    @ start flushing cache levels
 111 ENDPROC(v7_flush_dcache_louis)
 112
 113 /*
 114  *      v7_flush_dcache_all()
 115  *
 116  *      Flush the whole D-cache.
 117  *
 118  *      Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
 119  *
 120  *      - mm    - mm_struct describing address space
 121  */
 122 ENTRY(v7_flush_dcache_all)
 123         dmb                                     @ ensure ordering with previous memory accesses
 124         mrc     p15, 1, r0, c0, c0, 1           @ read clidr
 125         ands    r3, r0, #0x7000000              @ extract loc from clidr
 126         mov     r3, r3, lsr #23                 @ left align loc bit field
 127         beq     finished                        @ if loc is 0, then no need to clean
 128         mov     r10, #0                         @ start clean at cache level 0
 129 flush_levels:
 130         add     r2, r10, r10, lsr #1            @ work out 3x current cache level
 131         mov     r1, r0, lsr r2                  @ extract cache type bits from clidr
 132         and     r1, r1, #7                      @ mask of the bits for current cache only
 133         cmp     r1, #2                          @ see what cache we have at this level
 134         blt     skip                            @ skip if no cache, or just i-cache
 135 #ifdef CONFIG_PREEMPT
 136         save_and_disable_irqs_notrace r9        @ make cssr&csidr read atomic
 137 #endif
 138         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
 139         isb                                     @ isb to sych the new cssr&csidr
 140         mrc     p15, 1, r1, c0, c0, 0           @ read the new csidr
 141 #ifdef CONFIG_PREEMPT
 142         restore_irqs_notrace r9
 143 #endif
 144         and     r2, r1, #7                      @ extract the length of the cache lines
 145         add     r2, r2, #4                      @ add 4 (line length offset)
 146         ldr     r4, =0x3ff
 147         ands    r4, r4, r1, lsr #3              @ find maximum number on the way size
 148         clz     r5, r4                          @ find bit position of way size increment
 149         ldr     r7, =0x7fff
 150         ands    r7, r7, r1, lsr #13             @ extract max number of the index size
 151 loop1:
 152         mov     r9, r4                          @ create working copy of max way size
 153 loop2:
 154  ARM(   orr     r11, r10, r9, lsl r5    )       @ factor way and cache number into r11
 155  THUMB( lsl     r6, r9, r5              )
 156  THUMB( orr     r11, r10, r6            )       @ factor way and cache number into r11
 157  ARM(   orr     r11, r11, r7, lsl r2    )       @ factor index number into r11
 158  THUMB( lsl     r6, r7, r2              )
 159  THUMB( orr     r11, r11, r6            )       @ factor index number into r11
 160         mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
 161         subs    r9, r9, #1                      @ decrement the way
 162         bge     loop2
 163         subs    r7, r7, #1                      @ decrement the index
 164         bge     loop1
 165 skip:
 166         add     r10, r10, #2                    @ increment cache number
 167         cmp     r3, r10
 168         bgt     flush_levels
 169 finished:
 170         mov     r10, #0                         @ swith back to cache level 0
 171         mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
 172         dsb
 173         isb
 174         mov     pc, lr
 175 ENDPROC(v7_flush_dcache_all)
 176
 177 /*
 178  *      v7_flush_cache_all()
 179  *
 180  *      Flush the entire cache system.
 181  *  The data cache flush is now achieved using atomic clean / invalidates
 182  *  working outwards from L1 cache. This is done using Set/Way based cache
 183  *  maintenance instructions.
 184  *  The instruction cache can still be invalidated back to the point of
 185  *  unification in a single instruction.
 186  *
 187  */
 188 ENTRY(v7_flush_kern_cache_all)
 189  ARM(   stmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
 190  THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
 191         bl      v7_flush_dcache_all
 192         mov     r0, #0
 193         ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)  @ invalidate I-cache inner shareable
 194 #ifdef CONFIG_ARM_ERRATA_831171
 195         ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)  @ invalidate I-cache inner shareable
 196 #endif
 197         ALT_UP(mcr      p15, 0, r0, c7, c5, 0)  @ I+BTB cache invalidate
 198  ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
 199  THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
 200         mov     pc, lr
 201 ENDPROC(v7_flush_kern_cache_all)
 202
 203  /*
 204  *     v7_flush_kern_cache_louis(void)
 205  *
 206  *     Flush the data cache up to Level of Unification Inner Shareable.
 207  *     Invalidate the I-cache to the point of unification.
 208  */
 209 ENTRY(v7_flush_kern_cache_louis)
 210  ARM(   stmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
 211  THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
 212         bl      v7_flush_dcache_louis
 213         mov     r0, #0
 214         ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)  @ invalidate I-cache inner shareable
 215 #ifdef CONFIG_ARM_ERRATA_831171
 216         ALT_SMP(mcr     p15, 0, r0, c7, c1, 0)  @ invalidate I-cache inner shareable
 217 #endif
 218         ALT_UP(mcr      p15, 0, r0, c7, c5, 0)  @ I+BTB cache invalidate
 219  ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
 220  THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
 221         mov     pc, lr
 222 ENDPROC(v7_flush_kern_cache_louis)
 223
 224 /*
 225  *      v7_flush_cache_all()
 226  *
 227  *      Flush all TLB entries in a particular address space
 228  *
 229  *      - mm    - mm_struct describing address space
 230  */
 231 ENTRY(v7_flush_user_cache_all)
 232         /*FALLTHROUGH*/
 233
 234 /*
 235  *      v7_flush_cache_range(start, end, flags)
 236  *
 237  *      Flush a range of TLB entries in the specified address space.
 238  *
 239  *      - start - start address (may not be aligned)
 240  *      - end   - end address (exclusive, may not be aligned)
 241  *      - flags - vm_area_struct flags describing address space
 242  *
 243  *      It is assumed that:
 244  *      - we have a VIPT cache.
 245  */
 246 ENTRY(v7_flush_user_cache_range)
 247         mov     pc, lr
 248 ENDPROC(v7_flush_user_cache_all)
 249 ENDPROC(v7_flush_user_cache_range)
 250
 251 /*
 252  *      v7_coherent_kern_range(start,end)
 253  *
 254  *      Ensure that the I and D caches are coherent within specified
 255  *      region.  This is typically used when code has been written to
 256  *      a memory region, and will be executed.
 257  *
 258  *      - start   - virtual start address of region
 259  *      - end     - virtual end address of region
 260  *
 261  *      It is assumed that:
 262  *      - the Icache does not read data from the write buffer
 263  */
 264 ENTRY(v7_coherent_kern_range)
 265         /* FALLTHROUGH */
 266
 267 /*
 268  *      v7_coherent_user_range(start,end)
 269  *
 270  *      Ensure that the I and D caches are coherent within specified
 271  *      region.  This is typically used when code has been written to
 272  *      a memory region, and will be executed.
 273  *
 274  *      - start   - virtual start address of region
 275  *      - end     - virtual end address of region
 276  *
 277  *      It is assumed that:
 278  *      - the Icache does not read data from the write buffer
 279  */
 280 ENTRY(v7_coherent_user_range)
 281  UNWIND(.fnstart                )
 282         dcache_line_size r2, r3
 283         sub     r3, r2, #1
 284         bic     r12, r0, r3
 285 #ifdef CONFIG_ARM_ERRATA_764369
 286         ALT_SMP(W(dsb))
 287         ALT_UP(W(nop))
 288 #endif
 289 1:
 290 #ifdef CONFIG_ARM_ERRATA_824069
 291  USER(  mcr     p15, 0, r12, c7, c14, 1 )       @ clean & invalidate D line to the point of coherence
 292 #else
 293  USER(  mcr     p15, 0, r12, c7, c11, 1 )       @ clean D line to the point of unification
 294 #endif
 295         add     r12, r12, r2
 296         cmp     r12, r1
 297         blo     1b
 298         dsb
 299         icache_line_size r2, r3
 300         sub     r3, r2, #1
 301         bic     r12, r0, r3
 302 2:
 303 #ifdef CONFIG_ARM_ERRATA_828419
 304  USER(  mcr     p15, 0, r12, c7, c1, 0  )       @ invalidate I ALL
 305 #ifdef CONFIG_ARM_ERRATA_831171
 306  USER(  mcr     p15, 0, r12, c7, c1, 0  )       @ invalidate I ALL
 307 #endif
 308 #else
 309  USER(  mcr     p15, 0, r12, c7, c5, 1  )       @ invalidate I line
 310 #ifdef CONFIG_ARM_ERRATA_831171
 311   USER(  mcr     p15, 0, r12, c7, c5, 1  )       @ invalidate I line
 312 #endif
 313         add     r12, r12, r2
 314         cmp     r12, r1
 315         blo     2b
 316 #endif
 317         mov     r0, #0
 318         ALT_SMP(mcr     p15, 0, r0, c7, c1, 6)  @ invalidate BTB Inner Shareable
 319         ALT_UP(mcr      p15, 0, r0, c7, c5, 6)  @ invalidate BTB
 320         dsb
 321         isb
 322         mov     pc, lr
 323
 324 /*
 325  * Fault handling for the cache operation above. If the virtual address in r0
 326  * isn't mapped, fail with -EFAULT.
 327  */
 328 9001:
 329 #ifdef CONFIG_ARM_ERRATA_775420
 330         dsb
 331 #endif
 332         mov     r0, #-EFAULT
 333         mov     pc, lr
 334  UNWIND(.fnend          )
 335 ENDPROC(v7_coherent_kern_range)
 336 ENDPROC(v7_coherent_user_range)
 337
 338 /*
 339  *      v7_flush_kern_dcache_area(void *addr, size_t size)
 340  *
 341  *      Ensure that the data held in the page kaddr is written back
 342  *      to the page in question.
 343  *
 344  *      - addr  - kernel address
 345  *      - size  - region size
 346  */
 347 ENTRY(v7_flush_kern_dcache_area)
 348         dcache_line_size r2, r3
 349         add     r1, r0, r1
 350         sub     r3, r2, #1
 351         bic     r0, r0, r3
 352 #ifdef CONFIG_ARM_ERRATA_764369
 353         ALT_SMP(W(dsb))
 354         ALT_UP(W(nop))
 355 #endif
 356 1:
 357         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
 358         add     r0, r0, r2
 359         cmp     r0, r1
 360         blo     1b
 361         dsb
 362         mov     pc, lr
 363 ENDPROC(v7_flush_kern_dcache_area)
 364
 365 /*
 366  *      v7_dma_inv_range(start,end)
 367  *
 368  *      Invalidate the data cache within the specified region; we will
 369  *      be performing a DMA operation in this region and we want to
 370  *      purge old data in the cache.
 371  *
 372  *      - start   - virtual start address of region
 373  *      - end     - virtual end address of region
 374  */
 375 v7_dma_inv_range:
 376         dcache_line_size r2, r3
 377         sub     r3, r2, #1
 378         tst     r0, r3
 379         bic     r0, r0, r3
 380 #ifdef CONFIG_ARM_ERRATA_764369
 381         ALT_SMP(W(dsb))
 382         ALT_UP(W(nop))
 383 #endif
 384         mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
 385
 386         tst     r1, r3
 387         bic     r1, r1, r3
 388         mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D / U line
 389 1:
 390         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D / U line
 391         add     r0, r0, r2
 392         cmp     r0, r1
 393         blo     1b
 394         dsb
 395         mov     pc, lr
 396 ENDPROC(v7_dma_inv_range)
 397
 398 /*
 399  *      v7_dma_clean_range(start,end)
 400  *      - start   - virtual start address of region
 401  *      - end     - virtual end address of region
 402  */
 403 v7_dma_clean_range:
 404         dcache_line_size r2, r3
 405         sub     r3, r2, #1
 406         bic     r0, r0, r3
 407 #ifdef CONFIG_ARM_ERRATA_764369
 408         ALT_SMP(W(dsb))
 409         ALT_UP(W(nop))
 410 #endif
 411 1:
 412 #ifdef CONFIG_ARM_ERRATA_824069
 413         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
 414 #else
 415         mcr     p15, 0, r0, c7, c10, 1          @ clean D / U line
 416 #endif
 417         add     r0, r0, r2
 418         cmp     r0, r1
 419         blo     1b
 420         dsb
 421         mov     pc, lr
 422 ENDPROC(v7_dma_clean_range)
 423
 424 /*
 425  *      v7_dma_flush_range(start,end)
 426  *      - start   - virtual start address of region
 427  *      - end     - virtual end address of region
 428  */
 429 ENTRY(v7_dma_flush_range)
 430         dcache_line_size r2, r3
 431         sub     r3, r2, #1
 432         bic     r0, r0, r3
 433 #ifdef CONFIG_ARM_ERRATA_764369
 434         ALT_SMP(W(dsb))
 435         ALT_UP(W(nop))
 436 #endif
 437 1:
 438         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D / U line
 439         add     r0, r0, r2
 440         cmp     r0, r1
 441         blo     1b
 442         dsb
 443         mov     pc, lr
 444 ENDPROC(v7_dma_flush_range)
 445
 446 /*
 447  *      dma_map_area(start, size, dir)
 448  *      - start - kernel virtual start address
 449  *      - size  - size of region
 450  *      - dir   - DMA direction
 451  */
 452 ENTRY(v7_dma_map_area)
 453         add     r1, r1, r0
 454         teq     r2, #DMA_FROM_DEVICE
 455         beq     v7_dma_inv_range
 456         b       v7_dma_clean_range
 457 ENDPROC(v7_dma_map_area)
 458
 459 /*
 460  *      dma_unmap_area(start, size, dir)
 461  *      - start - kernel virtual start address
 462  *      - size  - size of region
 463  *      - dir   - DMA direction
 464  */
 465 ENTRY(v7_dma_unmap_area)
 466         add     r1, r1, r0
 467         teq     r2, #DMA_TO_DEVICE
 468         bne     v7_dma_inv_range
 469         mov     pc, lr
 470 ENDPROC(v7_dma_unmap_area)
 471
 472         __INITDATA
 473
 474         @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
 475         define_cache_functions v7