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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / tpw8127_tb_c_l / touchpanel / gt9xx_update.c
1 /* drivers/input/touchscreen/gt9xx_update.c
2 *
3 * 2010 - 2012 Goodix Technology.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be a reference
11 * to you, when you are integrating the GOODiX's CTP IC into your system,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * Version: 2.0
17 * Revision Record:
18 * V1.0: first release. by Andrew, 2012/08/27.
19 * V1.2: modify gt9110p pid map, by Andrew, 2012/10/15
20 * V1.4:
21 * 1. modify gup_enter_update_mode,
22 * 2. rewrite i2c read/write func
23 * 3. check update file checksum
24 * by Andrew, 2012/12/12
25 * v1.6:
26 * 1. delete GTP_FW_DOWNLOAD related things.
27 * 2. add GTP_HEADER_FW_UPDATE switch to update fw by gtp_default_fw in *.h directly
28 * by Meta, 2013/04/18
29 * V2.0:
30 * 1. GT9XXF main clock calibration
31 * 2. header fw update no fs related
32 * 3. update file searching optimization
33 * 4. config update as module, switchable
34 * by Meta, 2013/08/28
35 */
36 #include "tpd.h"
37 #include <linux/interrupt.h>
38 #include <cust_eint.h>
39 #include <linux/i2c.h>
40 #include <linux/sched.h>
41 #include <linux/kthread.h>
42 #include <linux/rtpm_prio.h>
43 #include <linux/wait.h>
44 #include <linux/time.h>
45 #include <linux/delay.h>
46 #include <linux/namei.h>
47 #include <linux/mount.h>
48 #include "cust_gpio_usage.h"
49 #include <asm/uaccess.h>
50 #define GUP_FW_INFO
51 #include "tpd_custom_gt9xx.h"
52
53 #if ( (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE) || GTP_COMPATIBLE_MODE )
54 #include "gt9xx_firmware.h"
55 #endif
56
57 #define GUP_REG_HW_INFO 0x4220
58 #define GUP_REG_FW_MSG 0x41E4
59 #define GUP_REG_PID_VID 0x8140
60
61 #define GUP_SEARCH_FILE_TIMES 50
62 #define UPDATE_FILE_PATH_1 "/data/_goodix_update_.bin"
63 #define UPDATE_FILE_PATH_2 "/sdcard/_goodix_update_.bin"
64
65 #define CONFIG_FILE_PATH_1 "/data/_goodix_config_.cfg"
66 #define CONFIG_FILE_PATH_2 "/sdcard/_goodix_config_.cfg"
67
68 #define FW_HEAD_LENGTH 14
69 #define FW_DOWNLOAD_LENGTH 0x4000
70 #define FW_SECTION_LENGTH 0x2000
71 #define FW_DSP_ISP_LENGTH 0x1000
72 #define FW_DSP_LENGTH 0x1000
73 #define FW_BOOT_LENGTH 0x800
74 #define FW_SS51_LENGTH (4 * FW_SECTION_LENGTH)
75 #define FW_BOOT_ISP_LENGTH 0x800 // 2k
76 #define FW_LINK_LENGTH 0x3000 // 12k
77 #define FW_APP_CODE_LENGTH (4 * FW_SECTION_LENGTH) // 32k
78
79 #define FIRMWARE_LENGTH (FW_SS51_LENGTH + FW_DSP_LENGTH + FW_BOOT_LENGTH + FW_DSP_ISP_LENGTH + FW_BOOT_ISP_LENGTH + FW_APP_CODE_LENGTH)
80
81 #define FW_HOTKNOT_LENGTH 0x3000
82 #define PACK_SIZE 256
83 #define MAX_FRAME_CHECK_TIME 5
84
85
86 #define _bRW_MISCTL__SRAM_BANK 0x4048
87 #define _bRW_MISCTL__MEM_CD_EN 0x4049
88 #define _bRW_MISCTL__CACHE_EN 0x404B
89 #define _bRW_MISCTL__TMR0_EN 0x40B0
90 #define _rRW_MISCTL__SWRST_B0_ 0x4180
91 #define _bWO_MISCTL__CPU_SWRST_PULSE 0x4184
92 #define _rRW_MISCTL__BOOTCTL_B0_ 0x4190
93 #define _rRW_MISCTL__BOOT_OPT_B0_ 0x4218
94 #define _rRW_MISCTL__BOOT_CTL_ 0x5094
95
96 #define AUTO_SEARCH_BIN 0x01
97 #define AUTO_SEARCH_CFG 0x02
98 #define BIN_FILE_READY 0x80
99 #define CFG_FILE_READY 0x08
100 #define HEADER_FW_READY 0x01
101
102 #define FAIL 0
103 #define SUCCESS 1
104
105 #define MAIN_SYSTEM_PATH "/sdcard/goodix/_main_.bin"
106 #define HOTKNOT_SYSTEM_PATH "/sdcard/goodix/_hotknot_.bin"
107 #define FX_SYSTEM_PATH "/sdcard/goodix/_authorization_.bin"
108
109 #pragma pack(1)
110 typedef struct
111 {
112 u8 hw_info[4]; //hardware info//
113 u8 pid[8]; //product id //
114 u16 vid; //version id //
115 } st_fw_head;
116 #pragma pack()
117
118 typedef struct
119 {
120 u8 force_update;
121 u8 fw_flag;
122 struct file *file;
123 struct file *cfg_file;
124 st_fw_head ic_fw_msg;
125 mm_segment_t old_fs;
126 u32 fw_total_len;
127 u32 fw_burned_len;
128 } st_update_msg;
129
130 st_update_msg update_msg;
131 extern struct i2c_client *i2c_client_point;
132 u16 show_len;
133 u16 total_len;
134 extern u8 fw_updating;
135 extern u8 cfg_len;
136 extern struct mutex i2c_access;
137 u8 searching_file = 0;
138 u8 got_file_flag = 0;
139 u8 load_fw_process = 0;
140
141 #if GTP_ESD_PROTECT
142 extern void gtp_esd_switch(struct i2c_client *client, s32 on);
143 #endif
144
145 #if (GTP_ESD_PROTECT || GTP_COMPATIBLE_MODE)
146 extern u8 is_reseting;
147 #endif
148
149
150 #if GTP_COMPATIBLE_MODE
151 extern CHIP_TYPE_T gtp_chip_type;
152 extern u8 rqst_processing;
153 extern u8 gtp_fw_startup(struct i2c_client *client);
154 static u8 gup_check_and_repair(struct i2c_client *, s32 , u8 *, u32 );
155 s32 gup_recovery_main_system(void);
156 s32 gup_load_main_system(char *filepath);
157 s32 gup_fw_download_proc(void *dir, u8 dwn_mode);
158 char * gup_load_fw_from_file(char *filepath);
159 s32 gup_load_system(char *firmware, s32 length, u8 need_check);
160 #endif
161
162 #define _CLOSE_FILE(p_file) if (p_file && !IS_ERR(p_file)) \
163 { \
164 filp_close(p_file, NULL); \
165 }
166
167
168 static u8 gup_burn_fw_app_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd );
169
170 static s32 gup_i2c_read(struct i2c_client *client, u8 *buf, s32 len)
171 {
172 s32 ret = -1;
173 u16 addr = (buf[0] << 8) + buf[1];
174
175 ret = i2c_read_bytes(client, addr, &buf[2], len - 2);
176
177 if (!ret)
178 {
179 return 2;
180 }
181 else
182 {
183 return ret;
184 }
185 }
186
187 static s32 gup_i2c_write(struct i2c_client *client, u8 *buf, s32 len)
188 {
189 s32 ret = -1;
190 u16 addr = (buf[0] << 8) + buf[1];
191
192 ret = i2c_write_bytes(client, addr, &buf[2], len - 2);
193
194 if (!ret)
195 {
196 return 1;
197 }
198 else
199 {
200 return ret;
201 }
202 }
203
204 static u8 gup_get_ic_msg(struct i2c_client *client, u16 addr, u8 *msg, s32 len)
205 {
206 s32 i = 0;
207
208 msg[0] = (addr >> 8) & 0xff;
209 msg[1] = addr & 0xff;
210
211 for (i = 0; i < 5; i++)
212 {
213 if (gup_i2c_read(client, msg, GTP_ADDR_LENGTH + len) > 0)
214 {
215 break;
216 }
217 }
218
219 if (i >= 5)
220 {
221 GTP_ERROR("Read data from 0x%02x%02x failed!", msg[0], msg[1]);
222 return FAIL;
223 }
224
225 return SUCCESS;
226 }
227
228 static u8 gup_set_ic_msg(struct i2c_client *client, u16 addr, u8 val)
229 {
230 s32 i = 0;
231 u8 msg[3];
232
233 msg[0] = (addr >> 8) & 0xff;
234 msg[1] = addr & 0xff;
235 msg[2] = val;
236
237 for (i = 0; i < 5; i++)
238 {
239 if (gup_i2c_write(client, msg, GTP_ADDR_LENGTH + 1) > 0)
240 {
241 break;
242 }
243 }
244
245 if (i >= 5)
246 {
247 GTP_ERROR("Set data to 0x%02x%02x failed!", msg[0], msg[1]);
248 return FAIL;
249 }
250
251 return SUCCESS;
252 }
253
254 static u8 gup_get_ic_fw_msg(struct i2c_client *client)
255 {
256 s32 ret = -1;
257 u8 retry = 0;
258 u8 buf[16];
259 u8 i;
260
261 //step1:get hardware info
262 ret = gtp_i2c_read_dbl_check(client, GUP_REG_HW_INFO, &buf[GTP_ADDR_LENGTH], 4);
263 if (FAIL == ret)
264 {
265 GTP_ERROR("[get_ic_fw_msg]get hw_info failed,exit");
266 return FAIL;
267 }
268
269 // buf[2~5]: 00 06 90 00
270 // hw_info: 00 90 06 00
271 for (i = 0; i < 4; i++)
272 {
273 update_msg.ic_fw_msg.hw_info[i] = buf[GTP_ADDR_LENGTH + 3 - i];
274 }
275
276 GTP_INFO("IC Hardware info:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
277 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
278
279 //step2:get firmware message
280 for (retry = 0; retry < 2; retry++)
281 {
282 ret = gup_get_ic_msg(client, GUP_REG_FW_MSG, buf, 1);
283
284 if (FAIL == ret)
285 {
286 GTP_ERROR("Read firmware message fail.");
287 return ret;
288 }
289
290 update_msg.force_update = buf[GTP_ADDR_LENGTH];
291
292 if ((0xBE != update_msg.force_update) && (!retry))
293 {
294 GTP_INFO("The check sum in ic is error.");
295 GTP_INFO("The IC will be updated by force.");
296 continue;
297 }
298 break;
299 }
300
301 GTP_INFO("IC force update flag:0x%x", update_msg.force_update);
302
303 //step3:get pid & vid
304 ret = gtp_i2c_read_dbl_check(client, GUP_REG_PID_VID, &buf[GTP_ADDR_LENGTH], 6);
305 if (FAIL == ret)
306 {
307 GTP_ERROR("[get_ic_fw_msg]get pid & vid failed,exit");
308 return FAIL;
309 }
310
311 memset(update_msg.ic_fw_msg.pid, 0, sizeof(update_msg.ic_fw_msg.pid));
312 memcpy(update_msg.ic_fw_msg.pid, &buf[GTP_ADDR_LENGTH], 4);
313
314
315 //GT9XX PID MAPPING
316 /*|-----FLASH-----RAM-----|
317 |------918------918-----|
318 |------968------968-----|
319 |------913------913-----|
320 |------913P-----913P----|
321 |------927------927-----|
322 |------927P-----927P----|
323 |------9110-----9110----|
324 |------9110P----9111----|*/
325 if(update_msg.ic_fw_msg.pid[0] != 0)
326 {
327 if (!memcmp(update_msg.ic_fw_msg.pid, "9111", 4))
328 {
329 GTP_INFO("IC Mapping Product id:%s", update_msg.ic_fw_msg.pid);
330 memcpy(update_msg.ic_fw_msg.pid, "9110P", 5);
331 }
332 }
333
334 update_msg.ic_fw_msg.vid = buf[GTP_ADDR_LENGTH + 4] + (buf[GTP_ADDR_LENGTH + 5] << 8);
335 return SUCCESS;
336 }
337
338 s32 gup_enter_update_mode(struct i2c_client *client)
339 {
340 s32 ret = -1;
341 s32 retry = 0;
342 u8 rd_buf[3];
343
344 //step1:RST output low last at least 2ms
345 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
346 msleep(2);
347
348 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
349 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
350 msleep(2);
351
352 //step3:RST output high reset guitar
353 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
354
355 //20121211 modify start
356 msleep(5);
357 while(retry++ < 200)
358 {
359 //step4:Hold ss51 & dsp
360 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
361 if(ret <= 0)
362 {
363 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
364 continue;
365 }
366
367 //step5:Confirm hold
368 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
369 if(ret <= 0)
370 {
371 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
372 continue;
373 }
374 if(0x0C == rd_buf[GTP_ADDR_LENGTH])
375 {
376 GTP_DEBUG("Hold ss51 & dsp confirm SUCCESS");
377 break;
378 }
379 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
380 }
381 if(retry >= 200)
382 {
383 GTP_ERROR("Enter update Hold ss51 failed.");
384 return FAIL;
385 }
386
387 //step6:DSP_CK and DSP_ALU_CK PowerOn
388 ret = gup_set_ic_msg(client, 0x4010, 0x00);
389
390 //20121211 modify end
391 return ret;
392 }
393
394 void gup_leave_update_mode(void)
395 {
396 GTP_GPIO_AS_INT(GTP_INT_PORT);
397
398 GTP_DEBUG("[leave_update_mode]reset chip.");
399 #if GTP_COMPATIBLE_MODE
400 if (CHIP_TYPE_GT9F == gtp_chip_type)
401 {
402 force_reset_guitar();
403 GTP_INFO("User layer reset GT9XXF.");
404 return;
405 }
406 #endif
407 gtp_reset_guitar(i2c_client_point, 20);
408 }
409
410 static u8 gup_enter_update_judge(st_fw_head *fw_head)
411 {
412 u16 u16_tmp;
413 s32 i = 0;
414 u32 fw_len = 0;
415 s32 pid_cmp_len = 0;
416 //Get the correct nvram data
417 //The correct conditions:
418 //1. the hardware info is the same
419 //2. the product id is the same
420 //3. the firmware version in update file is greater than the firmware version in ic
421 //or the check sum in ic is wrong
422
423 u16_tmp = fw_head->vid;
424 fw_head->vid = (u16)(u16_tmp >> 8) + (u16)(u16_tmp << 8);
425
426 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
427 GTP_INFO("FILE PID:%s", fw_head->pid);
428 GTP_INFO("FILE VID:%04x", fw_head->vid);
429 GTP_INFO("IC HARDWARE INFO:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
430 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
431 GTP_INFO("IC PID:%s", update_msg.ic_fw_msg.pid);
432 GTP_INFO("IC VID:%04x", update_msg.ic_fw_msg.vid);
433
434 if (!memcmp(fw_head->hw_info, update_msg.ic_fw_msg.hw_info, sizeof(update_msg.ic_fw_msg.hw_info)))
435 {
436 fw_len = 42 * 1024;
437 }
438 else
439 {
440 fw_len = fw_head->hw_info[3];
441 fw_len += (((u32)fw_head->hw_info[2]) << 8);
442 fw_len += (((u32)fw_head->hw_info[1]) << 16);
443 fw_len += (((u32)fw_head->hw_info[0]) << 24);
444 }
445 if (update_msg.fw_total_len != fw_len)
446 {
447 GTP_ERROR("Inconsistent firmware size, Update aborted! Default size: %d(%dK), actual size: %d(%dK)", fw_len, fw_len/1024, update_msg.fw_total_len, update_msg.fw_total_len/1024);
448 return FAIL;
449 }
450 if ((update_msg.fw_total_len < 36*1024) || (update_msg.fw_total_len > 128*1024))
451 {
452 GTP_ERROR("Invalid firmware length(%d), update aborted!", update_msg.fw_total_len);
453 return FAIL;
454 }
455 GTP_INFO("Firmware length:%d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
456
457 if (update_msg.force_update != 0xBE)
458 {
459 GTP_INFO("FW chksum error,need enter update.");
460 return SUCCESS;
461 }
462
463 // 20130523 start
464 if (strlen(update_msg.ic_fw_msg.pid) < 3)
465 {
466 GTP_INFO("Illegal IC pid, need enter update");
467 return SUCCESS;
468 }
469 else
470 {
471 for (i = 0; i < 3; i++)
472 {
473 if ((update_msg.ic_fw_msg.pid[i] < 0x30) || (update_msg.ic_fw_msg.pid[i] > 0x39))
474 {
475 GTP_INFO("Illegal IC pid, out of bound, need enter update");
476 return SUCCESS;
477 }
478 }
479 }
480 // 20130523 end
481
482 pid_cmp_len = strlen(fw_head->pid);
483 if (pid_cmp_len < strlen(update_msg.ic_fw_msg.pid))
484 {
485 pid_cmp_len = strlen(update_msg.ic_fw_msg.pid);
486 }
487
488 if ((!memcmp(fw_head->pid, update_msg.ic_fw_msg.pid, pid_cmp_len)) ||
489 (!memcmp(update_msg.ic_fw_msg.pid, "91XX", 4))||
490 (!memcmp(fw_head->pid, "91XX", 4)))
491 {
492 if(!memcmp(fw_head->pid, "91XX", 4))
493 {
494 GTP_DEBUG("Force none same pid update mode.");
495 }
496 else
497 {
498 GTP_DEBUG("Get the same pid.");
499 }
500
501 //The third condition
502 if (fw_head->vid > update_msg.ic_fw_msg.vid)
503 {
504
505 GTP_INFO("Need enter update.");
506 return SUCCESS;
507 }
508
509 GTP_INFO("Don't meet the third condition.");
510 GTP_ERROR("File VID <= IC VID, update aborted!");
511 }
512 else
513 {
514 GTP_ERROR("File PID != IC PID, update aborted!");
515 }
516
517 return FAIL;
518 }
519
520 #if GTP_AUTO_UPDATE_CFG
521 static u8 ascii2hex(u8 a)
522 {
523 s8 value = 0;
524
525 if(a >= '0' && a <= '9')
526 {
527 value = a - '0';
528 }
529 else if(a >= 'A' && a <= 'F')
530 {
531 value = a - 'A' + 0x0A;
532 }
533 else if(a >= 'a' && a <= 'f')
534 {
535 value = a - 'a' + 0x0A;
536 }
537 else
538 {
539 value = 0xff;
540 }
541
542 return value;
543 }
544
545 static s8 gup_update_config(struct i2c_client *client)
546 {
547 s32 file_len = 0;
548 s32 ret = 0;
549 s32 i = 0;
550 s32 file_cfg_len = 0;
551 s32 chip_cfg_len = 0;
552 s32 count = 0;
553 u8 *buf;
554 u8 *pre_buf;
555 u8 *file_config;
556 //u8 checksum = 0;
557
558 if(NULL == update_msg.cfg_file)
559 {
560 GTP_ERROR("[update_cfg]No need to upgrade config!");
561 return FAIL;
562 }
563 file_len = update_msg.cfg_file->f_op->llseek(update_msg.cfg_file, 0, SEEK_END);
564
565 chip_cfg_len = cfg_len;
566
567 GTP_DEBUG("[update_cfg]config file len:%d", file_len);
568 GTP_DEBUG("[update_cfg]need config len:%d",chip_cfg_len);
569 if((file_len+5) < chip_cfg_len*5)
570 {
571 GTP_ERROR("Config length error");
572 return -1;
573 }
574
575 buf = (u8*)kzalloc(file_len, GFP_KERNEL);
576 pre_buf = (u8*)kzalloc(file_len, GFP_KERNEL);
577 file_config = (u8*)kzalloc(chip_cfg_len + GTP_ADDR_LENGTH, GFP_KERNEL);
578 update_msg.cfg_file->f_op->llseek(update_msg.cfg_file, 0, SEEK_SET);
579
580 GTP_DEBUG("[update_cfg]Read config from file.");
581 ret = update_msg.cfg_file->f_op->read(update_msg.cfg_file, (char*)pre_buf, file_len, &update_msg.cfg_file->f_pos);
582 if(ret<0)
583 {
584 GTP_ERROR("[update_cfg]Read config file failed.");
585 goto update_cfg_file_failed;
586 }
587
588 GTP_DEBUG("[update_cfg]Delete illgal charactor.");
589 for(i=0,count=0; i<file_len; i++)
590 {
591 if (pre_buf[i] == ' ' || pre_buf[i] == '\r' || pre_buf[i] == '\n')
592 {
593 continue;
594 }
595 buf[count++] = pre_buf[i];
596 }
597
598 GTP_DEBUG("[update_cfg]Ascii to hex.");
599 file_config[0] = GTP_REG_CONFIG_DATA >> 8;
600 file_config[1] = GTP_REG_CONFIG_DATA & 0xff;
601 for(i=0,file_cfg_len=GTP_ADDR_LENGTH; i<count; i+=5)
602 {
603 if((buf[i]=='0') && ((buf[i+1]=='x') || (buf[i+1]=='X')))
604 {
605 u8 high,low;
606 high = ascii2hex(buf[i+2]);
607 low = ascii2hex(buf[i+3]);
608
609 if((high == 0xFF) || (low == 0xFF))
610 {
611 ret = 0;
612 GTP_ERROR("[update_cfg]Illegal config file.");
613 goto update_cfg_file_failed;
614 }
615 file_config[file_cfg_len++] = (high<<4) + low;
616 }
617 else
618 {
619 ret = 0;
620 GTP_ERROR("[update_cfg]Illegal config file.");
621 goto update_cfg_file_failed;
622 }
623 }
624
625
626 GTP_DEBUG("config:");
627 GTP_DEBUG_ARRAY(file_config+2, file_cfg_len);
628
629 i = 0;
630 while(i++ < 5)
631 {
632 ret = gup_i2c_write(client, file_config, file_cfg_len);
633 if(ret > 0)
634 {
635 GTP_INFO("[update_cfg]Send config SUCCESS.");
636 break;
637 }
638 GTP_ERROR("[update_cfg]Send config i2c error.");
639 }
640
641 update_cfg_file_failed:
642 kfree(pre_buf);
643 kfree(buf);
644 kfree(file_config);
645 return ret;
646 }
647 #endif
648
649 #if (GTP_AUTO_UPDATE && (!GTP_HEADER_FW_UPDATE || GTP_AUTO_UPDATE_CFG))
650 static void gup_search_file(s32 search_type)
651 {
652 s32 i = 0;
653 struct file *pfile = NULL;
654
655 got_file_flag = 0x00;
656
657 searching_file = 1;
658 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
659 {
660 if (0 == searching_file)
661 {
662 GTP_INFO("Force exiting file searching");
663 got_file_flag = 0x00;
664 return;
665 }
666
667 if (search_type & AUTO_SEARCH_BIN)
668 {
669 GTP_DEBUG("Search for %s, %s for fw update.(%d/%d)", UPDATE_FILE_PATH_1, UPDATE_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
670 pfile = filp_open(UPDATE_FILE_PATH_1, O_RDONLY, 0);
671 if (IS_ERR(pfile))
672 {
673 pfile = filp_open(UPDATE_FILE_PATH_2, O_RDONLY, 0);
674 if (!IS_ERR(pfile))
675 {
676 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_2);
677 got_file_flag |= BIN_FILE_READY;
678 update_msg.file = pfile;
679 }
680 }
681 else
682 {
683 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_1);
684 got_file_flag |= BIN_FILE_READY;
685 update_msg.file = pfile;
686 }
687 if (got_file_flag & BIN_FILE_READY)
688 {
689 #if GTP_AUTO_UPDATE_CFG
690 if (search_type & AUTO_SEARCH_CFG)
691 {
692 i = GUP_SEARCH_FILE_TIMES; // Bin & Cfg File required to be in the same directory
693 }
694 else
695 #endif
696 {
697 searching_file = 0;
698 return;
699 }
700 }
701 }
702
703 #if GTP_AUTO_UPDATE_CFG
704 if ( (search_type & AUTO_SEARCH_CFG) && !(got_file_flag & CFG_FILE_READY) )
705 {
706 GTP_DEBUG("Search for %s, %s for config update.(%d/%d)", CONFIG_FILE_PATH_1, CONFIG_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
707 pfile = filp_open(CONFIG_FILE_PATH_1, O_RDONLY, 0);
708 if (IS_ERR(pfile))
709 {
710 pfile = filp_open(CONFIG_FILE_PATH_2, O_RDONLY, 0);
711 if (!IS_ERR(pfile))
712 {
713 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_2);
714 got_file_flag |= CFG_FILE_READY;
715 update_msg.cfg_file = pfile;
716 }
717 }
718 else
719 {
720 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_1);
721 got_file_flag |= CFG_FILE_READY;
722 update_msg.cfg_file = pfile;
723 }
724 if (got_file_flag & CFG_FILE_READY)
725 {
726 searching_file = 0;
727 return;
728 }
729 }
730 #endif
731 msleep(3000);
732 }
733 searching_file = 0;
734 }
735 #endif
736
737 static u8 gup_check_update_file(struct i2c_client *client, st_fw_head *fw_head, u8 *path)
738 {
739 s32 ret = 0;
740 s32 i = 0;
741 s32 fw_checksum = 0;
742 u8 buf[FW_HEAD_LENGTH];
743
744 got_file_flag = 0x00;
745 if (path)
746 {
747 GTP_DEBUG("Update File path:%s, %d", path, strlen(path));
748 update_msg.file = filp_open(path, O_RDONLY, 0);
749
750 if (IS_ERR(update_msg.file))
751 {
752 GTP_ERROR("Open update file(%s) error!", path);
753 return FAIL;
754 }
755 got_file_flag = BIN_FILE_READY;
756 }
757 else
758 {
759 #if GTP_AUTO_UPDATE
760 #if GTP_HEADER_FW_UPDATE
761 GTP_INFO("Update by default firmware array");
762 update_msg.fw_total_len = sizeof(gtp_default_FW) - FW_HEAD_LENGTH;
763 if (sizeof(gtp_default_FW) < (FW_HEAD_LENGTH + FW_SECTION_LENGTH*4+FW_DSP_ISP_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH))
764 {
765 GTP_INFO("[check_update_file]default firmware array is INVALID!");
766 return FAIL;
767 }
768 GTP_DEBUG("Firmware actual size: %d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
769 memcpy(fw_head, &gtp_default_FW[0], FW_HEAD_LENGTH);
770
771 //check firmware legality
772 fw_checksum = 0;
773 for (i = 0; i < update_msg.fw_total_len; i += 2)
774 {
775 fw_checksum += (gtp_default_FW[FW_HEAD_LENGTH + i] << 8) + gtp_default_FW[FW_HEAD_LENGTH + i + 1];
776 }
777 if(fw_checksum&0xFFFF)
778 {
779 GTP_ERROR("Illegal firmware with checksum(0x%04X)", fw_checksum & 0xFFFF);
780 return FAIL;
781 }
782 got_file_flag = HEADER_FW_READY;
783 return SUCCESS;
784
785 #else
786 #if GTP_AUTO_UPDATE_CFG
787 gup_search_file(AUTO_SEARCH_BIN | AUTO_SEARCH_CFG);
788 if (got_file_flag & CFG_FILE_READY)
789 {
790 ret = gup_update_config(client);
791 if(ret <= 0)
792 {
793 GTP_ERROR("Update config failed!");
794 }
795 _CLOSE_FILE(update_msg.cfg_file);
796 msleep(500); //waiting config to be stored in FLASH.
797 }
798 #else
799 gup_search_file(AUTO_SEARCH_BIN);
800 #endif
801
802 if (!(got_file_flag & BIN_FILE_READY))
803 {
804 GTP_ERROR("No bin file for fw Update");
805 return FAIL;
806 }
807 #endif
808 #else
809 {
810 GTP_ERROR("NULL file for fw update!");
811 return FAIL;
812 }
813 #endif
814 }
815
816 update_msg.old_fs = get_fs();
817 set_fs(KERNEL_DS);
818
819 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
820 update_msg.fw_total_len = update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_END);
821
822 update_msg.fw_total_len -= FW_HEAD_LENGTH;
823
824 GTP_DEBUG("Bin firmware actual size: %d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
825
826 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
827 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, FW_HEAD_LENGTH, &update_msg.file->f_pos);
828
829 if (ret < 0)
830 {
831 GTP_ERROR("Read firmware head in update file error.");
832 goto load_failed;
833 }
834
835 memcpy(fw_head, buf, FW_HEAD_LENGTH);
836
837 //check firmware legality
838 fw_checksum = 0;
839 for(i=0; i < update_msg.fw_total_len; i+=2)
840 {
841 u16 temp;
842 ret = update_msg.file->f_op->read(update_msg.file, (char*)buf, 2, &update_msg.file->f_pos);
843 if (ret < 0)
844 {
845 GTP_ERROR("Read firmware file error.");
846 goto load_failed;
847 }
848 //GTP_DEBUG("BUF[0]:%x", buf[0]);
849 temp = (buf[0]<<8) + buf[1];
850 fw_checksum += temp;
851 }
852
853 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
854 if(fw_checksum&0xFFFF)
855 {
856 GTP_ERROR("Illegal firmware file.");
857 goto load_failed;
858 }
859
860 return SUCCESS;
861
862 load_failed:
863 set_fs(update_msg.old_fs);
864 _CLOSE_FILE(update_msg.file);
865 return FAIL;
866 }
867
868 static u8 gup_burn_proc(struct i2c_client *client, u8 *burn_buf, u16 start_addr, u16 total_length)
869 {
870 s32 ret = 0;
871 u16 burn_addr = start_addr;
872 u16 frame_length = 0;
873 u16 burn_length = 0;
874 u8 wr_buf[PACK_SIZE + GTP_ADDR_LENGTH];
875 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
876 u8 retry = 0;
877
878 GTP_DEBUG("Begin burn %dk data to addr 0x%x", (total_length / 1024), start_addr);
879
880 while (burn_length < total_length)
881 {
882 GTP_DEBUG("B/T:%04d/%04d", burn_length, total_length);
883 frame_length = ((total_length - burn_length) > PACK_SIZE) ? PACK_SIZE : (total_length - burn_length);
884 wr_buf[0] = (u8)(burn_addr >> 8);
885 rd_buf[0] = wr_buf[0];
886 wr_buf[1] = (u8)burn_addr;
887 rd_buf[1] = wr_buf[1];
888 memcpy(&wr_buf[GTP_ADDR_LENGTH], &burn_buf[burn_length], frame_length);
889
890 for (retry = 0; retry < MAX_FRAME_CHECK_TIME; retry++)
891 {
892 ret = gup_i2c_write(client, wr_buf, GTP_ADDR_LENGTH + frame_length);
893
894 if (ret <= 0)
895 {
896 GTP_ERROR("Write frame data i2c error.");
897 continue;
898 }
899
900 ret = gup_i2c_read(client, rd_buf, GTP_ADDR_LENGTH + frame_length);
901
902 if (ret <= 0)
903 {
904 GTP_ERROR("Read back frame data i2c error.");
905 continue;
906 }
907
908 if (memcmp(&wr_buf[GTP_ADDR_LENGTH], &rd_buf[GTP_ADDR_LENGTH], frame_length))
909 {
910 GTP_ERROR("Check frame data fail,not equal.");
911 GTP_DEBUG("write array:");
912 GTP_DEBUG_ARRAY(&wr_buf[GTP_ADDR_LENGTH], frame_length);
913 GTP_DEBUG("read array:");
914 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
915 continue;
916 }
917 else
918 {
919 //GTP_DEBUG("Check frame data success.");
920 break;
921 }
922 }
923
924 if (retry > MAX_FRAME_CHECK_TIME)
925 {
926 GTP_ERROR("Burn frame data time out,exit.");
927 return FAIL;
928 }
929
930 burn_length += frame_length;
931 burn_addr += frame_length;
932 }
933
934 return SUCCESS;
935 }
936
937 static u8 gup_load_section_file(u8 *buf, u32 offset, u16 length, u8 set_or_end)
938 {
939 #if (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE)
940 if (HEADER_FW_READY == got_file_flag)
941 {
942 if(SEEK_SET == set_or_end)
943 {
944 memcpy(buf, &gtp_default_FW[FW_HEAD_LENGTH + offset], length);
945 }
946 else //seek end
947 {
948 memcpy(buf, &gtp_default_FW[update_msg.fw_total_len + FW_HEAD_LENGTH - offset], length);
949 }
950 return SUCCESS;
951 }
952 #endif
953 {
954 s32 ret = 0;
955
956 if ( (update_msg.file == NULL) || IS_ERR(update_msg.file))
957 {
958 GTP_ERROR("cannot find update file,load section file fail.");
959 return FAIL;
960 }
961
962 if(SEEK_SET == set_or_end)
963 {
964 update_msg.file->f_pos = FW_HEAD_LENGTH + offset;
965 }
966 else //seek end
967 {
968 update_msg.file->f_pos = update_msg.fw_total_len + FW_HEAD_LENGTH - offset;
969 }
970
971 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, length, &update_msg.file->f_pos);
972
973 if (ret < 0)
974 {
975 GTP_ERROR("Read update file fail.");
976 return FAIL;
977 }
978
979 return SUCCESS;
980 }
981 }
982
983 static u8 gup_recall_check(struct i2c_client *client, u8 *chk_src, u16 start_rd_addr, u16 chk_length)
984 {
985 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
986 s32 ret = 0;
987 u16 recall_addr = start_rd_addr;
988 u16 recall_length = 0;
989 u16 frame_length = 0;
990
991 while (recall_length < chk_length)
992 {
993 frame_length = ((chk_length - recall_length) > PACK_SIZE) ? PACK_SIZE : (chk_length - recall_length);
994 ret = gup_get_ic_msg(client, recall_addr, rd_buf, frame_length);
995
996 if (ret <= 0)
997 {
998 GTP_ERROR("recall i2c error,exit");
999 return FAIL;
1000 }
1001
1002 if (memcmp(&rd_buf[GTP_ADDR_LENGTH], &chk_src[recall_length], frame_length))
1003 {
1004 GTP_ERROR("Recall frame data fail,not equal.");
1005 GTP_DEBUG("chk_src array:");
1006 GTP_DEBUG_ARRAY(&chk_src[recall_length], frame_length);
1007 GTP_DEBUG("recall array:");
1008 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
1009 return FAIL;
1010 }
1011
1012 recall_length += frame_length;
1013 recall_addr += frame_length;
1014 }
1015
1016 GTP_DEBUG("Recall check %dk firmware success.", (chk_length / 1024));
1017
1018 return SUCCESS;
1019 }
1020
1021 static u8 gup_burn_fw_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u8 bank_cmd)
1022 {
1023 s32 ret = 0;
1024 u8 rd_buf[5];
1025
1026 //step1:hold ss51 & dsp
1027 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1028
1029 if (ret <= 0)
1030 {
1031 GTP_ERROR("[burn_fw_section]hold ss51 & dsp fail.");
1032 return FAIL;
1033 }
1034
1035 //step2:set scramble
1036 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1037
1038 if (ret <= 0)
1039 {
1040 GTP_ERROR("[burn_fw_section]set scramble fail.");
1041 return FAIL;
1042 }
1043
1044 //step3:select bank
1045 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
1046
1047 if (ret <= 0)
1048 {
1049 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
1050 return FAIL;
1051 }
1052
1053 //step4:enable accessing code
1054 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1055
1056 if (ret <= 0)
1057 {
1058 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
1059 return FAIL;
1060 }
1061
1062 //step5:burn 8k fw section
1063 ret = gup_burn_proc(client, fw_section, start_addr, FW_SECTION_LENGTH);
1064
1065 if (FAIL == ret)
1066 {
1067 GTP_ERROR("[burn_fw_section]burn fw_section fail.");
1068 return FAIL;
1069 }
1070
1071 //step6:hold ss51 & release dsp
1072 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
1073
1074 if (ret <= 0)
1075 {
1076 GTP_ERROR("[burn_fw_section]hold ss51 & release dsp fail.");
1077 return FAIL;
1078 }
1079
1080 //must delay
1081 msleep(1);
1082
1083 //step7:send burn cmd to move data to flash from sram
1084 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd & 0x0f);
1085
1086 if (ret <= 0)
1087 {
1088 GTP_ERROR("[burn_fw_section]send burn cmd fail.");
1089 return FAIL;
1090 }
1091
1092 GTP_DEBUG("[burn_fw_section]Wait for the burn is complete......");
1093
1094 do
1095 {
1096 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1097
1098 if (ret <= 0)
1099 {
1100 GTP_ERROR("[burn_fw_section]Get burn state fail");
1101 return FAIL;
1102 }
1103
1104 msleep(10);
1105 //GTP_DEBUG("[burn_fw_section]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1106 }
1107 while (rd_buf[GTP_ADDR_LENGTH]);
1108
1109 //step8:select bank
1110 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
1111
1112 if (ret <= 0)
1113 {
1114 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
1115 return FAIL;
1116 }
1117
1118 //step9:enable accessing code
1119 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1120
1121 if (ret <= 0)
1122 {
1123 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
1124 return FAIL;
1125 }
1126
1127 //step10:recall 8k fw section
1128 ret = gup_recall_check(client, fw_section, start_addr, FW_SECTION_LENGTH);
1129
1130 if (FAIL == ret)
1131 {
1132 GTP_ERROR("[burn_fw_section]recall check %dk firmware fail.", FW_SECTION_LENGTH/1024);
1133 return FAIL;
1134 }
1135
1136 //step11:disable accessing code
1137 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x00);
1138
1139 if (ret <= 0)
1140 {
1141 GTP_ERROR("[burn_fw_section]disable accessing code fail.");
1142 return FAIL;
1143 }
1144
1145 return SUCCESS;
1146 }
1147
1148 static u8 gup_burn_dsp_isp(struct i2c_client *client)
1149 {
1150 s32 ret = 0;
1151 u8 *fw_dsp_isp = NULL;
1152 u8 retry = 0;
1153 //u32 offset;
1154
1155 GTP_INFO("[burn_dsp_isp]Begin burn dsp isp---->>");
1156
1157 //step1:alloc memory
1158 GTP_DEBUG("[burn_dsp_isp]step1:alloc memory");
1159
1160 while (retry++ < 5)
1161 {
1162 fw_dsp_isp = (u8 *)kzalloc(FW_DSP_ISP_LENGTH, GFP_KERNEL);
1163
1164 if (fw_dsp_isp == NULL)
1165 {
1166 continue;
1167 }
1168 else
1169 {
1170 GTP_INFO("[burn_dsp_isp]Alloc %dk byte memory success.", (FW_DSP_ISP_LENGTH / 1024));
1171 break;
1172 }
1173 }
1174
1175 if (retry >= 5)
1176 {
1177 GTP_ERROR("[burn_dsp_isp]Alloc memory fail,exit.");
1178 return FAIL;
1179 }
1180
1181 //step2:load dsp isp file data
1182 GTP_DEBUG("[burn_dsp_isp]step2:load dsp isp file data");
1183 ret = gup_load_section_file(fw_dsp_isp, FW_DSP_ISP_LENGTH, FW_DSP_ISP_LENGTH, SEEK_END);
1184
1185 if (FAIL == ret)
1186 {
1187 GTP_ERROR("[burn_dsp_isp]load firmware dsp_isp fail.");
1188 goto exit_burn_dsp_isp;
1189 }
1190
1191 //step3:disable wdt,clear cache enable
1192 GTP_DEBUG("[burn_dsp_isp]step3:disable wdt,clear cache enable");
1193 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
1194
1195 if (ret <= 0)
1196 {
1197 GTP_ERROR("[burn_dsp_isp]disable wdt fail.");
1198 ret = FAIL;
1199 goto exit_burn_dsp_isp;
1200 }
1201
1202 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
1203
1204 if (ret <= 0)
1205 {
1206 GTP_ERROR("[burn_dsp_isp]clear cache enable fail.");
1207 ret = FAIL;
1208 goto exit_burn_dsp_isp;
1209 }
1210
1211 //step4:hold ss51 & dsp
1212 GTP_DEBUG("[burn_dsp_isp]step4:hold ss51 & dsp");
1213 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1214
1215 if (ret <= 0)
1216 {
1217 GTP_ERROR("[burn_dsp_isp]hold ss51 & dsp fail.");
1218 ret = FAIL;
1219 goto exit_burn_dsp_isp;
1220 }
1221
1222 //step5:set boot from sram
1223 GTP_DEBUG("[burn_dsp_isp]step5:set boot from sram");
1224 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
1225
1226 if (ret <= 0)
1227 {
1228 GTP_ERROR("[burn_dsp_isp]set boot from sram fail.");
1229 ret = FAIL;
1230 goto exit_burn_dsp_isp;
1231 }
1232
1233 //step6:software reboot
1234 GTP_DEBUG("[burn_dsp_isp]step6:software reboot");
1235 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
1236
1237 if (ret <= 0)
1238 {
1239 GTP_ERROR("[burn_dsp_isp]software reboot fail.");
1240 ret = FAIL;
1241 goto exit_burn_dsp_isp;
1242 }
1243
1244 //step7:select bank2
1245 GTP_DEBUG("[burn_dsp_isp]step7:select bank2");
1246 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
1247
1248 if (ret <= 0)
1249 {
1250 GTP_ERROR("[burn_dsp_isp]select bank2 fail.");
1251 ret = FAIL;
1252 goto exit_burn_dsp_isp;
1253 }
1254
1255 //step8:enable accessing code
1256 GTP_DEBUG("[burn_dsp_isp]step8:enable accessing code");
1257 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1258
1259 if (ret <= 0)
1260 {
1261 GTP_ERROR("[burn_dsp_isp]enable accessing code fail.");
1262 ret = FAIL;
1263 goto exit_burn_dsp_isp;
1264 }
1265
1266 //step9:burn 4k dsp_isp
1267 GTP_DEBUG("[burn_dsp_isp]step9:burn 4k dsp_isp");
1268 ret = gup_burn_proc(client, fw_dsp_isp, 0xC000, FW_DSP_ISP_LENGTH);
1269
1270 if (FAIL == ret)
1271 {
1272 GTP_ERROR("[burn_dsp_isp]burn dsp_isp fail.");
1273 goto exit_burn_dsp_isp;
1274 }
1275
1276 //step10:set scramble
1277 GTP_DEBUG("[burn_dsp_isp]step10:set scramble");
1278 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1279
1280 if (ret <= 0)
1281 {
1282 GTP_ERROR("[burn_dsp_isp]set scramble fail.");
1283 ret = FAIL;
1284 goto exit_burn_dsp_isp;
1285 }
1286
1287 update_msg.fw_burned_len += FW_DSP_ISP_LENGTH;
1288 GTP_DEBUG("[burn_dsp_isp]Burned length:%d", update_msg.fw_burned_len);
1289 ret = SUCCESS;
1290
1291 exit_burn_dsp_isp:
1292 kfree(fw_dsp_isp);
1293 return ret;
1294 }
1295
1296 static u8 gup_burn_fw_ss51(struct i2c_client *client)
1297 {
1298 u8 *fw_ss51 = NULL;
1299 u8 retry = 0;
1300 s32 ret = 0;
1301
1302 GTP_INFO("[burn_fw_ss51]Begin burn ss51 firmware---->>");
1303
1304 //step1:alloc memory
1305 GTP_DEBUG("[burn_fw_ss51]step1:alloc memory");
1306
1307 while (retry++ < 5)
1308 {
1309 fw_ss51 = (u8 *)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
1310
1311 if (fw_ss51 == NULL)
1312 {
1313 continue;
1314 }
1315 else
1316 {
1317 GTP_INFO("[burn_fw_ss51]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1318 break;
1319 }
1320 }
1321
1322 if (retry >= 5)
1323 {
1324 GTP_ERROR("[burn_fw_ss51]Alloc memory fail,exit.");
1325 return FAIL;
1326 }
1327
1328 //step2:load ss51 firmware section 1 file data
1329 //GTP_DEBUG("[burn_fw_ss51]step2:load ss51 firmware section 1 file data");
1330 //ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
1331 //
1332 // if (FAIL == ret)
1333 // {
1334 // GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 1 fail.");
1335 // goto exit_burn_fw_ss51;
1336 // }
1337 GTP_INFO("[burn_fw_ss51]Reset first 8K of ss51 to 0xFF.");
1338 GTP_DEBUG("[burn_fw_ss51]step2: reset bank0 0xC000~0xD000");
1339 memset(fw_ss51, 0xFF, FW_SECTION_LENGTH);
1340
1341 //step3:clear control flag
1342 GTP_DEBUG("[burn_fw_ss51]step3:clear control flag");
1343 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
1344
1345 if (ret <= 0)
1346 {
1347 GTP_ERROR("[burn_fw_ss51]clear control flag fail.");
1348 ret = FAIL;
1349 goto exit_burn_fw_ss51;
1350 }
1351
1352 //step4:burn ss51 firmware section 1
1353 GTP_DEBUG("[burn_fw_ss51]step4:burn ss51 firmware section 1");
1354 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
1355
1356 if (FAIL == ret)
1357 {
1358 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 1 fail.");
1359 goto exit_burn_fw_ss51;
1360 }
1361
1362 //step5:load ss51 firmware section 2 file data
1363 GTP_DEBUG("[burn_fw_ss51]step5:load ss51 firmware section 2 file data");
1364 ret = gup_load_section_file(fw_ss51, FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1365
1366 if (FAIL == ret)
1367 {
1368 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 2 fail.");
1369 goto exit_burn_fw_ss51;
1370 }
1371
1372 //step6:burn ss51 firmware section 2
1373 GTP_DEBUG("[burn_fw_ss51]step6:burn ss51 firmware section 2");
1374 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x02);
1375
1376 if (FAIL == ret)
1377 {
1378 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 2 fail.");
1379 goto exit_burn_fw_ss51;
1380 }
1381
1382 //step7:load ss51 firmware section 3 file data
1383 GTP_DEBUG("[burn_fw_ss51]step7:load ss51 firmware section 3 file data");
1384 ret = gup_load_section_file(fw_ss51, 2 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1385
1386 if (FAIL == ret)
1387 {
1388 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 3 fail.");
1389 goto exit_burn_fw_ss51;
1390 }
1391
1392 //step8:burn ss51 firmware section 3
1393 GTP_DEBUG("[burn_fw_ss51]step8:burn ss51 firmware section 3");
1394 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x13);
1395
1396 if (FAIL == ret)
1397 {
1398 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 3 fail.");
1399 goto exit_burn_fw_ss51;
1400 }
1401
1402 //step9:load ss51 firmware section 4 file data
1403 GTP_DEBUG("[burn_fw_ss51]step9:load ss51 firmware section 4 file data");
1404 ret = gup_load_section_file(fw_ss51, 3 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1405
1406 if (FAIL == ret)
1407 {
1408 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 4 fail.");
1409 goto exit_burn_fw_ss51;
1410 }
1411
1412 //step10:burn ss51 firmware section 4
1413 GTP_DEBUG("[burn_fw_ss51]step10:burn ss51 firmware section 4");
1414 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x14);
1415
1416 if (FAIL == ret)
1417 {
1418 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 4 fail.");
1419 goto exit_burn_fw_ss51;
1420 }
1421
1422 update_msg.fw_burned_len += (FW_SECTION_LENGTH*4);
1423 GTP_DEBUG("[burn_fw_ss51]Burned length:%d", update_msg.fw_burned_len);
1424 ret = SUCCESS;
1425
1426 exit_burn_fw_ss51:
1427 kfree(fw_ss51);
1428 return ret;
1429 }
1430
1431 static u8 gup_burn_fw_dsp(struct i2c_client *client)
1432 {
1433 s32 ret = 0;
1434 u8 *fw_dsp = NULL;
1435 u8 retry = 0;
1436 u8 rd_buf[5];
1437
1438 GTP_INFO("[burn_fw_dsp]Begin burn dsp firmware---->>");
1439 //step1:alloc memory
1440 GTP_DEBUG("[burn_fw_dsp]step1:alloc memory");
1441
1442 while (retry++ < 5)
1443 {
1444 fw_dsp = (u8 *)kzalloc(FW_DSP_LENGTH, GFP_KERNEL);
1445
1446 if (fw_dsp == NULL)
1447 {
1448 continue;
1449 }
1450 else
1451 {
1452 GTP_INFO("[burn_fw_dsp]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1453 break;
1454 }
1455 }
1456
1457 if (retry >= 5)
1458 {
1459 GTP_ERROR("[burn_fw_dsp]Alloc memory fail,exit.");
1460 return FAIL;
1461 }
1462
1463 //step2:load firmware dsp
1464 GTP_DEBUG("[burn_fw_dsp]step2:load firmware dsp");
1465 ret = gup_load_section_file(fw_dsp, 4 * FW_SECTION_LENGTH, FW_DSP_LENGTH, SEEK_SET);
1466
1467 if (FAIL == ret)
1468 {
1469 GTP_ERROR("[burn_fw_dsp]load firmware dsp fail.");
1470 goto exit_burn_fw_dsp;
1471 }
1472
1473 //step3:select bank3
1474 GTP_DEBUG("[burn_fw_dsp]step3:select bank3");
1475 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1476
1477 if (ret <= 0)
1478 {
1479 GTP_ERROR("[burn_fw_dsp]select bank3 fail.");
1480 ret = FAIL;
1481 goto exit_burn_fw_dsp;
1482 }
1483
1484 //step4:hold ss51 & dsp
1485 GTP_DEBUG("[burn_fw_dsp]step4:hold ss51 & dsp");
1486 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1487
1488 if (ret <= 0)
1489 {
1490 GTP_ERROR("[burn_fw_dsp]hold ss51 & dsp fail.");
1491 ret = FAIL;
1492 goto exit_burn_fw_dsp;
1493 }
1494
1495 //step5:set scramble
1496 GTP_DEBUG("[burn_fw_dsp]step5:set scramble");
1497 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1498
1499 if (ret <= 0)
1500 {
1501 GTP_ERROR("[burn_fw_dsp]set scramble fail.");
1502 ret = FAIL;
1503 goto exit_burn_fw_dsp;
1504 }
1505
1506 //step6:release ss51 & dsp
1507 GTP_DEBUG("[burn_fw_dsp]step6:release ss51 & dsp");
1508 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121212
1509
1510 if (ret <= 0)
1511 {
1512 GTP_ERROR("[burn_fw_dsp]release ss51 & dsp fail.");
1513 ret = FAIL;
1514 goto exit_burn_fw_dsp;
1515 }
1516
1517 //must delay
1518 msleep(1);
1519
1520 //step7:burn 4k dsp firmware
1521 GTP_DEBUG("[burn_fw_dsp]step7:burn 4k dsp firmware");
1522 ret = gup_burn_proc(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1523
1524 if (FAIL == ret)
1525 {
1526 GTP_ERROR("[burn_fw_dsp]burn fw_section fail.");
1527 goto exit_burn_fw_dsp;
1528 }
1529
1530 //step8:send burn cmd to move data to flash from sram
1531 GTP_DEBUG("[burn_fw_dsp]step8:send burn cmd to move data to flash from sram");
1532 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x05);
1533
1534 if (ret <= 0)
1535 {
1536 GTP_ERROR("[burn_fw_dsp]send burn cmd fail.");
1537 goto exit_burn_fw_dsp;
1538 }
1539
1540 GTP_DEBUG("[burn_fw_dsp]Wait for the burn is complete......");
1541
1542 do
1543 {
1544 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1545
1546 if (ret <= 0)
1547 {
1548 GTP_ERROR("[burn_fw_dsp]Get burn state fail");
1549 goto exit_burn_fw_dsp;
1550 }
1551
1552 msleep(10);
1553 //GTP_DEBUG("[burn_fw_dsp]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1554 }
1555 while (rd_buf[GTP_ADDR_LENGTH]);
1556
1557 //step9:recall check 4k dsp firmware
1558 GTP_DEBUG("[burn_fw_dsp]step9:recall check 4k dsp firmware");
1559 ret = gup_recall_check(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1560
1561 if (FAIL == ret)
1562 {
1563 GTP_ERROR("[burn_fw_dsp]recall check 4k dsp firmware fail.");
1564 goto exit_burn_fw_dsp;
1565 }
1566
1567 update_msg.fw_burned_len += FW_DSP_LENGTH;
1568 GTP_DEBUG("[burn_fw_dsp]Burned length:%d", update_msg.fw_burned_len);
1569 ret = SUCCESS;
1570
1571 exit_burn_fw_dsp:
1572 kfree(fw_dsp);
1573 return ret;
1574 }
1575
1576 static u8 gup_burn_fw_boot(struct i2c_client *client)
1577 {
1578 s32 ret = 0;
1579 u8* fw_boot = NULL;
1580 u8 retry = 0;
1581 u8 rd_buf[5];
1582
1583 GTP_DEBUG("[burn_fw_boot]Begin burn bootloader firmware---->>");
1584
1585 //step1:Alloc memory
1586 GTP_DEBUG("[burn_fw_boot]step1:Alloc memory");
1587
1588 while(retry++ < 5)
1589 {
1590 fw_boot = (u8*)kzalloc(FW_BOOT_LENGTH, GFP_KERNEL);
1591
1592 if(fw_boot == NULL)
1593 {
1594 continue;
1595 }
1596 else
1597 {
1598 GTP_INFO("[burn_fw_boot]Alloc %dk byte memory success.", (FW_BOOT_LENGTH/1024));
1599 break;
1600 }
1601 }
1602
1603 if(retry >= 5)
1604 {
1605 GTP_ERROR("[burn_fw_boot]Alloc memory fail,exit.");
1606 return FAIL;
1607 }
1608
1609 //step2:load firmware bootloader
1610 GTP_DEBUG("[burn_fw_boot]step2:load firmware bootloader");
1611 ret = gup_load_section_file(fw_boot, (4 * FW_SECTION_LENGTH + FW_DSP_LENGTH), FW_BOOT_LENGTH, SEEK_SET);
1612
1613 if(FAIL == ret)
1614 {
1615 GTP_ERROR("[burn_fw_boot]load firmware bootcode fail.");
1616 goto exit_burn_fw_boot;
1617 }
1618
1619 //step3:hold ss51 & dsp
1620 GTP_DEBUG("[burn_fw_boot]step3:hold ss51 & dsp");
1621 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1622 if(ret <= 0)
1623 {
1624 GTP_ERROR("[burn_fw_boot]hold ss51 & dsp fail.");
1625 ret = FAIL;
1626 goto exit_burn_fw_boot;
1627 }
1628
1629 //step4:set scramble
1630 GTP_DEBUG("[burn_fw_boot]step4:set scramble");
1631 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1632 if(ret <= 0)
1633 {
1634 GTP_ERROR("[burn_fw_boot]set scramble fail.");
1635 ret = FAIL;
1636 goto exit_burn_fw_boot;
1637 }
1638
1639 //step5:hold ss51 & release dsp
1640 GTP_DEBUG("[burn_fw_boot]step5:hold ss51 & release dsp");
1641 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121211
1642 if(ret <= 0)
1643 {
1644 GTP_ERROR("[burn_fw_boot]release ss51 & dsp fail.");
1645 ret = FAIL;
1646 goto exit_burn_fw_boot;
1647 }
1648 //must delay
1649 msleep(1);
1650
1651 //step6:select bank3
1652 GTP_DEBUG("[burn_fw_boot]step6:select bank3");
1653 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1654 if(ret <= 0)
1655 {
1656 GTP_ERROR("[burn_fw_boot]select bank3 fail.");
1657 ret = FAIL;
1658 goto exit_burn_fw_boot;
1659 }
1660
1661 //step7:burn 2k bootloader firmware
1662 GTP_DEBUG("[burn_fw_boot]step7:burn 2k bootloader firmware");
1663 ret = gup_burn_proc(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1664 if(FAIL == ret)
1665 {
1666 GTP_ERROR("[burn_fw_boot]burn fw_boot fail.");
1667 goto exit_burn_fw_boot;
1668 }
1669
1670 //step7:send burn cmd to move data to flash from sram
1671 GTP_DEBUG("[burn_fw_boot]step7:send burn cmd to move data to flash from sram");
1672 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x06);
1673 if(ret <= 0)
1674 {
1675 GTP_ERROR("[burn_fw_boot]send burn cmd fail.");
1676 goto exit_burn_fw_boot;
1677 }
1678 GTP_DEBUG("[burn_fw_boot]Wait for the burn is complete......");
1679 do{
1680 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1681 if(ret <= 0)
1682 {
1683 GTP_ERROR("[burn_fw_boot]Get burn state fail");
1684 goto exit_burn_fw_boot;
1685 }
1686 msleep(10);
1687 //GTP_DEBUG("[burn_fw_boot]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1688 }while(rd_buf[GTP_ADDR_LENGTH]);
1689
1690 //step8:recall check 2k bootloader firmware
1691 GTP_DEBUG("[burn_fw_boot]step8:recall check 2k bootloader firmware");
1692 ret = gup_recall_check(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1693 if(FAIL == ret)
1694 {
1695 GTP_ERROR("[burn_fw_boot]recall check 2k bootcode firmware fail.");
1696 goto exit_burn_fw_boot;
1697 }
1698
1699 update_msg.fw_burned_len += FW_BOOT_LENGTH;
1700 GTP_DEBUG("[burn_fw_boot]Burned length:%d", update_msg.fw_burned_len);
1701 ret = SUCCESS;
1702
1703 exit_burn_fw_boot:
1704 kfree(fw_boot);
1705 return ret;
1706 }
1707
1708 static u8 gup_burn_fw_boot_isp(struct i2c_client *client)
1709 {
1710 s32 ret = 0;
1711 u8* fw_boot_isp = NULL;
1712 u8 retry = 0;
1713 u8 rd_buf[5];
1714
1715 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
1716 {
1717 GTP_INFO("No need to upgrade the boot_isp code!");
1718 return SUCCESS;
1719 }
1720 GTP_DEBUG("[burn_fw_boot_isp]Begin burn bootloader firmware---->>");
1721
1722 //step1:Alloc memory
1723 GTP_DEBUG("[burn_fw_boot_isp]step1:Alloc memory");
1724 while(retry++ < 5)
1725 {
1726 fw_boot_isp = (u8*)kzalloc(FW_BOOT_ISP_LENGTH, GFP_KERNEL);
1727 if(fw_boot_isp == NULL)
1728 {
1729 continue;
1730 }
1731 else
1732 {
1733 GTP_INFO("[burn_fw_boot_isp]Alloc %dk byte memory success.", (FW_BOOT_ISP_LENGTH/1024));
1734 break;
1735 }
1736 }
1737 if(retry >= 5)
1738 {
1739 GTP_ERROR("[burn_fw_boot_isp]Alloc memory fail,exit.");
1740 return FAIL;
1741 }
1742
1743 //step2:load firmware bootloader
1744 GTP_DEBUG("[burn_fw_boot_isp]step2:load firmware bootloader isp");
1745 //ret = gup_load_section_file(fw_boot_isp, (4*FW_SECTION_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH+FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
1746 ret = gup_load_section_file(fw_boot_isp, (update_msg.fw_burned_len - FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
1747 if(FAIL == ret)
1748 {
1749 GTP_ERROR("[burn_fw_boot_isp]load firmware boot_isp fail.");
1750 goto exit_burn_fw_boot_isp;
1751 }
1752
1753 //step3:hold ss51 & dsp
1754 GTP_DEBUG("[burn_fw_boot_isp]step3:hold ss51 & dsp");
1755 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1756 if(ret <= 0)
1757 {
1758 GTP_ERROR("[burn_fw_boot_isp]hold ss51 & dsp fail.");
1759 ret = FAIL;
1760 goto exit_burn_fw_boot_isp;
1761 }
1762
1763 //step4:set scramble
1764 GTP_DEBUG("[burn_fw_boot_isp]step4:set scramble");
1765 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1766 if(ret <= 0)
1767 {
1768 GTP_ERROR("[burn_fw_boot_isp]set scramble fail.");
1769 ret = FAIL;
1770 goto exit_burn_fw_boot_isp;
1771 }
1772
1773
1774 //step5:hold ss51 & release dsp
1775 GTP_DEBUG("[burn_fw_boot_isp]step5:hold ss51 & release dsp");
1776 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121211
1777 if(ret <= 0)
1778 {
1779 GTP_ERROR("[burn_fw_boot_isp]release ss51 & dsp fail.");
1780 ret = FAIL;
1781 goto exit_burn_fw_boot_isp;
1782 }
1783 //must delay
1784 msleep(1);
1785
1786 //step6:select bank3
1787 GTP_DEBUG("[burn_fw_boot_isp]step6:select bank3");
1788 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1789 if(ret <= 0)
1790 {
1791 GTP_ERROR("[burn_fw_boot_isp]select bank3 fail.");
1792 ret = FAIL;
1793 goto exit_burn_fw_boot_isp;
1794 }
1795
1796 //step7:burn 2k bootload_isp firmware
1797 GTP_DEBUG("[burn_fw_boot_isp]step7:burn 2k bootloader firmware");
1798 ret = gup_burn_proc(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
1799 if(FAIL == ret)
1800 {
1801 GTP_ERROR("[burn_fw_boot_isp]burn fw_section fail.");
1802 goto exit_burn_fw_boot_isp;
1803 }
1804
1805 //step7:send burn cmd to move data to flash from sram
1806 GTP_DEBUG("[burn_fw_boot_isp]step7:send burn cmd to move data to flash from sram");
1807 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x07);
1808 if(ret <= 0)
1809 {
1810 GTP_ERROR("[burn_fw_boot_isp]send burn cmd fail.");
1811 goto exit_burn_fw_boot_isp;
1812 }
1813 GTP_DEBUG("[burn_fw_boot_isp]Wait for the burn is complete......");
1814 do{
1815 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1816 if(ret <= 0)
1817 {
1818 GTP_ERROR("[burn_fw_boot_isp]Get burn state fail");
1819 goto exit_burn_fw_boot_isp;
1820 }
1821 msleep(10);
1822 //GTP_DEBUG("[burn_fw_boot_isp]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1823 }while(rd_buf[GTP_ADDR_LENGTH]);
1824
1825 //step8:recall check 2k bootload_isp firmware
1826 GTP_DEBUG("[burn_fw_boot_isp]step8:recall check 2k bootloader firmware");
1827 ret = gup_recall_check(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
1828 if(FAIL == ret)
1829 {
1830 GTP_ERROR("[burn_fw_boot_isp]recall check 2k bootcode_isp firmware fail.");
1831 goto exit_burn_fw_boot_isp;
1832 }
1833
1834 update_msg.fw_burned_len += FW_BOOT_ISP_LENGTH;
1835 GTP_DEBUG("[burn_fw_boot_isp]Burned length:%d", update_msg.fw_burned_len);
1836 ret = SUCCESS;
1837
1838 exit_burn_fw_boot_isp:
1839 kfree(fw_boot_isp);
1840 return ret;
1841 }
1842
1843 static u8 gup_burn_fw_link(struct i2c_client *client)
1844 {
1845 s32 ret = 0;
1846 u8* fw_link = NULL;
1847 u8 retry = 0;
1848 u32 offset;
1849
1850 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
1851 {
1852 GTP_INFO("No need to upgrade the link code!");
1853 return SUCCESS;
1854 }
1855 GTP_DEBUG("[burn_fw_link]Begin burn link firmware---->>");
1856
1857 //step1:Alloc memory
1858 GTP_DEBUG("[burn_fw_link]step1:Alloc memory");
1859 while(retry++ < 5)
1860 {
1861 fw_link = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
1862 if(fw_link == NULL)
1863 {
1864 continue;
1865 }
1866 else
1867 {
1868 GTP_INFO("[burn_fw_link]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
1869 break;
1870 }
1871 }
1872 if(retry >= 5)
1873 {
1874 GTP_ERROR("[burn_fw_link]Alloc memory fail,exit.");
1875 return FAIL;
1876 }
1877
1878 //step2:load firmware link section 1
1879 GTP_DEBUG("[burn_fw_link]step2:load firmware link section 1");
1880 offset = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
1881 ret = gup_load_section_file(fw_link, offset, FW_SECTION_LENGTH, SEEK_SET);
1882 if(FAIL == ret)
1883 {
1884 GTP_ERROR("[burn_fw_link]load firmware link section 1 fail.");
1885 goto exit_burn_fw_link;
1886 }
1887
1888
1889 //step3:burn link firmware section 1
1890 GTP_DEBUG("[burn_fw_link]step3:burn link firmware section 1");
1891 ret = gup_burn_fw_app_section(client, fw_link, 0x9000, FW_SECTION_LENGTH, 0x38);
1892
1893 if (FAIL == ret)
1894 {
1895 GTP_ERROR("[burn_fw_link]burn link firmware section 1 fail.");
1896 goto exit_burn_fw_link;
1897 }
1898
1899 //step4:load link firmware section 2 file data
1900 GTP_DEBUG("[burn_fw_link]step4:load link firmware section 2 file data");
1901 offset += FW_SECTION_LENGTH;
1902 ret = gup_load_section_file(fw_link, offset, FW_LINK_LENGTH - FW_SECTION_LENGTH, SEEK_SET);
1903
1904 if (FAIL == ret)
1905 {
1906 GTP_ERROR("[burn_fw_link]load link firmware section 2 fail.");
1907 goto exit_burn_fw_link;
1908 }
1909
1910 //step5:burn link firmware section 2
1911 GTP_DEBUG("[burn_fw_link]step4:burn link firmware section 2");
1912 ret = gup_burn_fw_app_section(client, fw_link, 0x9000, FW_LINK_LENGTH - FW_SECTION_LENGTH, 0x39);
1913
1914 if (FAIL == ret)
1915 {
1916 GTP_ERROR("[burn_fw_link]burn link firmware section 2 fail.");
1917 goto exit_burn_fw_link;
1918 }
1919
1920 update_msg.fw_burned_len += FW_LINK_LENGTH;
1921 GTP_DEBUG("[burn_fw_link]Burned length:%d", update_msg.fw_burned_len);
1922 ret = SUCCESS;
1923
1924 exit_burn_fw_link:
1925 kfree(fw_link);
1926 return ret;
1927 }
1928
1929 static u8 gup_burn_fw_app_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd )
1930 {
1931 s32 ret = 0;
1932 u8 rd_buf[5];
1933
1934 //step1:hold ss51 & dsp
1935 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1936 if(ret <= 0)
1937 {
1938 GTP_ERROR("[burn_fw_app_section]hold ss51 & dsp fail.");
1939 return FAIL;
1940 }
1941
1942 //step2:set scramble
1943 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1944 if(ret <= 0)
1945 {
1946 GTP_ERROR("[burn_fw_app_section]set scramble fail.");
1947 return FAIL;
1948 }
1949
1950 //step3:hold ss51 & release dsp
1951 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
1952 if(ret <= 0)
1953 {
1954 GTP_ERROR("[burn_fw_app_section]hold ss51 & release dsp fail.");
1955 return FAIL;
1956 }
1957 //must delay
1958 msleep(1);
1959
1960 //step4:select bank
1961 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4)&0x0F);
1962 if(ret <= 0)
1963 {
1964 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4)&0x0F);
1965 return FAIL;
1966 }
1967
1968 //step5:burn fw section
1969 ret = gup_burn_proc(client, fw_section, start_addr, len);
1970 if(FAIL == ret)
1971 {
1972 GTP_ERROR("[burn_fw_app_section]burn fw_section fail.");
1973 return FAIL;
1974 }
1975
1976 //step6:send burn cmd to move data to flash from sram
1977 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd&0x0F);
1978 if(ret <= 0)
1979 {
1980 GTP_ERROR("[burn_fw_app_section]send burn cmd fail.");
1981 return FAIL;
1982 }
1983 GTP_DEBUG("[burn_fw_section]Wait for the burn is complete......");
1984 do{
1985 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1986 if(ret <= 0)
1987 {
1988 GTP_ERROR("[burn_fw_app_section]Get burn state fail");
1989 return FAIL;
1990 }
1991 msleep(10);
1992 //GTP_DEBUG("[burn_fw_app_section]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1993 }while(rd_buf[GTP_ADDR_LENGTH]);
1994
1995 //step7:recall fw section
1996 ret = gup_recall_check(client, fw_section, start_addr, len);
1997 if(FAIL == ret)
1998 {
1999 GTP_ERROR("[burn_fw_app_section]recall check %dk firmware fail.", len/1024);
2000 return FAIL;
2001 }
2002
2003 return SUCCESS;
2004 }
2005
2006 static u8 gup_burn_fw_app_code(struct i2c_client *client)
2007 {
2008 u8* fw_app_code = NULL;
2009 u8 retry = 0;
2010 s32 ret = 0;
2011 //u16 start_index = 4*FW_SECTION_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH + FW_DSP_ISP_LENGTH + FW_BOOT_ISP_LENGTH; // 32 + 4 + 2 + 4 = 42K
2012 u16 start_index;
2013
2014 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
2015 {
2016 GTP_INFO("No need to upgrade the app code!");
2017 return SUCCESS;
2018 }
2019 start_index = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
2020 GTP_DEBUG("[burn_fw_app_code]Begin burn app_code firmware---->>");
2021
2022 //step1:alloc memory
2023 GTP_DEBUG("[burn_fw_app_code]step1:alloc memory");
2024 while(retry++ < 5)
2025 {
2026 fw_app_code = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
2027 if(fw_app_code == NULL)
2028 {
2029 continue;
2030 }
2031 else
2032 {
2033 GTP_INFO("[burn_fw_app_code]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
2034 break;
2035 }
2036 }
2037 if(retry >= 5)
2038 {
2039 GTP_ERROR("[burn_fw_app_code]Alloc memory fail,exit.");
2040 return FAIL;
2041 }
2042
2043 //step2:load app_code firmware section 1 file data
2044 GTP_DEBUG("[burn_fw_app_code]step2:load app_code firmware section 1 file data");
2045 ret = gup_load_section_file(fw_app_code, start_index, FW_SECTION_LENGTH, SEEK_SET);
2046 if(FAIL == ret)
2047 {
2048 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 1 fail.");
2049 goto exit_burn_fw_app_code;
2050 }
2051
2052 //step3:burn app_code firmware section 1
2053 GTP_DEBUG("[burn_fw_app_code]step3:burn app_code firmware section 1");
2054 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3A);
2055 if(FAIL == ret)
2056 {
2057 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 1 fail.");
2058 goto exit_burn_fw_app_code;
2059 }
2060
2061 //step5:load app_code firmware section 2 file data
2062 GTP_DEBUG("[burn_fw_app_code]step5:load app_code firmware section 2 file data");
2063 ret = gup_load_section_file(fw_app_code, start_index+FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2064 if(FAIL == ret)
2065 {
2066 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 2 fail.");
2067 goto exit_burn_fw_app_code;
2068 }
2069
2070 //step6:burn app_code firmware section 2
2071 GTP_DEBUG("[burn_fw_app_code]step6:burn app_code firmware section 2");
2072 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3B);
2073 if(FAIL == ret)
2074 {
2075 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 2 fail.");
2076 goto exit_burn_fw_app_code;
2077 }
2078
2079 //step7:load app_code firmware section 3 file data
2080 GTP_DEBUG("[burn_fw_app_code]step7:load app_code firmware section 3 file data");
2081 ret = gup_load_section_file(fw_app_code, start_index+2*FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2082 if(FAIL == ret)
2083 {
2084 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 3 fail.");
2085 goto exit_burn_fw_app_code;
2086 }
2087
2088 //step8:burn app_code firmware section 3
2089 GTP_DEBUG("[burn_fw_app_code]step8:burn app_code firmware section 3");
2090 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3C);
2091 if(FAIL == ret)
2092 {
2093 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 3 fail.");
2094 goto exit_burn_fw_app_code;
2095 }
2096
2097 //step9:load app_code firmware section 4 file data
2098 GTP_DEBUG("[burn_fw_app_code]step9:load app_code firmware section 4 file data");
2099 ret = gup_load_section_file(fw_app_code, start_index + 3*FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2100 if(FAIL == ret)
2101 {
2102 GTP_ERROR("[burn_fw_app_code]load app_code firmware section 4 fail.");
2103 goto exit_burn_fw_app_code;
2104 }
2105
2106 //step10:burn app_code firmware section 4
2107 GTP_DEBUG("[burn_fw_app_code]step10:burn app_code firmware section 4");
2108 ret = gup_burn_fw_app_section(client, fw_app_code, 0x9000, FW_SECTION_LENGTH, 0x3D);
2109 if(FAIL == ret)
2110 {
2111 GTP_ERROR("[burn_fw_app_code]burn app_code firmware section 4 fail.");
2112 goto exit_burn_fw_app_code;
2113 }
2114
2115 update_msg.fw_burned_len += FW_APP_CODE_LENGTH;
2116 GTP_DEBUG("[burn_fw_gwake]Burned length:%d", update_msg.fw_burned_len);
2117 ret = SUCCESS;
2118
2119 exit_burn_fw_app_code:
2120 kfree(fw_app_code);
2121 return ret;
2122 }
2123
2124 static u8 gup_burn_fw_finish(struct i2c_client *client)
2125 {
2126 u8* fw_ss51 = NULL;
2127 u8 retry = 0;
2128 s32 ret = 0;
2129
2130 GTP_INFO("[burn_fw_finish]burn first 8K of ss51 and finish update.");
2131 //step1:alloc memory
2132 GTP_DEBUG("[burn_fw_finish]step1:alloc memory");
2133 while(retry++ < 5)
2134 {
2135 fw_ss51 = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
2136 if(fw_ss51 == NULL)
2137 {
2138 continue;
2139 }
2140 else
2141 {
2142 GTP_DEBUG("[burn_fw_finish]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
2143 break;
2144 }
2145 }
2146 if(retry >= 5)
2147 {
2148 GTP_ERROR("[burn_fw_finish]Alloc memory fail,exit.");
2149 return FAIL;
2150 }
2151
2152 GTP_DEBUG("[burn_fw_finish]step2: burn ss51 first 8K.");
2153 ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
2154 if(FAIL == ret)
2155 {
2156 GTP_ERROR("[burn_fw_finish]load ss51 firmware section 1 fail.");
2157 goto exit_burn_fw_finish;
2158 }
2159
2160 GTP_DEBUG("[burn_fw_finish]step3:clear control flag");
2161 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
2162 if(ret <= 0)
2163 {
2164 GTP_ERROR("[burn_fw_finish]clear control flag fail.");
2165 goto exit_burn_fw_finish;
2166 }
2167
2168 GTP_DEBUG("[burn_fw_finish]step4:burn ss51 firmware section 1");
2169 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
2170 if(FAIL == ret)
2171 {
2172 GTP_ERROR("[burn_fw_finish]burn ss51 firmware section 1 fail.");
2173 goto exit_burn_fw_finish;
2174 }
2175
2176 //step11:enable download DSP code
2177 GTP_DEBUG("[burn_fw_finish]step5:enable download DSP code ");
2178 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x99);
2179 if(ret <= 0)
2180 {
2181 GTP_ERROR("[burn_fw_finish]enable download DSP code fail.");
2182 goto exit_burn_fw_finish;
2183 }
2184
2185 //step12:release ss51 & hold dsp
2186 GTP_DEBUG("[burn_fw_finish]step6:release ss51 & hold dsp");
2187 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x08);
2188 if(ret <= 0)
2189 {
2190 GTP_ERROR("[burn_fw_finish]release ss51 & hold dsp fail.");
2191 goto exit_burn_fw_finish;
2192 }
2193
2194 if (fw_ss51)
2195 {
2196 kfree(fw_ss51);
2197 }
2198 return SUCCESS;
2199
2200 exit_burn_fw_finish:
2201 if (fw_ss51)
2202 {
2203 kfree(fw_ss51);
2204 }
2205 return FAIL;
2206 }
2207
2208 s32 gup_update_proc(void *dir)
2209 {
2210 s32 ret = 0;
2211 u8 retry = 0;
2212 s32 update_ret = FAIL;
2213 st_fw_head fw_head;
2214
2215 GTP_INFO("[update_proc]Begin update ......");
2216
2217 #if GTP_AUTO_UPDATE
2218 if (1 == searching_file)
2219 {
2220 u8 timeout = 0;
2221 searching_file = 0; // exit .bin update file searching
2222 GTP_INFO("Exiting searching file for auto update.");
2223 while ((show_len != 200) && (show_len != 100) && (timeout++ < 150)) // wait for auto update quitted completely
2224 {
2225 msleep(100);
2226 }
2227 }
2228 #endif
2229
2230 show_len = 1;
2231 total_len = 100;
2232
2233 #if GTP_COMPATIBLE_MODE
2234 if (CHIP_TYPE_GT9F == gtp_chip_type)
2235 {
2236 return gup_fw_download_proc(dir, GTP_FL_FW_BURN);
2237 }
2238 #endif
2239 update_msg.file = NULL;
2240 ret = gup_check_update_file(i2c_client_point, &fw_head, (u8 *)dir); //20121212
2241
2242 if (FAIL == ret)
2243 {
2244 GTP_ERROR("[update_proc]check update file fail.");
2245 goto file_fail;
2246 }
2247
2248 //gtp_reset_guitar(i2c_client_point, 20);
2249 ret = gup_get_ic_fw_msg(i2c_client_point);
2250
2251 if (FAIL == ret)
2252 {
2253 GTP_ERROR("[update_proc]get ic message fail.");
2254 goto file_fail;
2255 }
2256
2257 ret = gup_enter_update_judge(&fw_head); //20121212
2258
2259 if (FAIL == ret)
2260 {
2261 GTP_ERROR("[update_proc]Check *.bin file fail.");
2262 goto file_fail;
2263 }
2264
2265 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
2266 #if GTP_ESD_PROTECT
2267 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
2268 #endif
2269 ret = gup_enter_update_mode(i2c_client_point);
2270
2271 if (FAIL == ret)
2272 {
2273 GTP_ERROR("[update_proc]enter update mode fail.");
2274 goto update_fail;
2275 }
2276
2277 while (retry++ < 5)
2278 {
2279 show_len = 10;
2280 total_len = 100;
2281 update_msg.fw_burned_len = 0;
2282 GTP_DEBUG("[update_proc]Burned length:%d", update_msg.fw_burned_len);
2283 ret = gup_burn_dsp_isp(i2c_client_point);
2284 if(FAIL == ret)
2285 {
2286 GTP_ERROR("[update_proc]burn dsp isp fail.");
2287 continue;
2288 }
2289
2290 show_len = 30;
2291 ret = gup_burn_fw_ss51(i2c_client_point);
2292 if(FAIL == ret)
2293 {
2294 GTP_ERROR("[update_proc]burn ss51 firmware fail.");
2295 continue;
2296 }
2297
2298 show_len = 40;
2299 ret = gup_burn_fw_dsp(i2c_client_point);
2300 if(FAIL == ret)
2301 {
2302 GTP_ERROR("[update_proc]burn dsp firmware fail.");
2303 continue;
2304 }
2305
2306 show_len = 50;
2307 ret = gup_burn_fw_boot(i2c_client_point);
2308 if(FAIL == ret)
2309 {
2310 GTP_ERROR("[update_proc]burn bootloader firmware fail.");
2311 continue;
2312 }
2313 show_len = 60;
2314
2315 ret = gup_burn_fw_boot_isp(i2c_client_point);
2316 if (FAIL == ret)
2317 {
2318 GTP_ERROR("[update_proc]burn boot_isp firmware fail.");
2319 continue;
2320 }
2321
2322 show_len = 70;
2323 ret = gup_burn_fw_link(i2c_client_point);
2324 if (FAIL == ret)
2325 {
2326 GTP_ERROR("[update_proc]burn link firmware fail.");
2327 continue;
2328 }
2329
2330 show_len = 80;
2331 ret = gup_burn_fw_app_code(i2c_client_point);
2332 if (FAIL == ret)
2333 {
2334 GTP_ERROR("[update_proc]burn app_code firmware fail.");
2335 continue;
2336 }
2337 show_len = 90;
2338 ret = gup_burn_fw_finish(i2c_client_point);
2339 if (FAIL == ret)
2340 {
2341 GTP_ERROR("[update_proc]burn finish fail.");
2342 continue;
2343 }
2344 show_len = 95;
2345 GTP_INFO("[update_proc]UPDATE SUCCESS.");
2346 break;
2347 }
2348
2349 if (retry >= 5)
2350 {
2351 GTP_ERROR("[update_proc]retry timeout,UPDATE FAIL.");
2352 update_ret = FAIL;
2353 }
2354 else
2355 {
2356 update_ret = SUCCESS;
2357 }
2358
2359 update_fail:
2360 GTP_DEBUG("[update_proc]leave update mode.");
2361 gup_leave_update_mode();
2362
2363 if (SUCCESS == update_ret)
2364 {
2365 GTP_DEBUG("[update_proc]send config.");
2366 ret = gtp_send_cfg(i2c_client_point);
2367 if (ret < 0)
2368 {
2369 GTP_ERROR("[update_proc]send config fail.");
2370 }
2371 }
2372
2373 #if GTP_ESD_PROTECT
2374 gtp_esd_switch(i2c_client_point, SWITCH_ON);
2375 #endif
2376
2377 file_fail:
2378 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
2379
2380 if (update_msg.file && !IS_ERR(update_msg.file))
2381 {
2382 if (update_msg.old_fs)
2383 {
2384 set_fs(update_msg.old_fs);
2385 }
2386 filp_close(update_msg.file, NULL);
2387 }
2388 #if (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE && GTP_AUTO_UPDATE_CFG)
2389 if (NULL == dir)
2390 {
2391 gup_search_file(AUTO_SEARCH_CFG);
2392 if (got_file_flag & CFG_FILE_READY)
2393 {
2394 ret = gup_update_config(i2c_client_point);
2395 if (FAIL == ret)
2396 {
2397 GTP_ERROR("Update config failed!");
2398 }
2399 }
2400 }
2401 #endif
2402
2403 total_len = 100;
2404 if (SUCCESS == update_ret)
2405 {
2406 show_len = 100;
2407 return SUCCESS;
2408 }
2409 else
2410 {
2411 show_len = 200;
2412 return FAIL;
2413 }
2414 }
2415
2416 u8 gup_init_update_proc(struct i2c_client *client)
2417 {
2418 struct task_struct *thread = NULL;
2419
2420 GTP_INFO("Ready to run auto update thread");
2421
2422 #if GTP_COMPATIBLE_MODE
2423 if (CHIP_TYPE_GT9F == gtp_chip_type)
2424 {
2425 thread = kthread_run(gup_update_proc, "update", "fl_auto_update");
2426 }
2427 else
2428 #endif
2429 {
2430 thread = kthread_run(gup_update_proc, (void *)NULL, "guitar_update");
2431 }
2432 if (IS_ERR(thread))
2433 {
2434 GTP_ERROR("Failed to create update thread.\n");
2435 return -1;
2436 }
2437
2438 return 0;
2439 }
2440
2441
2442 //******************* For GT9XXF Start ********************//
2443
2444 #define FL_UPDATE_PATH "/data/_fl_update_.bin"
2445 #define FL_UPDATE_PATH_SD "/sdcard/_fl_update_.bin"
2446
2447 #define GUP_FW_CHK_SIZE 256
2448 #define MAX_CHECK_TIMES 128 // max: 2 * (16 * 1024) / 256 = 128
2449
2450 //for clk cal
2451 #define PULSE_LENGTH (200)
2452 #define INIT_CLK_DAC (50)
2453 #define MAX_CLK_DAC (120)
2454 #define CLK_AVG_TIME (1)
2455 #define MILLION 1000000
2456
2457 #define _wRW_MISCTL__RG_DMY 0x4282
2458 #define _bRW_MISCTL__RG_OSC_CALIB 0x4268
2459 #define _fRW_MISCTL__GIO0 0x41e9
2460 #define _fRW_MISCTL__GIO1 0x41ed
2461 #define _fRW_MISCTL__GIO2 0x41f1
2462 #define _fRW_MISCTL__GIO3 0x41f5
2463 #define _fRW_MISCTL__GIO4 0x41f9
2464 #define _fRW_MISCTL__GIO5 0x41fd
2465 #define _fRW_MISCTL__GIO6 0x4201
2466 #define _fRW_MISCTL__GIO7 0x4205
2467 #define _fRW_MISCTL__GIO8 0x4209
2468 #define _fRW_MISCTL__GIO9 0x420d
2469 #define _fRW_MISCTL__MEA 0x41a0
2470 #define _bRW_MISCTL__MEA_MODE 0x41a1
2471 #define _wRW_MISCTL__MEA_MAX_NUM 0x41a4
2472 #define _dRO_MISCTL__MEA_VAL 0x41b0
2473 #define _bRW_MISCTL__MEA_SRCSEL 0x41a3
2474 #define _bRO_MISCTL__MEA_RDY 0x41a8
2475 #define _rRW_MISCTL__ANA_RXADC_B0_ 0x4250
2476 #define _bRW_MISCTL__RG_LDO_A18_PWD 0x426f
2477 #define _bRW_MISCTL__RG_BG_PWD 0x426a
2478 #define _bRW_MISCTL__RG_CLKGEN_PWD 0x4269
2479 #define _fRW_MISCTL__RG_RXADC_PWD 0x426a
2480 #define _bRW_MISCTL__OSC_CK_SEL 0x4030
2481 #define _rRW_MISCTL_RG_DMY83 0x4283
2482 #define _rRW_MISCTL__GIO1CTL_B2_ 0x41ee
2483 #define _rRW_MISCTL__GIO1CTL_B1_ 0x41ed
2484
2485 #if GTP_COMPATIBLE_MODE
2486
2487 u8 gup_check_fs_mounted(char *path_name)
2488 {
2489 struct path root_path;
2490 struct path path;
2491 int err;
2492 err = kern_path("/", LOOKUP_FOLLOW, &root_path);
2493
2494 if (err)
2495 return FAIL;
2496
2497 err = kern_path(path_name, LOOKUP_FOLLOW, &path);
2498
2499 if (err)
2500 return FAIL;
2501
2502 if (path.mnt->mnt_sb == root_path.mnt->mnt_sb)
2503 {
2504 //-- not mounted
2505 return FAIL;
2506 }
2507 else
2508 {
2509 return SUCCESS;
2510 }
2511 }
2512
2513 s32 gup_hold_ss51_dsp(struct i2c_client *client)
2514 {
2515 s32 ret = -1;
2516 s32 retry = 0;
2517 u8 rd_buf[3];
2518
2519 while(retry++ < 200)
2520 {
2521 // step4:Hold ss51 & dsp
2522 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
2523 if(ret <= 0)
2524 {
2525 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
2526 continue;
2527 }
2528
2529 // step5:Confirm hold
2530 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
2531 if (ret <= 0)
2532 {
2533 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
2534 continue;
2535 }
2536 if (0x0C == rd_buf[GTP_ADDR_LENGTH])
2537 {
2538 GTP_DEBUG("[enter_update_mode]Hold ss51 & dsp confirm SUCCESS");
2539 break;
2540 }
2541 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
2542 }
2543 if(retry >= 200)
2544 {
2545 GTP_ERROR("Enter update Hold ss51 failed.");
2546 return FAIL;
2547 }
2548 //DSP_CK and DSP_ALU_CK PowerOn
2549 ret = gup_set_ic_msg(client, 0x4010, 0x00);
2550 if (ret <= 0)
2551 {
2552 GTP_ERROR("[enter_update_mode]DSP_CK and DSP_ALU_CK PowerOn fail.");
2553 return FAIL;
2554 }
2555
2556 //disable wdt
2557 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
2558
2559 if (ret <= 0)
2560 {
2561 GTP_ERROR("[enter_update_mode]disable wdt fail.");
2562 return FAIL;
2563 }
2564
2565 //clear cache enable
2566 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
2567
2568 if (ret <= 0)
2569 {
2570 GTP_ERROR("[enter_update_mode]clear cache enable fail.");
2571 return FAIL;
2572 }
2573
2574 //set boot from sram
2575 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
2576
2577 if (ret <= 0)
2578 {
2579 GTP_ERROR("[enter_update_mode]set boot from sram fail.");
2580 return FAIL;
2581 }
2582
2583 //software reboot
2584 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
2585 if (ret <= 0)
2586 {
2587 GTP_ERROR("[enter_update_mode]software reboot fail.");
2588 return FAIL;
2589 }
2590
2591 return SUCCESS;
2592 }
2593
2594 s32 gup_enter_update_mode_fl(struct i2c_client *client)
2595 {
2596 s32 ret = -1;
2597 //s32 retry = 0;
2598 //u8 rd_buf[3];
2599
2600 //step1:RST output low last at least 2ms
2601 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
2602 msleep(2);
2603
2604 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
2605 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
2606 msleep(2);
2607
2608 //step3:RST output high reset guitar
2609 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
2610
2611 msleep(5);
2612
2613 //select addr & hold ss51_dsp
2614 ret = gup_hold_ss51_dsp(client);
2615 if (ret <= 0)
2616 {
2617 GTP_ERROR("[enter_update_mode]hold ss51 & dsp failed.");
2618 return FAIL;
2619 }
2620
2621 //clear control flag
2622 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
2623
2624 if (ret <= 0)
2625 {
2626 GTP_ERROR("[enter_update_mode]clear control flag fail.");
2627 return FAIL;
2628 }
2629
2630 //set scramble
2631 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
2632
2633 if (ret <= 0)
2634 {
2635 GTP_ERROR("[enter_update_mode]set scramble fail.");
2636 return FAIL;
2637 }
2638
2639 //enable accessing code
2640 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
2641
2642 if (ret <= 0)
2643 {
2644 GTP_ERROR("[enter_update_mode]enable accessing code fail.");
2645 return FAIL;
2646 }
2647
2648 return SUCCESS;
2649 }
2650
2651
2652 static s32 gup_prepare_fl_fw(char *path, st_fw_head *fw_head)
2653 {
2654 s32 i = 0;
2655 s32 ret = 0;
2656 s32 timeout = 0;
2657
2658 if (!memcmp(path, "update", 6))
2659 {
2660 GTP_INFO("Search for Flashless firmware file to update");
2661 searching_file = 1;
2662 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
2663 {
2664 if (0 == searching_file)
2665 {
2666 GTP_INFO("Force terminate searching file auto update.");
2667 return FAIL;
2668 }
2669 update_msg.file = filp_open(FL_UPDATE_PATH, O_RDONLY, 0);
2670 if (IS_ERR(update_msg.file))
2671 {
2672 update_msg.file = filp_open(FL_UPDATE_PATH_SD, O_RDONLY, 0);
2673 if (IS_ERR(update_msg.file))
2674 {
2675 msleep(2000);
2676 continue;
2677 }
2678 else
2679 {
2680 path = FL_UPDATE_PATH_SD;
2681 break;
2682 }
2683 }
2684 else
2685 {
2686 path = FL_UPDATE_PATH;
2687 break;
2688 }
2689 }
2690 searching_file = 0;
2691 if (i >= 50)
2692 {
2693 GTP_ERROR("Search timeout, update aborted");
2694 return FAIL;
2695 }
2696 else
2697 {
2698 _CLOSE_FILE(update_msg.file);
2699 }
2700 while (rqst_processing && (timeout++ < 15))
2701 {
2702 GTP_INFO("wait for request process completed!");
2703 msleep(1000);
2704 }
2705 }
2706
2707 GTP_INFO("Firmware update file path: %s", path);
2708 update_msg.file = filp_open(path, O_RDONLY, 0);
2709
2710 if (IS_ERR(update_msg.file))
2711 {
2712 GTP_ERROR("Open update file(%s) error!", path);
2713 return FAIL;
2714 }
2715
2716 update_msg.old_fs = get_fs();
2717 set_fs(KERNEL_DS);
2718 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2719 update_msg.fw_total_len = update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_END);
2720 if (sizeof(gtp_default_FW_fl) != update_msg.fw_total_len)
2721 {
2722 GTP_ERROR("Inconsistent firmware size. File size: %d, default fw size: %d", update_msg.fw_total_len, sizeof(gtp_default_FW_fl));
2723 set_fs(update_msg.old_fs);
2724 _CLOSE_FILE(update_msg.file);
2725 return FAIL;
2726 }
2727
2728 GTP_DEBUG("Firmware size: %d", update_msg.fw_total_len);
2729 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2730 update_msg.file->f_op->read(update_msg.file, (char*)fw_head, FW_HEAD_LENGTH, &update_msg.file->f_pos);
2731 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2732 //copy fw file to gtp_default_FW_fl array
2733 ret = update_msg.file->f_op->read(update_msg.file,
2734 (char*)gtp_default_FW_fl,
2735 update_msg.fw_total_len,
2736 &update_msg.file->f_pos);
2737 if (ret < 0)
2738 {
2739 GTP_ERROR("Failed to read firmware data from %s, err-code: %d", path, ret);
2740 ret = FAIL;
2741 }
2742 else
2743 {
2744 ret = SUCCESS;
2745 }
2746 set_fs(update_msg.old_fs);
2747 _CLOSE_FILE(update_msg.file);
2748 return ret;
2749 }
2750
2751 static u8 gup_check_update_file_fl(struct i2c_client *client, st_fw_head *fw_head, char *path)
2752 {
2753 s32 i = 0;
2754 s32 fw_checksum = 0;
2755 s32 ret = 0;
2756
2757 if (NULL != path)
2758 {
2759 ret = gup_prepare_fl_fw(path, fw_head);
2760 if (ret == FAIL)
2761 {
2762 return FAIL;
2763 }
2764 }
2765 else
2766 {
2767 memcpy(fw_head, gtp_default_FW_fl, FW_HEAD_LENGTH);
2768 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
2769 GTP_INFO("FILE PID:%s", fw_head->pid);
2770 fw_head->vid = ((fw_head->vid & 0xFF00) >> 8) + ((fw_head->vid & 0x00FF) << 8);
2771 GTP_INFO("FILE VID:%04x", fw_head->vid);
2772 }
2773
2774 //check firmware legality
2775 fw_checksum = 0;
2776 for (i = FW_HEAD_LENGTH; i < (FW_HEAD_LENGTH + update_msg.fw_total_len); i += 2)
2777 {
2778 fw_checksum = (gtp_default_FW_fl[i]<<8) + gtp_default_FW_fl[i+1];
2779 }
2780
2781 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
2782 if(fw_checksum&0xFFFF)
2783 {
2784 GTP_ERROR("Illegal firmware file.");
2785 return FAIL;
2786 }
2787
2788 return SUCCESS;
2789 }
2790
2791 static u8 gup_download_fw_ss51(struct i2c_client *client, u8 dwn_mode)
2792 {
2793 s32 ret = 0;
2794
2795 if(GTP_FL_FW_BURN == dwn_mode)
2796 {
2797 GTP_INFO("[download_fw_ss51]Begin download ss51 firmware---->>");
2798 }
2799 else
2800 {
2801 GTP_INFO("[download_fw_ss51]Begin check ss51 firmware----->>");
2802 }
2803 //step1:download FW section 1
2804 GTP_DEBUG("[download_fw_ss51]step1:download FW section 1");
2805 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x00);
2806
2807 if (ret <= 0)
2808 {
2809 GTP_ERROR("[download_fw_ss51]select bank0 fail.");
2810 ret = FAIL;
2811 goto exit_download_fw_ss51;
2812 }
2813
2814
2815 ret = i2c_write_bytes(client, 0xC000,
2816 &gtp_default_FW_fl[FW_HEAD_LENGTH], FW_DOWNLOAD_LENGTH); // write the first bank
2817
2818 if (ret == -1)
2819 {
2820 GTP_ERROR("[download_fw_ss51]download FW section 1 fail.");
2821 ret = FAIL;
2822 goto exit_download_fw_ss51;
2823 }
2824
2825
2826 if (GTP_FL_FW_BURN == dwn_mode)
2827 {
2828 ret = gup_check_and_repair(i2c_client_point,
2829 0xC000,
2830 &gtp_default_FW_fl[FW_HEAD_LENGTH],
2831 FW_DOWNLOAD_LENGTH);
2832 if(FAIL == ret)
2833 {
2834 GTP_ERROR("[download_fw_ss51]Checked FW section 1 fail.");
2835 goto exit_download_fw_ss51;
2836 }
2837 }
2838
2839 //step2:download FW section 2
2840 GTP_DEBUG("[download_fw_ss51]step2:download FW section 1");
2841 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x01);
2842
2843 if (ret <= 0)
2844 {
2845 GTP_ERROR("[download_fw_ss51]select bank1 fail.");
2846 ret = FAIL;
2847 goto exit_download_fw_ss51;
2848 }
2849
2850 ret = i2c_write_bytes(client, 0xC000, &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],FW_DOWNLOAD_LENGTH); // write the second bank
2851
2852 if (ret == -1)
2853 {
2854 GTP_ERROR("[download_fw_ss51]download FW section 2 fail.");
2855 ret = FAIL;
2856 goto exit_download_fw_ss51;
2857 }
2858
2859 if (GTP_FL_FW_BURN == dwn_mode)
2860 {
2861 ret = gup_check_and_repair(i2c_client_point,
2862 0xC000,
2863 &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],
2864 FW_DOWNLOAD_LENGTH);
2865
2866 if(FAIL == ret)
2867 {
2868 GTP_ERROR("[download_fw_ss51]Checked FW section 2 fail.");
2869 goto exit_download_fw_ss51;
2870 }
2871 }
2872 ret = SUCCESS;
2873
2874 exit_download_fw_ss51:
2875
2876 return ret;
2877 }
2878 #if (!GTP_SUPPORT_I2C_DMA)
2879 static s32 i2c_auto_read(struct i2c_client *client,u8 *rxbuf, int len)
2880 {
2881 u8 retry;
2882 u16 left = len;
2883 u16 offset = 0;
2884
2885 struct i2c_msg msg =
2886 {
2887 //.addr = ((client->addr &I2C_MASK_FLAG) | (I2C_ENEXT_FLAG)),
2888 .addr = ((client->addr &I2C_MASK_FLAG) | (I2C_PUSHPULL_FLAG)),
2889 .flags = I2C_M_RD,
2890 .timing = I2C_MASTER_CLOCK
2891 };
2892
2893 if(NULL == rxbuf)
2894 {
2895 return -1;
2896 }
2897
2898 while (left > 0)
2899 {
2900 msg.buf = &rxbuf[offset];
2901
2902 if (left > MAX_TRANSACTION_LENGTH)
2903 {
2904 msg.len = MAX_TRANSACTION_LENGTH;
2905 left -= MAX_TRANSACTION_LENGTH;
2906 offset += MAX_TRANSACTION_LENGTH;
2907 }
2908 else
2909 {
2910 msg.len = left;
2911 left = 0;
2912 }
2913
2914 retry = 0;
2915
2916 while (i2c_transfer(client->adapter, &msg, 1) != 1)
2917 {
2918 retry++;
2919
2920 if (retry == 20)
2921 {
2922 GTP_ERROR("I2C read 0x%X length=%d failed\n", offset, len);
2923 return -1;
2924 }
2925 }
2926 }
2927
2928 return 0;
2929 }
2930 #endif
2931 static u8 gup_check_and_repair(struct i2c_client *client, s32 chk_start_addr, u8 *target_fw, u32 chk_total_length)
2932 {
2933 s32 ret = 0;
2934 u32 chked_len = 0;
2935 u8 chked_times = 0;
2936 u32 chk_addr = 0;
2937 u8 chk_buf[GUP_FW_CHK_SIZE];
2938 u32 rd_size = 0;
2939 u8 flag_err = 0;
2940 s32 i = 0;
2941
2942 chk_addr = chk_start_addr;
2943 while((chked_times < MAX_CHECK_TIMES) && (chked_len < chk_total_length))
2944 {
2945 rd_size = chk_total_length - chked_len;
2946 if(rd_size >= GUP_FW_CHK_SIZE)
2947 {
2948 rd_size = GUP_FW_CHK_SIZE;
2949 }
2950 #if GTP_SUPPORT_I2C_DMA
2951 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
2952 #else
2953 if (!i)
2954 {
2955 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
2956 }
2957 else
2958 {
2959 ret = i2c_auto_read(client, chk_buf, rd_size);
2960 }
2961 #endif
2962
2963 if(-1 == ret)
2964 {
2965 GTP_ERROR("Read chk ram fw i2c error");
2966 chked_times++;
2967 continue;
2968 }
2969
2970 for(i=0; i<rd_size; i++)
2971 {
2972 if(chk_buf[i] != target_fw[i])
2973 {
2974 GTP_ERROR("Ram pos[0x%04x] checked failed,rewrite.", chk_addr + i);
2975 i2c_write_bytes(client, chk_addr+i, &target_fw[i], rd_size-i);
2976 flag_err = 1;
2977 i = 0;
2978 break;
2979 }
2980 }
2981
2982 if(!flag_err)
2983 {
2984 GTP_DEBUG("Ram pos[0x%04X] check pass!", chk_addr);
2985 chked_len += rd_size;
2986 target_fw += rd_size;
2987 chk_addr += rd_size;
2988 }
2989 else
2990 {
2991 flag_err = 0;
2992 chked_times++;
2993 }
2994 }
2995
2996 if(chked_times >= MAX_CHECK_TIMES)
2997 {
2998 GTP_ERROR("Ram data check failed.");
2999 return FAIL;
3000 }
3001 return SUCCESS;
3002 }
3003
3004 static u8 gup_download_fw_dsp(struct i2c_client *client, u8 dwn_mode)
3005 {
3006 s32 ret = 0;
3007
3008 if(GTP_FL_FW_BURN == dwn_mode)
3009 {
3010 GTP_INFO("[download_fw_dsp]Begin download dsp fw---->>");
3011 }
3012 else
3013 {
3014 GTP_INFO("[download_fw_dsp]Begin check dsp fw---->>");
3015 }
3016
3017 //step1:select bank2
3018 GTP_DEBUG("[download_fw_dsp]step1:select bank2");
3019 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
3020
3021 if (ret <= 0)
3022 {
3023 GTP_ERROR("[download_fw_dsp]select bank2 fail.");
3024 ret = FAIL;
3025 goto exit_download_fw_dsp;
3026 }
3027
3028 ret = i2c_write_bytes(client,
3029 0xC000,
3030 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
3031 FW_DSP_LENGTH); // write the second bank
3032 if (ret == -1)
3033 {
3034 GTP_ERROR("[download_fw_dsp]download FW dsp fail.");
3035 ret = FAIL;
3036 goto exit_download_fw_dsp;
3037 }
3038
3039 if (GTP_FL_FW_BURN == dwn_mode)
3040 {
3041 ret = gup_check_and_repair(client,
3042 0xC000,
3043 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
3044 FW_DSP_LENGTH);
3045
3046 if(FAIL == ret)
3047 {
3048 GTP_ERROR("[download_fw_dsp]Checked FW dsp fail.");
3049 goto exit_download_fw_dsp;
3050 }
3051
3052 }
3053 ret = SUCCESS;
3054
3055 exit_download_fw_dsp:
3056
3057 return ret;
3058 }
3059
3060 s32 gup_fw_download_proc(void *dir, u8 dwn_mode)
3061 {
3062 s32 ret = 0;
3063 u8 retry = 0;
3064 st_fw_head fw_head;
3065
3066 if(GTP_FL_FW_BURN == dwn_mode)
3067 {
3068 GTP_INFO("[fw_download_proc]Begin fw download ......");
3069 }
3070 else
3071 {
3072 GTP_INFO("[fw_download_proc]Begin fw check ......");
3073 }
3074 show_len = 0;
3075 total_len = 100;
3076
3077 ret = gup_check_update_file_fl(i2c_client_point, &fw_head, (char *)dir);
3078
3079 show_len = 10;
3080
3081 if (FAIL == ret)
3082 {
3083 GTP_ERROR("[fw_download_proc]check update file fail.");
3084 goto file_fail;
3085 }
3086
3087 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
3088 if (NULL != dir)
3089 {
3090 #if GTP_ESD_PROTECT
3091 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
3092 #endif
3093 }
3094
3095 ret = gup_enter_update_mode_fl(i2c_client_point);
3096 show_len = 20;
3097
3098 if (FAIL == ret)
3099 {
3100 GTP_ERROR("[fw_download_proc]enter update mode fail.");
3101 goto download_fail;
3102 }
3103
3104 while (retry++ < 5)
3105 {
3106 ret = gup_download_fw_ss51(i2c_client_point, dwn_mode);
3107 show_len = 60;
3108 if (FAIL == ret)
3109 {
3110 GTP_ERROR("[fw_download_proc]burn ss51 firmware fail.");
3111 continue;
3112 }
3113
3114 ret = gup_download_fw_dsp(i2c_client_point, dwn_mode);
3115 show_len = 80;
3116 if (FAIL == ret)
3117 {
3118 GTP_ERROR("[fw_download_proc]burn dsp firmware fail.");
3119 continue;
3120 }
3121
3122 GTP_INFO("[fw_download_proc]UPDATE SUCCESS.");
3123 break;
3124 }
3125
3126 if (retry >= 5)
3127 {
3128 GTP_ERROR("[fw_download_proc]retry timeout,UPDATE FAIL.");
3129 goto download_fail;
3130 }
3131
3132 if (NULL != dir)
3133 {
3134 gtp_fw_startup(i2c_client_point);
3135 #if GTP_ESD_PROTECT
3136 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3137 #endif
3138 }
3139 show_len = 100;
3140 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3141 return SUCCESS;
3142
3143 download_fail:
3144 if (NULL != dir)
3145 {
3146 gtp_fw_startup(i2c_client_point);
3147 #if GTP_ESD_PROTECT
3148 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3149 #endif
3150 }
3151
3152 file_fail:
3153 show_len = 200;
3154 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3155 return FAIL;
3156 }
3157
3158
3159 static void gup_bit_write(s32 addr, s32 bit, s32 val)
3160 {
3161 u8 buf;
3162 i2c_read_bytes(i2c_client_point, addr, &buf, 1);
3163
3164 buf = (buf & (~((u8)1 << bit))) | ((u8)val << bit);
3165
3166 i2c_write_bytes(i2c_client_point, addr, &buf, 1);
3167 }
3168
3169 static void gup_clk_count_init(s32 bCh, s32 bCNT)
3170 {
3171 u8 buf;
3172
3173 //_fRW_MISCTL__MEA_EN = 0; //Frequency measure enable
3174 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
3175 //_fRW_MISCTL__MEA_CLR = 1; //Frequency measure clear
3176 gup_bit_write(_fRW_MISCTL__MEA, 1, 1);
3177 //_bRW_MISCTL__MEA_MODE = 0; //Pulse mode
3178 buf = 0;
3179 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_MODE, &buf, 1);
3180 //_bRW_MISCTL__MEA_SRCSEL = 8 + bCh; //From GIO1
3181 buf = 8 + bCh;
3182 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_SRCSEL, &buf, 1);
3183 //_wRW_MISCTL__MEA_MAX_NUM = bCNT; //Set the Measure Counts = 1
3184 buf = bCNT;
3185 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__MEA_MAX_NUM, &buf, 1);
3186 //_fRW_MISCTL__MEA_CLR = 0; //Frequency measure not clear
3187 gup_bit_write(_fRW_MISCTL__MEA, 1, 0);
3188 //_fRW_MISCTL__MEA_EN = 1;
3189 gup_bit_write(_fRW_MISCTL__MEA, 0, 1);
3190 }
3191
3192 static u32 gup_clk_count_get(void)
3193 {
3194 s32 ready = 0;
3195 s32 temp;
3196 s8 buf[4];
3197
3198 while ((ready == 0)) //Wait for measurement complete
3199 {
3200 i2c_read_bytes(i2c_client_point, _bRO_MISCTL__MEA_RDY, buf, 1);
3201 ready = buf[0];
3202 }
3203
3204 udelay(50);
3205
3206 //_fRW_MISCTL__MEA_EN = 0;
3207 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
3208 i2c_read_bytes(i2c_client_point, _dRO_MISCTL__MEA_VAL, buf, 4);
3209 GTP_INFO("Clk_count 0: %2X", buf[0]);
3210 GTP_INFO("Clk_count 1: %2X", buf[1]);
3211 GTP_INFO("Clk_count 2: %2X", buf[2]);
3212 GTP_INFO("Clk_count 3: %2X", buf[3]);
3213
3214 temp = (s32)buf[0] + ((s32)buf[1] << 8) + ((s32)buf[2] << 16) + ((s32)buf[3] << 24);
3215 GTP_INFO("Clk_count : %d", temp);
3216 return temp;
3217 }
3218 u8 gup_clk_dac_setting(int dac)
3219 {
3220 s8 buf1, buf2;
3221
3222 i2c_read_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
3223 i2c_read_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
3224
3225 buf1 = (buf1 & 0xFFCF) | ((dac & 0x03) << 4);
3226 buf2 = (dac >> 2) & 0x3f;
3227
3228 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
3229 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
3230
3231 return 0;
3232 }
3233
3234 static u8 gup_clk_calibration_pin_select(s32 bCh)
3235 {
3236 s32 i2c_addr;
3237
3238 switch (bCh)
3239 {
3240 case 0:
3241 i2c_addr = _fRW_MISCTL__GIO0;
3242 break;
3243
3244 case 1:
3245 i2c_addr = _fRW_MISCTL__GIO1;
3246 break;
3247
3248 case 2:
3249 i2c_addr = _fRW_MISCTL__GIO2;
3250 break;
3251
3252 case 3:
3253 i2c_addr = _fRW_MISCTL__GIO3;
3254 break;
3255
3256 case 4:
3257 i2c_addr = _fRW_MISCTL__GIO4;
3258 break;
3259
3260 case 5:
3261 i2c_addr = _fRW_MISCTL__GIO5;
3262 break;
3263
3264 case 6:
3265 i2c_addr = _fRW_MISCTL__GIO6;
3266 break;
3267
3268 case 7:
3269 i2c_addr = _fRW_MISCTL__GIO7;
3270 break;
3271
3272 case 8:
3273 i2c_addr = _fRW_MISCTL__GIO8;
3274 break;
3275
3276 case 9:
3277 i2c_addr = _fRW_MISCTL__GIO9;
3278 break;
3279 }
3280
3281 gup_bit_write(i2c_addr, 1, 0);
3282
3283 return 0;
3284 }
3285
3286 void gup_output_pulse(int t)
3287 {
3288 unsigned long flags;
3289 //s32 i;
3290
3291 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3292 udelay(10);
3293
3294 local_irq_save(flags);
3295
3296 mt_set_gpio_out(GTP_INT_PORT, 1);
3297 udelay(50);
3298 mt_set_gpio_out(GTP_INT_PORT, 0);
3299 udelay(t - 50);
3300 mt_set_gpio_out(GTP_INT_PORT, 1);
3301
3302 local_irq_restore(flags);
3303
3304 udelay(20);
3305 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3306 }
3307
3308 static void gup_sys_clk_init(void)
3309 {
3310 u8 buf;
3311
3312 //_fRW_MISCTL__RG_RXADC_CKMUX = 0;
3313 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 5, 0);
3314 //_bRW_MISCTL__RG_LDO_A18_PWD = 0; //DrvMISCTL_A18_PowerON
3315 buf = 0;
3316 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_LDO_A18_PWD, &buf, 1);
3317 //_bRW_MISCTL__RG_BG_PWD = 0; //DrvMISCTL_BG_PowerON
3318 buf = 0;
3319 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_BG_PWD, &buf, 1);
3320 //_bRW_MISCTL__RG_CLKGEN_PWD = 0; //DrvMISCTL_CLKGEN_PowerON
3321 buf = 0;
3322 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_CLKGEN_PWD, &buf, 1);
3323 //_fRW_MISCTL__RG_RXADC_PWD = 0; //DrvMISCTL_RX_ADC_PowerON
3324 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 0, 0);
3325 //_fRW_MISCTL__RG_RXADC_REF_PWD = 0; //DrvMISCTL_RX_ADCREF_PowerON
3326 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 1, 0);
3327 //gup_clk_dac_setting(60);
3328 //_bRW_MISCTL__OSC_CK_SEL = 1;;
3329 buf = 1;
3330 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__OSC_CK_SEL, &buf, 1);
3331 }
3332
3333 u8 gup_clk_calibration(void)
3334 {
3335 //u8 buf;
3336 //u8 trigger;
3337 s32 i;
3338 struct timeval start, end;
3339 s32 count;
3340 s32 count_ref;
3341 s32 sec;
3342 s32 usec;
3343 s32 ret = 0;
3344 //unsigned long flags;
3345
3346 //buf = 0x0C; // hold ss51 and dsp
3347 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
3348 ret = gup_hold_ss51_dsp(i2c_client_point);
3349 if (ret <= 0)
3350 {
3351 GTP_ERROR("[gup_clk_calibration]hold ss51 & dsp failed.");
3352 return FAIL;
3353 }
3354
3355 //_fRW_MISCTL__CLK_BIAS = 0; //disable clock bias
3356 gup_bit_write(_rRW_MISCTL_RG_DMY83, 7, 0);
3357
3358 //_fRW_MISCTL__GIO1_PU = 0; //set TOUCH INT PIN MODE as input
3359 gup_bit_write(_rRW_MISCTL__GIO1CTL_B2_, 0, 0);
3360
3361 //_fRW_MISCTL__GIO1_OE = 0; //set TOUCH INT PIN MODE as input
3362 gup_bit_write(_rRW_MISCTL__GIO1CTL_B1_, 1, 0);
3363
3364 //buf = 0x00;
3365 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
3366 //msleep(1000);
3367
3368 GTP_INFO("CLK calibration GO");
3369 gup_sys_clk_init();
3370 gup_clk_calibration_pin_select(1);//use GIO1 to do the calibration
3371
3372 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3373
3374 for (i = INIT_CLK_DAC; i < MAX_CLK_DAC; i++)
3375 {
3376 if (tpd_halt)
3377 {
3378 i = 80; // if sleeping while calibrating main clock, set it default 80
3379 break;
3380 }
3381 GTP_INFO("CLK calibration DAC %d", i);
3382
3383 gup_clk_dac_setting(i);
3384 gup_clk_count_init(1, CLK_AVG_TIME);
3385
3386 #if 0
3387 gup_output_pulse(PULSE_LENGTH);
3388 count = gup_clk_count_get();
3389
3390 if (count > PULSE_LENGTH * 60)//60= 60Mhz * 1us
3391 {
3392 break;
3393 }
3394
3395 #else
3396 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3397
3398 //local_irq_save(flags);
3399 do_gettimeofday(&start);
3400 mt_set_gpio_out(GTP_INT_PORT, 1);
3401 //local_irq_restore(flags);
3402
3403 msleep(1);
3404 mt_set_gpio_out(GTP_INT_PORT, 0);
3405 msleep(1);
3406
3407 //local_irq_save(flags);
3408 do_gettimeofday(&end);
3409 mt_set_gpio_out(GTP_INT_PORT, 1);
3410 //local_irq_restore(flags);
3411
3412 count = gup_clk_count_get();
3413 udelay(20);
3414 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3415
3416 usec = end.tv_usec - start.tv_usec;
3417 sec = end.tv_sec - start.tv_sec;
3418 count_ref = 60 * (usec+ sec * MILLION);//60= 60Mhz * 1us
3419
3420 GTP_DEBUG("== time %d, %d, %d", sec, usec, count_ref);
3421
3422 if (count > count_ref)
3423 {
3424 GTP_DEBUG("== count_diff %d", count - count_ref);
3425 break;
3426 }
3427
3428 #endif
3429 }
3430
3431 //clk_dac = i;
3432
3433 //gtp_reset_guitar(i2c_client_point, 20);
3434
3435 #if 0//for debug
3436 //-- ouput clk to GPIO 4
3437 buf = 0x00;
3438 i2c_write_bytes(i2c_client_point, 0x41FA, &buf, 1);
3439 buf = 0x00;
3440 i2c_write_bytes(i2c_client_point, 0x4104, &buf, 1);
3441 buf = 0x00;
3442 i2c_write_bytes(i2c_client_point, 0x4105, &buf, 1);
3443 buf = 0x00;
3444 i2c_write_bytes(i2c_client_point, 0x4106, &buf, 1);
3445 buf = 0x01;
3446 i2c_write_bytes(i2c_client_point, 0x4107, &buf, 1);
3447 buf = 0x06;
3448 i2c_write_bytes(i2c_client_point, 0x41F8, &buf, 1);
3449 buf = 0x02;
3450 i2c_write_bytes(i2c_client_point, 0x41F9, &buf, 1);
3451 #endif
3452
3453 GTP_GPIO_AS_INT(GTP_INT_PORT);
3454 return i;
3455 }
3456
3457
3458 #define BANK_LENGTH (16*1024)
3459 #define FIRMWARE_HEADER_LEN 14
3460
3461 static u32 current_system_length = 0;
3462
3463 char * gup_load_fw_from_file(char *filepath)
3464 {
3465 struct file *fw_file = NULL;
3466 mm_segment_t old_fs;
3467 long len = 0;
3468 char *buffer = NULL;
3469
3470 if(filepath == NULL)
3471 {
3472 GTP_ERROR("[Load_firmware]filepath: NULL");
3473 goto load_firmware_exit;
3474 }
3475
3476 old_fs = get_fs();
3477 set_fs(KERNEL_DS);
3478
3479 fw_file = filp_open(filepath, O_RDONLY, 0);
3480 if (fw_file == NULL || IS_ERR(fw_file))
3481 {
3482 GTP_ERROR("[Load_firmware]Failed to open: %s", filepath);
3483 goto load_firmware_exit;
3484 }
3485 fw_file->f_op->llseek(fw_file, 0, SEEK_SET);
3486 len = fw_file->f_op->llseek(fw_file, 0, SEEK_END);
3487 if(len<1024)
3488 {
3489 GTP_ERROR("[Load_firmware]Firmware is too short: %ld", len);
3490 goto load_firmware_failed;
3491 }
3492 buffer = (char *)kmalloc(sizeof(char) * len, GFP_KERNEL);
3493 if(buffer == NULL)
3494 {
3495 GTP_ERROR("[Load_firmware]Failed to allocate buffer: %ld", len);
3496 goto load_firmware_failed;
3497 }
3498
3499 memset(buffer, 0, sizeof(char) * len);
3500
3501 fw_file->f_op->llseek(fw_file, 0, SEEK_SET);
3502 fw_file->f_op->read(fw_file, buffer, len, &fw_file->f_pos);
3503
3504 GTP_ERROR("[Load_firmware]Load from file success: %ld %s", len, filepath);
3505
3506
3507 load_firmware_failed:
3508 filp_close(fw_file, NULL);
3509 set_fs(old_fs);
3510
3511 load_firmware_exit:
3512 return buffer;
3513 }
3514
3515 s32 gup_check_firmware(char *fw, u32 length)
3516 {
3517 u32 i = 0;
3518 u32 fw_checksum = 0;
3519 u16 temp;
3520
3521 for(i=0; i<length; i+=2)
3522 {
3523 temp = (fw[i]<<8) + fw[i+1];
3524 fw_checksum += temp;
3525 }
3526
3527 GTP_DEBUG("firmware checksum: %4X", fw_checksum&0xFFFF);
3528 if(fw_checksum&0xFFFF)
3529 {
3530 return FAIL;
3531 }
3532 return SUCCESS;
3533 }
3534
3535 s32 gup_enter_update_mode_noreset(void)
3536 {
3537 s32 ret = FAIL;
3538
3539 // disable watchdog
3540 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__TMR0_EN, 0x00);
3541 if (ret <= 0)
3542 {
3543 GTP_ERROR("[enter_update_mode]disable wdt fail.");
3544 return FAIL;
3545 }
3546 //select addr & hold ss51_dsp
3547 ret = gup_hold_ss51_dsp(i2c_client_point);
3548 if (ret <= 0)
3549 {
3550 GTP_ERROR("[enter_update_mode]hold ss51 & dsp failed.");
3551 return FAIL;
3552 }
3553
3554 //clear control flag
3555 ret = gup_set_ic_msg(i2c_client_point, _rRW_MISCTL__BOOT_CTL_, 0x00);
3556
3557 if (ret <= 0)
3558 {
3559 GTP_ERROR("[enter_update_mode]clear control flag fail.");
3560 return FAIL;
3561 }
3562
3563 //set scramble
3564 ret = gup_set_ic_msg(i2c_client_point, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
3565
3566 if (ret <= 0)
3567 {
3568 GTP_ERROR("[enter_update_mode]set scramble fail.");
3569 return FAIL;
3570 }
3571
3572 //enable accessing code
3573 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__MEM_CD_EN, 0x01);
3574
3575 if (ret <= 0)
3576 {
3577 GTP_ERROR("[enter_update_mode]enable accessing code fail.");
3578 return FAIL;
3579 }
3580
3581 return SUCCESS;
3582 }
3583
3584 s32 gup_load_by_bank(u8 bank, u8 need_check, u8 *fw, u32 length)
3585 {
3586 s32 ret = FAIL;
3587 s32 retry = 0;
3588
3589 GTP_DEBUG("[load_by_bank]begin download [bank:%d,length:%d].",bank,length);
3590 while(retry++ < 5)
3591 {
3592 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, bank);
3593 if (ret <= 0)
3594 {
3595 GTP_ERROR("[load_by_bank]select bank fail.");
3596 continue;
3597 }
3598
3599 ret = i2c_write_bytes(i2c_client_point, 0xC000,fw, length);
3600 if (ret == -1)
3601 {
3602 GTP_ERROR("[load_by_bank]download bank fail.");
3603 continue;
3604 }
3605
3606 if(need_check)
3607 {
3608 ret = gup_check_and_repair(i2c_client_point, 0xC000, fw, length);
3609 if(FAIL == ret)
3610 {
3611 GTP_ERROR("[load_by_bank]checked FW bank fail.");
3612 continue;
3613 }
3614 }
3615 break;
3616 }
3617 if(retry<5)
3618 {
3619 return SUCCESS;
3620 }
3621 else
3622 {
3623 return FAIL;
3624 }
3625 }
3626
3627 s32 gup_load_system(char *firmware, s32 length, u8 need_check)
3628 {
3629 s32 ret = -1;
3630 u8 bank = 0;
3631
3632 //disable irq & ESD protect
3633 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
3634 #if GTP_ESD_PROTECT
3635 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
3636 #endif
3637 ret = gup_enter_update_mode_noreset();
3638 if (FAIL == ret)
3639 {
3640 goto gup_load_system_exit;
3641 }
3642 GTP_DEBUG("enter update mode success.");
3643 while(length > 0)
3644 {
3645 u32 len = length >BANK_LENGTH? BANK_LENGTH:length;
3646 ret = gup_load_by_bank(bank, need_check, &firmware[bank*BANK_LENGTH], len);
3647 if(FAIL == ret)
3648 {
3649 goto gup_load_system_exit;
3650 }
3651 GTP_DEBUG("load bank%d length:%d success.", bank, len);
3652 bank++;
3653 length -= len;
3654 }
3655
3656 ret = gtp_fw_startup(i2c_client_point);
3657
3658 gup_load_system_exit:
3659 #if GTP_ESD_PROTECT
3660 #if FLASHLESS_FLASH_WORKROUND
3661
3662 #else
3663 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3664 #endif
3665 #endif
3666 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3667 return ret;
3668 }
3669
3670 s32 gup_load_fx_system(void)
3671 {
3672 s32 ret = -1;
3673 char *firmware = NULL;
3674 u32 is_load_from_file = 0;
3675 u32 length = 0;
3676
3677 GTP_INFO("[load_fx_system] Load authorization system.");
3678
3679 firmware = gtp_default_FW_hotknot2;
3680
3681 #if GTP_AUTO_UPDATE
3682 firmware = gup_load_fw_from_file( FX_SYSTEM_PATH );
3683 if(firmware == NULL)
3684 {
3685 firmware = gtp_default_FW_hotknot2;
3686 GTP_INFO("[load_fx_system] Use default firmware.");
3687 }
3688 else
3689 {
3690 is_load_from_file = 1;
3691 }
3692 #endif
3693
3694 length = firmware[0]*256*256*256+
3695 firmware[1]*256*256+
3696 firmware[2]*256+
3697 firmware[3];
3698
3699 if(length > 32*1024 || length < 4*1024 )
3700 {
3701 GTP_ERROR("[load_fx_system]firmware's length is invalid.");
3702 goto load_fx_exit;
3703 }
3704
3705 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3706 if(ret == FAIL)
3707 {
3708 GTP_ERROR("[load_fx_system]firmware's checksum is error.");
3709 goto load_fx_exit;
3710 }
3711
3712 current_system_length = length;
3713
3714 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], length, 1);
3715
3716 load_fx_exit:
3717
3718 if(is_load_from_file)
3719 {
3720 kfree(firmware);
3721 }
3722
3723 return ret;
3724 }
3725
3726
3727 s32 gup_load_hotknot_system(void)
3728 {
3729 s32 ret = -1;
3730 char *firmware = NULL;
3731 u32 is_load_from_file = 0;
3732 u32 length = 0;
3733
3734 load_fw_process = 1;
3735 /*
3736 if(gtp_chip_type == CHIP_TYPE_GT9)
3737 {
3738 u8 retry = 0;
3739 u8 wr_buf[3] = {0x80, 0x46, 0x22};
3740 u8 rd_buf[4] = {0x81, 0xA8, 0x00, 0x00};
3741 while(retry++ < 10)
3742 {
3743 wr_buf[1] = 0x46;
3744 ret = gup_i2c_write(i2c_client_point, wr_buf, sizeof(wr_buf));
3745 if(ret <= 0)
3746 {
3747 continue;
3748 }
3749 wr_buf[1] = 0x40;
3750 ret = gup_i2c_write(i2c_client_point, wr_buf, sizeof(wr_buf));
3751 if(ret <= 0)
3752 {
3753 continue;
3754 }
3755 msleep(50);
3756 ret = gup_i2c_read(i2c_client_point, rd_buf, sizeof(rd_buf));
3757 if(ret <= 0)
3758 {
3759 continue;
3760 }
3761 if(rd_buf[GTP_ADDR_LENGTH] == 0xAA &&
3762 rd_buf[GTP_ADDR_LENGTH] == rd_buf[GTP_ADDR_LENGTH + 1])
3763 {
3764 GTP_INFO("[load_hotknot_system]Hotknot switch system success.");
3765 return SUCCESS;
3766 }
3767 }
3768 GTP_ERROR("[load_hotknot_system]Hotknot switch system failed.");
3769 return FAIL;
3770 }
3771 */
3772 GTP_INFO("[load_hotknot_system] Load hotknot system.");
3773
3774 firmware = gtp_default_FW_hotknot;
3775
3776 #if GTP_AUTO_UPDATE
3777 firmware = gup_load_fw_from_file( HOTKNOT_SYSTEM_PATH );
3778 if(firmware == NULL)
3779 {
3780 firmware = gtp_default_FW_hotknot;
3781 GTP_INFO("[load_hotknot_system] Use default firmware.");
3782 }
3783 else
3784 {
3785 is_load_from_file = 1;
3786 }
3787 #endif
3788
3789 length = firmware[0]*256*256*256+
3790 firmware[1]*256*256+
3791 firmware[2]*256+
3792 firmware[3];
3793 if(length > 32*1024 || length < 4*1024 )
3794 {
3795 GTP_ERROR("[load_hotknot_system]firmware's length is invalid.");
3796 goto load_hotknot_exit;
3797 }
3798
3799 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3800 if(ret == FAIL)
3801 {
3802 GTP_ERROR("[load_hotknot_system]firmware's checksum is error.");
3803 goto load_hotknot_exit;
3804 }
3805
3806 current_system_length = length;
3807
3808 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], length, 0);
3809
3810 load_hotknot_exit:
3811
3812 if(is_load_from_file)
3813 {
3814 kfree(firmware);
3815 }
3816
3817 return ret;
3818
3819 }
3820
3821
3822 s32 gup_recovery_main_system(void)
3823 {
3824 s32 ret = -1;
3825 char *firmware = NULL;
3826 u32 is_load_from_file = 0;
3827 u32 length = 0;
3828
3829 GTP_INFO("[recovery_main_system] Recovery main system.");
3830
3831 if(gtp_chip_type == CHIP_TYPE_GT9)
3832 {
3833 gtp_reset_guitar(i2c_client_point,10);
3834 load_fw_process = 0;
3835 return SUCCESS;
3836 }
3837
3838 firmware = gtp_default_FW_fl;
3839
3840 #if GTP_AUTO_UPDATE
3841 firmware = gup_load_fw_from_file(MAIN_SYSTEM_PATH);
3842 if(firmware == NULL)
3843 {
3844 firmware = gtp_default_FW_fl;
3845 GTP_INFO("[recovery_main_system]Use default firmware.");
3846 }
3847 else
3848 {
3849 is_load_from_file = 1;
3850 }
3851 #endif
3852
3853 if(firmware[0]==0x00&&firmware[1]==0x90&&firmware[2]==0x06&&firmware[3]==0x00)
3854 {
3855 length = 36*1024;
3856 }
3857 else
3858 {
3859 length = firmware[0]*256*256*256+
3860 firmware[1]*256*256+
3861 firmware[2]*256+
3862 firmware[3];
3863 }
3864 if(length > 36*1024 || length < 16*1024 )
3865 {
3866 GTP_ERROR("[recovery_main_system]firmware's length is invalid.");
3867 goto recovery_main_system_exit;
3868 }
3869
3870 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3871 if(ret == FAIL)
3872 {
3873 GTP_ERROR("[recovery_main_system]firmware's checksum is error.");
3874 goto recovery_main_system_exit;
3875 }
3876
3877 if(current_system_length == 0)
3878 {
3879 current_system_length = length;
3880 }
3881
3882 GTP_INFO("[recovery_main_system] Recovery length: %d.", current_system_length);
3883
3884 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], current_system_length, 0);
3885
3886 #if (FLASHLESS_FLASH_WORKROUND && GTP_ESD_PROTECT)
3887 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3888 #endif
3889
3890 recovery_main_system_exit:
3891
3892 if(is_load_from_file)
3893 {
3894 kfree(firmware);
3895 }
3896
3897 load_fw_process = 0;
3898 return ret;
3899
3900 }
3901
3902 s32 gup_load_main_system(char *filepath)
3903 {
3904 s32 ret = -1;
3905 char *firmware = NULL;
3906 u32 is_load_from_file = 0;
3907 u32 length = 0;
3908
3909 GTP_INFO("[load_main_system] Load main system.");
3910
3911 if(filepath != NULL)
3912 {
3913 firmware = gup_load_fw_from_file(filepath);
3914 if(firmware == NULL)
3915 {
3916 GTP_INFO("[load_main_system]can not open file: %s", filepath);
3917 goto load_main_system_exit;
3918 }
3919 else
3920 {
3921 is_load_from_file = 1;
3922 }
3923 }
3924 else
3925 {
3926 firmware = gtp_default_FW_fl;
3927 }
3928 #if GTP_AUTO_UPDATE
3929 firmware = gup_load_fw_from_file(filepath);
3930 if(firmware == NULL)
3931 {
3932 if(gtp_chip_type == CHIP_TYPE_GT9)
3933 firmware = gtp_default_FW;
3934 else
3935 firmware = gtp_default_FW_fl;
3936 GTP_INFO("[load_main_system]Use default firmware. type:%d", gtp_chip_type);
3937 }
3938 else
3939 {
3940 is_load_from_file = 1;
3941 }
3942 #endif
3943
3944 if(firmware[0]==0x00&&firmware[1]==0x90&&firmware[2]==0x06&&firmware[3]==0x00)
3945 {
3946 length = 36*1024;
3947 }
3948 else
3949 {
3950 length = firmware[0]*256*256*256+
3951 firmware[1]*256*256+
3952 firmware[2]*256+
3953 firmware[3];
3954 if(length > 36*1024)
3955 {
3956 length = 36*1024;
3957 }
3958 }
3959 ret = gup_check_firmware(&firmware[FIRMWARE_HEADER_LEN],length);
3960 if(ret == FAIL)
3961 {
3962 GTP_ERROR("[load_main_system]firmware's checksum is error.");
3963 goto load_main_system_exit;
3964 }
3965 GTP_INFO("[load_main_system] Firmware length: %d.", length);
3966
3967 //memcpy(gtp_default_FW_fl, firmware, length);
3968
3969 ret = gup_load_system(&firmware[FIRMWARE_HEADER_LEN], length, 1);
3970 show_len = 100;
3971
3972 #if (FLASHLESS_FLASH_WORKROUND && GTP_ESD_PROTECT)
3973 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3974 #endif
3975
3976 load_main_system_exit:
3977
3978 if(is_load_from_file)
3979 {
3980 kfree(firmware);
3981 }
3982
3983 return ret;
3984 }
3985 #endif
3986 //*************** For GT9XXF End ***********************//
kernel source for telekom puls (alcatel/mediatek)