arch/arm/mach-mt8127/mt_spm_mtcmos.c

   1 #include <linux/init.h>
   2 #include <linux/module.h>
   3 #include <linux/kernel.h>
   4 #include <linux/spinlock.h>
   5 #include <linux/delay.h>    //udelay
   6
   7 #include <mach/mt_typedefs.h>
   8 #include <mach/mt_spm.h>
   9 #include <mach/mt_spm_mtcmos.h>
  10 #include <mach/mt_clkmgr.h>
  11
  12 /**************************************
  13  * for CPU MTCMOS
  14  **************************************/
  15 /*
  16  * regiser bit difinition
  17  */
  18 /* SPM_FC1_PWR_CON */
  19 /* SPM_FC2_PWR_CON */
  20 /* SPM_FC3_PWR_CON */
  21 #define SRAM_ISOINT_B   (1U << 6)
  22 #define SRAM_CKISO      (1U << 5)
  23 #define PWR_CLK_DIS     (1U << 4)
  24 #define PWR_ON_S        (1U << 3)
  25 #define PWR_ON          (1U << 2)
  26 #define PWR_ISO         (1U << 1)
  27 #define PWR_RST_B       (1U << 0)
  28
  29 /* SPM_CPU_FC1_L1_PDN */
  30 /* SPM_CPU_FC2_L1_PDN */
  31 /* SPM_CPU_FC3_L1_PDN */
  32 #define L1_PDN_ACK      (1U << 8)
  33 #define L1_PDN          (1U << 0)
  34
  35 /* SPM_PWR_STATUS */
  36 /* SPM_PWR_STATUS_S */
  37 #define FC1             (1U << 11)
  38 #define FC2             (1U << 10)
  39 #define FC3             (1U <<  9)
  40
  41 /* SPM_SLEEP_TIMER_STA */
  42 #define APMCU3_SLEEP    (1U << 18)
  43 #define APMCU2_SLEEP    (1U << 17)
  44 #define APMCU1_SLEEP    (1U << 16)
  45
  46
  47 static DEFINE_SPINLOCK(spm_cpu_lock);
  48
  49
  50 void spm_mtcmos_cpu_lock(unsigned long *flags)
  51 {
  52     spin_lock_irqsave(&spm_cpu_lock, *flags);
  53 }
  54
  55 void spm_mtcmos_cpu_unlock(unsigned long *flags)
  56 {
  57     spin_unlock_irqrestore(&spm_cpu_lock, *flags);
  58 }
  59
  60 int spm_mtcmos_ctrl_cpu0(int state, int chkWfiBeforePdn)
  61 {
  62     if (state == STA_POWER_DOWN) {
  63
  64     } else {    /* STA_POWER_ON */
  65
  66     }
  67
  68     return 0;
  69 }
  70
  71 int spm_mtcmos_ctrl_cpu1(int state, int chkWfiBeforePdn)
  72 {
  73     unsigned long flags;
  74
  75     /* enable register control */
  76     spm_write(SPM_POWERON_CONFIG_SET, (SPM_PROJECT_CODE << 16) | (1U << 0));
  77
  78     spm_mtcmos_cpu_lock(&flags);
  79
  80     if (state == STA_POWER_DOWN)
  81     {
  82         if (chkWfiBeforePdn)
  83             while ((spm_read(SPM_SLEEP_TIMER_STA) & APMCU1_SLEEP) == 0);
  84
  85         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) | SRAM_CKISO);
  86         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) & ~SRAM_ISOINT_B);
  87         spm_write(SPM_CPU_FC1_L1_PDN, spm_read(SPM_CPU_FC1_L1_PDN) | L1_PDN);
  88         while ((spm_read(SPM_CPU_FC1_L1_PDN) & L1_PDN_ACK) != L1_PDN_ACK);
  89
  90         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) | PWR_ISO);
  91         spm_write(SPM_FC1_PWR_CON, (spm_read(SPM_FC1_PWR_CON) | PWR_CLK_DIS) & ~PWR_RST_B);
  92
  93         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) & ~PWR_ON);
  94         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) & ~PWR_ON_S);
  95         while (((spm_read(SPM_PWR_STATUS) & FC1) != 0) | ((spm_read(SPM_PWR_STATUS_S) & FC1) != 0));
  96     }
  97     else /* STA_POWER_ON */
  98     {
  99         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) | PWR_ON);
 100         udelay(1);
 101         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) | PWR_ON_S);
 102         while (((spm_read(SPM_PWR_STATUS) & FC1) != FC1) | ((spm_read(SPM_PWR_STATUS_S) & FC1) != FC1));
 103
 104         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) & ~PWR_CLK_DIS);
 105
 106         spm_write(SPM_CPU_FC1_L1_PDN, spm_read(SPM_CPU_FC1_L1_PDN) & ~L1_PDN);
 107         while ((spm_read(SPM_CPU_FC1_L1_PDN) & L1_PDN_ACK) != 0);
 108         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) | SRAM_ISOINT_B);
 109         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) & ~SRAM_CKISO);
 110
 111         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) & ~PWR_ISO);
 112         spm_write(SPM_FC1_PWR_CON, spm_read(SPM_FC1_PWR_CON) | PWR_RST_B);
 113     }
 114
 115     spm_mtcmos_cpu_unlock(&flags);
 116
 117     return 0;
 118 }
 119
 120 int spm_mtcmos_ctrl_cpu2(int state, int chkWfiBeforePdn)
 121 {
 122     unsigned long flags;
 123
 124     /* enable register control */
 125     spm_write(SPM_POWERON_CONFIG_SET, (SPM_PROJECT_CODE << 16) | (1U << 0));
 126
 127     spm_mtcmos_cpu_lock(&flags);
 128
 129     if (state == STA_POWER_DOWN)
 130     {
 131         if (chkWfiBeforePdn)
 132             while ((spm_read(SPM_SLEEP_TIMER_STA) & APMCU2_SLEEP) == 0);
 133
 134         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) | SRAM_CKISO);
 135         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) & ~SRAM_ISOINT_B);
 136         spm_write(SPM_CPU_FC2_L1_PDN, spm_read(SPM_CPU_FC2_L1_PDN) | L1_PDN);
 137         while ((spm_read(SPM_CPU_FC2_L1_PDN) & L1_PDN_ACK) != L1_PDN_ACK);
 138
 139         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) | PWR_ISO);
 140         spm_write(SPM_FC2_PWR_CON, (spm_read(SPM_FC2_PWR_CON) | PWR_CLK_DIS) & ~PWR_RST_B);
 141
 142         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) & ~PWR_ON);
 143         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) & ~PWR_ON_S);
 144         while (((spm_read(SPM_PWR_STATUS) & FC2) != 0) | ((spm_read(SPM_PWR_STATUS_S) & FC2) != 0));
 145     }
 146     else /* STA_POWER_ON */
 147     {
 148         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) | PWR_ON);
 149         udelay(1);
 150         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) | PWR_ON_S);
 151         while (((spm_read(SPM_PWR_STATUS) & FC2) != FC2) | ((spm_read(SPM_PWR_STATUS_S) & FC2) != FC2));
 152
 153         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) & ~PWR_CLK_DIS);
 154
 155         spm_write(SPM_CPU_FC2_L1_PDN, spm_read(SPM_CPU_FC2_L1_PDN) & ~L1_PDN);
 156         while ((spm_read(SPM_CPU_FC2_L1_PDN) & L1_PDN_ACK) != 0);
 157         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) | SRAM_ISOINT_B);
 158         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) & ~SRAM_CKISO);
 159
 160         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) & ~PWR_ISO);
 161         spm_write(SPM_FC2_PWR_CON, spm_read(SPM_FC2_PWR_CON) | PWR_RST_B);
 162     }
 163
 164     spm_mtcmos_cpu_unlock(&flags);
 165
 166     return 0;
 167 }
 168
 169 int spm_mtcmos_ctrl_cpu3(int state, int chkWfiBeforePdn)
 170 {
 171     unsigned long flags;
 172
 173     /* enable register control */
 174     spm_write(SPM_POWERON_CONFIG_SET, (SPM_PROJECT_CODE << 16) | (1U << 0));
 175
 176     spm_mtcmos_cpu_lock(&flags);
 177
 178     if (state == STA_POWER_DOWN)
 179     {
 180         if (chkWfiBeforePdn)
 181             while ((spm_read(SPM_SLEEP_TIMER_STA) & APMCU3_SLEEP) == 0);
 182
 183         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) | SRAM_CKISO);
 184         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) & ~SRAM_ISOINT_B);
 185         spm_write(SPM_CPU_FC3_L1_PDN, spm_read(SPM_CPU_FC3_L1_PDN) | L1_PDN);
 186         while ((spm_read(SPM_CPU_FC3_L1_PDN) & L1_PDN_ACK) != L1_PDN_ACK);
 187
 188         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) | PWR_ISO);
 189         spm_write(SPM_FC3_PWR_CON, (spm_read(SPM_FC3_PWR_CON) | PWR_CLK_DIS) & ~PWR_RST_B);
 190
 191         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) & ~PWR_ON);
 192         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) & ~PWR_ON_S);
 193         while (((spm_read(SPM_PWR_STATUS) & FC3) != 0) | ((spm_read(SPM_PWR_STATUS_S) & FC3) != 0));
 194     }
 195     else /* STA_POWER_ON */
 196     {
 197         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) | PWR_ON);
 198         udelay(1);
 199         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) | PWR_ON_S);
 200         while (((spm_read(SPM_PWR_STATUS) & FC3) != FC3) | ((spm_read(SPM_PWR_STATUS_S) & FC3) != FC3));
 201
 202         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) & ~PWR_CLK_DIS);
 203
 204         spm_write(SPM_CPU_FC3_L1_PDN, spm_read(SPM_CPU_FC3_L1_PDN) & ~L1_PDN);
 205         while ((spm_read(SPM_CPU_FC3_L1_PDN) & L1_PDN_ACK) != 0);
 206         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) | SRAM_ISOINT_B);
 207         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) & ~SRAM_CKISO);
 208
 209         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) & ~PWR_ISO);
 210         spm_write(SPM_FC3_PWR_CON, spm_read(SPM_FC3_PWR_CON) | PWR_RST_B);
 211     }
 212
 213     spm_mtcmos_cpu_unlock(&flags);
 214
 215     return 0;
 216 }
 217
 218 int spm_mtcmos_ctrl_dbg(int state)
 219 {
 220     if (state == STA_POWER_DOWN) {
 221
 222     } else {    /* STA_POWER_ON */
 223
 224     }
 225
 226     return 0;
 227 }
 228
 229 int spm_mtcmos_ctrl_cpusys(int state)
 230 {
 231     if (state == STA_POWER_DOWN) {
 232
 233     } else {    /* STA_POWER_ON */
 234
 235     }
 236
 237     return 0;
 238 }
 239
 240 bool spm_cpusys_can_power_down(void)
 241 {
 242     return !(spm_read(SPM_PWR_STATUS) & 0x00000E00) &&
 243            !(spm_read(SPM_PWR_STATUS_S) & 0x00000E00);
 244 }
 245
 246
 247 /**************************************
 248  * for non-CPU MTCMOS
 249  **************************************/
 250 static DEFINE_SPINLOCK(spm_noncpu_lock);
 251
 252 #if 0
 253 void spm_mtcmos_noncpu_lock(unsigned long *flags)
 254 {
 255     spin_lock_irqsave(&spm_noncpu_lock, *flags);
 256 }
 257
 258 void spm_mtcmos_noncpu_unlock(unsigned long *flags)
 259 {
 260     spin_unlock_irqrestore(&spm_noncpu_lock, *flags);
 261 }
 262 #else
 263 #define spm_mtcmos_noncpu_lock(flags)   \
 264 do {    \
 265     spin_lock_irqsave(&spm_noncpu_lock, flags);  \
 266 } while (0)
 267
 268 #define spm_mtcmos_noncpu_unlock(flags) \
 269 do {    \
 270     spin_unlock_irqrestore(&spm_noncpu_lock, flags);    \
 271 } while (0)
 272
 273 #endif
 274
 275
 276 #define VDE_PWR_STA_MASK    (0x1 << 7)
 277 //#define VEN_PWR_STA_MASK    (0x1 << 7)
 278 #define IFR_PWR_STA_MASK    (0x1 << 6)
 279 #define ISP_PWR_STA_MASK    (0x1 << 5)
 280 #define DIS_PWR_STA_MASK    (0x1 << 3)
 281 #define MFG_PWR_STA_MASK    (0x1 << 4)
 282 #define DPY_PWR_STA_MASK    (0x1 << 2)
 283 #define CONN_PWR_STA_MASK    (0x1 << 1)
 284 //#define MD2_PWR_STA_MASK    (0x1 << 1)
 285 #define MD1_PWR_STA_MASK    (0x1 << 0)
 286
 287 #if 0
 288 #define PWR_RST_B           (0x1 << 0)
 289 #define PWR_ISO             (0x1 << 1)
 290 #define PWR_ON              (0x1 << 2)
 291 #define PWR_ON_S            (0x1 << 3)
 292 #define PWR_CLK_DIS         (0x1 << 4)
 293 #endif
 294
 295 #define SRAM_PDN            (0xf << 8)
 296 //#define SRAM_ACK            (0xf << 12)
 297
 298 //#define SROM_PDN            (0xf << 16)
 299 //#define SROM_ACK            (0xf << 20)
 300
 301 #define MD_SRAM_PDN         (0x1 << 8)
 302
 303 #define VDE_SRAM_ACK        (0x1 << 12)
 304 //#define VEN_SRAM_ACK        (0xf << 12)
 305 #define IFR_SRAM_ACK        (0xf << 12)
 306 #define ISP_SRAM_ACK        (0x3 << 12)
 307 #define DIS_SRAM_ACK        (0xf << 12)
 308 #define MFG_SRAM_ACK        (0x1 << 12)
 309
 310 //#define TOPAXI_SI0_CTL      (INFRACFG_BASE + 0x0200)
 311 //#define TOPAXI_PROT_EN      (INFRACFG_AO_BASE + 0x0220)
 312 //#define TOPAXI_PROT_STA1    (INFRACFG_AO_BASE + 0x0228)
 313
 314 //#define MFG_PROT_MASK   0x0020
 315 //#define MD1_PROT_MASK   0x5300
 316 //#define MD2_PROT_MASK   0xAC00
 317 #define MD1_PROT_MASK     0x00B8
 318 #define CONN_PROT_MASK    0x0104
 319 #define DISP_PROT_MASK    0x0002//0x0042
 320
 321 //#define MFG_SI0_MASK    0x0400
 322
 323
 324 int spm_mtcmos_ctrl_vdec(int state)
 325 {
 326     int err = 0;
 327     volatile unsigned int val;
 328     unsigned long flags;
 329
 330     spm_mtcmos_noncpu_lock(flags);
 331
 332     if (state == STA_POWER_DOWN) {
 333         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | SRAM_PDN);
 334
 335         while ((spm_read(SPM_VDE_PWR_CON) & VDE_SRAM_ACK) != VDE_SRAM_ACK) {
 336         }
 337
 338         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_ISO);
 339
 340         val = spm_read(SPM_VDE_PWR_CON);
 341         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 342         spm_write(SPM_VDE_PWR_CON, val);
 343
 344         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 345
 346 #if 0
 347         udelay(1);
 348         if (spm_read(SPM_PWR_STATUS) & VDE_PWR_STA_MASK) {
 349             err = 1;
 350         }
 351 #else
 352         while ((spm_read(SPM_PWR_STATUS) & VDE_PWR_STA_MASK)
 353                 || (spm_read(SPM_PWR_STATUS_S) & VDE_PWR_STA_MASK)) {
 354         }
 355 #endif
 356     } else {    /* STA_POWER_ON */
 357         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_ON);
 358         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_ON_S);
 359 #if 0
 360         udelay(1);
 361 #else
 362         while (!(spm_read(SPM_PWR_STATUS) & VDE_PWR_STA_MASK)
 363                 || !(spm_read(SPM_PWR_STATUS_S) & VDE_PWR_STA_MASK)) {
 364         }
 365 #endif
 366
 367         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~PWR_CLK_DIS);
 368         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~PWR_ISO);
 369         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) | PWR_RST_B);
 370
 371         spm_write(SPM_VDE_PWR_CON, spm_read(SPM_VDE_PWR_CON) & ~SRAM_PDN);
 372
 373         while ((spm_read(SPM_VDE_PWR_CON) & VDE_SRAM_ACK)) {
 374         }
 375
 376 #if 0
 377         udelay(1);
 378         if (!(spm_read(SPM_PWR_STATUS) & VDE_PWR_STA_MASK)) {
 379             err = 1;
 380         }
 381 #endif
 382     }
 383
 384     spm_mtcmos_noncpu_unlock(flags);
 385
 386     return err;
 387 }
 388
 389 int spm_mtcmos_ctrl_isp(int state)
 390 {
 391     int err = 0;
 392     volatile unsigned int val;
 393     unsigned long flags;
 394
 395     spm_mtcmos_noncpu_lock(flags);
 396
 397     if (state == STA_POWER_DOWN) {
 398         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) | SRAM_PDN);
 399
 400         while ((spm_read(SPM_ISP_PWR_CON) & ISP_SRAM_ACK) != ISP_SRAM_ACK) {
 401         }
 402
 403         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) | PWR_ISO);
 404
 405         val = spm_read(SPM_ISP_PWR_CON);
 406         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 407         spm_write(SPM_ISP_PWR_CON, val);
 408
 409         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 410
 411 #if 0
 412         udelay(1);
 413         if (spm_read(SPM_PWR_STATUS) & ISP_PWR_STA_MASK) {
 414             err = 1;
 415         }
 416 #else
 417         while ((spm_read(SPM_PWR_STATUS) & ISP_PWR_STA_MASK)
 418                 || (spm_read(SPM_PWR_STATUS_S) & ISP_PWR_STA_MASK)) {
 419         }
 420 #endif
 421     } else {    /* STA_POWER_ON */
 422         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) | PWR_ON);
 423         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) | PWR_ON_S);
 424 #if 0
 425         udelay(1);
 426 #else
 427         while (!(spm_read(SPM_PWR_STATUS) & ISP_PWR_STA_MASK)
 428                 || !(spm_read(SPM_PWR_STATUS_S) & ISP_PWR_STA_MASK)) {
 429         }
 430 #endif
 431         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) & ~PWR_CLK_DIS);
 432         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) & ~PWR_ISO);
 433         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) | PWR_RST_B);
 434
 435         spm_write(SPM_ISP_PWR_CON, spm_read(SPM_ISP_PWR_CON) & ~SRAM_PDN);
 436
 437         while ((spm_read(SPM_ISP_PWR_CON) & ISP_SRAM_ACK)) {
 438         }
 439
 440 #if 0
 441         udelay(1);
 442         if (!(spm_read(SPM_PWR_STATUS) & ISP_PWR_STA_MASK)) {
 443             err = 1;
 444         }
 445 #endif
 446     }
 447
 448     spm_mtcmos_noncpu_unlock(flags);
 449
 450     return err;
 451 }
 452 #if 0
 453 int spm_mtcmos_ctrl_disp(int state)
 454 {
 455     int err = 0;
 456     volatile unsigned int val;
 457     unsigned long flags;
 458
 459     spm_mtcmos_noncpu_lock(flags);
 460
 461     if (state == STA_POWER_DOWN) {
 462         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | DISP_PROT_MASK);
 463         while ((spm_read(TOPAXI_PROT_STA1) & DISP_PROT_MASK) != DISP_PROT_MASK) {
 464         }
 465
 466         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | SRAM_PDN);
 467 #if 0
 468         while ((spm_read(SPM_DIS_PWR_CON) & DIS_SRAM_ACK) != DIS_SRAM_ACK) {
 469         }
 470 #endif
 471         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ISO);
 472
 473         val = spm_read(SPM_DIS_PWR_CON);
 474         //val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 475         val = val | PWR_CLK_DIS;
 476         spm_write(SPM_DIS_PWR_CON, val);
 477
 478         //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 479
 480 #if 0
 481         udelay(1);
 482         if (spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK) {
 483             err = 1;
 484         }
 485 #else
 486         //while ((spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
 487         //        || (spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
 488         //}
 489 #endif
 490     } else {    /* STA_POWER_ON */
 491         //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON);
 492         //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON_S);
 493 #if 0
 494         udelay(1);
 495 #else
 496         //while (!(spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
 497         //        || !(spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
 498         //}
 499 #endif
 500         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~PWR_CLK_DIS);
 501         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~PWR_ISO);
 502         //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_RST_B);
 503
 504         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~SRAM_PDN);
 505
 506 #if 0
 507         while ((spm_read(SPM_DIS_PWR_CON) & DIS_SRAM_ACK)) {
 508         }
 509 #endif
 510
 511 #if 0
 512         udelay(1);
 513         if (!(spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)) {
 514             err = 1;
 515         }
 516 #endif
 517         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~DISP_PROT_MASK);
 518         while (spm_read(TOPAXI_PROT_STA1) & DISP_PROT_MASK) {
 519         }
 520     }
 521
 522     spm_mtcmos_noncpu_unlock(flags);
 523
 524     return err;
 525 }
 526
 527 #else
 528
 529 int spm_mtcmos_ctrl_disp(int state)
 530 {
 531     int err = 0;
 532     volatile unsigned int val;
 533     unsigned long flags;
 534
 535     spm_mtcmos_noncpu_lock(flags);
 536
 537     if (state == STA_POWER_DOWN) {
 538         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | DISP_PROT_MASK);
 539         while ((spm_read(TOPAXI_PROT_STA1) & DISP_PROT_MASK) != DISP_PROT_MASK) {
 540         }
 541
 542         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | SRAM_PDN);
 543 #if 0
 544         while ((spm_read(SPM_DIS_PWR_CON) & DIS_SRAM_ACK) != DIS_SRAM_ACK) {
 545         }
 546 #endif
 547         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ISO);
 548
 549         val = spm_read(SPM_DIS_PWR_CON);
 550         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 551 //        val = val | PWR_CLK_DIS;
 552         spm_write(SPM_DIS_PWR_CON, val);
 553
 554         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 555
 556 #if 0
 557         udelay(1);
 558         if (spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK) {
 559             err = 1;
 560         }
 561 #else
 562         while ((spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
 563                 || (spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
 564         }
 565 #endif
 566     } else {    /* STA_POWER_ON */
 567         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON);
 568         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON_S);
 569 #if 0
 570         udelay(1);
 571 #else
 572         while (!(spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
 573                 || !(spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
 574         }
 575 #endif
 576         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~PWR_CLK_DIS);
 577         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~PWR_ISO);
 578         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_RST_B);
 579
 580         spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~SRAM_PDN);
 581
 582 #if 0
 583         while ((spm_read(SPM_DIS_PWR_CON) & DIS_SRAM_ACK)) {
 584         }
 585 #endif
 586
 587 #if 0
 588         udelay(1);
 589         if (!(spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)) {
 590             err = 1;
 591         }
 592 #endif
 593         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~DISP_PROT_MASK);
 594         while (spm_read(TOPAXI_PROT_STA1) & DISP_PROT_MASK) {
 595         }
 596     }
 597
 598     spm_mtcmos_noncpu_unlock(flags);
 599
 600     return err;
 601 }
 602 #endif
 603
 604 int spm_mtcmos_ctrl_mfg(int state)
 605 {
 606     int err = 0;
 607     volatile unsigned int val;
 608     unsigned long flags;
 609
 610     spm_mtcmos_noncpu_lock(flags);
 611
 612     if (state == STA_POWER_DOWN) {
 613 //        spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | MFG_PROT_MASK);
 614 //        while ((spm_read(TOPAXI_PROT_STA1) & MFG_PROT_MASK) != MFG_PROT_MASK) {
 615 //        }
 616
 617 //        spm_write(TOPAXI_SI0_CTL, spm_read(TOPAXI_SI0_CTL) & ~MFG_SI0_MASK);
 618
 619         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | SRAM_PDN);
 620
 621         while ((spm_read(SPM_MFG_PWR_CON) & MFG_SRAM_ACK) != MFG_SRAM_ACK) {
 622         }
 623
 624         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ISO);
 625
 626         val = spm_read(SPM_MFG_PWR_CON);
 627         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 628         spm_write(SPM_MFG_PWR_CON, val);
 629
 630         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 631
 632 #if 0
 633         udelay(1);
 634         if (spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK) {
 635             err = 1;
 636         }
 637 #else
 638         while ((spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK)
 639                 || (spm_read(SPM_PWR_STATUS_S) & MFG_PWR_STA_MASK)) {
 640         }
 641 #endif
 642     } else {    /* STA_POWER_ON */
 643         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON);
 644         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON_S);
 645 #if 0
 646         udelay(1);
 647 #else
 648         while (!(spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK) ||
 649                 !(spm_read(SPM_PWR_STATUS_S) & MFG_PWR_STA_MASK)) {
 650         }
 651 #endif
 652
 653         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~PWR_CLK_DIS);
 654         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~PWR_ISO);
 655         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_RST_B);
 656
 657         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~SRAM_PDN);
 658
 659         while ((spm_read(SPM_MFG_PWR_CON) & MFG_SRAM_ACK)) {
 660         }
 661
 662 #if 0
 663         udelay(1);
 664         if (!(spm_read(SPM_PWR_STATUS) & MFG_PWR_STA_MASK)) {
 665             err = 1;
 666         }
 667 #endif
 668 //        spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~MFG_PROT_MASK);
 669 //        while (spm_read(TOPAXI_PROT_STA1) & MFG_PROT_MASK) {
 670 //        }
 671 //        spm_write(TOPAXI_SI0_CTL, spm_read(TOPAXI_SI0_CTL) | MFG_SI0_MASK);
 672     }
 673
 674     spm_mtcmos_noncpu_unlock(flags);
 675
 676     return err;
 677 }
 678
 679 int spm_mtcmos_ctrl_infra(int state)
 680 {
 681     int err = 0;
 682     volatile unsigned int val;
 683     unsigned long flags;
 684
 685     spm_mtcmos_noncpu_lock(flags);
 686
 687     if (state == STA_POWER_DOWN) {
 688         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) | SRAM_PDN);
 689
 690         while ((spm_read(SPM_IFR_PWR_CON) & IFR_SRAM_ACK) != IFR_SRAM_ACK) {
 691         }
 692
 693         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) | PWR_ISO);
 694
 695         val = spm_read(SPM_IFR_PWR_CON);
 696         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 697         spm_write(SPM_IFR_PWR_CON, val);
 698
 699         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 700
 701 #if 0
 702         udelay(1);
 703         if (spm_read(SPM_PWR_STATUS) & IFR_PWR_STA_MASK) {
 704             err = 1;
 705         }
 706 #else
 707         while ((spm_read(SPM_PWR_STATUS) & IFR_PWR_STA_MASK)
 708                 || (spm_read(SPM_PWR_STATUS_S) & IFR_PWR_STA_MASK)) {
 709         }
 710 #endif
 711     } else {    /* STA_POWER_ON */
 712         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) | PWR_ON);
 713         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) | PWR_ON_S);
 714 #if 0
 715         udelay(1);
 716 #else
 717         while (!(spm_read(SPM_PWR_STATUS) & IFR_PWR_STA_MASK)
 718                 || !(spm_read(SPM_PWR_STATUS_S) & IFR_PWR_STA_MASK)) {
 719         }
 720 #endif
 721
 722         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) & ~PWR_CLK_DIS);
 723         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) & ~PWR_ISO);
 724         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) | PWR_RST_B);
 725
 726         spm_write(SPM_IFR_PWR_CON, spm_read(SPM_IFR_PWR_CON) & ~SRAM_PDN);
 727
 728         while ((spm_read(SPM_IFR_PWR_CON) & IFR_SRAM_ACK)) {
 729         }
 730
 731 #if 0
 732         udelay(1);
 733         if (!(spm_read(SPM_PWR_STATUS) & IFR_PWR_STA_MASK)) {
 734             err = 1;
 735         }
 736 #endif
 737     }
 738
 739     spm_mtcmos_noncpu_unlock(flags);
 740
 741     return err;
 742 }
 743
 744 int spm_mtcmos_ctrl_ddrphy(int state)
 745 {
 746     int err = 0;
 747     volatile unsigned int val;
 748     unsigned long flags;
 749
 750     spm_mtcmos_noncpu_lock(flags);
 751
 752     if (state == STA_POWER_DOWN) {
 753         spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_ISO);
 754
 755         val = spm_read(SPM_DPY_PWR_CON);
 756         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 757         spm_write(SPM_DPY_PWR_CON, val);
 758
 759         spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 760
 761 #if 0
 762         udelay(1);
 763         if (spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK) {
 764             err = 1;
 765         }
 766 #else
 767         while ((spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK)
 768                 || (spm_read(SPM_PWR_STATUS_S) & DPY_PWR_STA_MASK)) {
 769         }
 770 #endif
 771     } else {    /* STA_POWER_ON */
 772         spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_ON);
 773         spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_ON_S);
 774 #if 0
 775         udelay(1);
 776 #else
 777         while (!(spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK)
 778                 || !(spm_read(SPM_PWR_STATUS_S) & DPY_PWR_STA_MASK)) {
 779         }
 780 #endif
 781
 782         spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) & ~PWR_CLK_DIS);
 783         spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) & ~PWR_ISO);
 784         spm_write(SPM_DPY_PWR_CON, spm_read(SPM_DPY_PWR_CON) | PWR_RST_B);
 785
 786 #if 0
 787         udelay(1);
 788         if (!(spm_read(SPM_PWR_STATUS) & DPY_PWR_STA_MASK)) {
 789             err = 1;
 790         }
 791 #endif
 792     }
 793
 794     spm_mtcmos_noncpu_unlock(flags);
 795
 796     return err;
 797 }
 798
 799 int spm_mtcmos_ctrl_mdsys1(int state)
 800 {
 801     int err = 0;
 802     volatile unsigned int val;
 803     unsigned long flags;
 804     int count = 0;
 805
 806     spm_mtcmos_noncpu_lock(flags);
 807
 808     if (state == STA_POWER_DOWN) {
 809         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | MD1_PROT_MASK);
 810         while ((spm_read(TOPAXI_PROT_STA1) & MD1_PROT_MASK) != MD1_PROT_MASK) {
 811             count++;
 812             if(count>1000)
 813                 break;
 814         }
 815         printk("MD MTCMOS DOWN: TOPAXI_PROT_STA1=0x%x, count=%d.\n", spm_read(TOPAXI_PROT_STA1), count);
 816
 817         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | MD_SRAM_PDN);
 818
 819         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_ISO);
 820
 821         val = spm_read(SPM_MD_PWR_CON);
 822         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 823         spm_write(SPM_MD_PWR_CON, val);
 824
 825         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 826
 827 #if 0
 828         udelay(1);
 829         if (spm_read(SPM_PWR_STATUS) & MD1_PWR_STA_MASK) {
 830             err = 1;
 831         }
 832 #else
 833         while ((spm_read(SPM_PWR_STATUS) & MD1_PWR_STA_MASK)
 834                 || (spm_read(SPM_PWR_STATUS_S) & MD1_PWR_STA_MASK)) {
 835         }
 836 #endif
 837     } else {    /* STA_POWER_ON */
 838         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_ON);
 839         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_ON_S);
 840 #if 0
 841         udelay(1);
 842 #else
 843         while (!(spm_read(SPM_PWR_STATUS) & MD1_PWR_STA_MASK)
 844                 || !(spm_read(SPM_PWR_STATUS_S) & MD1_PWR_STA_MASK)) {
 845         }
 846 #endif
 847
 848         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~PWR_CLK_DIS);
 849         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~PWR_ISO);
 850         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) | PWR_RST_B);
 851
 852         spm_write(SPM_MD_PWR_CON, spm_read(SPM_MD_PWR_CON) & ~MD_SRAM_PDN);
 853
 854 #if 0
 855         udelay(1);
 856         if (!(spm_read(SPM_PWR_STATUS) & MD1_PWR_STA_MASK)) {
 857             err = 1;
 858         }
 859 #endif
 860         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~MD1_PROT_MASK);
 861         while (spm_read(TOPAXI_PROT_STA1) & MD1_PROT_MASK) {
 862         }
 863     }
 864
 865     spm_mtcmos_noncpu_unlock(flags);
 866
 867     return err;
 868 }
 869
 870 int spm_mtcmos_ctrl_connsys(int state)
 871 {
 872     int err = 0;
 873     volatile unsigned int val;
 874     unsigned long flags;
 875     int count = 0;
 876
 877     spm_mtcmos_noncpu_lock(flags);
 878
 879     if (state == STA_POWER_DOWN) {
 880         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | CONN_PROT_MASK);
 881         while ((spm_read(TOPAXI_PROT_STA1) & CONN_PROT_MASK) != CONN_PROT_MASK) {
 882             count++;
 883             if(count>1000)
 884                 break;
 885         }
 886
 887         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | MD_SRAM_PDN);
 888
 889         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_ISO);
 890
 891         val = spm_read(SPM_CONN_PWR_CON);
 892         val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
 893         spm_write(SPM_CONN_PWR_CON, val);
 894
 895         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 896
 897 #if 0
 898         udelay(1);
 899         if (spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK) {
 900             err = 1;
 901         }
 902 #else
 903         while ((spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK)
 904                 || (spm_read(SPM_PWR_STATUS_S) & CONN_PWR_STA_MASK)) {
 905         }
 906 #endif
 907     } else {
 908         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_ON);
 909         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_ON_S);
 910 #if 0
 911         udelay(1);
 912 #else
 913         while (!(spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK)
 914                 || !(spm_read(SPM_PWR_STATUS_S) & CONN_PWR_STA_MASK)) {
 915         }
 916 #endif
 917
 918         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~PWR_CLK_DIS);
 919         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~PWR_ISO);
 920         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) | PWR_RST_B);
 921
 922         spm_write(SPM_CONN_PWR_CON, spm_read(SPM_CONN_PWR_CON) & ~MD_SRAM_PDN);
 923
 924 #if 0
 925         udelay(1);
 926         if (!(spm_read(SPM_PWR_STATUS) & CONN_PWR_STA_MASK)) {
 927             err = 1;
 928         }
 929 #endif
 930         spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~CONN_PROT_MASK);
 931         while (spm_read(TOPAXI_PROT_STA1) & CONN_PROT_MASK) {
 932         }
 933     }
 934
 935     spm_mtcmos_noncpu_unlock(flags);
 936
 937     return err;
 938 }
 939
 940
 941
 942 /**
 943  *test_spm_gpu_power_on - test whether gpu could be powered on
 944  *
 945  *Returns 1 if power on operation succeed, 0 otherwise.
 946  */
 947 int test_spm_gpu_power_on(void)
 948 {
 949     int i;
 950     volatile unsigned int sta1, sta2;
 951     volatile unsigned int val;
 952     unsigned long flags;
 953
 954     sta1 = spm_read(SPM_PWR_STATUS);
 955     sta2 = spm_read(SPM_PWR_STATUS_S);
 956     if (((sta1 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK) &&
 957             ((sta2 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK)) {
 958         printk("[%s]: test_spm_gpu_power_on already on, return: 1.\n", __func__);
 959         return 1;
 960     }
 961
 962     spm_mtcmos_noncpu_lock(flags);
 963
 964     val = spm_read(SPM_MFG_PWR_CON);
 965     BUG_ON(!(val & PWR_ISO));
 966
 967     for(i = 0; i < 5; i++) {
 968
 969         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON);
 970         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) | PWR_ON_S);
 971
 972         udelay(5);
 973
 974         sta1 = spm_read(SPM_PWR_STATUS);
 975         sta2 = spm_read(SPM_PWR_STATUS_S);
 976         if (((sta1 & MFG_PWR_STA_MASK) != MFG_PWR_STA_MASK) ||
 977                 ((sta2 & MFG_PWR_STA_MASK) != MFG_PWR_STA_MASK)) {
 978             spm_mtcmos_noncpu_unlock(flags);
 979             printk("[%s]: test_spm_gpu_power_on return: 0.\n", __func__);
 980             return 0;
 981         }
 982
 983         spm_write(SPM_MFG_PWR_CON, spm_read(SPM_MFG_PWR_CON) & ~(PWR_ON | PWR_ON_S));
 984
 985         sta1 = spm_read(SPM_PWR_STATUS);
 986         sta2 = spm_read(SPM_PWR_STATUS_S);
 987         if (((sta1 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK) ||
 988                 ((sta2 & MFG_PWR_STA_MASK) == MFG_PWR_STA_MASK)) {
 989             spm_mtcmos_noncpu_unlock(flags);
 990             printk("[%s]: test_spm_gpu_power_on return: 0.\n", __func__);
 991             return 0;
 992         }
 993         mdelay(1);
 994     }
 995
 996     spm_mtcmos_noncpu_unlock(flags);
 997
 998     printk("[%s]: test_spm_gpu_power_on return: 1.\n", __func__);
 999     return 1;
1000 }
1001
1002 MODULE_DESCRIPTION("MT6582 SPM-MTCMOS Driver v0.1");