1 #include <linux/init.h>
2 #include <linux/module.h>
3 #include <linux/kernel.h>
4 #include <linux/spinlock.h>
5 #include <linux/delay.h> //udelay
7 #include <mach/mt_typedefs.h>
8 #include <mach/mt_spm.h>
9 #include <mach/mt_spm_mtcmos.h>
10 #include <mach/mt_clkmgr.h>
12 /**************************************
14 **************************************/
16 * regiser bit difinition
21 #define SRAM_ISOINT_B (1U << 6)
22 #define SRAM_CKISO (1U << 5)
23 #define PWR_CLK_DIS (1U << 4)
24 #define PWR_ON_S (1U << 3)
25 #define PWR_ON (1U << 2)
26 #define PWR_ISO (1U << 1)
27 #define PWR_RST_B (1U << 0)
29 /* SPM_CPU_FC1_L1_PDN */
30 /* SPM_CPU_FC2_L1_PDN */
31 /* SPM_CPU_FC3_L1_PDN */
32 #define L1_PDN_ACK (1U << 8)
33 #define L1_PDN (1U << 0)
36 /* SPM_PWR_STATUS_S */
37 #define FC1 (1U << 11)
38 #define FC2 (1U << 10)
41 /* SPM_SLEEP_TIMER_STA */
42 #define APMCU3_SLEEP (1U << 18)
43 #define APMCU2_SLEEP (1U << 17)
44 #define APMCU1_SLEEP (1U << 16)
47 static DEFINE_SPINLOCK(spm_cpu_lock
);
50 void spm_mtcmos_cpu_lock(unsigned long *flags
)
52 spin_lock_irqsave(&spm_cpu_lock
, *flags
);
55 void spm_mtcmos_cpu_unlock(unsigned long *flags
)
57 spin_unlock_irqrestore(&spm_cpu_lock
, *flags
);
60 int spm_mtcmos_ctrl_cpu0(int state
, int chkWfiBeforePdn
)
62 if (state
== STA_POWER_DOWN
) {
64 } else { /* STA_POWER_ON */
71 int spm_mtcmos_ctrl_cpu1(int state
, int chkWfiBeforePdn
)
75 /* enable register control */
76 spm_write(SPM_POWERON_CONFIG_SET
, (SPM_PROJECT_CODE
<< 16) | (1U << 0));
78 spm_mtcmos_cpu_lock(&flags
);
80 if (state
== STA_POWER_DOWN
)
83 while ((spm_read(SPM_SLEEP_TIMER_STA
) & APMCU1_SLEEP
) == 0);
85 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) | SRAM_CKISO
);
86 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) & ~SRAM_ISOINT_B
);
87 spm_write(SPM_CPU_FC1_L1_PDN
, spm_read(SPM_CPU_FC1_L1_PDN
) | L1_PDN
);
88 while ((spm_read(SPM_CPU_FC1_L1_PDN
) & L1_PDN_ACK
) != L1_PDN_ACK
);
90 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) | PWR_ISO
);
91 spm_write(SPM_FC1_PWR_CON
, (spm_read(SPM_FC1_PWR_CON
) | PWR_CLK_DIS
) & ~PWR_RST_B
);
93 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) & ~PWR_ON
);
94 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) & ~PWR_ON_S
);
95 while (((spm_read(SPM_PWR_STATUS
) & FC1
) != 0) | ((spm_read(SPM_PWR_STATUS_S
) & FC1
) != 0));
97 else /* STA_POWER_ON */
99 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) | PWR_ON
);
101 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) | PWR_ON_S
);
102 while (((spm_read(SPM_PWR_STATUS
) & FC1
) != FC1
) | ((spm_read(SPM_PWR_STATUS_S
) & FC1
) != FC1
));
104 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) & ~PWR_CLK_DIS
);
106 spm_write(SPM_CPU_FC1_L1_PDN
, spm_read(SPM_CPU_FC1_L1_PDN
) & ~L1_PDN
);
107 while ((spm_read(SPM_CPU_FC1_L1_PDN
) & L1_PDN_ACK
) != 0);
108 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) | SRAM_ISOINT_B
);
109 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) & ~SRAM_CKISO
);
111 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) & ~PWR_ISO
);
112 spm_write(SPM_FC1_PWR_CON
, spm_read(SPM_FC1_PWR_CON
) | PWR_RST_B
);
115 spm_mtcmos_cpu_unlock(&flags
);
120 int spm_mtcmos_ctrl_cpu2(int state
, int chkWfiBeforePdn
)
124 /* enable register control */
125 spm_write(SPM_POWERON_CONFIG_SET
, (SPM_PROJECT_CODE
<< 16) | (1U << 0));
127 spm_mtcmos_cpu_lock(&flags
);
129 if (state
== STA_POWER_DOWN
)
132 while ((spm_read(SPM_SLEEP_TIMER_STA
) & APMCU2_SLEEP
) == 0);
134 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) | SRAM_CKISO
);
135 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) & ~SRAM_ISOINT_B
);
136 spm_write(SPM_CPU_FC2_L1_PDN
, spm_read(SPM_CPU_FC2_L1_PDN
) | L1_PDN
);
137 while ((spm_read(SPM_CPU_FC2_L1_PDN
) & L1_PDN_ACK
) != L1_PDN_ACK
);
139 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) | PWR_ISO
);
140 spm_write(SPM_FC2_PWR_CON
, (spm_read(SPM_FC2_PWR_CON
) | PWR_CLK_DIS
) & ~PWR_RST_B
);
142 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) & ~PWR_ON
);
143 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) & ~PWR_ON_S
);
144 while (((spm_read(SPM_PWR_STATUS
) & FC2
) != 0) | ((spm_read(SPM_PWR_STATUS_S
) & FC2
) != 0));
146 else /* STA_POWER_ON */
148 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) | PWR_ON
);
150 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) | PWR_ON_S
);
151 while (((spm_read(SPM_PWR_STATUS
) & FC2
) != FC2
) | ((spm_read(SPM_PWR_STATUS_S
) & FC2
) != FC2
));
153 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) & ~PWR_CLK_DIS
);
155 spm_write(SPM_CPU_FC2_L1_PDN
, spm_read(SPM_CPU_FC2_L1_PDN
) & ~L1_PDN
);
156 while ((spm_read(SPM_CPU_FC2_L1_PDN
) & L1_PDN_ACK
) != 0);
157 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) | SRAM_ISOINT_B
);
158 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) & ~SRAM_CKISO
);
160 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) & ~PWR_ISO
);
161 spm_write(SPM_FC2_PWR_CON
, spm_read(SPM_FC2_PWR_CON
) | PWR_RST_B
);
164 spm_mtcmos_cpu_unlock(&flags
);
169 int spm_mtcmos_ctrl_cpu3(int state
, int chkWfiBeforePdn
)
173 /* enable register control */
174 spm_write(SPM_POWERON_CONFIG_SET
, (SPM_PROJECT_CODE
<< 16) | (1U << 0));
176 spm_mtcmos_cpu_lock(&flags
);
178 if (state
== STA_POWER_DOWN
)
181 while ((spm_read(SPM_SLEEP_TIMER_STA
) & APMCU3_SLEEP
) == 0);
183 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) | SRAM_CKISO
);
184 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) & ~SRAM_ISOINT_B
);
185 spm_write(SPM_CPU_FC3_L1_PDN
, spm_read(SPM_CPU_FC3_L1_PDN
) | L1_PDN
);
186 while ((spm_read(SPM_CPU_FC3_L1_PDN
) & L1_PDN_ACK
) != L1_PDN_ACK
);
188 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) | PWR_ISO
);
189 spm_write(SPM_FC3_PWR_CON
, (spm_read(SPM_FC3_PWR_CON
) | PWR_CLK_DIS
) & ~PWR_RST_B
);
191 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) & ~PWR_ON
);
192 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) & ~PWR_ON_S
);
193 while (((spm_read(SPM_PWR_STATUS
) & FC3
) != 0) | ((spm_read(SPM_PWR_STATUS_S
) & FC3
) != 0));
195 else /* STA_POWER_ON */
197 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) | PWR_ON
);
199 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) | PWR_ON_S
);
200 while (((spm_read(SPM_PWR_STATUS
) & FC3
) != FC3
) | ((spm_read(SPM_PWR_STATUS_S
) & FC3
) != FC3
));
202 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) & ~PWR_CLK_DIS
);
204 spm_write(SPM_CPU_FC3_L1_PDN
, spm_read(SPM_CPU_FC3_L1_PDN
) & ~L1_PDN
);
205 while ((spm_read(SPM_CPU_FC3_L1_PDN
) & L1_PDN_ACK
) != 0);
206 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) | SRAM_ISOINT_B
);
207 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) & ~SRAM_CKISO
);
209 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) & ~PWR_ISO
);
210 spm_write(SPM_FC3_PWR_CON
, spm_read(SPM_FC3_PWR_CON
) | PWR_RST_B
);
213 spm_mtcmos_cpu_unlock(&flags
);
218 int spm_mtcmos_ctrl_dbg(int state
)
220 if (state
== STA_POWER_DOWN
) {
222 } else { /* STA_POWER_ON */
229 int spm_mtcmos_ctrl_cpusys(int state
)
231 if (state
== STA_POWER_DOWN
) {
233 } else { /* STA_POWER_ON */
240 bool spm_cpusys_can_power_down(void)
242 return !(spm_read(SPM_PWR_STATUS
) & 0x00000E00) &&
243 !(spm_read(SPM_PWR_STATUS_S
) & 0x00000E00);
247 /**************************************
249 **************************************/
250 static DEFINE_SPINLOCK(spm_noncpu_lock
);
253 void spm_mtcmos_noncpu_lock(unsigned long *flags
)
255 spin_lock_irqsave(&spm_noncpu_lock
, *flags
);
258 void spm_mtcmos_noncpu_unlock(unsigned long *flags
)
260 spin_unlock_irqrestore(&spm_noncpu_lock
, *flags
);
263 #define spm_mtcmos_noncpu_lock(flags) \
265 spin_lock_irqsave(&spm_noncpu_lock, flags); \
268 #define spm_mtcmos_noncpu_unlock(flags) \
270 spin_unlock_irqrestore(&spm_noncpu_lock, flags); \
276 #define VDE_PWR_STA_MASK (0x1 << 7)
277 //#define VEN_PWR_STA_MASK (0x1 << 7)
278 #define IFR_PWR_STA_MASK (0x1 << 6)
279 #define ISP_PWR_STA_MASK (0x1 << 5)
280 #define DIS_PWR_STA_MASK (0x1 << 3)
281 #define MFG_PWR_STA_MASK (0x1 << 4)
282 #define DPY_PWR_STA_MASK (0x1 << 2)
283 #define CONN_PWR_STA_MASK (0x1 << 1)
284 //#define MD2_PWR_STA_MASK (0x1 << 1)
285 #define MD1_PWR_STA_MASK (0x1 << 0)
288 #define PWR_RST_B (0x1 << 0)
289 #define PWR_ISO (0x1 << 1)
290 #define PWR_ON (0x1 << 2)
291 #define PWR_ON_S (0x1 << 3)
292 #define PWR_CLK_DIS (0x1 << 4)
295 #define SRAM_PDN (0xf << 8)
296 //#define SRAM_ACK (0xf << 12)
298 //#define SROM_PDN (0xf << 16)
299 //#define SROM_ACK (0xf << 20)
301 #define MD_SRAM_PDN (0x1 << 8)
303 #define VDE_SRAM_ACK (0x1 << 12)
304 //#define VEN_SRAM_ACK (0xf << 12)
305 #define IFR_SRAM_ACK (0xf << 12)
306 #define ISP_SRAM_ACK (0x3 << 12)
307 #define DIS_SRAM_ACK (0xf << 12)
308 #define MFG_SRAM_ACK (0x1 << 12)
310 //#define TOPAXI_SI0_CTL (INFRACFG_BASE + 0x0200)
311 //#define TOPAXI_PROT_EN (INFRACFG_AO_BASE + 0x0220)
312 //#define TOPAXI_PROT_STA1 (INFRACFG_AO_BASE + 0x0228)
314 //#define MFG_PROT_MASK 0x0020
315 //#define MD1_PROT_MASK 0x5300
316 //#define MD2_PROT_MASK 0xAC00
317 #define MD1_PROT_MASK 0x00B8
318 #define CONN_PROT_MASK 0x0104
319 #define DISP_PROT_MASK 0x0002//0x0042
321 //#define MFG_SI0_MASK 0x0400
324 int spm_mtcmos_ctrl_vdec(int state
)
327 volatile unsigned int val
;
330 spm_mtcmos_noncpu_lock(flags
);
332 if (state
== STA_POWER_DOWN
) {
333 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) | SRAM_PDN
);
335 while ((spm_read(SPM_VDE_PWR_CON
) & VDE_SRAM_ACK
) != VDE_SRAM_ACK
) {
338 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) | PWR_ISO
);
340 val
= spm_read(SPM_VDE_PWR_CON
);
341 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
342 spm_write(SPM_VDE_PWR_CON
, val
);
344 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
348 if (spm_read(SPM_PWR_STATUS
) & VDE_PWR_STA_MASK
) {
352 while ((spm_read(SPM_PWR_STATUS
) & VDE_PWR_STA_MASK
)
353 || (spm_read(SPM_PWR_STATUS_S
) & VDE_PWR_STA_MASK
)) {
356 } else { /* STA_POWER_ON */
357 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) | PWR_ON
);
358 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) | PWR_ON_S
);
362 while (!(spm_read(SPM_PWR_STATUS
) & VDE_PWR_STA_MASK
)
363 || !(spm_read(SPM_PWR_STATUS_S
) & VDE_PWR_STA_MASK
)) {
367 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) & ~PWR_CLK_DIS
);
368 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) & ~PWR_ISO
);
369 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) | PWR_RST_B
);
371 spm_write(SPM_VDE_PWR_CON
, spm_read(SPM_VDE_PWR_CON
) & ~SRAM_PDN
);
373 while ((spm_read(SPM_VDE_PWR_CON
) & VDE_SRAM_ACK
)) {
378 if (!(spm_read(SPM_PWR_STATUS
) & VDE_PWR_STA_MASK
)) {
384 spm_mtcmos_noncpu_unlock(flags
);
389 int spm_mtcmos_ctrl_isp(int state
)
392 volatile unsigned int val
;
395 spm_mtcmos_noncpu_lock(flags
);
397 if (state
== STA_POWER_DOWN
) {
398 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) | SRAM_PDN
);
400 while ((spm_read(SPM_ISP_PWR_CON
) & ISP_SRAM_ACK
) != ISP_SRAM_ACK
) {
403 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) | PWR_ISO
);
405 val
= spm_read(SPM_ISP_PWR_CON
);
406 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
407 spm_write(SPM_ISP_PWR_CON
, val
);
409 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
413 if (spm_read(SPM_PWR_STATUS
) & ISP_PWR_STA_MASK
) {
417 while ((spm_read(SPM_PWR_STATUS
) & ISP_PWR_STA_MASK
)
418 || (spm_read(SPM_PWR_STATUS_S
) & ISP_PWR_STA_MASK
)) {
421 } else { /* STA_POWER_ON */
422 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) | PWR_ON
);
423 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) | PWR_ON_S
);
427 while (!(spm_read(SPM_PWR_STATUS
) & ISP_PWR_STA_MASK
)
428 || !(spm_read(SPM_PWR_STATUS_S
) & ISP_PWR_STA_MASK
)) {
431 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) & ~PWR_CLK_DIS
);
432 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) & ~PWR_ISO
);
433 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) | PWR_RST_B
);
435 spm_write(SPM_ISP_PWR_CON
, spm_read(SPM_ISP_PWR_CON
) & ~SRAM_PDN
);
437 while ((spm_read(SPM_ISP_PWR_CON
) & ISP_SRAM_ACK
)) {
442 if (!(spm_read(SPM_PWR_STATUS
) & ISP_PWR_STA_MASK
)) {
448 spm_mtcmos_noncpu_unlock(flags
);
453 int spm_mtcmos_ctrl_disp(int state
)
456 volatile unsigned int val
;
459 spm_mtcmos_noncpu_lock(flags
);
461 if (state
== STA_POWER_DOWN
) {
462 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) | DISP_PROT_MASK
);
463 while ((spm_read(TOPAXI_PROT_STA1
) & DISP_PROT_MASK
) != DISP_PROT_MASK
) {
466 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) | SRAM_PDN
);
468 while ((spm_read(SPM_DIS_PWR_CON
) & DIS_SRAM_ACK
) != DIS_SRAM_ACK
) {
471 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) | PWR_ISO
);
473 val
= spm_read(SPM_DIS_PWR_CON
);
474 //val = (val & ~PWR_RST_B) | PWR_CLK_DIS;
475 val
= val
| PWR_CLK_DIS
;
476 spm_write(SPM_DIS_PWR_CON
, val
);
478 //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) & ~(PWR_ON | PWR_ON_S));
482 if (spm_read(SPM_PWR_STATUS
) & DIS_PWR_STA_MASK
) {
486 //while ((spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
487 // || (spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
490 } else { /* STA_POWER_ON */
491 //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON);
492 //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_ON_S);
496 //while (!(spm_read(SPM_PWR_STATUS) & DIS_PWR_STA_MASK)
497 // || !(spm_read(SPM_PWR_STATUS_S) & DIS_PWR_STA_MASK)) {
500 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) & ~PWR_CLK_DIS
);
501 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) & ~PWR_ISO
);
502 //spm_write(SPM_DIS_PWR_CON, spm_read(SPM_DIS_PWR_CON) | PWR_RST_B);
504 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) & ~SRAM_PDN
);
507 while ((spm_read(SPM_DIS_PWR_CON
) & DIS_SRAM_ACK
)) {
513 if (!(spm_read(SPM_PWR_STATUS
) & DIS_PWR_STA_MASK
)) {
517 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) & ~DISP_PROT_MASK
);
518 while (spm_read(TOPAXI_PROT_STA1
) & DISP_PROT_MASK
) {
522 spm_mtcmos_noncpu_unlock(flags
);
529 int spm_mtcmos_ctrl_disp(int state
)
532 volatile unsigned int val
;
535 spm_mtcmos_noncpu_lock(flags
);
537 if (state
== STA_POWER_DOWN
) {
538 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) | DISP_PROT_MASK
);
539 while ((spm_read(TOPAXI_PROT_STA1
) & DISP_PROT_MASK
) != DISP_PROT_MASK
) {
542 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) | SRAM_PDN
);
544 while ((spm_read(SPM_DIS_PWR_CON
) & DIS_SRAM_ACK
) != DIS_SRAM_ACK
) {
547 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) | PWR_ISO
);
549 val
= spm_read(SPM_DIS_PWR_CON
);
550 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
551 // val = val | PWR_CLK_DIS;
552 spm_write(SPM_DIS_PWR_CON
, val
);
554 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
558 if (spm_read(SPM_PWR_STATUS
) & DIS_PWR_STA_MASK
) {
562 while ((spm_read(SPM_PWR_STATUS
) & DIS_PWR_STA_MASK
)
563 || (spm_read(SPM_PWR_STATUS_S
) & DIS_PWR_STA_MASK
)) {
566 } else { /* STA_POWER_ON */
567 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) | PWR_ON
);
568 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) | PWR_ON_S
);
572 while (!(spm_read(SPM_PWR_STATUS
) & DIS_PWR_STA_MASK
)
573 || !(spm_read(SPM_PWR_STATUS_S
) & DIS_PWR_STA_MASK
)) {
576 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) & ~PWR_CLK_DIS
);
577 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) & ~PWR_ISO
);
578 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) | PWR_RST_B
);
580 spm_write(SPM_DIS_PWR_CON
, spm_read(SPM_DIS_PWR_CON
) & ~SRAM_PDN
);
583 while ((spm_read(SPM_DIS_PWR_CON
) & DIS_SRAM_ACK
)) {
589 if (!(spm_read(SPM_PWR_STATUS
) & DIS_PWR_STA_MASK
)) {
593 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) & ~DISP_PROT_MASK
);
594 while (spm_read(TOPAXI_PROT_STA1
) & DISP_PROT_MASK
) {
598 spm_mtcmos_noncpu_unlock(flags
);
604 int spm_mtcmos_ctrl_mfg(int state
)
607 volatile unsigned int val
;
610 spm_mtcmos_noncpu_lock(flags
);
612 if (state
== STA_POWER_DOWN
) {
613 // spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) | MFG_PROT_MASK);
614 // while ((spm_read(TOPAXI_PROT_STA1) & MFG_PROT_MASK) != MFG_PROT_MASK) {
617 // spm_write(TOPAXI_SI0_CTL, spm_read(TOPAXI_SI0_CTL) & ~MFG_SI0_MASK);
619 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) | SRAM_PDN
);
621 while ((spm_read(SPM_MFG_PWR_CON
) & MFG_SRAM_ACK
) != MFG_SRAM_ACK
) {
624 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) | PWR_ISO
);
626 val
= spm_read(SPM_MFG_PWR_CON
);
627 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
628 spm_write(SPM_MFG_PWR_CON
, val
);
630 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
634 if (spm_read(SPM_PWR_STATUS
) & MFG_PWR_STA_MASK
) {
638 while ((spm_read(SPM_PWR_STATUS
) & MFG_PWR_STA_MASK
)
639 || (spm_read(SPM_PWR_STATUS_S
) & MFG_PWR_STA_MASK
)) {
642 } else { /* STA_POWER_ON */
643 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) | PWR_ON
);
644 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) | PWR_ON_S
);
648 while (!(spm_read(SPM_PWR_STATUS
) & MFG_PWR_STA_MASK
) ||
649 !(spm_read(SPM_PWR_STATUS_S
) & MFG_PWR_STA_MASK
)) {
653 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) & ~PWR_CLK_DIS
);
654 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) & ~PWR_ISO
);
655 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) | PWR_RST_B
);
657 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) & ~SRAM_PDN
);
659 while ((spm_read(SPM_MFG_PWR_CON
) & MFG_SRAM_ACK
)) {
664 if (!(spm_read(SPM_PWR_STATUS
) & MFG_PWR_STA_MASK
)) {
668 // spm_write(TOPAXI_PROT_EN, spm_read(TOPAXI_PROT_EN) & ~MFG_PROT_MASK);
669 // while (spm_read(TOPAXI_PROT_STA1) & MFG_PROT_MASK) {
671 // spm_write(TOPAXI_SI0_CTL, spm_read(TOPAXI_SI0_CTL) | MFG_SI0_MASK);
674 spm_mtcmos_noncpu_unlock(flags
);
679 int spm_mtcmos_ctrl_infra(int state
)
682 volatile unsigned int val
;
685 spm_mtcmos_noncpu_lock(flags
);
687 if (state
== STA_POWER_DOWN
) {
688 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) | SRAM_PDN
);
690 while ((spm_read(SPM_IFR_PWR_CON
) & IFR_SRAM_ACK
) != IFR_SRAM_ACK
) {
693 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) | PWR_ISO
);
695 val
= spm_read(SPM_IFR_PWR_CON
);
696 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
697 spm_write(SPM_IFR_PWR_CON
, val
);
699 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
703 if (spm_read(SPM_PWR_STATUS
) & IFR_PWR_STA_MASK
) {
707 while ((spm_read(SPM_PWR_STATUS
) & IFR_PWR_STA_MASK
)
708 || (spm_read(SPM_PWR_STATUS_S
) & IFR_PWR_STA_MASK
)) {
711 } else { /* STA_POWER_ON */
712 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) | PWR_ON
);
713 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) | PWR_ON_S
);
717 while (!(spm_read(SPM_PWR_STATUS
) & IFR_PWR_STA_MASK
)
718 || !(spm_read(SPM_PWR_STATUS_S
) & IFR_PWR_STA_MASK
)) {
722 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) & ~PWR_CLK_DIS
);
723 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) & ~PWR_ISO
);
724 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) | PWR_RST_B
);
726 spm_write(SPM_IFR_PWR_CON
, spm_read(SPM_IFR_PWR_CON
) & ~SRAM_PDN
);
728 while ((spm_read(SPM_IFR_PWR_CON
) & IFR_SRAM_ACK
)) {
733 if (!(spm_read(SPM_PWR_STATUS
) & IFR_PWR_STA_MASK
)) {
739 spm_mtcmos_noncpu_unlock(flags
);
744 int spm_mtcmos_ctrl_ddrphy(int state
)
747 volatile unsigned int val
;
750 spm_mtcmos_noncpu_lock(flags
);
752 if (state
== STA_POWER_DOWN
) {
753 spm_write(SPM_DPY_PWR_CON
, spm_read(SPM_DPY_PWR_CON
) | PWR_ISO
);
755 val
= spm_read(SPM_DPY_PWR_CON
);
756 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
757 spm_write(SPM_DPY_PWR_CON
, val
);
759 spm_write(SPM_DPY_PWR_CON
, spm_read(SPM_DPY_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
763 if (spm_read(SPM_PWR_STATUS
) & DPY_PWR_STA_MASK
) {
767 while ((spm_read(SPM_PWR_STATUS
) & DPY_PWR_STA_MASK
)
768 || (spm_read(SPM_PWR_STATUS_S
) & DPY_PWR_STA_MASK
)) {
771 } else { /* STA_POWER_ON */
772 spm_write(SPM_DPY_PWR_CON
, spm_read(SPM_DPY_PWR_CON
) | PWR_ON
);
773 spm_write(SPM_DPY_PWR_CON
, spm_read(SPM_DPY_PWR_CON
) | PWR_ON_S
);
777 while (!(spm_read(SPM_PWR_STATUS
) & DPY_PWR_STA_MASK
)
778 || !(spm_read(SPM_PWR_STATUS_S
) & DPY_PWR_STA_MASK
)) {
782 spm_write(SPM_DPY_PWR_CON
, spm_read(SPM_DPY_PWR_CON
) & ~PWR_CLK_DIS
);
783 spm_write(SPM_DPY_PWR_CON
, spm_read(SPM_DPY_PWR_CON
) & ~PWR_ISO
);
784 spm_write(SPM_DPY_PWR_CON
, spm_read(SPM_DPY_PWR_CON
) | PWR_RST_B
);
788 if (!(spm_read(SPM_PWR_STATUS
) & DPY_PWR_STA_MASK
)) {
794 spm_mtcmos_noncpu_unlock(flags
);
799 int spm_mtcmos_ctrl_mdsys1(int state
)
802 volatile unsigned int val
;
806 spm_mtcmos_noncpu_lock(flags
);
808 if (state
== STA_POWER_DOWN
) {
809 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) | MD1_PROT_MASK
);
810 while ((spm_read(TOPAXI_PROT_STA1
) & MD1_PROT_MASK
) != MD1_PROT_MASK
) {
815 printk("MD MTCMOS DOWN: TOPAXI_PROT_STA1=0x%x, count=%d.\n", spm_read(TOPAXI_PROT_STA1
), count
);
817 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) | MD_SRAM_PDN
);
819 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) | PWR_ISO
);
821 val
= spm_read(SPM_MD_PWR_CON
);
822 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
823 spm_write(SPM_MD_PWR_CON
, val
);
825 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
829 if (spm_read(SPM_PWR_STATUS
) & MD1_PWR_STA_MASK
) {
833 while ((spm_read(SPM_PWR_STATUS
) & MD1_PWR_STA_MASK
)
834 || (spm_read(SPM_PWR_STATUS_S
) & MD1_PWR_STA_MASK
)) {
837 } else { /* STA_POWER_ON */
838 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) | PWR_ON
);
839 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) | PWR_ON_S
);
843 while (!(spm_read(SPM_PWR_STATUS
) & MD1_PWR_STA_MASK
)
844 || !(spm_read(SPM_PWR_STATUS_S
) & MD1_PWR_STA_MASK
)) {
848 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) & ~PWR_CLK_DIS
);
849 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) & ~PWR_ISO
);
850 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) | PWR_RST_B
);
852 spm_write(SPM_MD_PWR_CON
, spm_read(SPM_MD_PWR_CON
) & ~MD_SRAM_PDN
);
856 if (!(spm_read(SPM_PWR_STATUS
) & MD1_PWR_STA_MASK
)) {
860 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) & ~MD1_PROT_MASK
);
861 while (spm_read(TOPAXI_PROT_STA1
) & MD1_PROT_MASK
) {
865 spm_mtcmos_noncpu_unlock(flags
);
870 int spm_mtcmos_ctrl_connsys(int state
)
873 volatile unsigned int val
;
877 spm_mtcmos_noncpu_lock(flags
);
879 if (state
== STA_POWER_DOWN
) {
880 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) | CONN_PROT_MASK
);
881 while ((spm_read(TOPAXI_PROT_STA1
) & CONN_PROT_MASK
) != CONN_PROT_MASK
) {
887 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) | MD_SRAM_PDN
);
889 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) | PWR_ISO
);
891 val
= spm_read(SPM_CONN_PWR_CON
);
892 val
= (val
& ~PWR_RST_B
) | PWR_CLK_DIS
;
893 spm_write(SPM_CONN_PWR_CON
, val
);
895 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
899 if (spm_read(SPM_PWR_STATUS
) & CONN_PWR_STA_MASK
) {
903 while ((spm_read(SPM_PWR_STATUS
) & CONN_PWR_STA_MASK
)
904 || (spm_read(SPM_PWR_STATUS_S
) & CONN_PWR_STA_MASK
)) {
908 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) | PWR_ON
);
909 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) | PWR_ON_S
);
913 while (!(spm_read(SPM_PWR_STATUS
) & CONN_PWR_STA_MASK
)
914 || !(spm_read(SPM_PWR_STATUS_S
) & CONN_PWR_STA_MASK
)) {
918 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) & ~PWR_CLK_DIS
);
919 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) & ~PWR_ISO
);
920 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) | PWR_RST_B
);
922 spm_write(SPM_CONN_PWR_CON
, spm_read(SPM_CONN_PWR_CON
) & ~MD_SRAM_PDN
);
926 if (!(spm_read(SPM_PWR_STATUS
) & CONN_PWR_STA_MASK
)) {
930 spm_write(TOPAXI_PROT_EN
, spm_read(TOPAXI_PROT_EN
) & ~CONN_PROT_MASK
);
931 while (spm_read(TOPAXI_PROT_STA1
) & CONN_PROT_MASK
) {
935 spm_mtcmos_noncpu_unlock(flags
);
943 *test_spm_gpu_power_on - test whether gpu could be powered on
945 *Returns 1 if power on operation succeed, 0 otherwise.
947 int test_spm_gpu_power_on(void)
950 volatile unsigned int sta1
, sta2
;
951 volatile unsigned int val
;
954 sta1
= spm_read(SPM_PWR_STATUS
);
955 sta2
= spm_read(SPM_PWR_STATUS_S
);
956 if (((sta1
& MFG_PWR_STA_MASK
) == MFG_PWR_STA_MASK
) &&
957 ((sta2
& MFG_PWR_STA_MASK
) == MFG_PWR_STA_MASK
)) {
958 printk("[%s]: test_spm_gpu_power_on already on, return: 1.\n", __func__
);
962 spm_mtcmos_noncpu_lock(flags
);
964 val
= spm_read(SPM_MFG_PWR_CON
);
965 BUG_ON(!(val
& PWR_ISO
));
967 for(i
= 0; i
< 5; i
++) {
969 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) | PWR_ON
);
970 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) | PWR_ON_S
);
974 sta1
= spm_read(SPM_PWR_STATUS
);
975 sta2
= spm_read(SPM_PWR_STATUS_S
);
976 if (((sta1
& MFG_PWR_STA_MASK
) != MFG_PWR_STA_MASK
) ||
977 ((sta2
& MFG_PWR_STA_MASK
) != MFG_PWR_STA_MASK
)) {
978 spm_mtcmos_noncpu_unlock(flags
);
979 printk("[%s]: test_spm_gpu_power_on return: 0.\n", __func__
);
983 spm_write(SPM_MFG_PWR_CON
, spm_read(SPM_MFG_PWR_CON
) & ~(PWR_ON
| PWR_ON_S
));
985 sta1
= spm_read(SPM_PWR_STATUS
);
986 sta2
= spm_read(SPM_PWR_STATUS_S
);
987 if (((sta1
& MFG_PWR_STA_MASK
) == MFG_PWR_STA_MASK
) ||
988 ((sta2
& MFG_PWR_STA_MASK
) == MFG_PWR_STA_MASK
)) {
989 spm_mtcmos_noncpu_unlock(flags
);
990 printk("[%s]: test_spm_gpu_power_on return: 0.\n", __func__
);
996 spm_mtcmos_noncpu_unlock(flags
);
998 printk("[%s]: test_spm_gpu_power_on return: 1.\n", __func__
);
1002 MODULE_DESCRIPTION("MT6582 SPM-MTCMOS Driver v0.1");