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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / mt_ptp.c
1 #include <linux/init.h>
2 #include <linux/module.h>
3 #include <linux/kernel.h>
4 #include <linux/proc_fs.h>
5 #include <linux/spinlock.h>
6 #include <linux/kthread.h>
7 #include <linux/hrtimer.h>
8 #include <linux/ktime.h>
9 #include <linux/interrupt.h>
10 #include <linux/syscore_ops.h>
11 #include <linux/platform_device.h>
12 #include <linux/kobject.h>
13 #include <linux/string.h>
14
15 #include "mach/mt_reg_base.h"
16 #include "mach/mt_typedefs.h"
17
18 #include "mach/irqs.h"
19 #include "mach/mt_ptp.h"
20 #include "mach/mt_cpufreq.h"
21 #include "mach/mt_thermal.h"
22 #include "mach/mt_spm_idle.h"
23 #include "mach/mt_pmic_wrap.h"
24 #include "mach/mt_clkmgr.h"
25
26 #include "mach/mtk_rtc_hal.h"
27 #include "mach/mt_rtc_hw.h"
28 #include "mach/mt_dcm.h"
29
30 /* Global variable */
31 #if EN_PTP_OD
32 volatile unsigned int ptp_data[3] = {0xffffffff, 0, 0};
33 #else
34 volatile unsigned int ptp_data[3] = {0, 0, 0};
35 #endif
36
37 #if 1
38 static unsigned int val_0 = 0x00000000;
39 static unsigned int val_1 = 0x00000000;
40 static unsigned int val_2 = 0x00000000;
41 static unsigned int val_3 = 0x00000000;
42 #endif
43
44 #if 0
45 static unsigned int val_0 = 0x142B1607;
46 static unsigned int val_1 = 0xB0AAAAAA;
47 static unsigned int val_2 = 0x00000000;
48 static unsigned int val_3 = 0x20EA0588;
49 #endif
50
51 #if 0
52 static unsigned int val_0 = 0x14052707;
53 static unsigned int val_1 = 0xB0AAAAAA;
54 static unsigned int val_2 = 0x00000000;
55 static unsigned int val_3 = 0x20EA0588;
56 #endif
57
58 #if 0
59 static unsigned int val_0 = 0x14182A07;
60 static unsigned int val_1 = 0xB0AAAAAA;
61 static unsigned int val_2 = 0x00000000;
62 static unsigned int val_3 = 0x205B0588;
63 #endif
64
65 #if 0
66 static unsigned int val_0 = 0x14E43D07;
67 static unsigned int val_1 = 0xB0AAAAAA;
68 static unsigned int val_2 = 0x00000000;
69 static unsigned int val_3 = 0x205B0588;
70 #endif
71
72 #define ptp_attr(_name) \
73 static struct kobj_attribute _name##_attr = { \
74 .attr = { \
75 .name = __stringify(_name), \
76 .mode = 0644, \
77 }, \
78 .show = _name##_show, \
79 .store = _name##_store, \
80 }
81
82 static unsigned char freq_0, freq_1, freq_2, freq_3;
83 static unsigned char freq_4, freq_5, freq_6, freq_7;
84
85 static unsigned int ptp_level;
86
87 static unsigned int ptp_array_size = 0;
88
89 static unsigned int ptp_volt_0, ptp_volt_1, ptp_volt_2, ptp_volt_3;
90 static unsigned int ptp_volt_4, ptp_volt_5, ptp_volt_6, ptp_volt_7;
91
92 static unsigned int ptp_init2_volt_0, ptp_init2_volt_1, ptp_init2_volt_2, ptp_init2_volt_3;
93 static unsigned int ptp_init2_volt_4, ptp_init2_volt_5, ptp_init2_volt_6, ptp_init2_volt_7;
94
95 static unsigned int ptp_dcvoffset = 0;
96 static unsigned int ptp_agevoffset = 0;
97
98 static unsigned int ptpod_pmic_volt[8] = {0x30, 0x30, 0x30, 0x30, 0x30, 0,0,0};
99
100 /* Extern function */
101 extern int mt_irq_mask_all(struct mtk_irq_mask *mask);
102 extern int mt_irq_mask_restore(struct mtk_irq_mask *mask);
103
104 extern unsigned int get_devinfo_with_index(unsigned int index);
105
106 extern void mt_fh_popod_save(void);
107 extern void mt_fh_popod_restore(void);
108
109 extern unsigned int mt_cpufreq_max_frequency_by_DVS(unsigned int num);
110 extern void mt_cpufreq_return_default_DVS_by_ptpod(void);
111 extern unsigned int mt_cpufreq_voltage_set_by_ptpod(unsigned int pmic_volt[], unsigned int array_size);
112 extern unsigned int mt_cpufreq_cur_vproc(void);
113
114 static struct hrtimer mt_ptp_log_timer;
115 struct task_struct *mt_ptp_log_thread = NULL;
116 static DECLARE_WAIT_QUEUE_HEAD(mt_ptp_log_timer_waiter);
117
118 static int mt_ptp_log_timer_flag = 0;
119 static int mt_ptp_log_period_s = 2;
120 static int mt_ptp_log_period_ns = 0;
121
122 static struct hrtimer mt_ptp_volt_timer;
123 struct task_struct *mt_ptp_volt_thread = NULL;
124 static DECLARE_WAIT_QUEUE_HEAD(mt_ptp_volt_timer_waiter);
125
126 static int mt_ptp_volt_timer_flag = 0;
127 static int mt_ptp_volt_period_s = 0;
128 static int mt_ptp_volt_period_ns = 10000;
129
130 static int mt_ptp_offset = 0;
131
132 #if EN_PTP_OD
133 static int mt_ptp_enable = 1;
134 #else
135 static int mt_ptp_enable = 0;
136 #endif
137
138 static unsigned int ptp_trasnfer_to_volt(unsigned int value)
139 {
140 return (((value * 625) / 100) + 700); // (700mv + n * 6.25mv)
141 }
142
143 enum hrtimer_restart mt_ptp_log_timer_func(struct hrtimer *timer)
144 {
145 mt_ptp_log_timer_flag = 1; wake_up_interruptible(&mt_ptp_log_timer_waiter);
146 return HRTIMER_NORESTART;
147 }
148
149 int mt_ptp_log_thread_handler(void *unused)
150 {
151 do
152 {
153 ktime_t ktime = ktime_set(mt_ptp_log_period_s, mt_ptp_log_period_ns);
154
155 wait_event_interruptible(mt_ptp_log_timer_waiter, mt_ptp_log_timer_flag != 0);
156 mt_ptp_log_timer_flag = 0;
157
158 ptp_notice("PTP_LOG: (%d) - (%d, %d, %d, %d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d, %d, %d, %d)\n", \
159 mtktscpu_get_cpu_temp(), \
160 ptp_trasnfer_to_volt(ptpod_pmic_volt[0]), \
161 ptp_trasnfer_to_volt(ptpod_pmic_volt[1]), \
162 ptp_trasnfer_to_volt(ptpod_pmic_volt[2]), \
163 ptp_trasnfer_to_volt(ptpod_pmic_volt[3]), \
164 ptp_trasnfer_to_volt(ptpod_pmic_volt[4]), \
165 ptp_trasnfer_to_volt(ptpod_pmic_volt[5]), \
166 ptp_trasnfer_to_volt(ptpod_pmic_volt[6]), \
167 ptp_trasnfer_to_volt(ptpod_pmic_volt[7]), \
168 mt_cpufreq_max_frequency_by_DVS(0), \
169 mt_cpufreq_max_frequency_by_DVS(1), \
170 mt_cpufreq_max_frequency_by_DVS(2), \
171 mt_cpufreq_max_frequency_by_DVS(3), \
172 mt_cpufreq_max_frequency_by_DVS(4), \
173 mt_cpufreq_max_frequency_by_DVS(5), \
174 mt_cpufreq_max_frequency_by_DVS(6), \
175 mt_cpufreq_max_frequency_by_DVS(7));
176
177 hrtimer_start(&mt_ptp_log_timer, ktime, HRTIMER_MODE_REL);
178 } while (!kthread_should_stop());
179
180 return 0;
181 }
182
183 enum hrtimer_restart mt_ptp_volt_timer_func(struct hrtimer *timer)
184 {
185 mt_ptp_volt_timer_flag = 1; wake_up_interruptible(&mt_ptp_volt_timer_waiter);
186 return HRTIMER_NORESTART;
187 }
188
189 int mt_ptp_volt_thread_handler(void *unused)
190 {
191 do
192 {
193 ktime_set(mt_ptp_volt_period_s, mt_ptp_volt_period_ns);
194
195 wait_event_interruptible(mt_ptp_volt_timer_waiter, mt_ptp_volt_timer_flag != 0);
196 mt_ptp_volt_timer_flag = 0;
197
198 mt_cpufreq_voltage_set_by_ptpod(ptpod_pmic_volt, ptp_array_size);
199
200 } while (!kthread_should_stop());
201
202 return 0;
203 }
204
205 unsigned int PTP_get_ptp_level(void)
206 {
207 #if defined(CONFIG_MTK_FORCE_CPU_27T)
208 return 3; // 1.5G
209 #else
210 unsigned int spd_bin_resv = 0, segment = 0, ret = 0;
211
212 segment = (get_devinfo_with_index(15) >> 31) & 0x1; //M_HW_RES4
213 if(segment == 0)
214 {
215 spd_bin_resv = get_devinfo_with_index(15) & 0xFFFF; //M_HW_RES4
216 }
217 else
218 {
219 spd_bin_resv = (get_devinfo_with_index(15) >> 16) & 0x7FFF; //M_HW_RES4
220 }
221
222 ptp_notice("spd_bin_resv(%d), M_HW_RES4(0x%x), M_HW2_RES2(0x%x)\n", spd_bin_resv,
223 get_devinfo_with_index(15), get_devinfo_with_index(24));
224
225 if(segment == 1)
226 {
227 if(spd_bin_resv == 0x1000)
228 ret = 0; // 1.3G
229 else if(spd_bin_resv == 0x1001)
230 ret = 5; // 1.222G
231 else if(spd_bin_resv == 0x1003)
232 ret = 6; // 1.118G
233 else
234 ret = 0; // 1.3G
235 }
236 else if(spd_bin_resv != 0)
237 {
238 if(spd_bin_resv == 0x1000)
239 ret = 3; // 1.5G, 8127T
240 else if(spd_bin_resv == 0x1001)
241 ret = 0; // 1.3G, 8127
242 else if(spd_bin_resv == 0x1003)
243 ret = 0; // 1.3G, 8117
244 else
245 ret = 0; // 1.3G,
246 }
247 else //free
248 {
249 spd_bin_resv = get_devinfo_with_index(24) & 0x7; //M_HW2_RES2
250 switch (spd_bin_resv)
251 {
252 case 0:
253 ret = 0; // 1.3G
254 break;
255 case 1:
256 ret = 3; // 1.5G
257 break;
258 case 2:
259 ret = 0; // 1.4G
260 break;
261 case 3:
262 ret = 0; // 1.3G
263 break;
264 case 4:
265 ret = 0; // 1.2G
266 break;
267 case 5:
268 ret = 0; // 1.1G
269 break;
270 case 6:
271 ret = 0; // 1.0G
272 break;
273 case 7:
274 ret = 0; // 1.0G
275 break;
276 default:
277 ret = 0; // 1.3G
278 break;
279 }
280 }
281 return ret;
282 #endif
283 }
284
285 static void PTP_Initialization_01(PTP_INIT_T* ptp_init_val)
286 {
287 unsigned int temp_i, temp_filter, temp_value;
288
289 // config PTP register
290 ptp_write(PTP_DESCHAR, ((((ptp_init_val->BDES)<<8) & 0xff00) | ((ptp_init_val->MDES) & 0xff)));
291 ptp_write(PTP_TEMPCHAR, ((((ptp_init_val->VCO)<<16) & 0xff0000) | (((ptp_init_val->MTDES)<<8) & 0xff00) | ((ptp_init_val->DVTFIXED) & 0xff)));
292 ptp_write(PTP_DETCHAR, ((((ptp_init_val->DCBDET)<<8) & 0xff00) | ((ptp_init_val->DCMDET) & 0xff)));
293 ptp_write(PTP_AGECHAR, ((((ptp_init_val->AGEDELTA)<<8) & 0xff00) | ((ptp_init_val->AGEM) & 0xff)));
294 ptp_write(PTP_DCCONFIG, ((ptp_init_val->DCCONFIG)));
295 ptp_write(PTP_AGECONFIG, ((ptp_init_val->AGECONFIG)));
296
297 if (ptp_init_val->AGEM == 0x0)
298 {
299 ptp_write(PTP_RUNCONFIG, 0x80000000);
300 }
301 else
302 {
303 temp_value = 0x0;
304
305 for (temp_i = 0 ; temp_i < 24 ; temp_i += 2)
306 {
307 temp_filter = 0x3 << temp_i;
308
309 if (((ptp_init_val->AGECONFIG) & temp_filter) == 0x0)
310 {
311 temp_value |= (0x1 << temp_i);
312 }
313 else
314 {
315 temp_value |= ((ptp_init_val->AGECONFIG) & temp_filter);
316 }
317 }
318 ptp_write(PTP_RUNCONFIG, temp_value);
319 }
320
321 ptp_write(PTP_FREQPCT30, ((((ptp_init_val->FREQPCT3) << 24)&0xff000000) | (((ptp_init_val->FREQPCT2) << 16) & 0xff0000) | (((ptp_init_val->FREQPCT1) << 8) & 0xff00) | ((ptp_init_val->FREQPCT0) & 0xff)));
322 ptp_write(PTP_FREQPCT74, ((((ptp_init_val->FREQPCT7) << 24)&0xff000000) | (((ptp_init_val->FREQPCT6) << 16) & 0xff0000) | (((ptp_init_val->FREQPCT5) << 8) & 0xff00) | ((ptp_init_val->FREQPCT4) & 0xff)));
323
324 ptp_write(PTP_LIMITVALS, ((((ptp_init_val->VMAX) << 24) & 0xff000000) | (((ptp_init_val->VMIN) << 16) & 0xff0000) | (((ptp_init_val->DTHI) << 8) & 0xff00) | ((ptp_init_val->DTLO) & 0xff)));
325 ptp_write(PTP_VBOOT, (((ptp_init_val->VBOOT) & 0xff)));
326 ptp_write(PTP_DETWINDOW, (((ptp_init_val->DETWINDOW) & 0xffff)));
327 ptp_write(PTP_PTPCONFIG, (((ptp_init_val->DETMAX) & 0xffff)));
328
329 // clear all pending PTP interrupt & config PTPINTEN
330 ptp_write(PTP_PTPINTSTS, 0xffffffff);
331
332 ptp_write(PTP_PTPINTEN, 0x00005f01);
333
334 // enable PTP INIT measurement
335 ptp_write(PTP_PTPEN, 0x00000001);
336 }
337
338 static void PTP_Initialization_02(PTP_INIT_T* ptp_init_val)
339 {
340 unsigned int temp_i, temp_filter, temp_value;
341
342 // config PTP register
343 ptp_write(PTP_DESCHAR, ((((ptp_init_val->BDES)<<8) & 0xff00) | ((ptp_init_val->MDES) & 0xff)));
344 ptp_write(PTP_TEMPCHAR, ((((ptp_init_val->VCO)<<16) & 0xff0000) | (((ptp_init_val->MTDES)<<8) & 0xff00) | ((ptp_init_val->DVTFIXED) & 0xff)));
345 ptp_write(PTP_DETCHAR, ((((ptp_init_val->DCBDET)<<8) & 0xff00) | ((ptp_init_val->DCMDET) & 0xff)));
346 ptp_write(PTP_AGECHAR, ((((ptp_init_val->AGEDELTA)<<8) & 0xff00) | ((ptp_init_val->AGEM) & 0xff)));
347 ptp_write(PTP_DCCONFIG, ((ptp_init_val->DCCONFIG)));
348 ptp_write(PTP_AGECONFIG, ((ptp_init_val->AGECONFIG)));
349
350 if (ptp_init_val->AGEM == 0x0)
351 {
352 ptp_write(PTP_RUNCONFIG, 0x80000000);
353 }
354 else
355 {
356 temp_value = 0x0;
357
358 for (temp_i = 0 ; temp_i < 24 ; temp_i += 2 )
359 {
360 temp_filter = 0x3 << temp_i;
361
362 if( ((ptp_init_val->AGECONFIG) & temp_filter) == 0x0 )
363 {
364 temp_value |= (0x1 << temp_i);
365 }
366 else
367 {
368 temp_value |= ((ptp_init_val->AGECONFIG) & temp_filter);
369 }
370 }
371
372 ptp_write(PTP_RUNCONFIG, temp_value);
373 }
374
375 ptp_write(PTP_FREQPCT30, ((((ptp_init_val->FREQPCT3)<<24)&0xff000000) | (((ptp_init_val->FREQPCT2)<<16)&0xff0000) | (((ptp_init_val->FREQPCT1)<<8)&0xff00) | ((ptp_init_val->FREQPCT0) & 0xff)));
376 ptp_write(PTP_FREQPCT74, ((((ptp_init_val->FREQPCT7)<<24)&0xff000000) | (((ptp_init_val->FREQPCT6)<<16)&0xff0000) | (((ptp_init_val->FREQPCT5)<<8)&0xff00) | ((ptp_init_val->FREQPCT4) & 0xff)));
377
378 ptp_write(PTP_LIMITVALS, ((((ptp_init_val->VMAX)<<24)&0xff000000) | (((ptp_init_val->VMIN)<<16)&0xff0000) | (((ptp_init_val->DTHI)<<8)&0xff00) | ((ptp_init_val->DTLO) & 0xff)));
379 ptp_write(PTP_VBOOT, (((ptp_init_val->VBOOT)&0xff)));
380 ptp_write(PTP_DETWINDOW, (((ptp_init_val->DETWINDOW)&0xffff)));
381 ptp_write(PTP_PTPCONFIG, (((ptp_init_val->DETMAX)&0xffff)));
382
383 // clear all pending PTP interrupt & config PTPINTEN
384 ptp_write(PTP_PTPINTSTS, 0xffffffff);
385
386 ptp_write(PTP_PTPINTEN, 0x00005f01);
387
388 ptp_write(PTP_INIT2VALS, ((((ptp_init_val->AGEVOFFSETIN)<<16) & 0xffff0000) | ((ptp_init_val->DCVOFFSETIN) & 0xffff)));
389
390 // enable PTP INIT measurement
391 ptp_write(PTP_PTPEN, 0x00000005);
392 }
393
394 static void PTP_Monitor_Mode(PTP_INIT_T* ptp_init_val)
395 {
396 unsigned int temp_i, temp_filter, temp_value;
397
398 // config PTP register
399 ptp_write(PTP_DESCHAR, ((((ptp_init_val->BDES)<<8) & 0xff00) | ((ptp_init_val->MDES) & 0xff)));
400 ptp_write(PTP_TEMPCHAR, ((((ptp_init_val->VCO)<<16) & 0xff0000) | (((ptp_init_val->MTDES)<<8) & 0xff00) | ((ptp_init_val->DVTFIXED) & 0xff)));
401 ptp_write(PTP_DETCHAR, ((((ptp_init_val->DCBDET)<<8) & 0xff00) | ((ptp_init_val->DCMDET) & 0xff)));
402 ptp_write(PTP_AGECHAR, ((((ptp_init_val->AGEDELTA)<<8) & 0xff00) | ((ptp_init_val->AGEM) & 0xff)));
403 ptp_write(PTP_DCCONFIG, ((ptp_init_val->DCCONFIG)));
404 ptp_write(PTP_AGECONFIG, ((ptp_init_val->AGECONFIG)));
405 ptp_write(PTP_TSCALCS, ((((ptp_init_val->BTS)<<12) & 0xfff000) | ((ptp_init_val->MTS) & 0xfff)));
406
407 if (ptp_init_val->AGEM == 0x0)
408 {
409 ptp_write(PTP_RUNCONFIG, 0x80000000);
410 }
411 else
412 {
413 temp_value = 0x0;
414
415 for (temp_i = 0 ; temp_i < 24 ; temp_i += 2 )
416 {
417 temp_filter = 0x3 << temp_i;
418
419 if( ((ptp_init_val->AGECONFIG) & temp_filter) == 0x0 )
420 {
421 temp_value |= (0x1 << temp_i);
422 }
423 else
424 {
425 temp_value |= ((ptp_init_val->AGECONFIG) & temp_filter);
426 }
427 }
428
429 ptp_write(PTP_RUNCONFIG, temp_value);
430 }
431
432 ptp_write(PTP_FREQPCT30, ((((ptp_init_val->FREQPCT3)<<24)&0xff000000) | (((ptp_init_val->FREQPCT2)<<16)&0xff0000) | (((ptp_init_val->FREQPCT1)<<8)&0xff00) | ((ptp_init_val->FREQPCT0) & 0xff)));
433 ptp_write(PTP_FREQPCT74, ((((ptp_init_val->FREQPCT7)<<24)&0xff000000) | (((ptp_init_val->FREQPCT6)<<16)&0xff0000) | (((ptp_init_val->FREQPCT5)<<8)&0xff00) | ((ptp_init_val->FREQPCT4) & 0xff)));
434
435 ptp_write(PTP_LIMITVALS, ((((ptp_init_val->VMAX)<<24)&0xff000000) | (((ptp_init_val->VMIN)<<16)&0xff0000) | (((ptp_init_val->DTHI)<<8)&0xff00) | ((ptp_init_val->DTLO) & 0xff)));
436 ptp_write(PTP_VBOOT, (((ptp_init_val->VBOOT)&0xff)));
437 ptp_write(PTP_DETWINDOW, (((ptp_init_val->DETWINDOW)&0xffff)));
438 ptp_write(PTP_PTPCONFIG, (((ptp_init_val->DETMAX)&0xffff)));
439
440 // clear all pending PTP interrupt & config PTPINTEN
441 ptp_write(PTP_PTPINTSTS, 0xffffffff);
442
443 ptp_write(PTP_PTPINTEN, 0x00FF0000);
444
445 // enable PTP monitor mode
446 ptp_write(PTP_PTPEN, 0x00000002);
447 }
448
449 unsigned int PTP_INIT_01(void)
450 {
451 PTP_INIT_T ptp_init_value;
452
453 ptp_data[0] = 0xffffffff;
454
455 ptp_notice("PTP_INIT_01() start (ptp_level = 0x%x).\n", ptp_level);
456
457 ptp_init_value.PTPINITEN = (val_0) & 0x1;
458 ptp_init_value.PTPMONEN = (val_0 >> 1) & 0x1;
459 ptp_init_value.MDES = (val_0 >> 8) & 0xff;
460 ptp_init_value.BDES = (val_0 >> 16) & 0xff;
461 ptp_init_value.DCMDET = (val_0 >> 24) & 0xff;
462
463 ptp_init_value.DCCONFIG = (val_1) & 0xffffff;
464 ptp_init_value.DCBDET = (val_1 >> 24) & 0xff;
465
466 ptp_init_value.AGECONFIG = (val_2) & 0xffffff;
467 ptp_init_value.AGEM = (val_2 >> 24) & 0xff;
468
469 ptp_init_value.AGEDELTA = (val_3) & 0xff;
470 ptp_init_value.DVTFIXED = (val_3 >> 8) & 0xff;
471 ptp_init_value.MTDES = (val_3 >> 16) & 0xff;
472 ptp_init_value.VCO = (val_3 >> 24) & 0xff;
473
474 ptp_init_value.FREQPCT0 = freq_0;
475 ptp_init_value.FREQPCT1 = freq_1;
476 ptp_init_value.FREQPCT2 = freq_2;
477 ptp_init_value.FREQPCT3 = freq_3;
478 ptp_init_value.FREQPCT4 = freq_4;
479 ptp_init_value.FREQPCT5 = freq_5;
480 ptp_init_value.FREQPCT6 = freq_6;
481 ptp_init_value.FREQPCT7 = freq_7;
482
483 ptp_init_value.DETWINDOW = 0xa28; // 100 us, This is the PTP Detector sampling time as represented in cycles of bclk_ck during INIT. 52 MHz
484 ptp_init_value.VMAX = 0x60; // 1.3v (700mv + n * 6.25mv)
485
486 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
487 ptp_init_value.VMIN = 0x38; // 1.05v (700mv + n * 6.25mv)
488 #else
489 ptp_init_value.VMIN = 0x48; // 1.15v (700mv + n * 6.25mv)
490 #endif
491
492 ptp_init_value.DTHI = 0x01; // positive
493 ptp_init_value.DTLO = 0xfe; // negative (2¡¦s compliment)
494 ptp_init_value.VBOOT = 0x48; // 1.15v (700mv + n * 6.25mv)
495 ptp_init_value.DETMAX = 0xffff; // This timeout value is in cycles of bclk_ck.
496
497 if (ptp_init_value.PTPINITEN == 0x0)
498 {
499 ptp_notice("PTPINITEN = 0x%x \n", ptp_init_value.PTPINITEN);
500 ptp_data[0] = 0;
501 return 1;
502 }
503
504 ptp_notice("PTPINITEN = 0x%x\n", ptp_init_value.PTPINITEN);
505 ptp_notice("PTPMONEN = 0x%x\n", ptp_init_value.PTPMONEN);
506 ptp_notice("MDES = 0x%x\n", ptp_init_value.MDES);
507 ptp_notice("BDES = 0x%x\n", ptp_init_value.BDES);
508 ptp_notice("DCMDET = 0x%x\n", ptp_init_value.DCMDET);
509 ptp_notice("DCCONFIG = 0x%x\n", ptp_init_value.DCCONFIG);
510 ptp_notice("DCBDET = 0x%x\n", ptp_init_value.DCBDET);
511 ptp_notice("AGECONFIG = 0x%x\n", ptp_init_value.AGECONFIG);
512 ptp_notice("AGEM = 0x%x\n", ptp_init_value.AGEM);
513 ptp_notice("AGEDELTA = 0x%x\n", ptp_init_value.AGEDELTA);
514 ptp_notice("DVTFIXED = 0x%x\n", ptp_init_value.DVTFIXED);
515 ptp_notice("MTDES = 0x%x\n", ptp_init_value.MTDES);
516 ptp_notice("VCO = 0x%x\n", ptp_init_value.VCO);
517 ptp_notice("FREQPCT0 = %d\n", ptp_init_value.FREQPCT0);
518 ptp_notice("FREQPCT1 = %d\n", ptp_init_value.FREQPCT1);
519 ptp_notice("FREQPCT2 = %d\n", ptp_init_value.FREQPCT2);
520 ptp_notice("FREQPCT3 = %d\n", ptp_init_value.FREQPCT3);
521 ptp_notice("FREQPCT4 = %d\n", ptp_init_value.FREQPCT4);
522 ptp_notice("FREQPCT5 = %d\n", ptp_init_value.FREQPCT5);
523 ptp_notice("FREQPCT6 = %d\n", ptp_init_value.FREQPCT6);
524 ptp_notice("FREQPCT7 = %d\n", ptp_init_value.FREQPCT7);
525
526 bus_dcm_disable(); //make sure bus dcm disable for PTP init 01
527 mt_fh_popod_save(); // disable frequency hopping (main PLL)
528 mt_cpufreq_disable_by_ptpod(); // disable DVFS and set vproc = 1.15v (1 GHz)
529
530 PTP_Initialization_01(&ptp_init_value);
531
532 return 0;
533 }
534
535 unsigned int PTP_INIT_02(void)
536 {
537 PTP_INIT_T ptp_init_value;
538
539 ptp_data[0] = 0xffffffff;
540
541 ptp_notice("PTP_INIT_02() start (ptp_level = 0x%x).\n", ptp_level);
542
543 ptp_init_value.PTPINITEN = (val_0) & 0x1;
544 ptp_init_value.PTPMONEN = (val_0 >> 1) & 0x1;
545 ptp_init_value.MDES = (val_0 >> 8) & 0xff;
546 ptp_init_value.BDES = (val_0 >> 16) & 0xff;
547 ptp_init_value.DCMDET = (val_0 >> 24) & 0xff;
548
549 ptp_init_value.DCCONFIG = (val_1) & 0xffffff;
550 ptp_init_value.DCBDET = (val_1 >> 24) & 0xff;
551
552 ptp_init_value.AGECONFIG = (val_2) & 0xffffff;
553 ptp_init_value.AGEM = (val_2 >> 24) & 0xff;
554
555 ptp_init_value.AGEDELTA = (val_3) & 0xff;
556 ptp_init_value.DVTFIXED = (val_3 >> 8) & 0xff;
557 ptp_init_value.MTDES = (val_3 >> 16) & 0xff;
558 ptp_init_value.VCO = (val_3 >> 24) & 0xff;
559
560 ptp_init_value.FREQPCT0 = freq_0;
561 ptp_init_value.FREQPCT1 = freq_1;
562 ptp_init_value.FREQPCT2 = freq_2;
563 ptp_init_value.FREQPCT3 = freq_3;
564 ptp_init_value.FREQPCT4 = freq_4;
565 ptp_init_value.FREQPCT5 = freq_5;
566 ptp_init_value.FREQPCT6 = freq_6;
567 ptp_init_value.FREQPCT7 = freq_7;
568
569 ptp_init_value.DETWINDOW = 0xa28; // 100 us, This is the PTP Detector sampling time as represented in cycles of bclk_ck during INIT. 52 MHz
570 ptp_init_value.VMAX = 0x60; // 1.3v (700mv + n * 6.25mv)
571
572 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
573 ptp_init_value.VMIN = 0x38; // 1.05v (700mv + n * 6.25mv)
574 #else
575 ptp_init_value.VMIN = 0x48; // 1.15v (700mv + n * 6.25mv)
576 #endif
577
578 ptp_init_value.DTHI = 0x01; // positive
579 ptp_init_value.DTLO = 0xfe; // negative (2¡¦s compliment)
580 ptp_init_value.VBOOT = 0x48; // 1.15v (700mv + n * 6.25mv)
581 ptp_init_value.DETMAX = 0xffff; // This timeout value is in cycles of bclk_ck.
582
583 ptp_init_value.DCVOFFSETIN= ptp_dcvoffset;
584 ptp_init_value.AGEVOFFSETIN= ptp_agevoffset;
585
586 ptp_notice("DCVOFFSETIN = 0x%x \n", ptp_init_value.DCVOFFSETIN);
587 ptp_notice("AGEVOFFSETIN = 0x%x \n", ptp_init_value.AGEVOFFSETIN);
588
589 if (ptp_init_value.PTPINITEN == 0x0)
590 {
591 ptp_notice("PTPINITEN = 0x%x \n", ptp_init_value.PTPINITEN);
592 ptp_data[0] = 0;
593 return 1;
594 }
595
596 ptp_isr_info("PTPINITEN = 0x%x\n", ptp_init_value.PTPINITEN);
597 ptp_isr_info("PTPMONEN = 0x%x\n", ptp_init_value.PTPMONEN);
598 ptp_isr_info("MDES = 0x%x\n", ptp_init_value.MDES);
599 ptp_isr_info("BDES = 0x%x\n", ptp_init_value.BDES);
600 ptp_isr_info("DCMDET = 0x%x\n", ptp_init_value.DCMDET);
601 ptp_isr_info("DCCONFIG = 0x%x\n", ptp_init_value.DCCONFIG);
602 ptp_isr_info("DCBDET = 0x%x\n", ptp_init_value.DCBDET);
603 ptp_isr_info("AGECONFIG = 0x%x\n", ptp_init_value.AGECONFIG);
604 ptp_isr_info("AGEM = 0x%x\n", ptp_init_value.AGEM);
605 ptp_isr_info("AGEDELTA = 0x%x\n", ptp_init_value.AGEDELTA);
606 ptp_isr_info("DVTFIXED = 0x%x\n", ptp_init_value.DVTFIXED);
607 ptp_isr_info("MTDES = 0x%x\n", ptp_init_value.MTDES);
608 ptp_isr_info("VCO = 0x%x\n", ptp_init_value.VCO);
609 ptp_isr_info("DCVOFFSETIN = 0x%x\n", ptp_init_value.DCVOFFSETIN);
610 ptp_isr_info("AGEVOFFSETIN = 0x%x\n", ptp_init_value.AGEVOFFSETIN);
611 ptp_isr_info("FREQPCT0 = %d\n", ptp_init_value.FREQPCT0);
612 ptp_isr_info("FREQPCT1 = %d\n", ptp_init_value.FREQPCT1);
613 ptp_isr_info("FREQPCT2 = %d\n", ptp_init_value.FREQPCT2);
614 ptp_isr_info("FREQPCT3 = %d\n", ptp_init_value.FREQPCT3);
615 ptp_isr_info("FREQPCT4 = %d\n", ptp_init_value.FREQPCT4);
616 ptp_isr_info("FREQPCT5 = %d\n", ptp_init_value.FREQPCT5);
617 ptp_isr_info("FREQPCT6 = %d\n", ptp_init_value.FREQPCT6);
618 ptp_isr_info("FREQPCT7 = %d\n", ptp_init_value.FREQPCT7);
619
620 PTP_Initialization_02(&ptp_init_value);
621
622 return 0;
623 }
624
625 unsigned int PTP_MON_MODE(void)
626 {
627 PTP_INIT_T ptp_init_value;
628 struct TS_PTPOD ts_info;
629
630 ptp_notice("PTP_MON_MODE() start (ptp_level = 0x%x).\n", ptp_level);
631
632 ptp_init_value.PTPINITEN = (val_0) & 0x1;
633 ptp_init_value.PTPMONEN = (val_0 >> 1) & 0x1;
634 ptp_init_value.ADC_CALI_EN = (val_0 >> 2) & 0x1;
635 ptp_init_value.MDES = (val_0 >> 8) & 0xff;
636 ptp_init_value.BDES = (val_0 >> 16) & 0xff;
637 ptp_init_value.DCMDET = (val_0 >> 24) & 0xff;
638
639 ptp_init_value.DCCONFIG = (val_1) & 0xffffff;
640 ptp_init_value.DCBDET = (val_1 >> 24) & 0xff;
641
642 ptp_init_value.AGECONFIG = (val_2) & 0xffffff;
643 ptp_init_value.AGEM = (val_2 >> 24) & 0xff;
644
645 ptp_init_value.AGEDELTA = (val_3) & 0xff;
646 ptp_init_value.DVTFIXED = (val_3 >> 8) & 0xff;
647 ptp_init_value.MTDES = (val_3 >> 16) & 0xff;
648 ptp_init_value.VCO = (val_3 >> 24) & 0xff;
649
650 get_thermal_slope_intercept(&ts_info);
651 ptp_init_value.MTS = ts_info.ts_MTS;
652 ptp_init_value.BTS = ts_info.ts_BTS;
653
654 ptp_init_value.FREQPCT0 = freq_0;
655 ptp_init_value.FREQPCT1 = freq_1;
656 ptp_init_value.FREQPCT2 = freq_2;
657 ptp_init_value.FREQPCT3 = freq_3;
658 ptp_init_value.FREQPCT4 = freq_4;
659 ptp_init_value.FREQPCT5 = freq_5;
660 ptp_init_value.FREQPCT6 = freq_6;
661 ptp_init_value.FREQPCT7 = freq_7;
662
663 ptp_init_value.DETWINDOW = 0xa28; // 100 us, This is the PTP Detector sampling time as represented in cycles of bclk_ck during INIT. 52 MHz
664 ptp_init_value.VMAX = 0x60; // 1.3v (700mv + n * 6.25mv)
665
666 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
667 ptp_init_value.VMIN = 0x38; // 1.05v (700mv + n * 6.25mv)
668 #else
669 ptp_init_value.VMIN = 0x48; // 1.15v (700mv + n * 6.25mv)
670 #endif
671
672 ptp_init_value.DTHI = 0x01; // positive
673 ptp_init_value.DTLO = 0xfe; // negative (2¡¦s compliment)
674 ptp_init_value.VBOOT = 0x48; // 1.15v (700mv + n * 6.25mv)
675 ptp_init_value.DETMAX = 0xffff; // This timeout value is in cycles of bclk_ck.
676
677 if( (ptp_init_value.PTPINITEN == 0x0) || (ptp_init_value.PTPMONEN == 0x0) )
678 {
679 ptp_notice("PTPINITEN = 0x%x, PTPMONEN = 0x%x, ADC_CALI_EN = 0x%x \n", ptp_init_value.PTPINITEN, ptp_init_value.PTPMONEN, ptp_init_value.ADC_CALI_EN);
680 return 1;
681 }
682
683 ptp_isr_info("PTPINITEN = 0x%x\n", ptp_init_value.PTPINITEN);
684 ptp_isr_info("PTPMONEN = 0x%x\n", ptp_init_value.PTPMONEN);
685 ptp_isr_info("MDES = 0x%x\n", ptp_init_value.MDES);
686 ptp_isr_info("BDES = 0x%x\n", ptp_init_value.BDES);
687 ptp_isr_info("DCMDET = 0x%x\n", ptp_init_value.DCMDET);
688 ptp_isr_info("DCCONFIG = 0x%x\n", ptp_init_value.DCCONFIG);
689 ptp_isr_info("DCBDET = 0x%x\n", ptp_init_value.DCBDET);
690 ptp_isr_info("AGECONFIG = 0x%x\n", ptp_init_value.AGECONFIG);
691 ptp_isr_info("AGEM = 0x%x\n", ptp_init_value.AGEM);
692 ptp_isr_info("AGEDELTA = 0x%x\n", ptp_init_value.AGEDELTA);
693 ptp_isr_info("DVTFIXED = 0x%x\n", ptp_init_value.DVTFIXED);
694 ptp_isr_info("MTDES = 0x%x\n", ptp_init_value.MTDES);
695 ptp_isr_info("VCO = 0x%x\n", ptp_init_value.VCO);
696 ptp_isr_info("MTS = 0x%x\n", ptp_init_value.MTS);
697 ptp_isr_info("BTS = 0x%x\n", ptp_init_value.BTS);
698 ptp_isr_info("FREQPCT0 = %d\n", ptp_init_value.FREQPCT0);
699 ptp_isr_info("FREQPCT1 = %d\n", ptp_init_value.FREQPCT1);
700 ptp_isr_info("FREQPCT2 = %d\n", ptp_init_value.FREQPCT2);
701 ptp_isr_info("FREQPCT3 = %d\n", ptp_init_value.FREQPCT3);
702 ptp_isr_info("FREQPCT4 = %d\n", ptp_init_value.FREQPCT4);
703 ptp_isr_info("FREQPCT5 = %d\n", ptp_init_value.FREQPCT5);
704 ptp_isr_info("FREQPCT6 = %d\n", ptp_init_value.FREQPCT6);
705 ptp_isr_info("FREQPCT7 = %d\n", ptp_init_value.FREQPCT7);
706
707 PTP_Monitor_Mode(&ptp_init_value);
708
709 return 0;
710 }
711
712 static void PTP_set_ptp_volt(void)
713 {
714 #if SET_PMIC_VOLT
715
716 ktime_t ktime = ktime_set(mt_ptp_volt_period_s, mt_ptp_volt_period_ns);
717
718 ptp_array_size = 0;
719
720 if (freq_0 != 0)
721 {
722 ptpod_pmic_volt[0] = ptp_volt_0 + mt_ptp_offset;
723 if (ptpod_pmic_volt[0] > 0x60)
724 {
725 ptpod_pmic_volt[0] = 0x60;
726 }
727 else
728 {
729 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
730 if (ptpod_pmic_volt[0] < 0x38)
731 {
732 ptpod_pmic_volt[0] = 0x38;
733 }
734 #else
735 if (ptpod_pmic_volt[0] < 0x48)
736 {
737 ptpod_pmic_volt[0] = 0x48;
738 }
739 #endif
740 }
741 ptp_array_size++;
742 }
743
744 if (freq_1 != 0)
745 {
746 ptpod_pmic_volt[1] = ptp_volt_1 + mt_ptp_offset;
747 if (ptpod_pmic_volt[1] > 0x60)
748 {
749 ptpod_pmic_volt[1] = 0x60;
750 }
751 else
752 {
753 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
754 if (ptpod_pmic_volt[1] < 0x38)
755 {
756 ptpod_pmic_volt[1] = 0x38;
757 }
758 #else
759 if (ptpod_pmic_volt[1] < 0x48)
760 {
761 ptpod_pmic_volt[1] = 0x48;
762 }
763 #endif
764 }
765 ptp_array_size++;
766 }
767
768 if (freq_2 != 0)
769 {
770 ptpod_pmic_volt[2] = ptp_volt_2 + mt_ptp_offset;
771 if (ptpod_pmic_volt[2] > 0x60)
772 {
773 ptpod_pmic_volt[2] = 0x60;
774 }
775 else
776 {
777 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
778 if (ptpod_pmic_volt[2] < 0x38)
779 {
780 ptpod_pmic_volt[2] = 0x38;
781 }
782 #else
783 if (ptpod_pmic_volt[2] < 0x48)
784 {
785 ptpod_pmic_volt[2] = 0x48;
786 }
787 #endif
788 }
789 ptp_array_size++;
790 }
791
792 if (freq_3 != 0)
793 {
794 ptpod_pmic_volt[3] = ptp_volt_3 + mt_ptp_offset;
795 if (ptpod_pmic_volt[3] > 0x60)
796 {
797 ptpod_pmic_volt[3] = 0x60;
798 }
799 else
800 {
801 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
802 if (ptpod_pmic_volt[3] < 0x38)
803 {
804 ptpod_pmic_volt[3] = 0x38;
805 }
806 #else
807 if (ptpod_pmic_volt[3] < 0x48)
808 {
809 ptpod_pmic_volt[3] = 0x48;
810 }
811 #endif
812 }
813 ptp_array_size++;
814 }
815
816 if (freq_4 != 0)
817 {
818 ptpod_pmic_volt[4] = ptp_volt_4 + mt_ptp_offset;
819 if (ptpod_pmic_volt[4] > 0x60)
820 {
821 ptpod_pmic_volt[4] = 0x60;
822 }
823 else
824 {
825 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
826 if (ptpod_pmic_volt[4] < 0x38)
827 {
828 ptpod_pmic_volt[4] = 0x38;
829 }
830 #else
831 if (ptpod_pmic_volt[4] < 0x48)
832 {
833 ptpod_pmic_volt[4] = 0x48;
834 }
835 #endif
836 }
837 ptp_array_size++;
838 }
839
840 if (freq_5 != 0)
841 {
842 ptpod_pmic_volt[5] = ptp_volt_5 + mt_ptp_offset;
843 if (ptpod_pmic_volt[5] > 0x60)
844 {
845 ptpod_pmic_volt[5] = 0x60;
846 }
847 else
848 {
849 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
850 if (ptpod_pmic_volt[5] < 0x38)
851 {
852 ptpod_pmic_volt[5] = 0x38;
853 }
854 #else
855 if (ptpod_pmic_volt[5] < 0x48)
856 {
857 ptpod_pmic_volt[5] = 0x48;
858 }
859 #endif
860 }
861 ptp_array_size++;
862 }
863
864 if (freq_6 != 0)
865 {
866 ptpod_pmic_volt[6] = ptp_volt_6 + mt_ptp_offset;
867 if (ptpod_pmic_volt[6] > 0x60)
868 {
869 ptpod_pmic_volt[6] = 0x60;
870 }
871 else
872 {
873 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
874 if (ptpod_pmic_volt[6] < 0x38)
875 {
876 ptpod_pmic_volt[6] = 0x38;
877 }
878 #else
879 if (ptpod_pmic_volt[6] < 0x48)
880 {
881 ptpod_pmic_volt[6] = 0x48;
882 }
883 #endif
884 }
885 ptp_array_size++;
886 }
887
888 if (freq_7 != 0)
889 {
890 ptpod_pmic_volt[7] = ptp_volt_7 + mt_ptp_offset;
891 if (ptpod_pmic_volt[7] > 0x60)
892 {
893 ptpod_pmic_volt[7] = 0x60;
894 }
895 else
896 {
897 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
898 if (ptpod_pmic_volt[7] < 0x38)
899 {
900 ptpod_pmic_volt[7] = 0x38;
901 }
902 #else
903 if (ptpod_pmic_volt[7] < 0x48)
904 {
905 ptpod_pmic_volt[7] = 0x48;
906 }
907 #endif
908 }
909 ptp_array_size++;
910 }
911
912 hrtimer_start(&mt_ptp_volt_timer, ktime, HRTIMER_MODE_REL);
913
914 #endif
915 }
916
917 void mt_ptp_reg_dump(void)
918 {
919 ptp_isr_info("DUMP PTP_DESCHAR = 0x%x\n", DRV_Reg32(PTP_DESCHAR));
920 ptp_isr_info("DUMP PTP_TEMPCHAR = 0x%x\n", DRV_Reg32(PTP_TEMPCHAR));
921 ptp_isr_info("DUMP PTP_DETCHAR = 0x%x\n", DRV_Reg32(PTP_DETCHAR));
922 ptp_isr_info("DUMP PTP_AGECHAR = 0x%x\n", DRV_Reg32(PTP_AGECHAR));
923 ptp_isr_info("DUMP PTP_DCCONFIG = 0x%x\n", DRV_Reg32(PTP_DCCONFIG));
924 ptp_isr_info("DUMP PTP_AGECONFIG = 0x%x\n", DRV_Reg32(PTP_AGECONFIG));
925 ptp_isr_info("DUMP PTP_FREQPCT30 = 0x%x\n", DRV_Reg32(PTP_FREQPCT30));
926 ptp_isr_info("DUMP PTP_FREQPCT74 = 0x%x\n", DRV_Reg32(PTP_FREQPCT74));
927 ptp_isr_info("DUMP PTP_LIMITVALS = 0x%x\n", DRV_Reg32(PTP_LIMITVALS));
928 ptp_isr_info("DUMP PTP_VBOOT = 0x%x\n", DRV_Reg32(PTP_VBOOT));
929 ptp_isr_info("DUMP PTP_DETWINDOW = 0x%x\n", DRV_Reg32(PTP_DETWINDOW));
930 ptp_isr_info("DUMP PTP_PTPCONFIG = 0x%x\n", DRV_Reg32(PTP_PTPCONFIG));
931 ptp_isr_info("DUMP PTP_TSCALCS = 0x%x\n", DRV_Reg32(PTP_TSCALCS));
932 ptp_isr_info("DUMP PTP_RUNCONFIG = 0x%x\n", DRV_Reg32(PTP_RUNCONFIG));
933 ptp_isr_info("DUMP PTP_PTPEN = 0x%x\n", DRV_Reg32(PTP_PTPEN));
934 ptp_isr_info("DUMP PTP_INIT2VALS = 0x%x\n", DRV_Reg32(PTP_INIT2VALS));
935 ptp_isr_info("DUMP PTP_DCVALUES = 0x%x\n", DRV_Reg32(PTP_DCVALUES));
936 ptp_isr_info("DUMP PTP_AGEVALUES = 0x%x\n", DRV_Reg32(PTP_AGEVALUES));
937 ptp_isr_info("DUMP PTP_VOP30 = 0x%x\n", DRV_Reg32(PTP_VOP30));
938 ptp_isr_info("DUMP PTP_VOP74 = 0x%x\n", DRV_Reg32(PTP_VOP74));
939 ptp_isr_info("DUMP PTP_TEMP = 0x%x\n", DRV_Reg32(PTP_TEMP));
940 ptp_isr_info("DUMP PTP_PTPINTSTS = 0x%x\n", DRV_Reg32(PTP_PTPINTSTS));
941 ptp_isr_info("DUMP PTP_PTPINTSTSRAW = 0x%x\n", DRV_Reg32(PTP_PTPINTSTSRAW));
942 ptp_isr_info("DUMP PTP_PTPINTEN = 0x%x\n", DRV_Reg32(PTP_PTPINTEN));
943 ptp_isr_info("DUMP PTP_SMSTATE0 = 0x%x\n", DRV_Reg32(PTP_SMSTATE0));
944 ptp_isr_info("DUMP PTP_SMSTATE1 = 0x%x\n", DRV_Reg32(PTP_SMSTATE1));
945
946 ptp_isr_info("DUMP PTP_TEMPMONCTL0 = 0x%x\n", DRV_Reg32(PTP_TEMPMONCTL0));
947 ptp_isr_info("DUMP PTP_TEMPMONCTL1 = 0x%x\n", DRV_Reg32(PTP_TEMPMONCTL1));
948 ptp_isr_info("DUMP PTP_TEMPMONCTL2 = 0x%x\n", DRV_Reg32(PTP_TEMPMONCTL2));
949 ptp_isr_info("DUMP PTP_TEMPMONINT = 0x%x\n", DRV_Reg32(PTP_TEMPMONINT));
950 ptp_isr_info("DUMP PTP_TEMPMONINTSTS = 0x%x\n", DRV_Reg32(PTP_TEMPMONINTSTS));
951 ptp_isr_info("DUMP PTP_TEMPMONIDET0 = 0x%x\n", DRV_Reg32(PTP_TEMPMONIDET0));
952 ptp_isr_info("DUMP PTP_TEMPMONIDET1 = 0x%x\n", DRV_Reg32(PTP_TEMPMONIDET1));
953 ptp_isr_info("DUMP PTP_TEMPMONIDET2 = 0x%x\n", DRV_Reg32(PTP_TEMPMONIDET2));
954 ptp_isr_info("DUMP PTP_TEMPH2NTHRE = 0x%x\n", DRV_Reg32(PTP_TEMPH2NTHRE));
955 ptp_isr_info("DUMP PTP_TEMPHTHRE = 0x%x\n", DRV_Reg32(PTP_TEMPHTHRE));
956 ptp_isr_info("DUMP PTP_TEMPCTHRE = 0x%x\n", DRV_Reg32(PTP_TEMPCTHRE));
957 ptp_isr_info("DUMP PTP_TEMPOFFSETH = 0x%x\n", DRV_Reg32(PTP_TEMPOFFSETH));
958 ptp_isr_info("DUMP PTP_TEMPOFFSETL = 0x%x\n", DRV_Reg32(PTP_TEMPOFFSETL));
959 ptp_isr_info("DUMP PTP_TEMPMSRCTL0 = 0x%x\n", DRV_Reg32(PTP_TEMPMSRCTL0));
960 ptp_isr_info("DUMP PTP_TEMPMSRCTL1 = 0x%x\n", DRV_Reg32(PTP_TEMPMSRCTL1));
961 ptp_isr_info("DUMP PTP_TEMPAHBPOLL = 0x%x\n", DRV_Reg32(PTP_TEMPAHBPOLL));
962 ptp_isr_info("DUMP PTP_TEMPAHBTO = 0x%x\n", DRV_Reg32(PTP_TEMPAHBTO));
963 ptp_isr_info("DUMP PTP_TEMPADCPNP0 = 0x%x\n", DRV_Reg32(PTP_TEMPADCPNP0));
964 ptp_isr_info("DUMP PTP_TEMPADCPNP1 = 0x%x\n", DRV_Reg32(PTP_TEMPADCPNP1));
965 ptp_isr_info("DUMP PTP_TEMPADCPNP2 = 0x%x\n", DRV_Reg32(PTP_TEMPADCPNP2));
966 ptp_isr_info("DUMP PTP_TEMPADCMUX = 0x%x\n", DRV_Reg32(PTP_TEMPADCMUX));
967 ptp_isr_info("DUMP PTP_TEMPADCEXT = 0x%x\n", DRV_Reg32(PTP_TEMPADCEXT));
968 ptp_isr_info("DUMP PTP_TEMPADCEXT1 = 0x%x\n", DRV_Reg32(PTP_TEMPADCEXT1));
969 ptp_isr_info("DUMP PTP_TEMPADCEN = 0x%x\n", DRV_Reg32(PTP_TEMPADCEN));
970 ptp_isr_info("DUMP PTP_TEMPPNPMUXADDR = 0x%x\n", DRV_Reg32(PTP_TEMPPNPMUXADDR));
971 ptp_isr_info("DUMP PTP_TEMPADCMUXADDR = 0x%x\n", DRV_Reg32(PTP_TEMPADCMUXADDR));
972 ptp_isr_info("DUMP PTP_TEMPADCEXTADDR = 0x%x\n", DRV_Reg32(PTP_TEMPADCEXTADDR));
973 ptp_isr_info("DUMP PTP_TEMPADCEXT1ADDR = 0x%x\n", DRV_Reg32(PTP_TEMPADCEXT1ADDR));
974 ptp_isr_info("DUMP PTP_TEMPADCENADDR = 0x%x\n", DRV_Reg32(PTP_TEMPADCENADDR));
975 ptp_isr_info("DUMP PTP_TEMPADCVALIDADDR = 0x%x\n", DRV_Reg32(PTP_TEMPADCVALIDADDR));
976 ptp_isr_info("DUMP PTP_TEMPADCVOLTADDR = 0x%x\n", DRV_Reg32(PTP_TEMPADCVOLTADDR));
977 ptp_isr_info("DUMP PTP_TEMPRDCTRL = 0x%x\n", DRV_Reg32(PTP_TEMPRDCTRL));
978 ptp_isr_info("DUMP PTP_TEMPADCVALIDMASK = 0x%x\n", DRV_Reg32(PTP_TEMPADCVALIDMASK));
979 ptp_isr_info("DUMP PTP_TEMPADCVOLTAGESHIFT = 0x%x\n", DRV_Reg32(PTP_TEMPADCVOLTAGESHIFT));
980 ptp_isr_info("DUMP PTP_TEMPADCWRITECTRL = 0x%x\n", DRV_Reg32(PTP_TEMPADCWRITECTRL));
981 ptp_isr_info("DUMP PTP_TEMPMSR0 = 0x%x\n", DRV_Reg32(PTP_TEMPMSR0));
982 ptp_isr_info("DUMP PTP_TEMPMSR1 = 0x%x\n", DRV_Reg32(PTP_TEMPMSR1));
983 ptp_isr_info("DUMP PTP_TEMPMSR2 = 0x%x\n", DRV_Reg32(PTP_TEMPMSR2));
984 ptp_isr_info("DUMP PTP_TEMPIMMD0 = 0x%x\n", DRV_Reg32(PTP_TEMPIMMD0));
985 ptp_isr_info("DUMP PTP_TEMPIMMD1 = 0x%x\n", DRV_Reg32(PTP_TEMPIMMD1));
986 ptp_isr_info("DUMP PTP_TEMPIMMD2 = 0x%x\n", DRV_Reg32(PTP_TEMPIMMD2));
987 ptp_isr_info("DUMP PTP_TEMPPROTCTL = 0x%x\n", DRV_Reg32(PTP_TEMPPROTCTL));
988 ptp_isr_info("DUMP PTP_TEMPPROTTA = 0x%x\n", DRV_Reg32(PTP_TEMPPROTTA));
989 ptp_isr_info("DUMP PTP_TEMPPROTTB = 0x%x\n", DRV_Reg32(PTP_TEMPPROTTB));
990 ptp_isr_info("DUMP PTP_TEMPPROTTC = 0x%x\n", DRV_Reg32(PTP_TEMPPROTTC));
991 ptp_isr_info("DUMP PTP_TEMPSPARE0 = 0x%x\n", DRV_Reg32(PTP_TEMPSPARE0));
992 }
993
994 irqreturn_t mt_ptp_isr(int irq, void *dev_id)
995 {
996 unsigned int PTPINTSTS, temp, temp_0, temp_ptpen;
997
998 #if 0
999 mt_ptp_reg_dump();
1000 #endif
1001
1002 PTPINTSTS = ptp_read(PTP_PTPINTSTS);
1003 temp_ptpen = ptp_read(PTP_PTPEN);
1004
1005 ptp_isr_info("PTPINTSTS = 0x%x\n", PTPINTSTS);
1006 ptp_isr_info("PTP_PTPEN = 0x%x\n", temp_ptpen);
1007
1008 ptp_data[1] = ptp_read(0xf100b240);
1009 ptp_data[2] = ptp_read(0xf100b27c);
1010
1011 ptp_isr_info("*(0x1100b240) = 0x%x\n", ptp_data[1]);
1012 ptp_isr_info("*(0x1100b27c) = 0x%x\n", ptp_data[2]);
1013
1014 ptp_data[0] = 0;
1015
1016 if (PTPINTSTS == 0x1) // PTP init1 or init2
1017 {
1018 if ((temp_ptpen & 0x7) == 0x1) // PTP init1
1019 {
1020 // Read & store 16 bit values DCVALUES.DCVOFFSET and AGEVALUES.AGEVOFFSET for later use in INIT2 procedure
1021 ptp_dcvoffset = ~(ptp_read(PTP_DCVALUES) & 0xffff) + 1; // hw bug, workaround
1022 ptp_agevoffset = ptp_read(PTP_AGEVALUES) & 0xffff;
1023
1024 // Set PTPEN.PTPINITEN/PTPEN.PTPINIT2EN = 0x0 & Clear PTP INIT interrupt PTPINTSTS = 0x00000001
1025 ptp_write(PTP_PTPEN, 0x0);
1026 ptp_write(PTP_PTPINTSTS, 0x1);
1027
1028 mt_cpufreq_enable_by_ptpod(); // enable DVFS
1029 mt_fh_popod_restore(); // enable frequency hopping (main PLL)
1030
1031 PTP_INIT_02();
1032 }
1033 else if ((temp_ptpen & 0x7) == 0x5) // PTP init2
1034 {
1035 temp = ptp_read(PTP_VOP30); // read ptp_volt_0 ~ ptp_volt_3
1036 ptp_volt_0 = temp & 0xff;
1037 ptp_volt_1 = (temp>>8) & 0xff;
1038 ptp_volt_2 = (temp>>16) & 0xff;
1039 ptp_volt_3 = (temp>>24) & 0xff;
1040
1041 temp = ptp_read(PTP_VOP74); // read ptp_volt_4 ~ ptp_volt_7
1042 ptp_volt_4 = temp & 0xff;
1043 ptp_volt_5 = (temp>>8) & 0xff;
1044 ptp_volt_6 = (temp>>16) & 0xff;
1045 ptp_volt_7 = (temp>>24) & 0xff;
1046
1047 // save ptp_init2_volt_0 ~ ptp_init2_volt_7
1048 ptp_init2_volt_0 = ptp_volt_0;
1049 ptp_init2_volt_1 = ptp_volt_1;
1050 ptp_init2_volt_2 = ptp_volt_2;
1051 ptp_init2_volt_3 = ptp_volt_3;
1052 ptp_init2_volt_4 = ptp_volt_4;
1053 ptp_init2_volt_5 = ptp_volt_5;
1054 ptp_init2_volt_6 = ptp_volt_6;
1055 ptp_init2_volt_7 = ptp_volt_7;
1056
1057 ptp_isr_info("ptp_volt_0 = 0x%x\n", ptp_volt_0);
1058 ptp_isr_info("ptp_volt_1 = 0x%x\n", ptp_volt_1);
1059 ptp_isr_info("ptp_volt_2 = 0x%x\n", ptp_volt_2);
1060 ptp_isr_info("ptp_volt_3 = 0x%x\n", ptp_volt_3);
1061 ptp_isr_info("ptp_volt_4 = 0x%x\n", ptp_volt_4);
1062 ptp_isr_info("ptp_volt_5 = 0x%x\n", ptp_volt_5);
1063 ptp_isr_info("ptp_volt_6 = 0x%x\n", ptp_volt_6);
1064 ptp_isr_info("ptp_volt_7 = 0x%x\n", ptp_volt_7);
1065 ptp_isr_info("ptp_level = 0x%x\n", ptp_level);
1066
1067 PTP_set_ptp_volt();
1068
1069 // Set PTPEN.PTPINITEN/PTPEN.PTPINIT2EN = 0x0 & Clear PTP INIT interrupt PTPINTSTS = 0x00000001
1070 ptp_write(PTP_PTPEN, 0x0);
1071 ptp_write(PTP_PTPINTSTS, 0x1);
1072 PTP_MON_MODE();
1073 }
1074 else // error : init1 or init2 , but enable setting is wrong.
1075 {
1076 ptp_isr_info("====================================================\n");
1077 ptp_isr_info("PTP error_0 (0x%x) : PTPINTSTS = 0x%x\n", temp_ptpen, PTPINTSTS);
1078 ptp_isr_info("PTP_SMSTATE0 (0x%x) = 0x%x\n", PTP_SMSTATE0, ptp_read(PTP_SMSTATE0));
1079 ptp_isr_info("PTP_SMSTATE1 (0x%x) = 0x%x\n", PTP_SMSTATE1, ptp_read(PTP_SMSTATE1));
1080 ptp_isr_info("====================================================\n");
1081
1082 // disable PTP
1083 ptp_write(PTP_PTPEN, 0x0);
1084
1085 // Clear PTP interrupt PTPINTSTS
1086 ptp_write(PTP_PTPINTSTS, 0x00ffffff);
1087
1088 // restore default DVFS table (PMIC)
1089 mt_cpufreq_return_default_DVS_by_ptpod();
1090 }
1091 }
1092 else if ((PTPINTSTS & 0x00ff0000) != 0x0) // PTP Monitor mode
1093 {
1094 // check if thermal sensor init completed?
1095 temp_0 = (ptp_read(PTP_TEMP) & 0xff);
1096
1097 if ((temp_0 > 0x4b) && (temp_0 < 0xd3))
1098 {
1099 ptp_isr_info("thermal sensor init has not been completed. (temp_0 = 0x%x)\n", temp_0);
1100 }
1101 else
1102 {
1103 temp = ptp_read(PTP_VOP30); // read ptp_volt_0 ~ ptp_volt_3
1104 ptp_volt_0 = temp & 0xff;
1105 ptp_volt_1 = (temp>>8) & 0xff;
1106 ptp_volt_2 = (temp>>16) & 0xff;
1107 ptp_volt_3 = (temp>>24) & 0xff;
1108
1109 temp = ptp_read(PTP_VOP74); // read ptp_volt_3 ~ ptp_volt_7
1110 ptp_volt_4 = temp & 0xff;
1111 ptp_volt_5 = (temp>>8) & 0xff;
1112 ptp_volt_6 = (temp>>16) & 0xff;
1113 ptp_volt_7 = (temp>>24) & 0xff;
1114
1115 ptp_isr_info("ptp_volt_0 = 0x%x\n", ptp_volt_0);
1116 ptp_isr_info("ptp_volt_1 = 0x%x\n", ptp_volt_1);
1117 ptp_isr_info("ptp_volt_2 = 0x%x\n", ptp_volt_2);
1118 ptp_isr_info("ptp_volt_3 = 0x%x\n", ptp_volt_3);
1119 ptp_isr_info("ptp_volt_4 = 0x%x\n", ptp_volt_4);
1120 ptp_isr_info("ptp_volt_5 = 0x%x\n", ptp_volt_5);
1121 ptp_isr_info("ptp_volt_6 = 0x%x\n", ptp_volt_6);
1122 ptp_isr_info("ptp_volt_7 = 0x%x\n", ptp_volt_7);
1123 ptp_isr_info("ptp_level = 0x%x\n", ptp_level);
1124 ptp_isr_info("ISR : TEMPSPARE1 = 0x%x\n", ptp_read(TEMPSPARE1));
1125
1126 PTP_set_ptp_volt();
1127 }
1128
1129 // Clear PTP INIT interrupt PTPINTSTS = 0x00ff0000
1130 ptp_write(PTP_PTPINTSTS, 0x00ff0000);
1131 }
1132 else // PTP error handler
1133 {
1134 if (((temp_ptpen & 0x7) == 0x1) || ((temp_ptpen & 0x7) == 0x5)) // init 1 || init 2 error handler
1135 {
1136 ptp_isr_info("====================================================\n");
1137 ptp_isr_info("PTP error_1 error_2 (0x%x) : PTPINTSTS = 0x%x\n", temp_ptpen, PTPINTSTS);
1138 ptp_isr_info("PTP_SMSTATE0 (0x%x) = 0x%x\n", PTP_SMSTATE0, ptp_read(PTP_SMSTATE0));
1139 ptp_isr_info("PTP_SMSTATE1 (0x%x) = 0x%x\n", PTP_SMSTATE1, ptp_read(PTP_SMSTATE1));
1140 ptp_isr_info("====================================================\n");
1141
1142 // disable PTP
1143 ptp_write(PTP_PTPEN, 0x0);
1144
1145 // Clear PTP interrupt PTPINTSTS
1146 ptp_write(PTP_PTPINTSTS, 0x00ffffff);
1147
1148 // restore default DVFS table (PMIC)
1149 mt_cpufreq_return_default_DVS_by_ptpod();
1150 }
1151 else // PTP Monitor mode error handler
1152 {
1153 ptp_isr_info("====================================================\n");
1154 ptp_isr_info("PTP error_m (0x%x) : PTPINTSTS = 0x%x\n", temp_ptpen, PTPINTSTS);
1155 ptp_isr_info("PTP_SMSTATE0 (0x%x) = 0x%x\n", PTP_SMSTATE0, ptp_read(PTP_SMSTATE0));
1156 ptp_isr_info("PTP_SMSTATE1 (0x%x) = 0x%x\n", PTP_SMSTATE1, ptp_read(PTP_SMSTATE1));
1157 ptp_isr_info("PTP_TEMP (0x%x) = 0x%x\n", PTP_TEMP, ptp_read(PTP_TEMP) );
1158 ptp_isr_info("PTP_TEMPMSR0 (0x%x) = 0x%x\n", PTP_TEMPMSR0, ptp_read(PTP_TEMPMSR0));
1159 ptp_isr_info("PTP_TEMPMSR1 (0x%x) = 0x%x\n", PTP_TEMPMSR1, ptp_read(PTP_TEMPMSR1));
1160 ptp_isr_info("PTP_TEMPMSR2 (0x%x) = 0x%x\n", PTP_TEMPMSR2, ptp_read(PTP_TEMPMSR2));
1161 ptp_isr_info("PTP_TEMPMONCTL0 (0x%x) = 0x%x\n", PTP_TEMPMONCTL0, ptp_read(PTP_TEMPMONCTL0));
1162 ptp_isr_info("PTP_TEMPMSRCTL1 (0x%x) = 0x%x\n", PTP_TEMPMSRCTL1, ptp_read(PTP_TEMPMSRCTL1));
1163 ptp_isr_info("====================================================\n");
1164
1165 // disable PTP
1166 ptp_write(PTP_PTPEN, 0x0);
1167
1168 // Clear PTP interrupt PTPINTSTS
1169 ptp_write(PTP_PTPINTSTS, 0x00ffffff);
1170
1171 // set init2 value to DVFS table (PMIC)
1172 ptp_volt_0 = ptp_init2_volt_0;
1173 ptp_volt_1 = ptp_init2_volt_1;
1174 ptp_volt_2 = ptp_init2_volt_2;
1175 ptp_volt_3 = ptp_init2_volt_3;
1176 ptp_volt_4 = ptp_init2_volt_4;
1177 ptp_volt_5 = ptp_init2_volt_5;
1178 ptp_volt_6 = ptp_init2_volt_6;
1179 ptp_volt_7 = ptp_init2_volt_7;
1180 PTP_set_ptp_volt();
1181 }
1182 }
1183
1184 return IRQ_HANDLED;
1185 }
1186
1187 unsigned int PTP_INIT_01_API(void)
1188 {
1189 /* only for CPU stress */
1190
1191 PTP_INIT_T ptp_init_value;
1192
1193 unsigned int ptp_counter = 0;
1194
1195 ptp_notice("PTP_INIT_01_API() start.\n");
1196
1197 ptp_data[0] = 0xffffffff;
1198 ptp_data[1] = 0xffffffff;
1199 ptp_data[2] = 0xffffffff;
1200
1201 // disable PTP
1202 ptp_write(PTP_PTPEN, 0x0);
1203
1204 ptp_init_value.PTPINITEN = (val_0) & 0x1;
1205 ptp_init_value.PTPMONEN = (val_0 >> 1) & 0x1;
1206 ptp_init_value.MDES = (val_0 >> 8) & 0xff;
1207 ptp_init_value.BDES = (val_0 >> 16) & 0xff;
1208 ptp_init_value.DCMDET = (val_0 >> 24) & 0xff;
1209
1210 ptp_init_value.DCCONFIG = (val_1) & 0xffffff;
1211 ptp_init_value.DCBDET = (val_1 >> 24) & 0xff;
1212
1213 ptp_init_value.AGECONFIG = (val_2) & 0xffffff;
1214 ptp_init_value.AGEM = (val_2 >> 24) & 0xff;
1215
1216 //ptp_init_value.AGEDELTA = (val_3) & 0xff;
1217 ptp_init_value.AGEDELTA = 0x88;
1218 ptp_init_value.DVTFIXED = (val_3 >> 8) & 0xff;
1219 ptp_init_value.MTDES = (val_3 >> 16) & 0xff;
1220 ptp_init_value.VCO = (val_3 >> 24) & 0xff;
1221
1222 // Get DVFS frequency table
1223 freq_0 = (u8)(mt_cpufreq_max_frequency_by_DVS(0) / 13000); // max freq 1300 x 100%
1224 freq_1 = (u8)(mt_cpufreq_max_frequency_by_DVS(1) / 13000);
1225 freq_2 = (u8)(mt_cpufreq_max_frequency_by_DVS(2) / 13000);
1226 freq_3 = (u8)(mt_cpufreq_max_frequency_by_DVS(3) / 13000);
1227 freq_4 = (u8)(mt_cpufreq_max_frequency_by_DVS(4) / 13000);
1228 freq_5 = (u8)(mt_cpufreq_max_frequency_by_DVS(5) / 13000);
1229 freq_6 = (u8)(mt_cpufreq_max_frequency_by_DVS(6) / 13000);
1230 freq_7 = (u8)(mt_cpufreq_max_frequency_by_DVS(7) / 13000);
1231
1232 ptp_init_value.FREQPCT0 = freq_0;
1233 ptp_init_value.FREQPCT1 = freq_1;
1234 ptp_init_value.FREQPCT2 = freq_2;
1235 ptp_init_value.FREQPCT3 = freq_3;
1236 ptp_init_value.FREQPCT4 = freq_4;
1237 ptp_init_value.FREQPCT5 = freq_5;
1238 ptp_init_value.FREQPCT6 = freq_6;
1239 ptp_init_value.FREQPCT7 = freq_7;
1240
1241 ptp_init_value.DETWINDOW = 0xa28; // 100 us, This is the PTP Detector sampling time as represented in cycles of bclk_ck during INIT. 52 MHz
1242 ptp_init_value.VMAX = 0x60; // 1.3v (700mv + n * 6.25mv)
1243
1244 #if (defined(IS_VCORE_USE_6333VCORE) || defined(CONFIG_MTK_PMIC_MT6397)) && !defined(MTK_DVFS_DISABLE_LOW_VOLTAGE_SUPPORT)
1245 ptp_init_value.VMIN = 0x38; // 1.05v (700mv + n * 6.25mv)
1246 #else
1247 ptp_init_value.VMIN = 0x48; // 1.15v (700mv + n * 6.25mv)
1248 #endif
1249
1250 ptp_init_value.DTHI = 0x01; // positive
1251 ptp_init_value.DTLO = 0xfe; // negative (2¡¦s compliment)
1252 ptp_init_value.VBOOT = 0x48; // 1.15v (700mv + n * 6.25mv)
1253 ptp_init_value.DETMAX = 0xffff; // This timeout value is in cycles of bclk_ck.
1254
1255 if (ptp_init_value.PTPINITEN == 0x0)
1256 {
1257 ptp_notice("PTPINITEN = 0x%x \n", ptp_init_value.PTPINITEN);
1258 ptp_data[0] = 0;
1259 return 0;
1260 }
1261
1262 #if 0
1263 // set PTP IRQ
1264 ret = request_irq(MT_PTP_FSM_IRQ_ID, mt_ptp_isr, IRQF_TRIGGER_LOW, "ptp", NULL);
1265 if (ret)
1266 {
1267 ptp_notice("PTP IRQ register failed (%d)\n", ret);
1268 WARN_ON(1);
1269 }
1270 ptp_notice("Set PTP IRQ OK.\n");
1271 #endif
1272
1273 PTP_Initialization_01(&ptp_init_value);
1274
1275 while(1)
1276 {
1277 ptp_counter++;
1278
1279 if (ptp_counter >= 0xffffff)
1280 {
1281 ptp_notice("ptp_counter = 0x%x \n", ptp_counter);
1282 return 0;
1283 }
1284
1285 if (ptp_data[0] == 0)
1286 {
1287 break;
1288 }
1289 }
1290
1291 return ((unsigned int)(&ptp_data[1]));
1292 }
1293
1294 #if EN_PTP_OD
1295 static int ptp_probe(struct platform_device *pdev)
1296 {
1297 int ret;
1298 u32 rdata = 0, test_mode = 0;
1299
1300 if (pwrap_read((u32)RTC_AL_DOM, &rdata) == 0)
1301 {
1302 rdata = (rdata >> 8) & 0x7;
1303 ptp_notice("rdata = 0x%x \n", rdata);
1304
1305 /* don't care */
1306 test_mode = 0;
1307 }
1308
1309 #if PTP_GET_REAL_VAL
1310 if (!test_mode)
1311 {
1312 val_0 = get_devinfo_with_index(16);
1313 val_1 = get_devinfo_with_index(17);
1314 val_2 = get_devinfo_with_index(18);
1315 val_3 = get_devinfo_with_index(19);
1316 }
1317 #endif
1318
1319 if ((val_0 & 0x1) == 0x0)
1320 {
1321 ptp_notice("PTPINITEN = 0x%x \n", (val_0 & 0x1));
1322 return 0;
1323 }
1324
1325 // enable thermal CG
1326 enable_clock(MT_CG_PERI_THERM, "PTPOD");
1327
1328 // set PTP IRQ
1329 ret = request_irq(MT_PTP_FSM_IRQ_ID, mt_ptp_isr, IRQF_TRIGGER_LOW, "ptp", NULL);
1330 if (ret)
1331 {
1332 ptp_notice("PTP IRQ register failed (%d)\n", ret);
1333 WARN_ON(1);
1334 }
1335
1336 ptp_notice("Set PTP IRQ OK.\n");
1337
1338 // get DVFS frequency table
1339 freq_0 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(0) / 13000); // max freq 1300 x 100%
1340 if (freq_0 != 0)
1341 freq_0 += 1;
1342
1343 freq_1 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(1) / 13000);
1344 if (freq_1 != 0)
1345 freq_1 += 1;
1346
1347 freq_2 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(2) / 13000);
1348 if (freq_2 != 0)
1349 freq_2 += 1;
1350
1351 freq_3 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(3) / 13000);
1352 if (freq_3 != 0)
1353 freq_3 += 1;
1354
1355 freq_4 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(4) / 13000);
1356 if (freq_4 != 0)
1357 freq_4 += 1;
1358
1359 freq_5 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(5) / 13000);
1360 if (freq_5 != 0)
1361 freq_5 += 1;
1362
1363 freq_6 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(6) / 13000);
1364 if (freq_6 != 0)
1365 freq_6 += 1;
1366
1367 freq_7 = (unsigned char)(mt_cpufreq_max_frequency_by_DVS(7) / 13000);
1368 if (freq_7 != 0)
1369 freq_7 += 1;
1370
1371 ptp_level = PTP_get_ptp_level();
1372
1373 mt_ptp_volt_thread = kthread_run(mt_ptp_volt_thread_handler, 0, "ptp volt");
1374 if (IS_ERR(mt_ptp_volt_thread))
1375 {
1376 printk("[%s]: failed to create ptp volt thread\n", __FUNCTION__);
1377 }
1378
1379 PTP_INIT_01();
1380
1381 return 0;
1382 }
1383
1384 static int ptp_suspend(struct platform_device *dev, pm_message_t state)
1385 {
1386 /*
1387 kthread_stop(mt_ptp_volt_thread);
1388 */
1389
1390 return 0;
1391 }
1392
1393 static int ptp_resume(struct platform_device *pdev)
1394 {
1395 /*
1396 mt_ptp_volt_thread = kthread_run(mt_ptp_volt_thread_handler, 0, "ptp volt");
1397 if (IS_ERR(mt_ptp_volt_thread))
1398 {
1399 printk("[%s]: failed to create ptp volt thread\n", __FUNCTION__);
1400 }
1401 */
1402
1403 if(mt_ptp_enable)
1404 {
1405 if((val_0 & 0x1) == 0x0)
1406 {
1407 ptp_notice("PTPINITEN = 0x%x \n", (val_0 & 0x1));
1408 ptp_data[0] = 0;
1409 return 0;
1410 }
1411 PTP_INIT_02();
1412 }
1413 return 0;
1414 }
1415
1416 static struct platform_driver ptp_driver = {
1417 .remove = NULL,
1418 .shutdown = NULL,
1419 .probe = ptp_probe,
1420 .suspend = ptp_suspend,
1421 .resume = ptp_resume,
1422 .driver = {
1423 .name = "mt-ptp",
1424 },
1425 };
1426
1427 int ptp_opp_num(void)
1428 {
1429 int num = 0;
1430
1431 while (1)
1432 {
1433 if (mt_cpufreq_max_frequency_by_DVS(num) == 0)
1434 break;
1435 num++;
1436 }
1437
1438 return num;
1439 }
1440 EXPORT_SYMBOL(ptp_opp_num);
1441
1442 void ptp_opp_freq(unsigned int *freq)
1443 {
1444 int i = 0;
1445
1446 while (1)
1447 {
1448 if (mt_cpufreq_max_frequency_by_DVS(i) == 0)
1449 break;
1450 freq[i] = mt_cpufreq_max_frequency_by_DVS(i);
1451 i++;
1452 }
1453 }
1454 EXPORT_SYMBOL(ptp_opp_freq);
1455
1456 void ptp_opp_status(unsigned int *temp, unsigned int *volt)
1457 {
1458 int i = 0;
1459
1460 *temp = mtktscpu_get_cpu_temp();
1461
1462 while (1)
1463 {
1464 if (mt_cpufreq_max_frequency_by_DVS(i) == 0)
1465 break;
1466 volt[i] = ptp_trasnfer_to_volt(ptpod_pmic_volt[i]);
1467 i++;
1468 }
1469 }
1470 EXPORT_SYMBOL(ptp_opp_status);
1471
1472 void ptp_disable(void)
1473 {
1474 unsigned long flags;
1475
1476 // Mask ARM i bit
1477 local_irq_save(flags);
1478
1479 // disable PTP
1480 ptp_write(PTP_PTPEN, 0x0);
1481
1482 // Clear PTP interrupt PTPINTSTS
1483 ptp_write(PTP_PTPINTSTS, 0x00ffffff);
1484
1485 // restore default DVFS table (PMIC)
1486 mt_cpufreq_return_default_DVS_by_ptpod();
1487
1488 mt_ptp_enable = 0;
1489
1490 ptp_notice("Disable PTP-OD done.\n");
1491
1492 // Un-Mask ARM i bit
1493 local_irq_restore(flags);
1494 }
1495
1496 /***************************
1497 * return current PTP stauts
1498 ****************************/
1499 int ptp_status(void)
1500 {
1501 int ret = 0;
1502
1503 if (ptp_read(PTP_PTPEN) != 0)
1504 ret = 1;
1505 else
1506 ret = 0;
1507
1508 return ret;
1509 }
1510
1511 /***************************
1512 * show current PTP offset
1513 ****************************/
1514 static ssize_t ptp_offset_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
1515 {
1516 int len = 0;
1517 char *p = buf;
1518
1519 p += sprintf(p, "mt_ptp_offset = %d\n", mt_ptp_offset);
1520
1521 len = p - buf;
1522 return len;
1523 }
1524
1525 /************************************
1526 * set PTP offset by sysfs interface
1527 *************************************/
1528 static ssize_t ptp_offset_store(struct kobject *kobj,
1529 struct kobj_attribute *attr, const char *buf, size_t n)
1530 {
1531 int offset = 0;
1532
1533 if (sscanf(buf, "%d", &offset) == 1)
1534 {
1535 mt_ptp_offset = offset;
1536 PTP_set_ptp_volt();
1537 }
1538 else
1539 {
1540 ptp_notice("bad argument_1!! argument should be \"0\"\n");
1541 }
1542
1543 return n;
1544 }
1545
1546 ptp_attr(ptp_offset);
1547
1548 /***************************
1549 * show current PTP status
1550 ****************************/
1551 static ssize_t ptp_debug_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
1552 {
1553 int len = 0;
1554 char *p = buf;
1555
1556 if (ptp_read(PTP_PTPEN) != 0)
1557 p += sprintf(p, "PTP enabled (ptp_level = 0x%x)\n", ptp_level);
1558 else
1559 p += sprintf(p, "PTP disabled (ptp_level = 0x%x)\n", ptp_level);
1560
1561 len = p - buf;
1562 return len;
1563 }
1564
1565 /************************************
1566 * set PTP stauts by sysfs interface
1567 *************************************/
1568 static ssize_t ptp_debug_store(struct kobject *kobj,
1569 struct kobj_attribute *attr, const char *buf, size_t n)
1570 {
1571 int enabled = 0;
1572
1573 if (sscanf(buf, "%d", &enabled) == 1)
1574 {
1575 if (enabled == 0)
1576 {
1577 ptp_disable(); // Disable PTP and restore default DVFS table (PMIC)
1578 }
1579 else
1580 {
1581 ptp_notice("bad argument_0!! argument should be \"0\"\n");
1582 }
1583 }
1584 else
1585 {
1586 ptp_notice("bad argument_1!! argument should be \"0\"\n");
1587 }
1588
1589 return n;
1590 }
1591
1592 ptp_attr(ptp_debug);
1593
1594 /***************************
1595 * show current PTP data
1596 ****************************/
1597 static ssize_t ptp_dump_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
1598 {
1599 int len = 0;
1600 char *p = buf;
1601
1602 p += sprintf(p, "(0x%x, 0x%x, 0x%x, 0x%x)\n", val_0, val_1, val_2, val_3);
1603
1604 len = p - buf;
1605 return len;
1606 }
1607
1608 /************************************
1609 * set PTP data by sysfs interface
1610 *************************************/
1611 static ssize_t ptp_dump_store(struct kobject *kobj,
1612 struct kobj_attribute *attr, const char *buf, size_t n)
1613 {
1614 return n;
1615 }
1616
1617 ptp_attr(ptp_dump);
1618
1619 /***********************
1620 * show current voltage
1621 ************************/
1622 static ssize_t ptp_cur_volt_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
1623 {
1624 int len = 0;
1625 char *p = buf;
1626 u32 rdata = 0;
1627
1628 // rdata = mt_cpufreq_cur_vproc(); //mask till dvfs driver ready
1629
1630 if (rdata != 0)
1631 {
1632 p += sprintf(p, "current voltage: (%d)\n", rdata);
1633 }
1634 else
1635 {
1636 p += sprintf(p, "read current voltage fail\n");
1637 }
1638
1639 len = p - buf;
1640 return len;
1641 }
1642
1643 /************************************
1644 * set current voltage by sysfs interface
1645 *************************************/
1646 static ssize_t ptp_cur_volt_store(struct kobject *kobj,
1647 struct kobj_attribute *attr, const char *buf, size_t n)
1648 {
1649 return n;
1650 }
1651
1652 ptp_attr(ptp_cur_volt);
1653
1654 /**************************
1655 * show current PTP status
1656 ***************************/
1657 static ssize_t ptp_status_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
1658 {
1659 int len = 0;
1660 char *p = buf;
1661
1662 p += sprintf(p, "PTP_LOG: (%d) - (%d, %d, %d, %d, %d, %d, %d, %d) - (%d, %d, %d, %d, %d, %d, %d, %d)\n", \
1663 mtktscpu_get_cpu_temp(), \
1664 ptp_trasnfer_to_volt(ptpod_pmic_volt[0]), \
1665 ptp_trasnfer_to_volt(ptpod_pmic_volt[1]), \
1666 ptp_trasnfer_to_volt(ptpod_pmic_volt[2]), \
1667 ptp_trasnfer_to_volt(ptpod_pmic_volt[3]), \
1668 ptp_trasnfer_to_volt(ptpod_pmic_volt[4]), \
1669 ptp_trasnfer_to_volt(ptpod_pmic_volt[5]), \
1670 ptp_trasnfer_to_volt(ptpod_pmic_volt[6]), \
1671 ptp_trasnfer_to_volt(ptpod_pmic_volt[7]), \
1672 mt_cpufreq_max_frequency_by_DVS(0), \
1673 mt_cpufreq_max_frequency_by_DVS(1), \
1674 mt_cpufreq_max_frequency_by_DVS(2), \
1675 mt_cpufreq_max_frequency_by_DVS(3), \
1676 mt_cpufreq_max_frequency_by_DVS(4), \
1677 mt_cpufreq_max_frequency_by_DVS(5), \
1678 mt_cpufreq_max_frequency_by_DVS(6), \
1679 mt_cpufreq_max_frequency_by_DVS(7));
1680
1681 len = p - buf;
1682 return len;
1683 }
1684
1685 /************************************
1686 * set current PTP status by sysfs interface
1687 *************************************/
1688 static ssize_t ptp_status_store(struct kobject *kobj,
1689 struct kobj_attribute *attr, const char *buf, size_t n)
1690 {
1691 return n;
1692 }
1693
1694 ptp_attr(ptp_status);
1695
1696 /***************************
1697 * show PTP log enable
1698 ****************************/
1699 static ssize_t ptp_log_en_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
1700 {
1701 return 0;
1702 }
1703
1704 /***************************************
1705 * set PTP log enable by sysfs interface
1706 ****************************************/
1707 static ssize_t ptp_log_en_store(struct kobject *kobj,
1708 struct kobj_attribute *attr, const char *buf, size_t n)
1709 {
1710 int enabled = 0;
1711 ktime_t ktime = ktime_set(mt_ptp_log_period_s, mt_ptp_log_period_ns);
1712
1713 if (sscanf(buf, "%d", &enabled) == 1)
1714 {
1715 if (enabled == 1)
1716 {
1717 ptp_notice("ptp log enabled.\n");
1718 mt_ptp_log_thread = kthread_run(mt_ptp_log_thread_handler, 0, "ptp logging");
1719 if (IS_ERR(mt_ptp_log_thread))
1720 {
1721 printk("[%s]: failed to create ptp logging thread\n", __FUNCTION__);
1722 }
1723 hrtimer_start(&mt_ptp_log_timer, ktime, HRTIMER_MODE_REL);
1724 }
1725 else if (enabled == 0)
1726 {
1727 kthread_stop(mt_ptp_log_thread);
1728 hrtimer_cancel(&mt_ptp_log_timer);
1729 }
1730 else
1731 {
1732 ptp_notice("ptp log disabled.\n");
1733 ptp_notice("bad argument!! argument should be \"0\" or \"1\"\n");
1734 }
1735 }
1736 else
1737 {
1738 ptp_notice("bad argument!! argument should be \"0\" or \"1\"\n");
1739 }
1740
1741 return n;
1742 }
1743
1744 ptp_attr(ptp_log_en);
1745
1746 struct kobject *ptp_kobj;
1747 EXPORT_SYMBOL_GPL(ptp_kobj);
1748
1749 static struct attribute *g[] = {
1750 &ptp_offset_attr.attr,
1751 &ptp_debug_attr.attr,
1752 &ptp_dump_attr.attr,
1753 &ptp_cur_volt_attr.attr,
1754 &ptp_status_attr.attr,
1755 &ptp_log_en_attr.attr,
1756 NULL,
1757 };
1758
1759 static struct attribute_group attr_group = {
1760 .attrs = g,
1761 };
1762
1763 static int __init ptp_init(void)
1764 {
1765 int err = 0;
1766
1767 ptp_data[0] = 0;
1768
1769 hrtimer_init(&mt_ptp_log_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1770 mt_ptp_log_timer.function = mt_ptp_log_timer_func;
1771
1772 hrtimer_init(&mt_ptp_volt_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1773 mt_ptp_volt_timer.function = mt_ptp_volt_timer_func;
1774
1775 ptp_kobj = kobject_create_and_add("ptp", NULL);
1776 if (!ptp_kobj) {
1777 ptp_notice("[%s]: ptp_kobj create failed\n", __func__);
1778 }
1779
1780 err = sysfs_create_group(ptp_kobj, &attr_group);
1781 if (err) {
1782 ptp_notice("[%s]: ptp_kobj->attr_group create failed\n", __func__);
1783 }
1784
1785 err = platform_driver_register(&ptp_driver);
1786
1787 if (err)
1788 {
1789 ptp_notice("PTP driver callback register failed..\n");
1790 return err;
1791 }
1792
1793 return 0;
1794 }
1795
1796 static void __exit ptp_exit(void)
1797 {
1798 ptp_notice("PTP de-initialization\n");
1799 }
1800
1801 late_initcall(ptp_init);
1802 #endif
1803
1804 MODULE_DESCRIPTION("MediaTek PTPOD Driver v0.2");
1805 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)