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Merge tag 'v3.10.55' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / mt_gpufreq.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/sched.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/proc_fs.h>
15 #include <linux/miscdevice.h>
16 #include <linux/platform_device.h>
17 #include <linux/earlysuspend.h>
18 #include <linux/spinlock.h>
19 #include <linux/kthread.h>
20 #include <linux/hrtimer.h>
21 #include <linux/ktime.h>
22 #include <linux/xlog.h>
23 #include <linux/jiffies.h>
24 #ifdef GPU_CLOCK_RATIO
25 #include <linux/time.h>
26 #endif
27
28 #include <asm/system.h>
29 #include <asm/uaccess.h>
30
31 #include "mach/mt_typedefs.h"
32 #include "mach/mt_clkmgr.h"
33 #include "mach/mt_gpufreq.h"
34 #include "mach/upmu_common.h"
35 #include "mach/sync_write.h"
36
37 /***************************
38 * debug message
39 ****************************/
40 #define dprintk(fmt, args...) \
41 do { \
42 if (mt_gpufreq_debug) { \
43 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", fmt, ##args); \
44 } \
45 } while(0)
46
47 #ifdef CONFIG_HAS_EARLYSUSPEND
48 static struct early_suspend mt_gpufreq_early_suspend_handler =
49 {
50 .level = EARLY_SUSPEND_LEVEL_DISABLE_FB + 200,
51 .suspend = NULL,
52 .resume = NULL,
53 };
54 #endif
55
56 /***************************
57 * MT6589 GPU Power Table
58 ****************************/
59 static struct mt_gpufreq_power_info mt_gpufreqs_golden_power[] = {
60 {.gpufreq_khz = GPU_DVFS_F2, .gpufreq_power = 761},
61 {.gpufreq_khz = GPU_DVFS_F3, .gpufreq_power = 625},
62 {.gpufreq_khz = GPU_DVFS_F4, .gpufreq_power = 581},
63 {.gpufreq_khz = GPU_DVFS_F5, .gpufreq_power = 456},
64 {.gpufreq_khz = GPU_DVFS_F7, .gpufreq_power = 414},
65 {.gpufreq_khz = GPU_DVFS_F8, .gpufreq_power = 336},
66 };
67
68 /**************************
69 * enable GPU DVFS count
70 ***************************/
71 static int g_gpufreq_dvfs_disable_count = 0;
72
73 static unsigned int g_cur_freq = 286000;
74 static unsigned int g_cur_volt = 0;
75 static unsigned int g_cur_load = 0;
76
77 static unsigned int g_cur_freq_init_keep = 0;
78 static unsigned int g_volt_set_init_step_1 = 0;
79 static unsigned int g_volt_set_init_step_2 = 0;
80 static unsigned int g_volt_set_init_step_3 = 0;
81 static unsigned int g_freq_new_init_keep = 0;
82 static unsigned int g_volt_new_init_keep = 0;
83
84 /* In default settiing, freq_table[0] is max frequency, freq_table[num-1] is min frequency,*/
85 static unsigned int g_gpufreq_max_id = 0;
86
87 /* If not limited, it should be set to freq_table[0] (MAX frequency) */
88 static unsigned int g_limited_max_id;
89 static unsigned int g_limited_min_id;
90
91 static bool mt_gpufreq_debug = false;
92 static bool mt_gpufreq_pause = false;
93 static bool mt_gpufreq_keep_max_frequency = false;
94 static bool mt_gpufreq_keep_specific_frequency = false;
95 static unsigned int mt_gpufreq_fixed_frequency = 0;
96 static unsigned int mt_gpufreq_fixed_voltage = 0;
97
98 static DEFINE_SPINLOCK(mt_gpufreq_lock);
99
100 static unsigned int mt_gpufreqs_num = 0;
101 static struct mt_gpufreq_info *mt_gpufreqs;
102 static struct mt_gpufreq_power_info *mt_gpufreqs_power;
103 static struct mt_gpufreq_power_info *mt_gpufreqs_default_power;
104
105 static bool mt_gpufreq_registered = false;
106 static bool mt_gpufreq_registered_statewrite = false;
107 static bool mt_gpufreq_already_non_registered = false;
108
109 #ifdef GPU_CLOCK_RATIO
110 //static DEFINE_SPINLOCK(mt_gpufreq_load_lock);
111 //static struct mt_gpufreq_info *mt_gpufreqs_test;
112
113 static int mt_gpufreq_clock_on = 0;
114 static unsigned int mt_gpufreq_cur_wall_time = 0;
115 static unsigned int mt_gpufreq_prev_wall_time = 0;
116 static unsigned int mt_gpufreq_period_time = 0;
117 static unsigned int mt_gpu_clock_on_time_start = 0;
118 static unsigned int mt_gpu_clock_total_on_time = 0;
119 #endif
120
121 static unsigned int mt_gpufreq_enable_mainpll = 0;
122 static unsigned int mt_gpufreq_enable_mmpll = 0;
123
124 /******************************
125 * Extern Function Declaration
126 *******************************/
127 extern int mtk_gpufreq_register(struct mt_gpufreq_power_info *freqs, int num);
128
129 /**************************
130 * GPU DVFS timer & thread
131 ***************************/
132 static struct hrtimer mt_gpufreq_timer;
133 struct task_struct *mt_gpufreq_thread = NULL;
134 static DECLARE_WAIT_QUEUE_HEAD(mt_gpufreq_timer_waiter);
135
136 static int mt_gpufreq_sample_s = 0;
137 static int mt_gpufreq_sample_ns = 30000000; // 30ms
138 static int mt_gpufreq_timer_flag = 0;
139
140 /******************************
141 * Extern Function Declaration
142 *******************************/
143 extern int pmic_get_gpu_status_bit_info(void);
144
145 /******************************
146 * Internal prototypes
147 *******************************/
148 enum hrtimer_restart mt_gpufreq_timer_func(struct hrtimer *timer);
149 static int mt_gpufreq_thread_handler(void *unused);
150
151
152 /*****************************************************************
153 * Check GPU current frequency and enable pll in initial and late resume.
154 *****************************************************************/
155 static void mt_gpufreq_check_freq_and_set_pll(void)
156 {
157 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_check_freq_and_set_pll, g_cur_freq = %d\n", g_cur_freq);
158
159 switch (g_cur_freq)
160 {
161 case GPU_MMPLL_D3: // 476Mhz
162 if(mt_gpufreq_enable_mmpll == 0)
163 {
164 enable_pll(MMPLL, "GPU_DVFS");
165 mt_gpufreq_enable_mmpll = 1;
166 }
167 break;
168
169 case GPU_SYSPLL_D2: // 403Mhz
170 if(mt_gpufreq_enable_mainpll == 0)
171 {
172 enable_pll(MAINPLL, "GPU_DVFS");
173 mt_gpufreq_enable_mainpll = 1;
174 }
175 break;
176
177 case GPU_MMPLL_D4: // 357Mhz
178 if(mt_gpufreq_enable_mmpll == 0)
179 {
180 enable_pll(MMPLL, "GPU_DVFS");
181 mt_gpufreq_enable_mmpll = 1;
182 }
183 break;
184
185 case GPU_UNIVPLL1_D2: // 312Mhz
186 break;
187
188 case GPU_MMPLL_D5: // 286Mhz
189 if(mt_gpufreq_enable_mmpll == 0)
190 {
191 enable_pll(MMPLL, "GPU_DVFS");
192 mt_gpufreq_enable_mmpll = 1;
193 }
194 break;
195
196 case GPU_SYSPLL_D3: // 268Mhz
197 if(mt_gpufreq_enable_mainpll == 0)
198 {
199 enable_pll(MAINPLL, "GPU_DVFS");
200 mt_gpufreq_enable_mainpll = 1;
201 }
202 break;
203
204 case GPU_MMPLL_D6: // 238Mhz
205 if(mt_gpufreq_enable_mmpll == 0)
206 {
207 enable_pll(MMPLL, "GPU_DVFS");
208 mt_gpufreq_enable_mmpll = 1;
209 }
210 break;
211
212 case GPU_UNIVPLL1_D4: // 156Mhz
213 break;
214
215 default:
216 break;
217 }
218 }
219
220 /**************************************
221 * check if maximum frequency is needed
222 ***************************************/
223 static int mt_gpufreq_keep_max_freq(unsigned int freq_old, unsigned int freq_new)
224 {
225 if (mt_gpufreq_keep_max_frequency == true)
226 return 1;
227
228 return 0;
229 }
230
231 /*****************************************************************
232 * Check if gpufreq registration is done
233 *****************************************************************/
234 bool mt_gpufreq_is_registered_get(void)
235 {
236 if((mt_gpufreq_registered == true) || (mt_gpufreq_already_non_registered == true))
237 return true;
238 else
239 return false;
240 }
241 EXPORT_SYMBOL(mt_gpufreq_is_registered_get);
242
243 #ifdef GPU_CLOCK_RATIO
244 /*****************************************************************
245 * When gpu dvfs initialize or re-enable, record period time start,
246 * and reset total clock on time, period time.
247 *****************************************************************/
248 static void mt_gpufreq_period_time_reset(void)
249 {
250 struct timeval t1;
251 do_gettimeofday(&t1);
252
253 mt_gpufreq_prev_wall_time = (unsigned int)t1.tv_usec;
254 mt_gpu_clock_total_on_time = 0;
255 mt_gpufreq_period_time = 0;
256
257 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_period_time_reset(), mt_gpufreq_prev_wall_time = %d\n", mt_gpufreq_prev_wall_time);
258 }
259
260 /*****************************************************************
261 * Function to calculate clock on time ratio
262 *****************************************************************/
263 unsigned int mt_gpufreq_gpu_clock_ratio(enum mt_gpufreq_clock_ratio act)
264 {
265 unsigned long flags;
266 unsigned int load = 0;
267 struct timeval t2;
268
269 spin_lock_irqsave(&mt_gpufreq_lock, flags);
270
271 do_gettimeofday(&t2);
272
273 if(act == GPU_DVFS_CLOCK_RATIO_ON && mt_gpufreq_clock_on == 0)
274 {
275 /* Remember clock on starting time. */
276 mt_gpufreq_clock_on = 1;
277 mt_gpu_clock_on_time_start = (unsigned int)t2.tv_usec;
278 dprintk("ON = %d\n", mt_gpu_clock_on_time_start);
279 }
280 else if(act == GPU_DVFS_CLOCK_RATIO_OFF && mt_gpufreq_clock_on == 1)
281 {
282 /* Calculate this clock on time and add it into total clock on time. */
283 mt_gpufreq_clock_on = 0;
284 mt_gpufreq_cur_wall_time = (unsigned int)t2.tv_usec;
285
286 if(mt_gpufreq_cur_wall_time >= mt_gpu_clock_on_time_start)
287 mt_gpu_clock_total_on_time += (mt_gpufreq_cur_wall_time - mt_gpu_clock_on_time_start);
288 else
289 mt_gpu_clock_total_on_time += ((GPU_COUNT_OVERFLOW - mt_gpu_clock_on_time_start) + mt_gpufreq_cur_wall_time);
290
291 dprintk("OFF = %d, mt_gpu_clock_total_on_time = %d\n", mt_gpufreq_cur_wall_time, mt_gpu_clock_total_on_time);
292 }
293 else if(act == GPU_DVFS_CLOCK_RATIO_GET)
294 {
295 mt_gpufreq_cur_wall_time = (unsigned int)t2.tv_usec;
296 dprintk("GET 1, mt_gpufreq_cur_wall_time = %d\n", mt_gpufreq_cur_wall_time);
297
298 /* If polling timeout and clock still on. */
299 if(mt_gpufreq_clock_on == 1)
300 {
301 /* Calculate this clock on time and add it into total clock on time. */
302 if(mt_gpufreq_cur_wall_time >= mt_gpu_clock_on_time_start)
303 mt_gpu_clock_total_on_time += (mt_gpufreq_cur_wall_time - mt_gpu_clock_on_time_start);
304 else
305 mt_gpu_clock_total_on_time += ((GPU_COUNT_OVERFLOW - mt_gpu_clock_on_time_start) + mt_gpufreq_cur_wall_time);
306
307 /* Use current time as next clock on starting time */
308 mt_gpu_clock_on_time_start = mt_gpufreq_cur_wall_time;
309 dprintk("GET, clock is still ON!\n");
310 }
311
312 /* Calculate period time. */
313 if(mt_gpufreq_cur_wall_time >= mt_gpufreq_prev_wall_time)
314 mt_gpufreq_period_time = mt_gpufreq_cur_wall_time - mt_gpufreq_prev_wall_time;
315 else
316 mt_gpufreq_period_time = (GPU_COUNT_OVERFLOW - mt_gpufreq_prev_wall_time) + mt_gpufreq_cur_wall_time;
317 dprintk("GET 2, mt_gpu_clock_on_time_start = %d, mt_gpu_clock_total_on_time = %d\n", mt_gpu_clock_on_time_start, mt_gpu_clock_total_on_time);
318 dprintk("GET 3, mt_gpufreq_prev_wall_time = %d, mt_gpufreq_period_time = %d\n", mt_gpufreq_prev_wall_time, mt_gpufreq_period_time);
319 mt_gpufreq_prev_wall_time = mt_gpufreq_cur_wall_time;
320
321 /* Calculate ratio. */
322 load = 100 * mt_gpu_clock_total_on_time / mt_gpufreq_period_time;
323 mt_gpu_clock_total_on_time = 0;
324 mt_gpufreq_period_time = 0;
325 dprintk("GET 4, ratio = %d\n", load);
326 }
327
328 spin_unlock_irqrestore(&mt_gpufreq_lock, flags);
329
330 return load;
331 }
332 EXPORT_SYMBOL(mt_gpufreq_gpu_clock_ratio);
333 #endif
334
335 /* Default power table when mt_gpufreq_non_register() */
336 static void mt_setup_gpufreqs_default_power_table(int num)
337 {
338 int j = 0;
339
340 mt_gpufreqs_default_power = kzalloc((1) * sizeof(struct mt_gpufreq_power_info), GFP_KERNEL);
341 if (mt_gpufreqs_default_power == NULL)
342 {
343 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "GPU default power table memory allocation fail\n");
344 return;
345 }
346
347 mt_gpufreqs_default_power[0].gpufreq_khz = g_cur_freq;
348
349 for (j = 0; j < ARRAY_SIZE(mt_gpufreqs_golden_power); j++)
350 {
351 if (g_cur_freq == mt_gpufreqs_golden_power[j].gpufreq_khz)
352 {
353 mt_gpufreqs_default_power[0].gpufreq_power = mt_gpufreqs_golden_power[j].gpufreq_power;
354 break;
355 }
356 }
357
358 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreqs_default_power[0].gpufreq_khz = %u\n", mt_gpufreqs_default_power[0].gpufreq_khz);
359 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreqs_default_power[0].gpufreq_power = %u\n", mt_gpufreqs_default_power[0].gpufreq_power);
360
361 #ifdef CONFIG_THERMAL
362 mtk_gpufreq_register(mt_gpufreqs_default_power, 1);
363 #endif
364 }
365
366 static void mt_setup_gpufreqs_power_table(int num)
367 {
368 int i = 0, j = 0;
369
370 mt_gpufreqs_power = kzalloc((num) * sizeof(struct mt_gpufreq_power_info), GFP_KERNEL);
371 if (mt_gpufreqs_power == NULL)
372 {
373 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "GPU power table memory allocation fail\n");
374 return;
375 }
376
377 for (i = 0; i < num; i++) {
378 mt_gpufreqs_power[i].gpufreq_khz = mt_gpufreqs[i].gpufreq_khz;
379
380 for (j = 0; j < ARRAY_SIZE(mt_gpufreqs_golden_power); j++)
381 {
382 if (mt_gpufreqs[i].gpufreq_khz == mt_gpufreqs_golden_power[j].gpufreq_khz)
383 {
384 mt_gpufreqs_power[i].gpufreq_power = mt_gpufreqs_golden_power[j].gpufreq_power;
385 break;
386 }
387 }
388
389 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreqs_power[%d].gpufreq_khz = %u\n", i, mt_gpufreqs_power[i].gpufreq_khz);
390 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreqs_power[%d].gpufreq_power = %u\n", i, mt_gpufreqs_power[i].gpufreq_power);
391 }
392
393 #ifdef CONFIG_THERMAL
394 mtk_gpufreq_register(mt_gpufreqs_power, num);
395 #endif
396 }
397
398 /***********************************************
399 * register frequency table to gpufreq subsystem
400 ************************************************/
401 static int mt_setup_gpufreqs_table(struct mt_gpufreq_info *freqs, int num)
402 {
403 int i = 0;
404
405 mt_gpufreqs = kzalloc((num) * sizeof(*freqs), GFP_KERNEL);
406 if (mt_gpufreqs == NULL)
407 return -ENOMEM;
408
409 for (i = 0; i < num; i++) {
410 mt_gpufreqs[i].gpufreq_khz = freqs[i].gpufreq_khz;
411 mt_gpufreqs[i].gpufreq_lower_bound = freqs[i].gpufreq_lower_bound;
412 mt_gpufreqs[i].gpufreq_upper_bound = freqs[i].gpufreq_upper_bound;
413 mt_gpufreqs[i].gpufreq_volt = freqs[i].gpufreq_volt;
414 mt_gpufreqs[i].gpufreq_remap = freqs[i].gpufreq_remap;
415
416 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[%d].gpufreq_khz = %u\n", i, freqs[i].gpufreq_khz);
417 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[%d].gpufreq_lower_bound = %u\n", i, freqs[i].gpufreq_lower_bound);
418 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[%d].gpufreq_upper_bound = %u\n", i, freqs[i].gpufreq_upper_bound);
419 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[%d].gpufreq_volt = %u\n", i, freqs[i].gpufreq_volt);
420 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[%d].gpufreq_remap = %u\n", i, freqs[i].gpufreq_remap);
421 }
422
423 mt_gpufreqs_num = num;
424
425 /* Initial frequency and voltage was already set in mt_gpufreq_set_initial() */
426 #if 0//1
427 g_cur_freq = freqs[0].gpufreq_khz;
428 g_cur_volt = freqs[0].gpufreq_volt;
429 #endif
430 g_limited_max_id = 0;
431 g_limited_min_id = mt_gpufreqs_num - 1;
432
433 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_setup_gpufreqs_table, g_cur_freq = %d, g_cur_volt = %d\n", g_cur_freq, g_cur_volt);
434
435 mt_setup_gpufreqs_power_table(num);
436
437 return 0;
438 }
439
440 /*****************************
441 * set GPU DVFS status
442 ******************************/
443 int mt_gpufreq_state_set(int enabled)
444 {
445 ktime_t ktime = ktime_set(mt_gpufreq_sample_s, mt_gpufreq_sample_ns);
446
447 if (enabled)
448 {
449 if (!mt_gpufreq_pause)
450 {
451 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "gpufreq already enabled\n");
452 return 0;
453 }
454
455 /*****************
456 * enable GPU DVFS
457 ******************/
458 g_gpufreq_dvfs_disable_count--;
459 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "enable GPU DVFS: g_gpufreq_dvfs_disable_count = %d\n", g_gpufreq_dvfs_disable_count);
460
461 /***********************************************
462 * enable DVFS if no any module still disable it
463 ************************************************/
464 if (g_gpufreq_dvfs_disable_count <= 0)
465 {
466 mt_gpufreq_pause = false;
467 hrtimer_start(&mt_gpufreq_timer, ktime, HRTIMER_MODE_REL);
468 #ifdef GPU_CLOCK_RATIO
469 mt_gpufreq_period_time_reset();
470 #endif
471 }
472 else
473 {
474 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "someone still disable gpufreq, cannot enable it\n");
475 }
476 }
477 else
478 {
479 /******************
480 * disable GPU DVFS
481 *******************/
482 g_gpufreq_dvfs_disable_count++;
483 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "disable GPU DVFS: g_gpufreq_dvfs_disable_count = %d\n", g_gpufreq_dvfs_disable_count);
484
485 if (mt_gpufreq_pause)
486 {
487 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "gpufreq already disabled\n");
488 return 0;
489 }
490
491 mt_gpufreq_pause = true;
492 hrtimer_cancel(&mt_gpufreq_timer);
493 }
494
495 return 0;
496 }
497 EXPORT_SYMBOL(mt_gpufreq_state_set);
498
499 static void mt_gpu_clock_switch(unsigned int sel)
500 {
501 unsigned int clk_cfg_0 = 0, clk_cfg_4 = 0;
502
503 clk_cfg_0 = DRV_Reg32(CLK_CFG_0);
504 clk_cfg_4 = DRV_Reg32(CLK_CFG_4);
505
506 switch (sel)
507 {
508 case GPU_MMPLL_D3: // 476Mhz
509 if(mt_gpufreq_enable_mmpll == 0)
510 {
511 enable_pll(MMPLL, "GPU_DVFS");
512 mt_gpufreq_enable_mmpll = 1;
513 }
514
515 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x5 << 16);
516 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
517 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_MMPLL_D3\n");
518
519 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x5);
520 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
521 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_MMPLL_D3\n");
522
523 if(mt_gpufreq_enable_mainpll == 1)
524 {
525 disable_pll(MAINPLL, "GPU_DVFS");
526 mt_gpufreq_enable_mainpll = 0;
527 }
528 break;
529 case GPU_SYSPLL_D2: // 403Mhz
530 if(mt_gpufreq_enable_mainpll == 0)
531 {
532 enable_pll(MAINPLL, "GPU_DVFS");
533 mt_gpufreq_enable_mainpll = 1;
534 }
535
536 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x2 << 16);
537 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
538 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_SYSPLL_D2\n");
539
540 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x2);
541 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
542 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_SYSPLL_D2\n");
543
544 if(mt_gpufreq_enable_mmpll == 1)
545 {
546 disable_pll(MMPLL, "GPU_DVFS");
547 mt_gpufreq_enable_mmpll = 0;
548 }
549 break;
550 case GPU_MMPLL_D4: // 357Mhz
551 if(mt_gpufreq_enable_mmpll == 0)
552 {
553 enable_pll(MMPLL, "GPU_DVFS");
554 mt_gpufreq_enable_mmpll = 1;
555 }
556
557 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x6 << 16);
558 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
559 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_MMPLL_D4\n");
560
561 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x6);
562 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
563 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_MMPLL_D4\n");
564
565 if(mt_gpufreq_enable_mainpll == 1)
566 {
567 disable_pll(MAINPLL, "GPU_DVFS");
568 mt_gpufreq_enable_mainpll = 0;
569 }
570 break;
571 case GPU_UNIVPLL1_D2: // 312Mhz
572 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x4 << 16);
573 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
574 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_UNIVPLL1_D2\n");
575
576 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x4);
577 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
578 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_UNIVPLL1_D2\n");
579
580 if(mt_gpufreq_enable_mainpll == 1)
581 {
582 disable_pll(MAINPLL, "GPU_DVFS");
583 mt_gpufreq_enable_mainpll = 0;
584 }
585
586 if(mt_gpufreq_enable_mmpll == 1)
587 {
588 disable_pll(MMPLL, "GPU_DVFS");
589 mt_gpufreq_enable_mmpll = 0;
590 }
591 break;
592 case GPU_MMPLL_D5: // 286Mhz
593 if(mt_gpufreq_enable_mmpll == 0)
594 {
595 enable_pll(MMPLL, "GPU_DVFS");
596 mt_gpufreq_enable_mmpll = 1;
597 }
598
599 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x7 << 16);
600 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
601 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_MMPLL_D5\n");
602
603 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x7);
604 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
605 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_MMPLL_D5\n");
606
607 if(mt_gpufreq_enable_mainpll == 1)
608 {
609 disable_pll(MAINPLL, "GPU_DVFS");
610 mt_gpufreq_enable_mainpll = 0;
611 }
612 break;
613 case GPU_SYSPLL_D3: // 268Mhz
614 if(mt_gpufreq_enable_mainpll == 0)
615 {
616 enable_pll(MAINPLL, "GPU_DVFS");
617 mt_gpufreq_enable_mainpll = 1;
618 }
619
620 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x3 << 16);
621 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
622 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_SYSPLL_D3\n");
623
624 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x7);
625 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
626 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_MMPLL_D5\n");
627
628 if(mt_gpufreq_enable_mmpll == 1)
629 {
630 disable_pll(MMPLL, "GPU_DVFS");
631 mt_gpufreq_enable_mmpll = 0;
632 }
633 break;
634 case GPU_MMPLL_D6: // 238Mhz
635 if(mt_gpufreq_enable_mmpll == 0)
636 {
637 enable_pll(MMPLL, "GPU_DVFS");
638 mt_gpufreq_enable_mmpll = 1;
639 }
640
641 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x1 << 16);
642 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
643 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_MMPLL_D6\n");
644
645 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x7);
646 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
647 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_MMPLL_D5\n");
648
649 if(mt_gpufreq_enable_mainpll == 1)
650 {
651 disable_pll(MAINPLL, "GPU_DVFS");
652 mt_gpufreq_enable_mainpll = 0;
653 }
654 break;
655 case GPU_UNIVPLL1_D4: // 156Mhz
656 clk_cfg_0 = (clk_cfg_0 & 0xFFF8FFFF) | (0x0 << 16);
657 mt65xx_reg_sync_writel(clk_cfg_0, CLK_CFG_0);
658 dprintk("mt_gpu_clock_switch: switch MFG clock to GPU_UNIVPLL1_D4\n");
659
660 clk_cfg_4 = (clk_cfg_4 & 0xFFFFFFF8) | (0x7);
661 mt65xx_reg_sync_writel(clk_cfg_4, CLK_CFG_4);
662 dprintk("mt_gpu_clock_switch: switch HYD clock to GPU_MMPLL_D5\n");
663
664 if(mt_gpufreq_enable_mainpll == 1)
665 {
666 disable_pll(MAINPLL, "GPU_DVFS");
667 mt_gpufreq_enable_mainpll = 0;
668 }
669
670 if(mt_gpufreq_enable_mmpll == 1)
671 {
672 disable_pll(MMPLL, "GPU_DVFS");
673 mt_gpufreq_enable_mmpll = 0;
674 }
675 break;
676 default:
677 dprintk("mt_gpu_clock_switch: do not support specified clock (%d)\n", sel);
678 break;
679 }
680
681 dprintk("CLK_CFG_0 = 0x%x, CLK_CFG_4 = 0x%x\n", DRV_Reg32(CLK_CFG_0), DRV_Reg32(CLK_CFG_4));
682 }
683
684 static void mt_gpu_volt_switch(unsigned int volt_old, unsigned int volt_new)
685 {
686 int i = 0;
687
688 upmu_set_vrf18_2_vosel_ctrl(0); // SW control mode
689
690 if (volt_new == GPU_POWER_VRF18_1_15V)
691 {
692 dprintk("mt_gpu_volt_switch: switch MFG power to GPU_POWER_VRF18_1_15V\n");
693 }
694 else if (volt_new == GPU_POWER_VRF18_1_10V)
695 {
696 dprintk("mt_gpu_volt_switch: switch MFG power to GPU_POWER_VRF18_1_10V\n");
697 }
698 else if (volt_new == GPU_POWER_VRF18_1_05V)
699 {
700 dprintk("mt_gpu_volt_switch: switch MFG power to GPU_POWER_VRF18_1_05V\n");
701 }
702 else if (volt_new == GPU_POWER_VCORE_1_05V)
703 {
704 dprintk("mt_gpu_volt_switch: use VCORE, not support voltage scaling\n");
705 return;
706 }
707 else
708 {
709 dprintk("mt_gpu_volt_switch: do not support specified volt (%d)\n", volt_new);
710 return;
711 }
712
713 if (volt_old < volt_new)
714 {
715 for (i = ((int)volt_old + 1); i <= (int)volt_new; i++)
716 {
717 dprintk("mt_gpu_volt_switch: volt_old < volt_new, i=(%d)\n", i);
718 upmu_set_vrf18_2_vosel(i);
719 udelay(PMIC_SETTLE_TIME);
720 }
721 }
722 else
723 {
724 for (i = ((int)volt_old - 1); i >= (int)volt_new ; i--)
725 {
726 dprintk("mt_gpu_volt_switch: volt_old > volt_new, i=(%d)\n", i);
727 upmu_set_vrf18_2_vosel(i);
728 udelay(PMIC_SETTLE_TIME);
729 }
730 }
731 }
732
733 static void mt_gpu_volt_switch_initial(unsigned int volt_new)
734 {
735 upmu_set_vrf18_2_vosel_ctrl(0); // SW control mode
736
737 if (volt_new == GPU_POWER_VRF18_1_15V)
738 {
739 upmu_set_vrf18_2_vosel(4);
740 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpu_volt_switch_initial: switch MFG power to GPU_POWER_VRF18_1_15V\n");
741 }
742 else if (volt_new == GPU_POWER_VRF18_1_10V)
743 {
744 upmu_set_vrf18_2_vosel(2);
745 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpu_volt_switch_initial: switch MFG power to GPU_POWER_VRF18_1_10V\n");
746 }
747 else if (volt_new == GPU_POWER_VRF18_1_05V)
748 {
749 upmu_set_vrf18_2_vosel(0);
750 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpu_volt_switch_initial: switch MFG power to GPU_POWER_VRF18_1_05V\n");
751 }
752 else if (volt_new == GPU_POWER_VCORE_1_05V)
753 {
754 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpu_volt_switch_initial: use VCORE, not support voltage scaling\n");
755 return;
756 }
757 else
758 {
759 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpu_volt_switch_initial: do not support specified volt (%d)\n");
760 return;
761 }
762
763 }
764
765 /***********************************************************
766 * 1. 3D driver will check efuse and set initial frequency and voltage
767 * 2. When GPU idle in intial, voltage could be set directly.
768 ************************************************************/
769 void mt_gpufreq_set_initial(unsigned int freq_new, unsigned int volt_new)
770 {
771 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_set_initial, freq_new = %d, volt_new = %d, g_cur_freq = %d\n", freq_new, volt_new, g_cur_freq);
772 g_freq_new_init_keep = freq_new;
773 g_volt_new_init_keep = volt_new;
774
775 mt_gpufreq_check_freq_and_set_pll();
776
777 if(freq_new == g_cur_freq)
778 {
779 g_volt_set_init_step_1 = 1;
780 return;
781 }
782
783 if (freq_new > g_cur_freq)
784 {
785 #ifdef MT_BUCK_ADJUST
786 if (pmic_get_gpu_status_bit_info() == 0) // 1: VCORE, 0: VRF18_2
787 {
788 g_volt_set_init_step_2 = 1;
789 mt_gpu_volt_switch_initial(volt_new);
790 udelay(PMIC_SETTLE_TIME);
791 }
792 #endif
793
794 mt_gpu_clock_switch(freq_new);
795 }
796 else
797 {
798 mt_gpu_clock_switch(freq_new);
799
800 #ifdef MT_BUCK_ADJUST
801 if (pmic_get_gpu_status_bit_info() == 0) // 1: VCORE, 0: VRF18_2
802 {
803 g_volt_set_init_step_3 = 1;
804 mt_gpu_volt_switch_initial(volt_new);
805 }
806 #endif
807 }
808
809 g_cur_freq = freq_new;
810 g_cur_volt = volt_new;
811 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_set_initial, g_cur_freq = %d, g_cur_volt = %d\n", g_cur_freq, g_cur_volt);
812 }
813 EXPORT_SYMBOL(mt_gpufreq_set_initial);
814
815
816 /*****************************************
817 * frequency ramp up and ramp down handler
818 ******************************************/
819 /***********************************************************
820 * [note]
821 * 1. frequency ramp up need to wait voltage settle
822 * 2. frequency ramp down do not need to wait voltage settle
823 ************************************************************/
824 static void mt_gpufreq_set(unsigned int freq_old, unsigned int freq_new, unsigned int volt_old, unsigned int volt_new)
825 {
826 if (freq_new > freq_old)
827 {
828 #ifdef MT_BUCK_ADJUST
829 if (pmic_get_gpu_status_bit_info() == 0) // 1: VCORE, 0: VRF18_2
830 {
831 if (volt_old != volt_new)
832 {
833 mt_gpu_volt_switch(volt_old, volt_new);
834 }
835 }
836 #endif
837
838 mt_gpu_clock_switch(freq_new);
839 }
840 else
841 {
842 mt_gpu_clock_switch(freq_new);
843
844 #ifdef MT_BUCK_ADJUST
845 if (pmic_get_gpu_status_bit_info() == 0) // 1: VCORE, 0: VRF18_2
846 {
847 if (volt_old != volt_new)
848 {
849 mt_gpu_volt_switch(volt_old, volt_new);
850 }
851 }
852 #endif
853 }
854
855 g_cur_freq = freq_new;
856 g_cur_volt = volt_new;
857 }
858
859 static int mt_gpufreq_look_up(unsigned int load)
860 {
861 int i = 0, remap = 100;
862
863 /**************************
864 * look up the remap value
865 ***************************/
866 for (i = 0; i < mt_gpufreqs_num; i++)
867 {
868 if (mt_gpufreqs[i].gpufreq_khz == g_cur_freq)
869 {
870 remap = mt_gpufreqs[i].gpufreq_remap;
871 break;
872 }
873 }
874
875 load = (load * remap) / 100;
876 g_cur_load = load;
877 dprintk("GPU Loading = %d\n", load);
878
879 /******************************
880 * look up the target frequency
881 *******************************/
882 for (i = 0; i < mt_gpufreqs_num; i++)
883 {
884 if (load > mt_gpufreqs[i].gpufreq_lower_bound && load <= mt_gpufreqs[i].gpufreq_upper_bound)
885 {
886 return i;
887 }
888 }
889
890 return (mt_gpufreqs_num - 1);
891 }
892
893 /**********************************
894 * gpufreq target callback function
895 ***********************************/
896 /*************************************************
897 * [note]
898 * 1. handle frequency change request
899 * 2. call mt_gpufreq_set to set target frequency
900 **************************************************/
901 static int mt_gpufreq_target(int idx)
902 {
903 unsigned long flags, target_freq, target_volt;
904
905 spin_lock_irqsave(&mt_gpufreq_lock, flags);
906
907 /**********************************
908 * look up for the target GPU OPP
909 ***********************************/
910 target_freq = mt_gpufreqs[idx].gpufreq_khz;
911 target_volt = mt_gpufreqs[idx].gpufreq_volt;
912
913 /**********************************
914 * Check if need to keep max frequency
915 ***********************************/
916 if (mt_gpufreq_keep_max_freq(g_cur_freq, target_freq))
917 {
918 target_freq = mt_gpufreqs[g_gpufreq_max_id].gpufreq_khz;
919 target_volt = mt_gpufreqs[g_gpufreq_max_id].gpufreq_volt;
920 dprintk("Keep MAX frequency %d !\n", target_freq);
921 }
922
923 /****************************************************
924 * If need to raise frequency, raise to max frequency
925 *****************************************************/
926 if(target_freq > g_cur_freq)
927 {
928 target_freq = mt_gpufreqs[g_gpufreq_max_id].gpufreq_khz;
929 target_volt = mt_gpufreqs[g_gpufreq_max_id].gpufreq_volt;
930 dprintk("Need to raise frequency, raise to MAX frequency %d !\n", target_freq);
931 }
932
933 if (target_freq > mt_gpufreqs[g_limited_max_id].gpufreq_khz)
934 {
935 /*********************************************
936 * target_freq > limited_freq, need to adjust
937 **********************************************/
938 target_freq = mt_gpufreqs[g_limited_max_id].gpufreq_khz;
939 target_volt = mt_gpufreqs[g_limited_max_id].gpufreq_volt;
940 dprintk("Limit! Target freq %d > Thermal limit frequency %d\n", target_freq, mt_gpufreqs[g_limited_max_id].gpufreq_khz);
941 }
942
943 /************************************************
944 * If /proc command fix the frequency.
945 *************************************************/
946 if(mt_gpufreq_keep_specific_frequency == true)
947 {
948 target_freq = mt_gpufreq_fixed_frequency;
949 target_volt = mt_gpufreq_fixed_voltage;
950 dprintk("Fixed! fixed frequency %d, fixed voltage %d\n", target_freq, target_volt);
951 }
952
953 /************************************************
954 * target frequency == current frequency, skip it
955 *************************************************/
956 if (g_cur_freq == target_freq)
957 {
958 spin_unlock_irqrestore(&mt_gpufreq_lock, flags);
959 dprintk("GPU frequency from %d MHz to %d MHz (skipped) due to same frequency\n", g_cur_freq / 1000, target_freq / 1000);
960 return 0;
961 }
962
963 dprintk("GPU current frequency %d MHz, target frequency %d MHz\n", g_cur_freq / 1000, target_freq / 1000);
964
965 /******************************
966 * set to the target freeuency
967 *******************************/
968 mt_gpufreq_set(g_cur_freq, target_freq, g_cur_volt, target_volt);
969
970 spin_unlock_irqrestore(&mt_gpufreq_lock, flags);
971
972 return 0;
973 }
974
975 /*********************************
976 * early suspend callback function
977 **********************************/
978 void mt_gpufreq_early_suspend(struct early_suspend *h)
979 {
980 mt_gpufreq_state_set(0);
981
982 if(mt_gpufreq_enable_mainpll == 1)
983 {
984 disable_pll(MAINPLL, "GPU_DVFS");
985 mt_gpufreq_enable_mainpll = 0;
986 }
987
988 if(mt_gpufreq_enable_mmpll == 1)
989 {
990 disable_pll(MMPLL, "GPU_DVFS");
991 mt_gpufreq_enable_mmpll = 0;
992 }
993 }
994
995 /*******************************
996 * late resume callback function
997 ********************************/
998 void mt_gpufreq_late_resume(struct early_suspend *h)
999 {
1000 mt_gpufreq_check_freq_and_set_pll();
1001
1002 mt_gpufreq_state_set(1);
1003 }
1004
1005 /************************************************
1006 * frequency adjust interface for thermal protect
1007 *************************************************/
1008 /******************************************************
1009 * parameter: target power
1010 *******************************************************/
1011 void mt_gpufreq_thermal_protect(unsigned int limited_power)
1012 {
1013 int i = 0;
1014 unsigned int limited_freq = 0;
1015
1016 if (mt_gpufreqs_num == 0)
1017 return;
1018
1019 if (limited_power == 0)
1020 {
1021 g_limited_max_id = 0;
1022 }
1023 else
1024 {
1025 g_limited_max_id = mt_gpufreqs_num - 1;
1026
1027 for (i = 0; i < ARRAY_SIZE(mt_gpufreqs_golden_power); i++)
1028 {
1029 if (mt_gpufreqs_golden_power[i].gpufreq_power <= limited_power)
1030 {
1031 limited_freq = mt_gpufreqs_golden_power[i].gpufreq_khz;
1032 break;
1033 }
1034 }
1035
1036 for (i = 0; i < mt_gpufreqs_num; i++)
1037 {
1038 if (mt_gpufreqs[i].gpufreq_khz <= limited_freq)
1039 {
1040 g_limited_max_id = i;
1041 break;
1042 }
1043 }
1044 }
1045
1046 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "limit frequency upper bound to id = %d, frequency = %d\n", g_limited_max_id, mt_gpufreqs[g_limited_max_id].gpufreq_khz);
1047 mt_gpufreq_target(g_limited_max_id);
1048
1049 return;
1050 }
1051 EXPORT_SYMBOL(mt_gpufreq_thermal_protect);
1052
1053 /************************************************
1054 * return current GPU frequency
1055 *************************************************/
1056 unsigned int mt_gpufreq_cur_freq(void)
1057 {
1058 dprintk("current GPU frequency is %d MHz\n", g_cur_freq / 1000);
1059 return g_cur_freq;
1060 }
1061 EXPORT_SYMBOL(mt_gpufreq_cur_freq);
1062
1063 /************************************************
1064 * return current GPU loading
1065 *************************************************/
1066 unsigned int mt_gpufreq_cur_load(void)
1067 {
1068 dprintk("current GPU load is %d\n", g_cur_load);
1069 return g_cur_load;
1070 }
1071 EXPORT_SYMBOL(mt_gpufreq_cur_load);
1072
1073 /******************************
1074 * show current GPU DVFS stauts
1075 *******************************/
1076 static int mt_gpufreq_state_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
1077 {
1078 int len = 0;
1079 char *p = buf;
1080
1081 if (!mt_gpufreq_pause)
1082 p += sprintf(p, "GPU DVFS enabled\n");
1083 else
1084 p += sprintf(p, "GPU DVFS disabled\n");
1085
1086 len = p - buf;
1087 return len;
1088 }
1089
1090 /****************************************
1091 * set GPU DVFS stauts by sysfs interface
1092 *****************************************/
1093 static ssize_t mt_gpufreq_state_write(struct file *file, const char *buffer, unsigned long count, void *data)
1094 {
1095 int enabled = 0;
1096
1097 /* If 3D not registered, it need to init timer and create kthread. */
1098 if((mt_gpufreq_registered == false) && (mt_gpufreq_registered_statewrite == false))
1099 {
1100 mt_gpufreq_pause = true;
1101
1102 mt_gpufreqs = kzalloc((1) * sizeof(struct mt_gpufreq_info), GFP_KERNEL);
1103 mt_gpufreqs[0].gpufreq_khz = g_cur_freq;
1104 mt_gpufreqs[0].gpufreq_lower_bound = 0;
1105 mt_gpufreqs[0].gpufreq_upper_bound = 100;
1106 mt_gpufreqs[0].gpufreq_volt = 0;
1107 mt_gpufreqs[0].gpufreq_remap = 100;
1108 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[0].gpufreq_khz = %u\n", mt_gpufreqs[0].gpufreq_khz);
1109 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[0].gpufreq_lower_bound = %u\n", mt_gpufreqs[0].gpufreq_lower_bound);
1110 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[0].gpufreq_upper_bound = %u\n", mt_gpufreqs[0].gpufreq_upper_bound);
1111 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[0].gpufreq_volt = %u\n", mt_gpufreqs[0].gpufreq_volt);
1112 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "freqs[0].gpufreq_remap = %u\n", mt_gpufreqs[0].gpufreq_remap);
1113
1114 mt_gpufreq_timer.function = mt_gpufreq_timer_func;
1115 mt_gpufreq_thread = kthread_run(mt_gpufreq_thread_handler, 0, "mt_gpufreq");
1116 if (IS_ERR(mt_gpufreq_thread))
1117 {
1118 printk("[%s]: failed to create mt_gpufreq thread\n", __FUNCTION__);
1119 }
1120 mt_gpufreq_registered_statewrite = true;
1121 }
1122
1123 if (sscanf(buffer, "%d", &enabled) == 1)
1124 {
1125 if (enabled == 1)
1126 {
1127 mt_gpufreq_keep_max_frequency = false;
1128 mt_gpufreq_state_set(1);
1129 }
1130 else if (enabled == 0)
1131 {
1132 /* Keep MAX frequency when GPU DVFS disabled. */
1133 mt_gpufreq_keep_max_frequency = true;
1134 mt_gpufreq_target(g_gpufreq_max_id);
1135 mt_gpufreq_state_set(0);
1136 }
1137 else
1138 {
1139 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! argument should be \"1\" or \"0\"\n");
1140 }
1141 }
1142 else
1143 {
1144 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! argument should be \"1\" or \"0\"\n");
1145 }
1146
1147 return count;
1148 }
1149
1150 /****************************
1151 * show current limited power
1152 *****************************/
1153 static int mt_gpufreq_limited_power_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
1154 {
1155 int len = 0;
1156 char *p = buf;
1157
1158 p += sprintf(p, "g_limited_max_id = %d, frequency = %d\n", g_limited_max_id, mt_gpufreqs[g_limited_max_id].gpufreq_khz);
1159
1160 len = p - buf;
1161 return len;
1162 }
1163
1164 /**********************************
1165 * limited power for thermal protect
1166 ***********************************/
1167 static ssize_t mt_gpufreq_limited_power_write(struct file *file, const char *buffer, unsigned long count, void *data)
1168 {
1169 unsigned int power = 0;
1170
1171 if (sscanf(buffer, "%u", &power) == 1)
1172 {
1173 mt_gpufreq_thermal_protect(power);
1174 return count;
1175 }
1176 else
1177 {
1178 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! please provide the maximum limited power\n");
1179 }
1180
1181 return -EINVAL;
1182 }
1183
1184 /***************************
1185 * show current debug status
1186 ****************************/
1187 static int mt_gpufreq_debug_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
1188 {
1189 int len = 0;
1190 char *p = buf;
1191
1192 if (mt_gpufreq_debug)
1193 p += sprintf(p, "gpufreq debug enabled\n");
1194 else
1195 p += sprintf(p, "gpufreq debug disabled\n");
1196
1197 len = p - buf;
1198 return len;
1199 }
1200
1201 /***********************
1202 * enable debug message
1203 ************************/
1204 static ssize_t mt_gpufreq_debug_write(struct file *file, const char *buffer, unsigned long count, void *data)
1205 {
1206 int debug = 0;
1207
1208 if (sscanf(buffer, "%d", &debug) == 1)
1209 {
1210 if (debug == 0)
1211 {
1212 mt_gpufreq_debug = 0;
1213 return count;
1214 }
1215 else if (debug == 1)
1216 {
1217 mt_gpufreq_debug = 1;
1218 return count;
1219 }
1220 else
1221 {
1222 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! should be 0 or 1 [0: disable, 1: enable]\n");
1223 }
1224 }
1225 else
1226 {
1227 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! should be 0 or 1 [0: disable, 1: enable]\n");
1228 }
1229
1230 return -EINVAL;
1231 }
1232
1233 /********************
1234 * show sampling rate
1235 *********************/
1236 static int mt_gpufreq_sampling_rate_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
1237 {
1238 int len = 0;
1239 char *p = buf;
1240
1241 p += sprintf(p, "get sampling rate = %d (s) %d (ns)\n", mt_gpufreq_sample_s, mt_gpufreq_sample_ns);
1242
1243 len = p - buf;
1244 return len;
1245 }
1246
1247 /********************
1248 * set sampling rate
1249 *********************/
1250 static ssize_t mt_gpufreq_sampling_rate_write(struct file *file, const char *buffer, unsigned long count, void *data)
1251 {
1252 int len = 0, s = 0, ns = 0;
1253 char desc[32];
1254
1255 len = (count < (sizeof(desc) - 1)) ? count : (sizeof(desc) - 1);
1256 if (copy_from_user(desc, buffer, len))
1257 {
1258 return 0;
1259 }
1260 desc[len] = '\0';
1261
1262 if (sscanf(desc, "%d %d", &s, &ns) == 2)
1263 {
1264 printk("[%s]: set sampling rate = %d (s), %d (ns)\n", __FUNCTION__, s, ns);
1265 mt_gpufreq_sample_s = s;
1266 mt_gpufreq_sample_ns = ns;
1267 return count;
1268 }
1269 else
1270 {
1271 printk("[%s]: bad argument!! should be \"[s]\" or \"[ns]\"\n", __FUNCTION__);
1272 }
1273
1274 return -EINVAL;
1275 }
1276
1277 /********************
1278 * show GPU OPP table
1279 *********************/
1280 static int mt_gpufreq_opp_dump_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
1281 {
1282 int i = 0, j = 0, len = 0;
1283 char *p = buf;
1284
1285 for (i = 0; i < mt_gpufreqs_num; i++)
1286 {
1287 p += sprintf(p, "[%d] ", i);
1288 p += sprintf(p, "freq = %d, ", mt_gpufreqs[i].gpufreq_khz);
1289 p += sprintf(p, "lower_bound = %d, ", mt_gpufreqs[i].gpufreq_lower_bound);
1290 p += sprintf(p, "upper_bound = %d, ", mt_gpufreqs[i].gpufreq_upper_bound);
1291 p += sprintf(p, "volt = %d, ", mt_gpufreqs[i].gpufreq_volt);
1292 p += sprintf(p, "remap = %d, ", mt_gpufreqs[i].gpufreq_remap);
1293
1294 for (j = 0; j < ARRAY_SIZE(mt_gpufreqs_golden_power); j++)
1295 {
1296 if (mt_gpufreqs_golden_power[j].gpufreq_khz == mt_gpufreqs[i].gpufreq_khz)
1297 {
1298 p += sprintf(p, "power = %d\n", mt_gpufreqs_golden_power[j].gpufreq_power);
1299 break;
1300 }
1301 }
1302 }
1303
1304 len = p - buf;
1305 return len;
1306 }
1307
1308 /***************************
1309 * show current specific frequency status
1310 ****************************/
1311 static int mt_gpufreq_fixed_frequency_read(char *buf, char **start, off_t off, int count, int *eof, void *data)
1312 {
1313 int len = 0;
1314 char *p = buf;
1315
1316 if (mt_gpufreq_keep_specific_frequency)
1317 p += sprintf(p, "gpufreq fixed frequency enabled\n");
1318 else
1319 p += sprintf(p, "gpufreq fixed frequency disabled\n");
1320
1321 len = p - buf;
1322 return len;
1323 }
1324
1325 /***********************
1326 * enable specific frequency
1327 ************************/
1328 static ssize_t mt_gpufreq_fixed_frequency_write(struct file *file, const char *buffer, unsigned long count, void *data)
1329 {
1330 int enable = 0;
1331 int fixed_freq = 0;
1332 int fixed_volt = 0;
1333
1334 if (sscanf(buffer, "%d %d %d", &enable, &fixed_freq, &fixed_volt) == 3)
1335 {
1336 if (enable == 0)
1337 {
1338 mt_gpufreq_keep_specific_frequency = false;
1339 return count;
1340 }
1341 else if (enable == 1)
1342 {
1343 mt_gpufreq_keep_specific_frequency = true;
1344 mt_gpufreq_fixed_frequency = fixed_freq;
1345 mt_gpufreq_fixed_voltage = fixed_volt;
1346 return count;
1347 }
1348 else
1349 {
1350 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! should be [enable fixed_freq fixed_volt]\n");
1351 }
1352 }
1353 else
1354 {
1355 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! should be [enable fixed_freq fixed_volt]\n");
1356 }
1357
1358 return -EINVAL;
1359 }
1360
1361 /********************
1362 * show variable dump
1363 *********************/
1364 static int mt_gpufreq_var_dump(char *buf, char **start, off_t off, int count, int *eof, void *data)
1365 {
1366 int len = 0;
1367 char *p = buf;
1368
1369 unsigned int clk_cfg_0 = 0;
1370 clk_cfg_0 = DRV_Reg32(CLK_CFG_0);
1371 clk_cfg_0 = (clk_cfg_0 & 0x00070000) >> 16;
1372 p += sprintf(p, "clk_cfg_0 = %d\n", clk_cfg_0);
1373 p += sprintf(p, "pmic_get_gpu_status_bit_info() = %d\n", pmic_get_gpu_status_bit_info());
1374 p += sprintf(p, "mt_gpufreq_enable_mainpll = %d\n", mt_gpufreq_enable_mainpll);
1375 p += sprintf(p, "mt_gpufreq_enable_mmpll = %d\n", mt_gpufreq_enable_mmpll);
1376
1377 p += sprintf(p, "g_cur_freq_init_keep = %d\n", g_cur_freq_init_keep);
1378 p += sprintf(p, "g_volt_set_init_step_1 = %d, g_volt_set_init_step_2 = %d, g_volt_set_init_step_3 = %d\n", g_volt_set_init_step_1, g_volt_set_init_step_2, g_volt_set_init_step_3);
1379 p += sprintf(p, "g_freq_new_init_keep = %d, g_volt_new_init_keep = %d\n", g_freq_new_init_keep, g_volt_new_init_keep);
1380 p += sprintf(p, "mt_gpufreq_registered = %d, mt_gpufreq_already_non_registered = %d\n", mt_gpufreq_registered, mt_gpufreq_already_non_registered);
1381
1382 len = p - buf;
1383 return len;
1384 }
1385
1386 #ifdef GPU_CLOCK_RATIO
1387 /**********************************
1388 * Clock on ratio with mdelay
1389 ***********************************/
1390 static ssize_t mt_gpufreq_clock_on_ratio_write(struct file *file, const char *buffer, unsigned long count, void *data)
1391 {
1392 unsigned int delay = 0;
1393
1394 if (sscanf(buffer, "%u", &delay) == 1)
1395 {
1396 mt_gpufreq_gpu_clock_ratio(GPU_DVFS_CLOCK_RATIO_ON);
1397 mdelay(delay);
1398 mt_gpufreq_gpu_clock_ratio(GPU_DVFS_CLOCK_RATIO_OFF);
1399
1400 return count;
1401 }
1402 else
1403 {
1404 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "bad argument!! please provide proper mdelay time\n");
1405 }
1406
1407 return -EINVAL;
1408 }
1409 #endif
1410
1411 enum hrtimer_restart mt_gpufreq_timer_func(struct hrtimer *timer)
1412 {
1413 mt_gpufreq_timer_flag = 1; wake_up_interruptible(&mt_gpufreq_timer_waiter);
1414
1415 return HRTIMER_NORESTART;
1416 }
1417
1418 static int mt_gpufreq_thread_handler(void *unused)
1419 {
1420 int idx = 0;
1421 unsigned int load = 0;
1422
1423 do
1424 {
1425 ktime_t ktime = ktime_set(mt_gpufreq_sample_s, mt_gpufreq_sample_ns);
1426
1427 wait_event_interruptible(mt_gpufreq_timer_waiter, mt_gpufreq_timer_flag != 0);
1428 mt_gpufreq_timer_flag = 0;
1429
1430 /**********************************
1431 * get GPU loading
1432 ***********************************/
1433 #ifdef GPU_CLOCK_RATIO
1434 load = mt_gpufreq_gpu_clock_ratio(GPU_DVFS_CLOCK_RATIO_GET);
1435 #endif
1436
1437 idx = mt_gpufreq_look_up(load);
1438
1439 mt_gpufreq_target(idx);
1440
1441 if(mt_gpufreq_pause == false)
1442 hrtimer_start(&mt_gpufreq_timer, ktime, HRTIMER_MODE_REL);
1443
1444 } while (!kthread_should_stop());
1445
1446 return 0;
1447 }
1448
1449 /*********************************
1450 * mediatek gpufreq registration
1451 **********************************/
1452 int mt_gpufreq_register(struct mt_gpufreq_info *freqs, int num)
1453 {
1454 if(mt_gpufreq_registered == false)
1455 {
1456 ktime_t ktime = ktime_set(mt_gpufreq_sample_s, mt_gpufreq_sample_ns);
1457
1458 mt_gpufreq_registered = true;
1459
1460 #ifdef CONFIG_HAS_EARLYSUSPEND
1461 mt_gpufreq_early_suspend_handler.suspend = mt_gpufreq_early_suspend;
1462 mt_gpufreq_early_suspend_handler.resume = mt_gpufreq_late_resume;
1463 register_early_suspend(&mt_gpufreq_early_suspend_handler);
1464 #endif
1465
1466 /**********************
1467 * setup gpufreq table
1468 ***********************/
1469 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "setup gpufreqs table\n");
1470
1471 mt_setup_gpufreqs_table(freqs, num);
1472
1473 /************************************
1474 * launch a timer for period sampling
1475 *************************************/
1476 hrtimer_init(&mt_gpufreq_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1477 mt_gpufreq_timer.function = mt_gpufreq_timer_func;
1478
1479 mt_gpufreq_thread = kthread_run(mt_gpufreq_thread_handler, 0, "mt_gpufreq");
1480 if (IS_ERR(mt_gpufreq_thread))
1481 {
1482 printk("[%s]: failed to create mt_gpufreq thread\n", __FUNCTION__);
1483 }
1484
1485 #ifdef GPU_DVFS_DEFAULT_DISABLED
1486 mt_gpufreq_state_set(0);
1487 #endif
1488
1489 if(mt_gpufreq_pause == false)
1490 {
1491 hrtimer_start(&mt_gpufreq_timer, ktime, HRTIMER_MODE_REL);
1492 #ifdef GPU_CLOCK_RATIO
1493 mt_gpufreq_period_time_reset();
1494 #endif
1495 }
1496
1497 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mediatek gpufreq registration done\n");
1498 }
1499 else
1500 {
1501 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mediatek gpufreq already registered !\n");
1502 }
1503 return 0;
1504 }
1505 EXPORT_SYMBOL(mt_gpufreq_register);
1506
1507 /*********************************
1508 * mediatek gpufreq non registration
1509 **********************************/
1510 int mt_gpufreq_non_register(void)
1511 {
1512 if(mt_gpufreq_already_non_registered == false)
1513 {
1514 mt_gpufreq_already_non_registered = true;
1515 mt_setup_gpufreqs_default_power_table(1);
1516
1517 hrtimer_init(&mt_gpufreq_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1518 mt_gpufreq_state_set(0);
1519 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_non_register() done\n");
1520 }
1521 else
1522 {
1523 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_non_register() already called !\n");
1524 }
1525 return 0;
1526 }
1527 EXPORT_SYMBOL(mt_gpufreq_non_register);
1528
1529 /**********************************
1530 * mediatek gpufreq initialization
1531 ***********************************/
1532 static int __init mt_gpufreq_init(void)
1533 {
1534 struct proc_dir_entry *mt_entry = NULL;
1535 struct proc_dir_entry *mt_gpufreq_dir = NULL;
1536 unsigned int clk_cfg_0 = 0;
1537
1538 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_init\n");
1539
1540 mt_gpufreq_dir = proc_mkdir("gpufreq", NULL);
1541 if (!mt_gpufreq_dir)
1542 {
1543 pr_err("[%s]: mkdir /proc/gpufreq failed\n", __FUNCTION__);
1544 }
1545 else
1546 {
1547 mt_entry = create_proc_entry("gpufreq_debug", S_IRUGO | S_IWUSR | S_IWGRP, mt_gpufreq_dir);
1548 if (mt_entry)
1549 {
1550 mt_entry->read_proc = mt_gpufreq_debug_read;
1551 mt_entry->write_proc = mt_gpufreq_debug_write;
1552 }
1553
1554 mt_entry = create_proc_entry("gpufreq_limited_power", S_IRUGO | S_IWUSR | S_IWGRP, mt_gpufreq_dir);
1555 if (mt_entry)
1556 {
1557 mt_entry->read_proc = mt_gpufreq_limited_power_read;
1558 mt_entry->write_proc = mt_gpufreq_limited_power_write;
1559 }
1560
1561 mt_entry = create_proc_entry("gpufreq_state", S_IRUGO | S_IWUSR | S_IWGRP, mt_gpufreq_dir);
1562 if (mt_entry)
1563 {
1564 mt_entry->read_proc = mt_gpufreq_state_read;
1565 mt_entry->write_proc = mt_gpufreq_state_write;
1566 }
1567
1568 mt_entry = create_proc_entry("gpufreq_sampling_rate", S_IRUGO | S_IWUSR | S_IWGRP, mt_gpufreq_dir);
1569 if (mt_entry)
1570 {
1571 mt_entry->read_proc = mt_gpufreq_sampling_rate_read;
1572 mt_entry->write_proc = mt_gpufreq_sampling_rate_write;
1573 }
1574
1575 mt_entry = create_proc_entry("gpufreq_opp_dump", S_IRUGO, mt_gpufreq_dir);
1576 if (mt_entry)
1577 {
1578 mt_entry->read_proc = mt_gpufreq_opp_dump_read;
1579 }
1580
1581 #ifdef GPU_CLOCK_RATIO
1582 mt_entry = create_proc_entry("gpufreq_clock_on", S_IRUGO | S_IWUSR | S_IWGRP, mt_gpufreq_dir);
1583 if (mt_entry)
1584 {
1585 mt_entry->write_proc = mt_gpufreq_clock_on_ratio_write;
1586 }
1587 #endif
1588
1589 mt_entry = create_proc_entry("gpufreq_fix_frequency", S_IRUGO | S_IWUSR | S_IWGRP, mt_gpufreq_dir);
1590 if (mt_entry)
1591 {
1592 mt_entry->read_proc = mt_gpufreq_fixed_frequency_read;
1593 mt_entry->write_proc = mt_gpufreq_fixed_frequency_write;
1594 }
1595
1596 mt_entry = create_proc_entry("gpufreq_var_dump", S_IRUGO | S_IWUSR | S_IWGRP, mt_gpufreq_dir);
1597 if (mt_entry)
1598 {
1599 mt_entry->read_proc = mt_gpufreq_var_dump;
1600 }
1601 }
1602
1603 clk_cfg_0 = DRV_Reg32(CLK_CFG_0);
1604 clk_cfg_0 = (clk_cfg_0 & 0x00070000) >> 16;
1605
1606 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_init, clk_cfg_0 = %d\n", clk_cfg_0);
1607
1608 switch (clk_cfg_0)
1609 {
1610 case 0x5: // 476Mhz
1611 g_cur_freq = GPU_MMPLL_D3;
1612 break;
1613 case 0x2: // 403Mhz
1614 g_cur_freq = GPU_SYSPLL_D2;
1615 break;
1616 case 0x6: // 357Mhz
1617 g_cur_freq = GPU_MMPLL_D4;
1618 break;
1619 case 0x4: // 312Mhz
1620 g_cur_freq = GPU_UNIVPLL1_D2;
1621 break;
1622 case 0x7: // 286Mhz
1623 g_cur_freq = GPU_MMPLL_D5;
1624 break;
1625 case 0x3: // 268Mhz
1626 g_cur_freq = GPU_SYSPLL_D3;
1627 break;
1628 case 0x1: // 238Mhz
1629 g_cur_freq = GPU_MMPLL_D6;
1630 break;
1631 case 0x0: // 156Mhz
1632 g_cur_freq = GPU_UNIVPLL1_D4;
1633 break;
1634 default:
1635 break;
1636 }
1637
1638 g_cur_freq_init_keep = g_cur_freq;
1639 xlog_printk(ANDROID_LOG_INFO, "Power/GPU_DVFS", "mt_gpufreq_init, g_cur_freq_init_keep = %d\n", g_cur_freq_init_keep);
1640
1641 return 0;
1642 }
1643
1644 static void __exit mt_gpufreq_exit(void)
1645 {
1646
1647 }
1648
1649 module_init(mt_gpufreq_init);
1650 module_exit(mt_gpufreq_exit);
1651
1652 MODULE_DESCRIPTION("MediaTek GPU Frequency Scaling driver");
1653 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)