1 #include <linux/kernel.h>
4 #include <mach/mt_reg_base.h>
5 #include <mach/mt_emi_bm.h>
6 #include <mach/sync_write.h>
7 #include <mach/mt_typedefs.h>
9 static unsigned char g_cBWL
;
16 * make sure BW limiter counts consumed Soft-mode bandwidth of each master
18 if (readl(IOMEM(EMI_ARBA
)) & 0x00008000) {
20 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBA
)) & ~0x00008000, EMI_ARBA
);
23 if (readl(IOMEM(EMI_ARBB
)) & 0x00008000) {
25 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBB
)) & ~0x00008000, EMI_ARBB
);
28 if (readl(IOMEM(EMI_ARBC
)) & 0x00008000) {
30 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBC
)) & ~0x00008000, EMI_ARBC
);
33 if (readl(IOMEM(EMI_ARBD
)) & 0x00008000) {
35 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBD
)) & ~0x00008000, EMI_ARBD
);
38 if (readl(IOMEM(EMI_ARBE
)) & 0x00008000) {
40 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBE
)) & ~0x00008000, EMI_ARBE
);
47 if (g_cBWL
& (1 << 0)) {
49 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBA
)) | 0x00008000, EMI_ARBA
);
52 if (g_cBWL
& (1 << 1)) {
54 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBB
)) | 0x00008000, EMI_ARBB
);
57 if (g_cBWL
& (1 << 2)) {
59 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBC
)) | 0x00008000, EMI_ARBC
);
62 if (g_cBWL
& (1 << 3)) {
64 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBD
)) | 0x00008000, EMI_ARBD
);
67 if (g_cBWL
& (1 << 4)) {
69 mt65xx_reg_sync_writel(readl(IOMEM(EMI_ARBE
)) | 0x00008000, EMI_ARBE
);
74 void BM_Enable(const unsigned int enable
)
76 const unsigned int value
= readl(IOMEM(EMI_BMEN
));
78 mt65xx_reg_sync_writel((value
& ~(BUS_MON_PAUSE
| BUS_MON_EN
)) | (enable
? BUS_MON_EN
: 0), EMI_BMEN
);
84 const unsigned int value = readl(EMI_BMEN);
86 mt65xx_reg_sync_writel(value & (~BUS_MON_EN), EMI_BMEN);
92 const unsigned int value
= readl(IOMEM(EMI_BMEN
));
94 mt65xx_reg_sync_writel(value
| BUS_MON_PAUSE
, EMI_BMEN
);
97 void BM_Continue(void)
99 const unsigned int value
= readl(IOMEM(EMI_BMEN
));
101 mt65xx_reg_sync_writel(value
& (~BUS_MON_PAUSE
), EMI_BMEN
);
104 unsigned int BM_IsOverrun(void)
107 * return 0 if EMI_BCNT(bus cycle counts) or EMI_WACT(total word counts) is overrun,
108 * otherwise return an !0 value
110 const unsigned int value
= readl(IOMEM(EMI_BMEN
));
112 return (value
& BC_OVERRUN
);
115 void BM_SetReadWriteType(const unsigned int ReadWriteType
)
117 const unsigned int value
= readl(IOMEM(EMI_BMEN
));
120 * ReadWriteType: 00/11 --> both R/W
124 mt65xx_reg_sync_writel((value
& 0xFFFFFFCF) | (ReadWriteType
<< 4), EMI_BMEN
);
127 int BM_GetBusCycCount(void)
129 return BM_IsOverrun() ? BM_ERR_OVERRUN
: readl(IOMEM(EMI_BCNT
));
132 unsigned int BM_GetTransAllCount(void)
134 return readl(IOMEM(EMI_TACT
));
137 int BM_GetTransCount(const unsigned int counter_num
)
141 switch (counter_num
) {
143 iCount
= readl(IOMEM(EMI_TSCT
));
147 iCount
= readl(IOMEM(EMI_TSCT2
));
151 iCount
= readl(IOMEM(EMI_TSCT3
));
155 return BM_ERR_WRONG_REQ
;
161 int BM_GetWordAllCount(void)
163 return BM_IsOverrun() ? BM_ERR_OVERRUN
: readl(IOMEM(EMI_WACT
));
166 int BM_GetWordCount(const unsigned int counter_num
)
170 switch (counter_num
) {
172 iCount
= readl(IOMEM(EMI_WSCT
));
176 iCount
= readl(IOMEM(EMI_WSCT2
));
180 iCount
= readl(IOMEM(EMI_WSCT3
));
184 iCount
= readl(IOMEM(EMI_WSCT4
));
188 return BM_ERR_WRONG_REQ
;
194 unsigned int BM_GetBandwidthWordCount(void)
196 return readl(IOMEM(EMI_BACT
));
199 unsigned int BM_GetOverheadWordCount(void)
201 return readl(IOMEM(EMI_BSCT
));
204 int BM_GetTransTypeCount(const unsigned int counter_num
)
206 return (counter_num
< 1 || counter_num
> BM_COUNTER_MAX
) ? BM_ERR_WRONG_REQ
: readl(IOMEM(EMI_TTYPE1
+ (counter_num
- 1) * 8));
209 int BM_SetMonitorCounter(const unsigned int counter_num
, const unsigned int master
, const unsigned int trans_type
)
211 unsigned int value
, addr
;
212 const unsigned int iMask
= 0xFF7F;
214 if (counter_num
< 1 || counter_num
> BM_COUNTER_MAX
) {
215 return BM_ERR_WRONG_REQ
;
218 if (counter_num
== 1) {
220 value
= (readl(IOMEM(addr
)) & ~(iMask
<< 16)) | ((trans_type
& 0xFF) << 24) | ((master
& 0x7F) << 16);
222 addr
= (counter_num
<= 3) ? EMI_MSEL
: (EMI_MSEL2
+ (counter_num
/ 2 - 2) * 8);
224 // clear master and transaction type fields
225 value
= readl(IOMEM(addr
)) & ~(iMask
<< ((counter_num
% 2) * 16));
227 // set master and transaction type fields
228 value
|= (((trans_type
& 0xFF) << 8) | (master
& 0x7F)) << ((counter_num
% 2) * 16);
231 mt65xx_reg_sync_writel(value
, addr
);
236 int BM_SetMaster(const unsigned int counter_num
, const unsigned int master
)
238 unsigned int value
, addr
;
239 const unsigned int iMask
= 0x7F;
241 if (counter_num
< 1 || counter_num
> BM_COUNTER_MAX
) {
242 return BM_ERR_WRONG_REQ
;
245 if (counter_num
== 1) {
247 value
= (readl(IOMEM(addr
)) & ~(iMask
<< 16)) | ((master
& iMask
) << 16);
249 addr
= (counter_num
<= 3) ? EMI_MSEL
: (EMI_MSEL2
+ (counter_num
/ 2 - 2) * 8);
251 // clear master and transaction type fields
252 value
= readl(IOMEM(addr
)) & ~(iMask
<< ((counter_num
% 2) * 16));
254 // set master and transaction type fields
255 value
|= ((master
& iMask
) << ((counter_num
% 2) * 16));
258 mt65xx_reg_sync_writel(value
, addr
);
263 int BM_SetIDSelect(const unsigned int counter_num
, const unsigned int id
, const unsigned int enable
)
265 unsigned int value
, addr
, shift_num
;
267 if ((counter_num
< 1 || counter_num
> BM_COUNTER_MAX
)
270 return BM_ERR_WRONG_REQ
;
273 addr
= EMI_BMID0
+ (counter_num
- 1) / 4 * 8;
275 // field's offset in the target EMI_BMIDx register
276 shift_num
= ((counter_num
- 1) % 4) * 8;
278 // clear SELx_ID field
279 value
= readl(IOMEM(addr
)) & ~(0xFF << shift_num
);
282 value
|= id
<< shift_num
;
284 mt65xx_reg_sync_writel(value
, addr
);
286 value
= (readl(IOMEM(EMI_BMEN2
)) & ~(1 << (counter_num
- 1))) | (enable
<< (counter_num
- 1));
291 int BM_SetUltraHighFilter(const unsigned int counter_num
, const unsigned int enable
)
295 if ((counter_num
< 1 || counter_num
> BM_COUNTER_MAX
)
297 return BM_ERR_WRONG_REQ
;
300 value
= (readl(IOMEM(EMI_BMEN1
)) & ~(1 << (counter_num
- 1))) | (enable
<< (counter_num
- 1));
302 mt65xx_reg_sync_writel(value
, EMI_BMEN1
);
307 int BM_SetLatencyCounter(void)
310 value
= readl(IOMEM(EMI_BMEN2
)) & ~(0b11 << 24);
311 //emi_ttype1 -- emi_ttype7 change as total latencies for m0 -- m6, and emi_ttype9 -- emi_ttype15 change as total transaction counts for m0 -- m6
312 value
|= (0b10 << 24);
313 mt65xx_reg_sync_writel(value
, EMI_BMEN2
);
317 int BM_GetLatencyCycle(const unsigned int counter_num
)
319 unsigned int cycle_count
;
324 cycle_count
= readl(IOMEM(EMI_TTYPE1
));
327 cycle_count
= readl(IOMEM(EMI_TTYPE2
));
330 cycle_count
= readl(IOMEM(EMI_TTYPE3
));
333 cycle_count
= readl(IOMEM(EMI_TTYPE4
));
336 cycle_count
= readl(IOMEM(EMI_TTYPE5
));
339 cycle_count
= readl(IOMEM(EMI_TTYPE9
));
342 cycle_count
= readl(IOMEM(EMI_TTYPE10
));
345 cycle_count
= readl(IOMEM(EMI_TTYPE11
));
348 cycle_count
= readl(IOMEM(EMI_TTYPE12
));
351 cycle_count
= readl(IOMEM(EMI_TTYPE13
));
354 return BM_ERR_WRONG_REQ
;
359 int BM_GetEmiDcm(void)
361 return ((readl(IOMEM(EMI_CONM
)) >> 24) ? 1 : 0);
364 int BM_SetEmiDcm(const unsigned int setting
)
368 value
= readl(IOMEM(EMI_CONM
));
369 mt65xx_reg_sync_writel( (value
& 0x00FFFFFF) | (setting
<< 24), EMI_CONM
);
374 unsigned int DRAMC_GetPageHitCount(DRAMC_Cnt_Type CountType
)
380 iCount
= readl(IOMEM(DRAMC_R2R_PAGE_HIT
));
384 iCount
= readl(IOMEM(DRAMC_R2W_PAGE_HIT
));
388 iCount
= readl(IOMEM(DRAMC_W2R_PAGE_HIT
));
392 iCount
= readl(IOMEM(DRAMC_W2W_PAGE_HIT
));
395 iCount
= readl(IOMEM(DRAMC_R2R_PAGE_HIT
)) + readl(IOMEM(DRAMC_R2W_PAGE_HIT
)) +
396 readl(IOMEM(DRAMC_W2R_PAGE_HIT
)) + readl(IOMEM(DRAMC_W2W_PAGE_HIT
));
399 return BM_ERR_WRONG_REQ
;
405 unsigned int DRAMC_GetPageMissCount(DRAMC_Cnt_Type CountType
)
411 iCount
= readl(IOMEM(DRAMC_R2R_PAGE_MISS
));
415 iCount
= readl(IOMEM(DRAMC_R2W_PAGE_MISS
));
419 iCount
= readl(IOMEM(DRAMC_W2R_PAGE_MISS
));
423 iCount
= readl(IOMEM(DRAMC_W2W_PAGE_MISS
));
426 iCount
= readl(IOMEM(DRAMC_R2R_PAGE_MISS
)) + readl(IOMEM(DRAMC_R2W_PAGE_MISS
)) +
427 readl(IOMEM(DRAMC_W2R_PAGE_MISS
)) + readl(IOMEM(DRAMC_W2W_PAGE_MISS
));
430 return BM_ERR_WRONG_REQ
;
436 unsigned int DRAMC_GetInterbankCount(DRAMC_Cnt_Type CountType
)
442 iCount
= readl(IOMEM(DRAMC_R2R_INTERBANK
));
446 iCount
= readl(IOMEM(DRAMC_R2W_INTERBANK
));
450 iCount
= readl(IOMEM(DRAMC_W2R_INTERBANK
));
454 iCount
= readl(IOMEM(DRAMC_W2W_INTERBANK
));
457 iCount
= readl(IOMEM(DRAMC_R2R_INTERBANK
)) + readl(IOMEM(DRAMC_R2W_INTERBANK
)) +
458 readl(IOMEM(DRAMC_W2R_INTERBANK
)) + readl(IOMEM(DRAMC_W2W_INTERBANK
));
461 return BM_ERR_WRONG_REQ
;
467 unsigned int DRAMC_GetIdleCount(void)
469 return readl(IOMEM(DRAMC_IDLE_COUNT
));