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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / kr076_nand / touchpanel / gt9xx_update.c
1 /* drivers/input/touchscreen/gt9xx_update.c
2 *
3 * 2010 - 2012 Goodix Technology.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be a reference
11 * to you, when you are integrating the GOODiX's CTP IC into your system,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * Version: 2.2
17 * Revision Record:
18 * V1.0: first release. by Andrew, 2012/08/27.
19 * V1.2: modify gt9110p pid map, by Andrew, 2012/10/15
20 * V1.4:
21 * 1. modify gup_enter_update_mode,
22 * 2. rewrite i2c read/write func
23 * 3. check update file checksum
24 * by Andrew, 2012/12/12
25 * v1.6:
26 * 1. delete GTP_FW_DOWNLOAD related things.
27 * 2. add GTP_HEADER_FW_UPDATE switch to update fw by gtp_default_fw in *.h directly
28 * by Meta, 2013/04/18
29 * V2.0:
30 * 1. GT9XXF main clock calibration
31 * 2. header fw update no fs related
32 * 3. update file searching optimization
33 * 4. config update as module, switchable
34 * by Meta, 2013/08/28
35 * V2.2:
36 * 1. multi-system supported
37 * 2. flashless update no pid vid compare
38 * By Meta, 2014/01/14
39 * V2.2.6:
40 * Special edition for GT910 flashless
41 * 1. firmware check
42 */
43 #include "tpd.h"
44 #include <linux/interrupt.h>
45 #include <cust_eint.h>
46 #include <linux/i2c.h>
47 #include <linux/sched.h>
48 #include <linux/kthread.h>
49 #include <linux/rtpm_prio.h>
50 #include <linux/wait.h>
51 #include <linux/time.h>
52 #include <linux/delay.h>
53 #include <linux/namei.h>
54 #include <linux/mount.h>
55 #include "cust_gpio_usage.h"
56 #include <asm/uaccess.h>
57
58 #include "tpd_custom_gt9xx.h"
59
60 #if ( (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE) || GTP_COMPATIBLE_MODE )
61 #include "gt9xx_firmware.h"
62 #endif
63
64 #define GUP_REG_HW_INFO 0x4220
65 #define GUP_REG_FW_MSG 0x41E4
66 #define GUP_REG_PID_VID 0x8140
67
68 #define GUP_SEARCH_FILE_TIMES 50
69 #define UPDATE_FILE_PATH_1 "/data/_goodix_update_.bin"
70 #define UPDATE_FILE_PATH_2 "/sdcard/_goodix_update_.bin"
71
72 #define CONFIG_FILE_PATH_1 "/data/_goodix_config_.cfg"
73 #define CONFIG_FILE_PATH_2 "/sdcard/_goodix_config_.cfg"
74
75 #define FW_HEAD_LENGTH 14
76 #define FW_DOWNLOAD_LENGTH 0x4000
77 #define FW_SECTION_LENGTH 0x2000
78 #define FW_DSP_ISP_LENGTH 0x1000
79 #define FW_DSP_LENGTH 0x1000
80 #define FW_BOOT_LENGTH 0x800
81 #define FW_SS51_LENGTH (4 * FW_SECTION_LENGTH)
82 #define FW_BOOT_ISP_LENGTH 0x800 // 2k
83 #define FW_GLINK_LENGTH 0x3000 // 12k
84 #define FW_GWAKE_LENGTH (4 * FW_SECTION_LENGTH) // 32k
85
86 #define PACK_SIZE 256
87 #define MAX_FRAME_CHECK_TIME 5
88
89
90 #define _bRW_MISCTL__SRAM_BANK 0x4048
91 #define _bRW_MISCTL__MEM_CD_EN 0x4049
92 #define _bRW_MISCTL__CACHE_EN 0x404B
93 #define _bRW_MISCTL__TMR0_EN 0x40B0
94 #define _rRW_MISCTL__SWRST_B0_ 0x4180
95 #define _bWO_MISCTL__CPU_SWRST_PULSE 0x4184
96 #define _rRW_MISCTL__BOOTCTL_B0_ 0x4190
97 #define _rRW_MISCTL__BOOT_OPT_B0_ 0x4218
98 #define _rRW_MISCTL__BOOT_CTL_ 0x5094
99
100 #define AUTO_SEARCH_BIN 0x01
101 #define AUTO_SEARCH_CFG 0x02
102 #define BIN_FILE_READY 0x80
103 #define CFG_FILE_READY 0x08
104 #define HEADER_FW_READY 0x01
105
106 #pragma pack(1)
107 typedef struct
108 {
109 u8 hw_info[4]; //hardware info//
110 u8 pid[8]; //product id //
111 u16 vid; //version id //
112 } st_fw_head;
113 #pragma pack()
114
115 typedef struct
116 {
117 u8 force_update;
118 u8 fw_flag;
119 struct file *file;
120 struct file *cfg_file;
121 st_fw_head ic_fw_msg;
122 mm_segment_t old_fs;
123 u32 fw_total_len;
124 u32 fw_burned_len;
125 } st_update_msg;
126
127 st_update_msg update_msg;
128 extern struct i2c_client *i2c_client_point;
129 u16 show_len;
130 u16 total_len;
131 extern u8 fw_updating;
132 extern u8 cfg_len;
133 u8 searching_file = 0;
134 u8 got_file_flag = 0;
135
136 #if GTP_ESD_PROTECT
137 extern void gtp_esd_switch(struct i2c_client *client, s32 on);
138 #endif
139
140 #if GTP_COMPATIBLE_MODE
141 extern CHIP_TYPE_T gtp_chip_type;
142 extern u8 rqst_processing;
143 extern u8 is_950;
144 extern u8 after_912_1020;
145 extern u8 gtp_fw_startup(struct i2c_client *client);
146 static u8 gup_check_and_repair(struct i2c_client *, s32 , u8 *, u32 );
147 s32 gup_fw_download_proc(void *dir, u8 dwn_mode);
148
149 #if GTP_FL_LITTLE_SYSTEM
150 extern u8 power_is_down;
151 #endif
152
153 #endif
154
155 #define _CLOSE_FILE(p_file) if (p_file && !IS_ERR(p_file)) \
156 { \
157 filp_close(p_file, NULL); \
158 }
159
160
161 static u8 gup_burn_fw_gwake_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd );
162
163 static s32 gup_i2c_read(struct i2c_client *client, u8 *buf, s32 len)
164 {
165 s32 ret = -1;
166 u16 addr = (buf[0] << 8) + buf[1];
167
168 ret = i2c_read_bytes(client, addr, &buf[2], len - 2);
169
170 if (!ret)
171 {
172 return 2;
173 }
174 else
175 {
176 return ret;
177 }
178 }
179
180 static s32 gup_i2c_write(struct i2c_client *client, u8 *buf, s32 len)
181 {
182 s32 ret = -1;
183 u16 addr = (buf[0] << 8) + buf[1];
184
185 ret = i2c_write_bytes(client, addr, &buf[2], len - 2);
186
187 if (!ret)
188 {
189 return 1;
190 }
191 else
192 {
193 return ret;
194 }
195 }
196
197 static u8 gup_get_ic_msg(struct i2c_client *client, u16 addr, u8 *msg, s32 len)
198 {
199 s32 i = 0;
200
201 msg[0] = (addr >> 8) & 0xff;
202 msg[1] = addr & 0xff;
203
204 for (i = 0; i < 5; i++)
205 {
206 if (gup_i2c_read(client, msg, GTP_ADDR_LENGTH + len) > 0)
207 {
208 break;
209 }
210 }
211
212 if (i >= 5)
213 {
214 GTP_ERROR("Read data from 0x%02x%02x failed!", msg[0], msg[1]);
215 return FAIL;
216 }
217
218 return SUCCESS;
219 }
220
221 static u8 gup_set_ic_msg(struct i2c_client *client, u16 addr, u8 val)
222 {
223 s32 i = 0;
224 u8 msg[3];
225
226 msg[0] = (addr >> 8) & 0xff;
227 msg[1] = addr & 0xff;
228 msg[2] = val;
229
230 for (i = 0; i < 5; i++)
231 {
232 if (gup_i2c_write(client, msg, GTP_ADDR_LENGTH + 1) > 0)
233 {
234 break;
235 }
236 }
237
238 if (i >= 5)
239 {
240 GTP_ERROR("Set data to 0x%02x%02x failed!", msg[0], msg[1]);
241 return FAIL;
242 }
243
244 return SUCCESS;
245 }
246
247 static u8 gup_get_ic_fw_msg(struct i2c_client *client)
248 {
249 s32 ret = -1;
250 u8 retry = 0;
251 u8 buf[16];
252 u8 i;
253
254 //step1:get hardware info
255 ret = gtp_i2c_read_dbl_check(client, GUP_REG_HW_INFO, &buf[GTP_ADDR_LENGTH], 4);
256 if (FAIL == ret)
257 {
258 GTP_ERROR("[get_ic_fw_msg]get hw_info failed,exit");
259 return FAIL;
260 }
261
262 // buf[2~5]: 00 06 90 00
263 // hw_info: 00 90 06 00
264 for (i = 0; i < 4; i++)
265 {
266 update_msg.ic_fw_msg.hw_info[i] = buf[GTP_ADDR_LENGTH + 3 - i];
267 }
268
269 GTP_INFO("IC Hardware info:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
270 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
271
272 //step2:get firmware message
273 for (retry = 0; retry < 2; retry++)
274 {
275 ret = gup_get_ic_msg(client, GUP_REG_FW_MSG, buf, 1);
276
277 if (FAIL == ret)
278 {
279 GTP_ERROR("Read firmware message fail.");
280 return ret;
281 }
282
283 update_msg.force_update = buf[GTP_ADDR_LENGTH];
284
285 if ((0xBE != update_msg.force_update) && (!retry))
286 {
287 GTP_ERROR("The check sum in ic is error.");
288 GTP_INFO("The IC will be updated by force.");
289 continue;
290 }
291 break;
292 }
293
294 GTP_INFO("IC force update flag:0x%x", update_msg.force_update);
295
296 //step3:get pid & vid
297 ret = gtp_i2c_read_dbl_check(client, GUP_REG_PID_VID, &buf[GTP_ADDR_LENGTH], 6);
298 if (FAIL == ret)
299 {
300 GTP_ERROR("[get_ic_fw_msg]get pid & vid failed,exit");
301 return FAIL;
302 }
303
304 memset(update_msg.ic_fw_msg.pid, 0, sizeof(update_msg.ic_fw_msg.pid));
305 memcpy(update_msg.ic_fw_msg.pid, &buf[GTP_ADDR_LENGTH], 4);
306
307
308 //GT9XX PID MAPPING
309 /*|-----FLASH-----RAM-----|
310 |------918------918-----|
311 |------968------968-----|
312 |------913------913-----|
313 |------913P-----913P----|
314 |------927------927-----|
315 |------927P-----927P----|
316 |------9110-----9110----|
317 |------9110P----9111----|*/
318 if(update_msg.ic_fw_msg.pid[0] != 0)
319 {
320 if (!memcmp(update_msg.ic_fw_msg.pid, "9111", 4))
321 {
322 GTP_INFO("IC Mapping Product id:%s", update_msg.ic_fw_msg.pid);
323 memcpy(update_msg.ic_fw_msg.pid, "9110P", 5);
324 }
325 }
326
327 update_msg.ic_fw_msg.vid = buf[GTP_ADDR_LENGTH + 4] + (buf[GTP_ADDR_LENGTH + 5] << 8);
328 return SUCCESS;
329 }
330
331 s32 gup_enter_update_mode(struct i2c_client *client)
332 {
333 s32 ret = -1;
334 s32 retry = 0;
335 u8 rd_buf[3];
336
337 //step1:RST output low last at least 2ms
338 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
339 msleep(2);
340
341 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
342 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
343 msleep(2);
344
345 //step3:RST output high reset guitar
346 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
347
348 //20121211 modify start
349 msleep(5);
350 while(retry++ < 200)
351 {
352 //step4:Hold ss51 & dsp
353 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
354 if(ret <= 0)
355 {
356 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
357 continue;
358 }
359
360 //step5:Confirm hold
361 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
362 if(ret <= 0)
363 {
364 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
365 continue;
366 }
367 if(0x0C == rd_buf[GTP_ADDR_LENGTH])
368 {
369 GTP_DEBUG("Hold ss51 & dsp confirm SUCCESS");
370 break;
371 }
372 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
373 }
374 if(retry >= 200)
375 {
376 GTP_ERROR("Enter update Hold ss51 failed.");
377 return FAIL;
378 }
379
380 //step6:DSP_CK and DSP_ALU_CK PowerOn
381 ret = gup_set_ic_msg(client, 0x4010, 0x00);
382
383 //20121211 modify end
384 return ret;
385 }
386
387 void gup_leave_update_mode(void)
388 {
389 GTP_GPIO_AS_INT(GTP_INT_PORT);
390
391 GTP_DEBUG("[leave_update_mode]reset chip.");
392 gtp_reset_guitar(i2c_client_point, 20);
393 }
394
395 static u8 gup_enter_update_judge(st_fw_head *fw_head)
396 {
397 u16 u16_tmp;
398 s32 i = 0;
399 u32 fw_len = 0;
400 s32 pid_cmp_len = 0;
401 //Get the correct nvram data
402 //The correct conditions:
403 //1. the hardware info is the same
404 //2. the product id is the same
405 //3. the firmware version in update file is greater than the firmware version in ic
406 //or the check sum in ic is wrong
407
408 u16_tmp = fw_head->vid;
409 fw_head->vid = (u16)(u16_tmp >> 8) + (u16)(u16_tmp << 8);
410
411 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
412 GTP_INFO("FILE PID:%s", fw_head->pid);
413 GTP_INFO("FILE VID:%04x", fw_head->vid);
414 GTP_INFO("IC HARDWARE INFO:%02x%02x%02x%02x", update_msg.ic_fw_msg.hw_info[0], update_msg.ic_fw_msg.hw_info[1],
415 update_msg.ic_fw_msg.hw_info[2], update_msg.ic_fw_msg.hw_info[3]);
416 GTP_INFO("IC PID:%s", update_msg.ic_fw_msg.pid);
417 GTP_INFO("IC VID:%04x", update_msg.ic_fw_msg.vid);
418
419 if (!memcmp(fw_head->pid, "9158", 4) && !memcmp(update_msg.ic_fw_msg.pid, "915S", 4))
420 {
421 GTP_INFO("Update GT915S to GT9158 directly!");
422 return SUCCESS;
423 }
424
425 if (!memcmp(fw_head->hw_info, update_msg.ic_fw_msg.hw_info, sizeof(update_msg.ic_fw_msg.hw_info)))
426 {
427 fw_len = 42 * 1024;
428 }
429 else
430 {
431 fw_len = fw_head->hw_info[3];
432 fw_len += (((u32)fw_head->hw_info[2]) << 8);
433 fw_len += (((u32)fw_head->hw_info[1]) << 16);
434 fw_len += (((u32)fw_head->hw_info[0]) << 24);
435 }
436 if (update_msg.fw_total_len != fw_len)
437 {
438 GTP_ERROR("Inconsistent firmware size, Update aborted! Default size: %d(%dK), actual size: %d(%dK)", fw_len, fw_len/1024, update_msg.fw_total_len, update_msg.fw_total_len/1024);
439 return FAIL;
440 }
441 GTP_INFO("Firmware length:%d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
442
443 if (update_msg.force_update != 0xBE)
444 {
445 GTP_INFO("FW chksum error,need enter update.");
446 return SUCCESS;
447 }
448 // 20130523 start
449 if (strlen(update_msg.ic_fw_msg.pid) < 3)
450 {
451 GTP_INFO("Illegal IC pid, need enter update");
452 return SUCCESS;
453 }
454 else
455 {
456 for (i = 0; i < 3; i++)
457 {
458 if ((update_msg.ic_fw_msg.pid[i] < 0x30) || (update_msg.ic_fw_msg.pid[i] > 0x39))
459 {
460 GTP_INFO("Illegal IC pid, out of bound, need enter update");
461 return SUCCESS;
462 }
463 }
464 }
465 // 20130523 end
466
467 pid_cmp_len = strlen(fw_head->pid);
468 if (pid_cmp_len < strlen(update_msg.ic_fw_msg.pid))
469 {
470 pid_cmp_len = strlen(update_msg.ic_fw_msg.pid);
471 }
472
473 if ((!memcmp(fw_head->pid, update_msg.ic_fw_msg.pid, pid_cmp_len)) ||
474 (!memcmp(update_msg.ic_fw_msg.pid, "91XX", 4))||
475 (!memcmp(fw_head->pid, "91XX", 4)))
476 {
477 if(!memcmp(fw_head->pid, "91XX", 4))
478 {
479 GTP_DEBUG("Force none same pid update mode.");
480 }
481 else
482 {
483 GTP_DEBUG("Get the same pid.");
484 }
485
486 //The third condition
487 if (fw_head->vid > update_msg.ic_fw_msg.vid)
488 {
489
490 GTP_INFO("Need enter update.");
491 return SUCCESS;
492 }
493
494 GTP_INFO("Don't meet the third condition.");
495 GTP_ERROR("File VID <= IC VID, update aborted!");
496 }
497 else
498 {
499 GTP_ERROR("File PID != IC PID, update aborted!");
500 }
501
502 return FAIL;
503 }
504
505 #if GTP_AUTO_UPDATE_CFG
506 static u8 ascii2hex(u8 a)
507 {
508 s8 value = 0;
509
510 if(a >= '0' && a <= '9')
511 {
512 value = a - '0';
513 }
514 else if(a >= 'A' && a <= 'F')
515 {
516 value = a - 'A' + 0x0A;
517 }
518 else if(a >= 'a' && a <= 'f')
519 {
520 value = a - 'a' + 0x0A;
521 }
522 else
523 {
524 value = 0xff;
525 }
526
527 return value;
528 }
529
530 static s8 gup_update_config(struct i2c_client *client)
531 {
532 s32 file_len = 0;
533 s32 ret = 0;
534 s32 i = 0;
535 s32 file_cfg_len = 0;
536 s32 chip_cfg_len = 0;
537 s32 count = 0;
538 u8 *buf;
539 u8 *pre_buf;
540 u8 *file_config;
541 //u8 checksum = 0;
542
543 if(NULL == update_msg.cfg_file)
544 {
545 GTP_ERROR("[update_cfg]No need to upgrade config!");
546 return FAIL;
547 }
548 file_len = update_msg.cfg_file->f_op->llseek(update_msg.cfg_file, 0, SEEK_END);
549
550 chip_cfg_len = cfg_len;
551
552 GTP_DEBUG("[update_cfg]config file len:%d", file_len);
553 GTP_DEBUG("[update_cfg]need config len:%d",chip_cfg_len);
554 if((file_len+5) < chip_cfg_len*5)
555 {
556 GTP_ERROR("Config length error");
557 return -1;
558 }
559
560 buf = (u8*)kzalloc(file_len, GFP_KERNEL);
561 pre_buf = (u8*)kzalloc(file_len, GFP_KERNEL);
562 file_config = (u8*)kzalloc(chip_cfg_len + GTP_ADDR_LENGTH, GFP_KERNEL);
563 update_msg.cfg_file->f_op->llseek(update_msg.cfg_file, 0, SEEK_SET);
564
565 GTP_DEBUG("[update_cfg]Read config from file.");
566 ret = update_msg.cfg_file->f_op->read(update_msg.cfg_file, (char*)pre_buf, file_len, &update_msg.cfg_file->f_pos);
567 if(ret<0)
568 {
569 GTP_ERROR("[update_cfg]Read config file failed.");
570 goto update_cfg_file_failed;
571 }
572
573 GTP_DEBUG("[update_cfg]Delete illgal charactor.");
574 for(i=0,count=0; i<file_len; i++)
575 {
576 if (pre_buf[i] == ' ' || pre_buf[i] == '\r' || pre_buf[i] == '\n')
577 {
578 continue;
579 }
580 buf[count++] = pre_buf[i];
581 }
582
583 GTP_DEBUG("[update_cfg]Ascii to hex.");
584 file_config[0] = GTP_REG_CONFIG_DATA >> 8;
585 file_config[1] = GTP_REG_CONFIG_DATA & 0xff;
586 for(i=0,file_cfg_len=GTP_ADDR_LENGTH; i<count; i+=5)
587 {
588 if((buf[i]=='0') && ((buf[i+1]=='x') || (buf[i+1]=='X')))
589 {
590 u8 high,low;
591 high = ascii2hex(buf[i+2]);
592 low = ascii2hex(buf[i+3]);
593
594 if((high == 0xFF) || (low == 0xFF))
595 {
596 ret = 0;
597 GTP_ERROR("[update_cfg]Illegal config file.");
598 goto update_cfg_file_failed;
599 }
600 file_config[file_cfg_len++] = (high<<4) + low;
601 }
602 else
603 {
604 ret = 0;
605 GTP_ERROR("[update_cfg]Illegal config file.");
606 goto update_cfg_file_failed;
607 }
608 }
609
610
611 GTP_DEBUG("config:");
612 GTP_DEBUG_ARRAY(file_config+2, file_cfg_len);
613
614 i = 0;
615 while(i++ < 5)
616 {
617 ret = gup_i2c_write(client, file_config, file_cfg_len);
618 if(ret > 0)
619 {
620 GTP_INFO("[update_cfg]Send config SUCCESS.");
621 break;
622 }
623 GTP_ERROR("[update_cfg]Send config i2c error.");
624 }
625
626 update_cfg_file_failed:
627 kfree(pre_buf);
628 kfree(buf);
629 kfree(file_config);
630 return ret;
631 }
632
633 #endif
634
635 #if (GTP_AUTO_UPDATE && (!GTP_HEADER_FW_UPDATE || GTP_AUTO_UPDATE_CFG))
636 static void gup_search_file(s32 search_type)
637 {
638 s32 i = 0;
639 struct file *pfile = NULL;
640
641 got_file_flag = 0x00;
642
643 searching_file = 1;
644 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
645 {
646 if (0 == searching_file)
647 {
648 GTP_INFO("Force exiting file searching");
649 got_file_flag = 0x00;
650 return;
651 }
652
653 if (search_type & AUTO_SEARCH_BIN)
654 {
655 GTP_DEBUG("Search for %s, %s for fw update.(%d/%d)", UPDATE_FILE_PATH_1, UPDATE_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
656 pfile = filp_open(UPDATE_FILE_PATH_1, O_RDONLY, 0);
657 if (IS_ERR(pfile))
658 {
659 pfile = filp_open(UPDATE_FILE_PATH_2, O_RDONLY, 0);
660 if (!IS_ERR(pfile))
661 {
662 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_2);
663 got_file_flag |= BIN_FILE_READY;
664 update_msg.file = pfile;
665 }
666 }
667 else
668 {
669 GTP_INFO("Bin file: %s for fw update.", UPDATE_FILE_PATH_1);
670 got_file_flag |= BIN_FILE_READY;
671 update_msg.file = pfile;
672 }
673 if (got_file_flag & BIN_FILE_READY)
674 {
675 #if GTP_AUTO_UPDATE_CFG
676 if (search_type & AUTO_SEARCH_CFG)
677 {
678 i = GUP_SEARCH_FILE_TIMES; // Bin & Cfg File required to be in the same directory
679 }
680 else
681 #endif
682 {
683 searching_file = 0;
684 return;
685 }
686 }
687 }
688
689 #if GTP_AUTO_UPDATE_CFG
690 if ( (search_type & AUTO_SEARCH_CFG) && !(got_file_flag & CFG_FILE_READY) )
691 {
692 GTP_DEBUG("Search for %s, %s for config update.(%d/%d)", CONFIG_FILE_PATH_1, CONFIG_FILE_PATH_2, i+1, GUP_SEARCH_FILE_TIMES);
693 pfile = filp_open(CONFIG_FILE_PATH_1, O_RDONLY, 0);
694 if (IS_ERR(pfile))
695 {
696 pfile = filp_open(CONFIG_FILE_PATH_2, O_RDONLY, 0);
697 if (!IS_ERR(pfile))
698 {
699 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_2);
700 got_file_flag |= CFG_FILE_READY;
701 update_msg.cfg_file = pfile;
702 }
703 }
704 else
705 {
706 GTP_INFO("Cfg file: %s for config update.", CONFIG_FILE_PATH_1);
707 got_file_flag |= CFG_FILE_READY;
708 update_msg.cfg_file = pfile;
709 }
710 if (got_file_flag & CFG_FILE_READY)
711 {
712 searching_file = 0;
713 return;
714 }
715 }
716 #endif
717 msleep(3000);
718 }
719 searching_file = 0;
720 }
721 #endif
722
723 static u8 gup_check_update_file(struct i2c_client *client, st_fw_head *fw_head, u8 *path)
724 {
725 s32 ret = 0;
726 s32 i = 0;
727 s32 fw_checksum = 0;
728 u8 buf[FW_HEAD_LENGTH];
729
730 got_file_flag = 0x00;
731 if (path)
732 {
733 GTP_DEBUG("Update File path:%s, %d", path, strlen(path));
734 update_msg.file = filp_open(path, O_RDONLY, 0);
735
736 if (IS_ERR(update_msg.file))
737 {
738 GTP_ERROR("Open update file(%s) error!", path);
739 return FAIL;
740 }
741 got_file_flag = BIN_FILE_READY;
742 }
743 else
744 {
745 #if GTP_AUTO_UPDATE
746 #if GTP_HEADER_FW_UPDATE
747 GTP_INFO("Update by default firmware array");
748 update_msg.fw_total_len = sizeof(gtp_default_FW) - FW_HEAD_LENGTH;
749 if (sizeof(gtp_default_FW) < (FW_HEAD_LENGTH + FW_SECTION_LENGTH*4+FW_DSP_ISP_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH))
750 {
751 GTP_ERROR("INVALID gtp_default_FW, check your gt9xx_firmware.h file!");
752 return FAIL;
753 }
754 GTP_DEBUG("Firmware actual size: %d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
755 memcpy(fw_head, &gtp_default_FW[0], FW_HEAD_LENGTH);
756
757 //check firmware legality
758 fw_checksum = 0;
759 for (i = 0; i < update_msg.fw_total_len; i += 2)
760 {
761 fw_checksum += (gtp_default_FW[FW_HEAD_LENGTH + i] << 8) + gtp_default_FW[FW_HEAD_LENGTH + i + 1];
762 }
763
764 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
765 if(fw_checksum&0xFFFF)
766 {
767 GTP_ERROR("Illegal firmware file.");
768 return FAIL;
769 }
770 got_file_flag = HEADER_FW_READY;
771 return SUCCESS;
772
773 #else
774 #if GTP_AUTO_UPDATE_CFG
775 gup_search_file(AUTO_SEARCH_BIN | AUTO_SEARCH_CFG);
776 if (got_file_flag & CFG_FILE_READY)
777 {
778 ret = gup_update_config(client);
779 if(ret <= 0)
780 {
781 GTP_ERROR("Update config failed!");
782 }
783 _CLOSE_FILE(update_msg.cfg_file);
784 msleep(500); //waiting config to be stored in FLASH.
785 }
786 #else
787 gup_search_file(AUTO_SEARCH_BIN);
788 #endif
789
790 if (!(got_file_flag & BIN_FILE_READY))
791 {
792 GTP_ERROR("No bin file for fw Update");
793 return FAIL;
794 }
795 #endif
796 #else
797 {
798 GTP_ERROR("NULL file for fw update!");
799 return FAIL;
800 }
801 #endif
802 }
803
804 update_msg.old_fs = get_fs();
805 set_fs(KERNEL_DS);
806
807 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
808 update_msg.fw_total_len = update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_END);
809
810 if (update_msg.fw_total_len < (FW_HEAD_LENGTH + FW_SECTION_LENGTH*4+FW_DSP_ISP_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH))
811 {
812 GTP_ERROR("INVALID bin file(size: %d), update aborted.", update_msg.fw_total_len);
813 return FAIL;
814 }
815
816 update_msg.fw_total_len -= FW_HEAD_LENGTH;
817
818 GTP_DEBUG("Bin firmware actual size: %d(%dK)", update_msg.fw_total_len, update_msg.fw_total_len/1024);
819
820 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
821 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, FW_HEAD_LENGTH, &update_msg.file->f_pos);
822 if (ret < 0)
823 {
824 GTP_ERROR("Read firmware head in update file error.");
825 return FAIL;
826 }
827
828 memcpy(fw_head, buf, FW_HEAD_LENGTH);
829
830 //check firmware legality
831 fw_checksum = 0;
832 for(i=0; i < update_msg.fw_total_len; i+=2)
833 {
834 u16 temp;
835 ret = update_msg.file->f_op->read(update_msg.file, (char*)buf, 2, &update_msg.file->f_pos);
836 if (ret < 0)
837 {
838 GTP_ERROR("Read firmware file error.");
839 return FAIL;
840 }
841 //GTP_DEBUG("BUF[0]:%x", buf[0]);
842 temp = (buf[0]<<8) + buf[1];
843 fw_checksum += temp;
844 }
845
846 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
847 if(fw_checksum&0xFFFF)
848 {
849 GTP_ERROR("Illegal firmware file.");
850 return FAIL;
851 }
852
853 return SUCCESS;
854 }
855
856 static u8 gup_burn_proc(struct i2c_client *client, u8 *burn_buf, u16 start_addr, u16 total_length)
857 {
858 s32 ret = 0;
859 u16 burn_addr = start_addr;
860 u16 frame_length = 0;
861 u16 burn_length = 0;
862 u8 wr_buf[PACK_SIZE + GTP_ADDR_LENGTH];
863 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
864 u8 retry = 0;
865
866 GTP_DEBUG("Begin burn %dk data to addr 0x%x", (total_length / 1024), start_addr);
867
868 while (burn_length < total_length)
869 {
870 GTP_DEBUG("B/T:%04d/%04d", burn_length, total_length);
871 frame_length = ((total_length - burn_length) > PACK_SIZE) ? PACK_SIZE : (total_length - burn_length);
872 wr_buf[0] = (u8)(burn_addr >> 8);
873 rd_buf[0] = wr_buf[0];
874 wr_buf[1] = (u8)burn_addr;
875 rd_buf[1] = wr_buf[1];
876 memcpy(&wr_buf[GTP_ADDR_LENGTH], &burn_buf[burn_length], frame_length);
877
878 for (retry = 0; retry < MAX_FRAME_CHECK_TIME; retry++)
879 {
880 ret = gup_i2c_write(client, wr_buf, GTP_ADDR_LENGTH + frame_length);
881
882 if (ret <= 0)
883 {
884 GTP_ERROR("Write frame data i2c error.");
885 continue;
886 }
887
888 ret = gup_i2c_read(client, rd_buf, GTP_ADDR_LENGTH + frame_length);
889
890 if (ret <= 0)
891 {
892 GTP_ERROR("Read back frame data i2c error.");
893 continue;
894 }
895
896 if (memcmp(&wr_buf[GTP_ADDR_LENGTH], &rd_buf[GTP_ADDR_LENGTH], frame_length))
897 {
898 GTP_ERROR("Check frame data fail,not equal.");
899 GTP_DEBUG("write array:");
900 GTP_DEBUG_ARRAY(&wr_buf[GTP_ADDR_LENGTH], frame_length);
901 GTP_DEBUG("read array:");
902 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
903 continue;
904 }
905 else
906 {
907 //GTP_DEBUG("Check frame data success.");
908 break;
909 }
910 }
911 if(retry >= MAX_FRAME_CHECK_TIME)
912 {
913 GTP_ERROR("Burn frame data time out,exit.");
914 return FAIL;
915 }
916 burn_length += frame_length;
917 burn_addr += frame_length;
918 }
919 return SUCCESS;
920 }
921
922 static u8 gup_load_section_file(u8 *buf, u32 offset, u16 length, u8 set_or_end)
923 {
924 #if (GTP_AUTO_UPDATE && GTP_HEADER_FW_UPDATE)
925 if (HEADER_FW_READY == got_file_flag)
926 {
927 if(SEEK_SET == set_or_end)
928 {
929 memcpy(buf, &gtp_default_FW[FW_HEAD_LENGTH + offset], length);
930 }
931 else //seek end
932 {
933 memcpy(buf, &gtp_default_FW[update_msg.fw_total_len + FW_HEAD_LENGTH - offset], length);
934 }
935 return SUCCESS;
936 }
937 #endif
938 {
939 s32 ret = 0;
940
941 if ( (update_msg.file == NULL) || IS_ERR(update_msg.file))
942 {
943 GTP_ERROR("cannot find update file,load section file fail.");
944 return FAIL;
945 }
946
947 if(SEEK_SET == set_or_end)
948 {
949 update_msg.file->f_pos = FW_HEAD_LENGTH + offset;
950 }
951 else //seek end
952 {
953 update_msg.file->f_pos = update_msg.fw_total_len + FW_HEAD_LENGTH - offset;
954 }
955
956 ret = update_msg.file->f_op->read(update_msg.file, (char *)buf, length, &update_msg.file->f_pos);
957
958 if (ret < 0)
959 {
960 GTP_ERROR("Read update file fail.");
961 return FAIL;
962 }
963
964 return SUCCESS;
965 }
966 }
967
968 static u8 gup_recall_check(struct i2c_client *client, u8 *chk_src, u16 start_rd_addr, u16 chk_length)
969 {
970 u8 rd_buf[PACK_SIZE + GTP_ADDR_LENGTH];
971 s32 ret = 0;
972 u16 recall_addr = start_rd_addr;
973 u16 recall_length = 0;
974 u16 frame_length = 0;
975
976 while (recall_length < chk_length)
977 {
978 frame_length = ((chk_length - recall_length) > PACK_SIZE) ? PACK_SIZE : (chk_length - recall_length);
979 ret = gup_get_ic_msg(client, recall_addr, rd_buf, frame_length);
980
981 if (ret <= 0)
982 {
983 GTP_ERROR("recall i2c error,exit");
984 return FAIL;
985 }
986
987 if (memcmp(&rd_buf[GTP_ADDR_LENGTH], &chk_src[recall_length], frame_length))
988 {
989 GTP_ERROR("Recall frame data fail,not equal.");
990 GTP_DEBUG("chk_src array:");
991 GTP_DEBUG_ARRAY(&chk_src[recall_length], frame_length);
992 GTP_DEBUG("recall array:");
993 GTP_DEBUG_ARRAY(&rd_buf[GTP_ADDR_LENGTH], frame_length);
994 return FAIL;
995 }
996
997 recall_length += frame_length;
998 recall_addr += frame_length;
999 }
1000
1001 GTP_DEBUG("Recall check %dk firmware success.", (chk_length / 1024));
1002
1003 return SUCCESS;
1004 }
1005
1006 static u8 gup_burn_fw_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u8 bank_cmd)
1007 {
1008 s32 ret = 0;
1009 u8 rd_buf[5];
1010
1011 //step1:hold ss51 & dsp
1012 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1013
1014 if (ret <= 0)
1015 {
1016 GTP_ERROR("[burn_fw_section]hold ss51 & dsp fail.");
1017 return FAIL;
1018 }
1019
1020 //step2:set scramble
1021 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1022
1023 if (ret <= 0)
1024 {
1025 GTP_ERROR("[burn_fw_section]set scramble fail.");
1026 return FAIL;
1027 }
1028
1029 //step3:select bank
1030 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
1031
1032 if (ret <= 0)
1033 {
1034 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
1035 return FAIL;
1036 }
1037
1038 //step4:enable accessing code
1039 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1040
1041 if (ret <= 0)
1042 {
1043 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
1044 return FAIL;
1045 }
1046
1047 //step5:burn 8k fw section
1048 ret = gup_burn_proc(client, fw_section, start_addr, FW_SECTION_LENGTH);
1049
1050 if (FAIL == ret)
1051 {
1052 GTP_ERROR("[burn_fw_section]burn fw_section fail.");
1053 return FAIL;
1054 }
1055
1056 //step6:hold ss51 & release dsp
1057 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
1058
1059 if (ret <= 0)
1060 {
1061 GTP_ERROR("[burn_fw_section]hold ss51 & release dsp fail.");
1062 return FAIL;
1063 }
1064
1065 //must delay
1066 msleep(1);
1067
1068 //step7:send burn cmd to move data to flash from sram
1069 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd & 0x0f);
1070
1071 if (ret <= 0)
1072 {
1073 GTP_ERROR("[burn_fw_section]send burn cmd fail.");
1074 return FAIL;
1075 }
1076
1077 GTP_DEBUG("[burn_fw_section]Wait for the burn is complete......");
1078
1079 do
1080 {
1081 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1082
1083 if (ret <= 0)
1084 {
1085 GTP_ERROR("[burn_fw_section]Get burn state fail");
1086 return FAIL;
1087 }
1088
1089 msleep(10);
1090 //GTP_DEBUG("[burn_fw_section]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1091 }
1092 while (rd_buf[GTP_ADDR_LENGTH]);
1093
1094 //step8:select bank
1095 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4) & 0x0F);
1096
1097 if (ret <= 0)
1098 {
1099 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4) & 0x0F);
1100 return FAIL;
1101 }
1102
1103 //step9:enable accessing code
1104 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1105
1106 if (ret <= 0)
1107 {
1108 GTP_ERROR("[burn_fw_section]enable accessing code fail.");
1109 return FAIL;
1110 }
1111
1112 //step10:recall 8k fw section
1113 ret = gup_recall_check(client, fw_section, start_addr, FW_SECTION_LENGTH);
1114
1115 if (FAIL == ret)
1116 {
1117 GTP_ERROR("[burn_fw_section]recall check %dk firmware fail.", FW_SECTION_LENGTH/1024);
1118 return FAIL;
1119 }
1120
1121 //step11:disable accessing code
1122 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x00);
1123
1124 if (ret <= 0)
1125 {
1126 GTP_ERROR("[burn_fw_section]disable accessing code fail.");
1127 return FAIL;
1128 }
1129
1130 return SUCCESS;
1131 }
1132
1133 static u8 gup_burn_dsp_isp(struct i2c_client *client)
1134 {
1135 s32 ret = 0;
1136 u8 *fw_dsp_isp = NULL;
1137 u8 retry = 0;
1138 //u32 offset;
1139
1140 GTP_INFO("[burn_dsp_isp]Begin burn dsp isp---->>");
1141
1142 //step1:alloc memory
1143 GTP_DEBUG("[burn_dsp_isp]step1:alloc memory");
1144
1145 while (retry++ < 5)
1146 {
1147 fw_dsp_isp = (u8 *)kzalloc(FW_DSP_ISP_LENGTH, GFP_KERNEL);
1148
1149 if (fw_dsp_isp == NULL)
1150 {
1151 continue;
1152 }
1153 else
1154 {
1155 GTP_DEBUG("[burn_dsp_isp]Alloc %dk byte memory success.", (FW_DSP_ISP_LENGTH / 1024));
1156 break;
1157 }
1158 }
1159
1160 if (retry >= 5)
1161 {
1162 GTP_ERROR("[burn_dsp_isp]Alloc memory fail,exit.");
1163 return FAIL;
1164 }
1165
1166 //step2:load dsp isp file data
1167 GTP_DEBUG("[burn_dsp_isp]step2:load dsp isp file data");
1168 ret = gup_load_section_file(fw_dsp_isp, FW_DSP_ISP_LENGTH, FW_DSP_ISP_LENGTH, SEEK_END);
1169
1170 if (FAIL == ret)
1171 {
1172 GTP_ERROR("[burn_dsp_isp]load firmware dsp_isp fail.");
1173 goto exit_burn_dsp_isp;
1174 }
1175
1176 //step3:disable wdt,clear cache enable
1177 GTP_DEBUG("[burn_dsp_isp]step3:disable wdt,clear cache enable");
1178 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
1179
1180 if (ret <= 0)
1181 {
1182 GTP_ERROR("[burn_dsp_isp]disable wdt fail.");
1183 ret = FAIL;
1184 goto exit_burn_dsp_isp;
1185 }
1186
1187 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
1188
1189 if (ret <= 0)
1190 {
1191 GTP_ERROR("[burn_dsp_isp]clear cache enable fail.");
1192 ret = FAIL;
1193 goto exit_burn_dsp_isp;
1194 }
1195
1196 //step4:hold ss51 & dsp
1197 GTP_DEBUG("[burn_dsp_isp]step4:hold ss51 & dsp");
1198 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1199
1200 if (ret <= 0)
1201 {
1202 GTP_ERROR("[burn_dsp_isp]hold ss51 & dsp fail.");
1203 ret = FAIL;
1204 goto exit_burn_dsp_isp;
1205 }
1206
1207 //step5:set boot from sram
1208 GTP_DEBUG("[burn_dsp_isp]step5:set boot from sram");
1209 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
1210
1211 if (ret <= 0)
1212 {
1213 GTP_ERROR("[burn_dsp_isp]set boot from sram fail.");
1214 ret = FAIL;
1215 goto exit_burn_dsp_isp;
1216 }
1217
1218 //step6:software reboot
1219 GTP_DEBUG("[burn_dsp_isp]step6:software reboot");
1220 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
1221
1222 if (ret <= 0)
1223 {
1224 GTP_ERROR("[burn_dsp_isp]software reboot fail.");
1225 ret = FAIL;
1226 goto exit_burn_dsp_isp;
1227 }
1228
1229 //step7:select bank2
1230 GTP_DEBUG("[burn_dsp_isp]step7:select bank2");
1231 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
1232
1233 if (ret <= 0)
1234 {
1235 GTP_ERROR("[burn_dsp_isp]select bank2 fail.");
1236 ret = FAIL;
1237 goto exit_burn_dsp_isp;
1238 }
1239
1240 //step8:enable accessing code
1241 GTP_DEBUG("[burn_dsp_isp]step8:enable accessing code");
1242 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
1243
1244 if (ret <= 0)
1245 {
1246 GTP_ERROR("[burn_dsp_isp]enable accessing code fail.");
1247 ret = FAIL;
1248 goto exit_burn_dsp_isp;
1249 }
1250
1251 //step9:burn 4k dsp_isp
1252 GTP_DEBUG("[burn_dsp_isp]step9:burn 4k dsp_isp");
1253 ret = gup_burn_proc(client, fw_dsp_isp, 0xC000, FW_DSP_ISP_LENGTH);
1254
1255 if (FAIL == ret)
1256 {
1257 GTP_ERROR("[burn_dsp_isp]burn dsp_isp fail.");
1258 goto exit_burn_dsp_isp;
1259 }
1260
1261 //step10:set scramble
1262 GTP_DEBUG("[burn_dsp_isp]step10:set scramble");
1263 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1264
1265 if (ret <= 0)
1266 {
1267 GTP_ERROR("[burn_dsp_isp]set scramble fail.");
1268 ret = FAIL;
1269 goto exit_burn_dsp_isp;
1270 }
1271
1272 update_msg.fw_burned_len += FW_DSP_ISP_LENGTH;
1273 GTP_DEBUG("[burn_dsp_isp]Burned length:%d", update_msg.fw_burned_len);
1274 ret = SUCCESS;
1275
1276 exit_burn_dsp_isp:
1277 kfree(fw_dsp_isp);
1278 return ret;
1279 }
1280
1281 static u8 gup_burn_fw_ss51(struct i2c_client *client)
1282 {
1283 u8 *fw_ss51 = NULL;
1284 u8 retry = 0;
1285 s32 ret = 0;
1286
1287 GTP_INFO("[burn_fw_ss51]Begin burn ss51 firmware---->>");
1288
1289 //step1:alloc memory
1290 GTP_DEBUG("[burn_fw_ss51]step1:alloc memory");
1291
1292 while (retry++ < 5)
1293 {
1294 fw_ss51 = (u8 *)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
1295
1296 if (fw_ss51 == NULL)
1297 {
1298 continue;
1299 }
1300 else
1301 {
1302 GTP_DEBUG("[burn_fw_ss51]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1303 break;
1304 }
1305 }
1306
1307 if (retry >= 5)
1308 {
1309 GTP_ERROR("[burn_fw_ss51]Alloc memory fail,exit.");
1310 return FAIL;
1311 }
1312
1313 //step2:load ss51 firmware section 1 file data
1314 //GTP_DEBUG("[burn_fw_ss51]step2:load ss51 firmware section 1 file data");
1315 //ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
1316 //
1317 // if (FAIL == ret)
1318 // {
1319 // GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 1 fail.");
1320 // goto exit_burn_fw_ss51;
1321 // }
1322 GTP_INFO("[burn_fw_ss51]Reset first 8K of ss51 to 0xFF.");
1323 GTP_DEBUG("[burn_fw_ss51]step2: reset bank0 0xC000~0xD000");
1324 memset(fw_ss51, 0xFF, FW_SECTION_LENGTH);
1325
1326 //step3:clear control flag
1327 GTP_DEBUG("[burn_fw_ss51]step3:clear control flag");
1328 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
1329
1330 if (ret <= 0)
1331 {
1332 GTP_ERROR("[burn_fw_ss51]clear control flag fail.");
1333 ret = FAIL;
1334 goto exit_burn_fw_ss51;
1335 }
1336
1337 //step4:burn ss51 firmware section 1
1338 GTP_DEBUG("[burn_fw_ss51]step4:burn ss51 firmware section 1");
1339 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
1340
1341 if (FAIL == ret)
1342 {
1343 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 1 fail.");
1344 goto exit_burn_fw_ss51;
1345 }
1346
1347 //step5:load ss51 firmware section 2 file data
1348 GTP_DEBUG("[burn_fw_ss51]step5:load ss51 firmware section 2 file data");
1349 ret = gup_load_section_file(fw_ss51, FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1350
1351 if (FAIL == ret)
1352 {
1353 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 2 fail.");
1354 goto exit_burn_fw_ss51;
1355 }
1356
1357 //step6:burn ss51 firmware section 2
1358 GTP_DEBUG("[burn_fw_ss51]step6:burn ss51 firmware section 2");
1359 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x02);
1360
1361 if (FAIL == ret)
1362 {
1363 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 2 fail.");
1364 goto exit_burn_fw_ss51;
1365 }
1366
1367 //step7:load ss51 firmware section 3 file data
1368 GTP_DEBUG("[burn_fw_ss51]step7:load ss51 firmware section 3 file data");
1369 ret = gup_load_section_file(fw_ss51, 2 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1370
1371 if (FAIL == ret)
1372 {
1373 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 3 fail.");
1374 goto exit_burn_fw_ss51;
1375 }
1376
1377 //step8:burn ss51 firmware section 3
1378 GTP_DEBUG("[burn_fw_ss51]step8:burn ss51 firmware section 3");
1379 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x13);
1380
1381 if (FAIL == ret)
1382 {
1383 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 3 fail.");
1384 goto exit_burn_fw_ss51;
1385 }
1386
1387 //step9:load ss51 firmware section 4 file data
1388 GTP_DEBUG("[burn_fw_ss51]step9:load ss51 firmware section 4 file data");
1389 ret = gup_load_section_file(fw_ss51, 3 * FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
1390
1391 if (FAIL == ret)
1392 {
1393 GTP_ERROR("[burn_fw_ss51]load ss51 firmware section 4 fail.");
1394 goto exit_burn_fw_ss51;
1395 }
1396
1397 //step10:burn ss51 firmware section 4
1398 GTP_DEBUG("[burn_fw_ss51]step10:burn ss51 firmware section 4");
1399 ret = gup_burn_fw_section(client, fw_ss51, 0xE000, 0x14);
1400
1401 if (FAIL == ret)
1402 {
1403 GTP_ERROR("[burn_fw_ss51]burn ss51 firmware section 4 fail.");
1404 goto exit_burn_fw_ss51;
1405 }
1406
1407 update_msg.fw_burned_len += (FW_SECTION_LENGTH*4);
1408 GTP_DEBUG("[burn_fw_ss51]Burned length:%d", update_msg.fw_burned_len);
1409 ret = SUCCESS;
1410
1411 exit_burn_fw_ss51:
1412 kfree(fw_ss51);
1413 return ret;
1414 }
1415
1416 static u8 gup_burn_fw_dsp(struct i2c_client *client)
1417 {
1418 s32 ret = 0;
1419 u8 *fw_dsp = NULL;
1420 u8 retry = 0;
1421 u8 rd_buf[5];
1422
1423 GTP_INFO("[burn_fw_dsp]Begin burn dsp firmware---->>");
1424 //step1:alloc memory
1425 GTP_DEBUG("[burn_fw_dsp]step1:alloc memory");
1426
1427 while (retry++ < 5)
1428 {
1429 fw_dsp = (u8 *)kzalloc(FW_DSP_LENGTH, GFP_KERNEL);
1430
1431 if (fw_dsp == NULL)
1432 {
1433 continue;
1434 }
1435 else
1436 {
1437 GTP_DEBUG("[burn_fw_dsp]Alloc %dk byte memory success.", (FW_SECTION_LENGTH / 1024));
1438 break;
1439 }
1440 }
1441
1442 if (retry >= 5)
1443 {
1444 GTP_ERROR("[burn_fw_dsp]Alloc memory fail,exit.");
1445 return FAIL;
1446 }
1447
1448 //step2:load firmware dsp
1449 GTP_DEBUG("[burn_fw_dsp]step2:load firmware dsp");
1450 ret = gup_load_section_file(fw_dsp, 4 * FW_SECTION_LENGTH, FW_DSP_LENGTH, SEEK_SET);
1451
1452 if (FAIL == ret)
1453 {
1454 GTP_ERROR("[burn_fw_dsp]load firmware dsp fail.");
1455 goto exit_burn_fw_dsp;
1456 }
1457
1458 //step3:select bank3
1459 GTP_DEBUG("[burn_fw_dsp]step3:select bank3");
1460 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1461
1462 if (ret <= 0)
1463 {
1464 GTP_ERROR("[burn_fw_dsp]select bank3 fail.");
1465 ret = FAIL;
1466 goto exit_burn_fw_dsp;
1467 }
1468
1469 //step4:hold ss51 & dsp
1470 GTP_DEBUG("[burn_fw_dsp]step4:hold ss51 & dsp");
1471 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1472
1473 if (ret <= 0)
1474 {
1475 GTP_ERROR("[burn_fw_dsp]hold ss51 & dsp fail.");
1476 ret = FAIL;
1477 goto exit_burn_fw_dsp;
1478 }
1479
1480 //step5:set scramble
1481 GTP_DEBUG("[burn_fw_dsp]step5:set scramble");
1482 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1483
1484 if (ret <= 0)
1485 {
1486 GTP_ERROR("[burn_fw_dsp]set scramble fail.");
1487 ret = FAIL;
1488 goto exit_burn_fw_dsp;
1489 }
1490
1491 //step6:release ss51 & dsp
1492 GTP_DEBUG("[burn_fw_dsp]step6:release ss51 & dsp");
1493 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121212
1494
1495 if (ret <= 0)
1496 {
1497 GTP_ERROR("[burn_fw_dsp]release ss51 & dsp fail.");
1498 ret = FAIL;
1499 goto exit_burn_fw_dsp;
1500 }
1501
1502 //must delay
1503 msleep(1);
1504
1505 //step7:burn 4k dsp firmware
1506 GTP_DEBUG("[burn_fw_dsp]step7:burn 4k dsp firmware");
1507 ret = gup_burn_proc(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1508
1509 if (FAIL == ret)
1510 {
1511 GTP_ERROR("[burn_fw_dsp]burn fw_section fail.");
1512 goto exit_burn_fw_dsp;
1513 }
1514
1515 //step8:send burn cmd to move data to flash from sram
1516 GTP_DEBUG("[burn_fw_dsp]step8:send burn cmd to move data to flash from sram");
1517 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x05);
1518
1519 if (ret <= 0)
1520 {
1521 GTP_ERROR("[burn_fw_dsp]send burn cmd fail.");
1522 goto exit_burn_fw_dsp;
1523 }
1524
1525 GTP_DEBUG("[burn_fw_dsp]Wait for the burn is complete......");
1526
1527 do
1528 {
1529 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1530
1531 if (ret <= 0)
1532 {
1533 GTP_ERROR("[burn_fw_dsp]Get burn state fail");
1534 goto exit_burn_fw_dsp;
1535 }
1536
1537 msleep(10);
1538 //GTP_DEBUG("[burn_fw_dsp]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1539 }
1540 while (rd_buf[GTP_ADDR_LENGTH]);
1541
1542 //step9:recall check 4k dsp firmware
1543 GTP_DEBUG("[burn_fw_dsp]step9:recall check 4k dsp firmware");
1544 ret = gup_recall_check(client, fw_dsp, 0x9000, FW_DSP_LENGTH);
1545
1546 if (FAIL == ret)
1547 {
1548 GTP_ERROR("[burn_fw_dsp]recall check 4k dsp firmware fail.");
1549 goto exit_burn_fw_dsp;
1550 }
1551
1552 update_msg.fw_burned_len += FW_DSP_LENGTH;
1553 GTP_DEBUG("[burn_fw_dsp]Burned length:%d", update_msg.fw_burned_len);
1554 ret = SUCCESS;
1555
1556 exit_burn_fw_dsp:
1557 kfree(fw_dsp);
1558 return ret;
1559 }
1560
1561 static u8 gup_burn_fw_boot(struct i2c_client *client)
1562 {
1563 s32 ret = 0;
1564 u8* fw_boot = NULL;
1565 u8 retry = 0;
1566 u8 rd_buf[5];
1567
1568 GTP_INFO("[burn_fw_boot]Begin burn bootloader firmware---->>");
1569
1570 //step1:Alloc memory
1571 GTP_DEBUG("[burn_fw_boot]step1:Alloc memory");
1572
1573 while(retry++ < 5)
1574 {
1575 fw_boot = (u8*)kzalloc(FW_BOOT_LENGTH, GFP_KERNEL);
1576
1577 if(fw_boot == NULL)
1578 {
1579 continue;
1580 }
1581 else
1582 {
1583 GTP_DEBUG("[burn_fw_boot]Alloc %dk byte memory success.", (FW_BOOT_LENGTH/1024));
1584 break;
1585 }
1586 }
1587
1588 if(retry >= 5)
1589 {
1590 GTP_ERROR("[burn_fw_boot]Alloc memory fail,exit.");
1591 return FAIL;
1592 }
1593
1594 //step2:load firmware bootloader
1595 GTP_DEBUG("[burn_fw_boot]step2:load firmware bootloader");
1596 ret = gup_load_section_file(fw_boot, (4 * FW_SECTION_LENGTH + FW_DSP_LENGTH), FW_BOOT_LENGTH, SEEK_SET);
1597
1598 if(FAIL == ret)
1599 {
1600 GTP_ERROR("[burn_fw_boot]load firmware bootcode fail.");
1601 goto exit_burn_fw_boot;
1602 }
1603
1604 //step3:hold ss51 & dsp
1605 GTP_DEBUG("[burn_fw_boot]step3:hold ss51 & dsp");
1606 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1607 if(ret <= 0)
1608 {
1609 GTP_ERROR("[burn_fw_boot]hold ss51 & dsp fail.");
1610 ret = FAIL;
1611 goto exit_burn_fw_boot;
1612 }
1613
1614 //step4:set scramble
1615 GTP_DEBUG("[burn_fw_boot]step4:set scramble");
1616 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1617 if(ret <= 0)
1618 {
1619 GTP_ERROR("[burn_fw_boot]set scramble fail.");
1620 ret = FAIL;
1621 goto exit_burn_fw_boot;
1622 }
1623
1624 //step5:hold ss51 & release dsp
1625 GTP_DEBUG("[burn_fw_boot]step5:hold ss51 & release dsp");
1626 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121211
1627 if(ret <= 0)
1628 {
1629 GTP_ERROR("[burn_fw_boot]release ss51 & dsp fail.");
1630 ret = FAIL;
1631 goto exit_burn_fw_boot;
1632 }
1633 //must delay
1634 msleep(1);
1635
1636 //step6:select bank3
1637 GTP_DEBUG("[burn_fw_boot]step6:select bank3");
1638 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1639 if(ret <= 0)
1640 {
1641 GTP_ERROR("[burn_fw_boot]select bank3 fail.");
1642 ret = FAIL;
1643 goto exit_burn_fw_boot;
1644 }
1645
1646 //step7:burn 2k bootloader firmware
1647 GTP_DEBUG("[burn_fw_boot]step7:burn 2k bootloader firmware");
1648 ret = gup_burn_proc(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1649 if(FAIL == ret)
1650 {
1651 GTP_ERROR("[burn_fw_boot]burn fw_boot fail.");
1652 goto exit_burn_fw_boot;
1653 }
1654
1655 //step7:send burn cmd to move data to flash from sram
1656 GTP_DEBUG("[burn_fw_boot]step7:send burn cmd to move data to flash from sram");
1657 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x06);
1658 if(ret <= 0)
1659 {
1660 GTP_ERROR("[burn_fw_boot]send burn cmd fail.");
1661 goto exit_burn_fw_boot;
1662 }
1663 GTP_DEBUG("[burn_fw_boot]Wait for the burn is complete......");
1664 do{
1665 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1666 if(ret <= 0)
1667 {
1668 GTP_ERROR("[burn_fw_boot]Get burn state fail");
1669 goto exit_burn_fw_boot;
1670 }
1671 msleep(10);
1672 //GTP_DEBUG("[burn_fw_boot]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1673 }while(rd_buf[GTP_ADDR_LENGTH]);
1674
1675 //step8:recall check 2k bootloader firmware
1676 GTP_DEBUG("[burn_fw_boot]step8:recall check 2k bootloader firmware");
1677 ret = gup_recall_check(client, fw_boot, 0x9000, FW_BOOT_LENGTH);
1678 if(FAIL == ret)
1679 {
1680 GTP_ERROR("[burn_fw_boot]recall check 2k bootcode firmware fail.");
1681 goto exit_burn_fw_boot;
1682 }
1683
1684 update_msg.fw_burned_len += FW_BOOT_LENGTH;
1685 GTP_DEBUG("[burn_fw_boot]Burned length:%d", update_msg.fw_burned_len);
1686 ret = SUCCESS;
1687
1688 exit_burn_fw_boot:
1689 kfree(fw_boot);
1690 return ret;
1691 }
1692
1693
1694 static u8 gup_burn_fw_boot_isp(struct i2c_client *client)
1695 {
1696 s32 ret = 0;
1697 u8* fw_boot_isp = NULL;
1698 u8 retry = 0;
1699 u8 rd_buf[5];
1700
1701 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
1702 {
1703 GTP_DEBUG("No need to upgrade the boot_isp code!");
1704 return SUCCESS;
1705 }
1706 GTP_INFO("[burn_fw_boot_isp]Begin burn boot_isp firmware---->>");
1707
1708 //step1:Alloc memory
1709 GTP_DEBUG("[burn_fw_boot_isp]step1:Alloc memory");
1710 while(retry++ < 5)
1711 {
1712 fw_boot_isp = (u8*)kzalloc(FW_BOOT_ISP_LENGTH, GFP_KERNEL);
1713 if(fw_boot_isp == NULL)
1714 {
1715 continue;
1716 }
1717 else
1718 {
1719 GTP_DEBUG("[burn_fw_boot_isp]Alloc %dk byte memory success.", (FW_BOOT_ISP_LENGTH/1024));
1720 break;
1721 }
1722 }
1723 if(retry >= 5)
1724 {
1725 GTP_ERROR("[burn_fw_boot_isp]Alloc memory fail,exit.");
1726 return FAIL;
1727 }
1728
1729 //step2:load firmware bootloader
1730 GTP_DEBUG("[burn_fw_boot_isp]step2:load firmware bootloader isp");
1731 //ret = gup_load_section_file(fw_boot_isp, (4*FW_SECTION_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH+FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
1732 ret = gup_load_section_file(fw_boot_isp, (update_msg.fw_burned_len - FW_DSP_ISP_LENGTH), FW_BOOT_ISP_LENGTH, SEEK_SET);
1733 if(FAIL == ret)
1734 {
1735 GTP_ERROR("[burn_fw_boot_isp]load firmware boot_isp fail.");
1736 goto exit_burn_fw_boot_isp;
1737 }
1738
1739 //step3:hold ss51 & dsp
1740 GTP_DEBUG("[burn_fw_boot_isp]step3:hold ss51 & dsp");
1741 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1742 if(ret <= 0)
1743 {
1744 GTP_ERROR("[burn_fw_boot_isp]hold ss51 & dsp fail.");
1745 ret = FAIL;
1746 goto exit_burn_fw_boot_isp;
1747 }
1748
1749 //step4:set scramble
1750 GTP_DEBUG("[burn_fw_boot_isp]step4:set scramble");
1751 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1752 if(ret <= 0)
1753 {
1754 GTP_ERROR("[burn_fw_boot_isp]set scramble fail.");
1755 ret = FAIL;
1756 goto exit_burn_fw_boot_isp;
1757 }
1758
1759
1760 //step5:hold ss51 & release dsp
1761 GTP_DEBUG("[burn_fw_boot_isp]step5:hold ss51 & release dsp");
1762 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04); //20121211
1763 if(ret <= 0)
1764 {
1765 GTP_ERROR("[burn_fw_boot_isp]release ss51 & dsp fail.");
1766 ret = FAIL;
1767 goto exit_burn_fw_boot_isp;
1768 }
1769 //must delay
1770 msleep(1);
1771
1772 //step6:select bank3
1773 GTP_DEBUG("[burn_fw_boot_isp]step6:select bank3");
1774 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x03);
1775 if(ret <= 0)
1776 {
1777 GTP_ERROR("[burn_fw_boot_isp]select bank3 fail.");
1778 ret = FAIL;
1779 goto exit_burn_fw_boot_isp;
1780 }
1781
1782 //step7:burn 2k bootload_isp firmware
1783 GTP_DEBUG("[burn_fw_boot_isp]step7:burn 2k bootloader firmware");
1784 ret = gup_burn_proc(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
1785 if(FAIL == ret)
1786 {
1787 GTP_ERROR("[burn_fw_boot_isp]burn fw_section fail.");
1788 goto exit_burn_fw_boot_isp;
1789 }
1790
1791 //step7:send burn cmd to move data to flash from sram
1792 GTP_DEBUG("[burn_fw_boot_isp]step8:send burn cmd to move data to flash from sram");
1793 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x07);
1794 if(ret <= 0)
1795 {
1796 GTP_ERROR("[burn_fw_boot_isp]send burn cmd fail.");
1797 goto exit_burn_fw_boot_isp;
1798 }
1799 GTP_DEBUG("[burn_fw_boot_isp]Wait for the burn is complete......");
1800 do{
1801 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1802 if(ret <= 0)
1803 {
1804 GTP_ERROR("[burn_fw_boot_isp]Get burn state fail");
1805 goto exit_burn_fw_boot_isp;
1806 }
1807 msleep(10);
1808 //GTP_DEBUG("[burn_fw_boot_isp]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1809 }while(rd_buf[GTP_ADDR_LENGTH]);
1810
1811 //step8:recall check 2k bootload_isp firmware
1812 GTP_DEBUG("[burn_fw_boot_isp]step9:recall check 2k bootloader firmware");
1813 ret = gup_recall_check(client, fw_boot_isp, 0x9000, FW_BOOT_ISP_LENGTH);
1814 if(FAIL == ret)
1815 {
1816 GTP_ERROR("[burn_fw_boot_isp]recall check 2k bootcode_isp firmware fail.");
1817 goto exit_burn_fw_boot_isp;
1818 }
1819
1820 update_msg.fw_burned_len += FW_BOOT_ISP_LENGTH;
1821 GTP_DEBUG("[burn_fw_boot_isp]Burned length:%d", update_msg.fw_burned_len);
1822 ret = SUCCESS;
1823
1824 exit_burn_fw_boot_isp:
1825 kfree(fw_boot_isp);
1826 return ret;
1827 }
1828
1829 static u8 gup_burn_fw_link(struct i2c_client *client)
1830 {
1831 s32 ret = 0;
1832 u8* fw_link = NULL;
1833 u8 retry = 0;
1834 u32 offset;
1835
1836 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
1837 {
1838 GTP_DEBUG("No need to upgrade the link code!");
1839 return SUCCESS;
1840 }
1841 GTP_INFO("[burn_fw_link]Begin burn link firmware---->>");
1842
1843 //step1:Alloc memory
1844 GTP_DEBUG("[burn_fw_link]step1:Alloc memory");
1845 while(retry++ < 5)
1846 {
1847 fw_link = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
1848 if(fw_link == NULL)
1849 {
1850 continue;
1851 }
1852 else
1853 {
1854 GTP_DEBUG("[burn_fw_link]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
1855 break;
1856 }
1857 }
1858 if(retry >= 5)
1859 {
1860 GTP_ERROR("[burn_fw_link]Alloc memory fail,exit.");
1861 return FAIL;
1862 }
1863
1864 //step2:load firmware link section 1
1865 GTP_DEBUG("[burn_fw_link]step2:load firmware link section 1");
1866 offset = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
1867 ret = gup_load_section_file(fw_link, offset, FW_SECTION_LENGTH, SEEK_SET);
1868 if(FAIL == ret)
1869 {
1870 GTP_ERROR("[burn_fw_link]load firmware link section 1 fail.");
1871 goto exit_burn_fw_link;
1872 }
1873
1874 //step3:burn link firmware section 1
1875 GTP_DEBUG("[burn_fw_link]step3:burn link firmware section 1");
1876 ret = gup_burn_fw_gwake_section(client, fw_link, 0x9000, FW_SECTION_LENGTH, 0x38);
1877
1878 if (FAIL == ret)
1879 {
1880 GTP_ERROR("[burn_fw_link]burn link firmware section 1 fail.");
1881 goto exit_burn_fw_link;
1882 }
1883
1884 //step4:load link firmware section 2 file data
1885 GTP_DEBUG("[burn_fw_link]step4:load link firmware section 2 file data");
1886 offset += FW_SECTION_LENGTH;
1887 ret = gup_load_section_file(fw_link, offset, FW_GLINK_LENGTH - FW_SECTION_LENGTH, SEEK_SET);
1888
1889 if (FAIL == ret)
1890 {
1891 GTP_ERROR("[burn_fw_link]load link firmware section 2 fail.");
1892 goto exit_burn_fw_link;
1893 }
1894
1895 //step5:burn link firmware section 2
1896 GTP_DEBUG("[burn_fw_link]step4:burn link firmware section 2");
1897 ret = gup_burn_fw_gwake_section(client, fw_link, 0x9000, FW_GLINK_LENGTH - FW_SECTION_LENGTH, 0x39);
1898
1899 if (FAIL == ret)
1900 {
1901 GTP_ERROR("[burn_fw_link]burn link firmware section 2 fail.");
1902 goto exit_burn_fw_link;
1903 }
1904
1905 update_msg.fw_burned_len += FW_GLINK_LENGTH;
1906 GTP_DEBUG("[burn_fw_link]Burned length:%d", update_msg.fw_burned_len);
1907 ret = SUCCESS;
1908
1909 exit_burn_fw_link:
1910 kfree(fw_link);
1911 return ret;
1912 }
1913
1914 static u8 gup_burn_fw_gwake_section(struct i2c_client *client, u8 *fw_section, u16 start_addr, u32 len, u8 bank_cmd )
1915 {
1916 s32 ret = 0;
1917 u8 rd_buf[5];
1918
1919 //step1:hold ss51 & dsp
1920 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
1921 if(ret <= 0)
1922 {
1923 GTP_ERROR("[burn_fw_app_section]hold ss51 & dsp fail.");
1924 return FAIL;
1925 }
1926
1927 //step2:set scramble
1928 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
1929 if(ret <= 0)
1930 {
1931 GTP_ERROR("[burn_fw_app_section]set scramble fail.");
1932 return FAIL;
1933 }
1934
1935 //step3:hold ss51 & release dsp
1936 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x04);
1937 if(ret <= 0)
1938 {
1939 GTP_ERROR("[burn_fw_app_section]hold ss51 & release dsp fail.");
1940 return FAIL;
1941 }
1942 //must delay
1943 msleep(1);
1944
1945 //step4:select bank
1946 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, (bank_cmd >> 4)&0x0F);
1947 if(ret <= 0)
1948 {
1949 GTP_ERROR("[burn_fw_section]select bank %d fail.", (bank_cmd >> 4)&0x0F);
1950 return FAIL;
1951 }
1952
1953 //step5:burn fw section
1954 ret = gup_burn_proc(client, fw_section, start_addr, len);
1955 if(FAIL == ret)
1956 {
1957 GTP_ERROR("[burn_fw_app_section]burn fw_section fail.");
1958 return FAIL;
1959 }
1960
1961 //step6:send burn cmd to move data to flash from sram
1962 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, bank_cmd&0x0F);
1963 if(ret <= 0)
1964 {
1965 GTP_ERROR("[burn_fw_app_section]send burn cmd fail.");
1966 return FAIL;
1967 }
1968 GTP_DEBUG("[burn_fw_section]Wait for the burn is complete......");
1969 do{
1970 ret = gup_get_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, rd_buf, 1);
1971 if(ret <= 0)
1972 {
1973 GTP_ERROR("[burn_fw_app_section]Get burn state fail");
1974 return FAIL;
1975 }
1976 msleep(10);
1977 //GTP_DEBUG("[burn_fw_app_section]Get burn state:%d.", rd_buf[GTP_ADDR_LENGTH]);
1978 }while(rd_buf[GTP_ADDR_LENGTH]);
1979
1980 //step7:recall fw section
1981 ret = gup_recall_check(client, fw_section, start_addr, len);
1982 if(FAIL == ret)
1983 {
1984 GTP_ERROR("[burn_fw_app_section]recall check %dk firmware fail.", len/1024);
1985 return FAIL;
1986 }
1987
1988 return SUCCESS;
1989 }
1990
1991 static u8 gup_burn_fw_gwake(struct i2c_client *client)
1992 {
1993 u8* fw_gwake = NULL;
1994 u8 retry = 0;
1995 s32 ret = 0;
1996 //u16 start_index = 4*FW_SECTION_LENGTH+FW_DSP_LENGTH+FW_BOOT_LENGTH + FW_DSP_ISP_LENGTH + FW_BOOT_ISP_LENGTH; // 32 + 4 + 2 + 4 = 42K
1997 u16 start_index;
1998
1999 if(update_msg.fw_burned_len >= update_msg.fw_total_len)
2000 {
2001 GTP_DEBUG("No need to upgrade the gwake code!");
2002 return SUCCESS;
2003 }
2004 start_index = update_msg.fw_burned_len - FW_DSP_ISP_LENGTH;
2005 GTP_INFO("[burn_fw_gwake]Begin burn gwake firmware---->>");
2006
2007 //step1:alloc memory
2008 GTP_DEBUG("[burn_fw_gwake]step1:alloc memory");
2009 while(retry++ < 5)
2010 {
2011 fw_gwake = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
2012 if(fw_gwake == NULL)
2013 {
2014 continue;
2015 }
2016 else
2017 {
2018 GTP_DEBUG("[burn_fw_gwake]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
2019 break;
2020 }
2021 }
2022 if(retry >= 5)
2023 {
2024 GTP_ERROR("[burn_fw_gwake]Alloc memory fail,exit.");
2025 return FAIL;
2026 }
2027
2028 //step2:load app_code firmware section 1 file data
2029 GTP_DEBUG("[burn_fw_gwake]step2:load app_code firmware section 1 file data");
2030 ret = gup_load_section_file(fw_gwake, start_index, FW_SECTION_LENGTH, SEEK_SET);
2031 if(FAIL == ret)
2032 {
2033 GTP_ERROR("[burn_fw_gwake]load app_code firmware section 1 fail.");
2034 goto exit_burn_fw_gwake;
2035 }
2036
2037 //step3:burn app_code firmware section 1
2038 GTP_DEBUG("[burn_fw_gwake]step3:burn app_code firmware section 1");
2039 ret = gup_burn_fw_gwake_section(client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3A);
2040 if(FAIL == ret)
2041 {
2042 GTP_ERROR("[burn_fw_gwake]burn app_code firmware section 1 fail.");
2043 goto exit_burn_fw_gwake;
2044 }
2045
2046 //step5:load app_code firmware section 2 file data
2047 GTP_DEBUG("[burn_fw_gwake]step5:load app_code firmware section 2 file data");
2048 ret = gup_load_section_file(fw_gwake, start_index+FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2049 if(FAIL == ret)
2050 {
2051 GTP_ERROR("[burn_fw_gwake]load app_code firmware section 2 fail.");
2052 goto exit_burn_fw_gwake;
2053 }
2054
2055 //step6:burn app_code firmware section 2
2056 GTP_DEBUG("[burn_fw_gwake]step6:burn app_code firmware section 2");
2057 ret = gup_burn_fw_gwake_section(client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3B);
2058 if(FAIL == ret)
2059 {
2060 GTP_ERROR("[burn_fw_gwake]burn app_code firmware section 2 fail.");
2061 goto exit_burn_fw_gwake;
2062 }
2063
2064 //step7:load app_code firmware section 3 file data
2065 GTP_DEBUG("[burn_fw_gwake]step7:load app_code firmware section 3 file data");
2066 ret = gup_load_section_file(fw_gwake, start_index+2*FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2067 if(FAIL == ret)
2068 {
2069 GTP_ERROR("[burn_fw_gwake]load app_code firmware section 3 fail.");
2070 goto exit_burn_fw_gwake;
2071 }
2072
2073 //step8:burn app_code firmware section 3
2074 GTP_DEBUG("[burn_fw_gwake]step8:burn app_code firmware section 3");
2075 ret = gup_burn_fw_gwake_section(client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3C);
2076 if(FAIL == ret)
2077 {
2078 GTP_ERROR("[burn_fw_gwake]burn app_code firmware section 3 fail.");
2079 goto exit_burn_fw_gwake;
2080 }
2081
2082 //step9:load app_code firmware section 4 file data
2083 GTP_DEBUG("[burn_fw_gwake]step9:load app_code firmware section 4 file data");
2084 ret = gup_load_section_file(fw_gwake, start_index + 3*FW_SECTION_LENGTH, FW_SECTION_LENGTH, SEEK_SET);
2085 if(FAIL == ret)
2086 {
2087 GTP_ERROR("[burn_fw_gwake]load app_code firmware section 4 fail.");
2088 goto exit_burn_fw_gwake;
2089 }
2090
2091 //step10:burn app_code firmware section 4
2092 GTP_DEBUG("[burn_fw_gwake]step10:burn app_code firmware section 4");
2093 ret = gup_burn_fw_gwake_section(client, fw_gwake, 0x9000, FW_SECTION_LENGTH, 0x3D);
2094 if(FAIL == ret)
2095 {
2096 GTP_ERROR("[burn_fw_gwake]burn app_code firmware section 4 fail.");
2097 goto exit_burn_fw_gwake;
2098 }
2099
2100 update_msg.fw_burned_len += FW_GWAKE_LENGTH;
2101 GTP_DEBUG("[burn_fw_gwake]Burned length:%d", update_msg.fw_burned_len);
2102 ret = SUCCESS;
2103
2104 exit_burn_fw_gwake:
2105 kfree(fw_gwake);
2106 return ret;
2107 }
2108
2109 static u8 gup_burn_fw_finish(struct i2c_client *client)
2110 {
2111 u8* fw_ss51 = NULL;
2112 u8 retry = 0;
2113 s32 ret = 0;
2114
2115 GTP_INFO("[burn_fw_finish]burn first 8K of ss51 and finish update.");
2116 //step1:alloc memory
2117 GTP_DEBUG("[burn_fw_finish]step1:alloc memory");
2118 while(retry++ < 5)
2119 {
2120 fw_ss51 = (u8*)kzalloc(FW_SECTION_LENGTH, GFP_KERNEL);
2121 if(fw_ss51 == NULL)
2122 {
2123 continue;
2124 }
2125 else
2126 {
2127 GTP_DEBUG("[burn_fw_finish]Alloc %dk byte memory success.", (FW_SECTION_LENGTH/1024));
2128 break;
2129 }
2130 }
2131 if(retry >= 5)
2132 {
2133 GTP_ERROR("[burn_fw_finish]Alloc memory fail,exit.");
2134 return FAIL;
2135 }
2136
2137 GTP_DEBUG("[burn_fw_finish]step2: burn ss51 first 8K.");
2138 ret = gup_load_section_file(fw_ss51, 0, FW_SECTION_LENGTH, SEEK_SET);
2139 if(FAIL == ret)
2140 {
2141 GTP_ERROR("[burn_fw_finish]load ss51 firmware section 1 fail.");
2142 goto exit_burn_fw_finish;
2143 }
2144
2145 GTP_DEBUG("[burn_fw_finish]step3:clear control flag");
2146 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
2147 if(ret <= 0)
2148 {
2149 GTP_ERROR("[burn_fw_finish]clear control flag fail.");
2150 goto exit_burn_fw_finish;
2151 }
2152
2153 GTP_DEBUG("[burn_fw_finish]step4:burn ss51 firmware section 1");
2154 ret = gup_burn_fw_section(client, fw_ss51, 0xC000, 0x01);
2155 if(FAIL == ret)
2156 {
2157 GTP_ERROR("[burn_fw_finish]burn ss51 firmware section 1 fail.");
2158 goto exit_burn_fw_finish;
2159 }
2160
2161 //step11:enable download DSP code
2162 GTP_DEBUG("[burn_fw_finish]step5:enable download DSP code ");
2163 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x99);
2164 if(ret <= 0)
2165 {
2166 GTP_ERROR("[burn_fw_finish]enable download DSP code fail.");
2167 goto exit_burn_fw_finish;
2168 }
2169
2170 //step12:release ss51 & hold dsp
2171 GTP_DEBUG("[burn_fw_finish]step6:release ss51 & hold dsp");
2172 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x08);
2173 if(ret <= 0)
2174 {
2175 GTP_ERROR("[burn_fw_finish]release ss51 & hold dsp fail.");
2176 goto exit_burn_fw_finish;
2177 }
2178
2179 if (fw_ss51)
2180 {
2181 kfree(fw_ss51);
2182 }
2183 return SUCCESS;
2184
2185 exit_burn_fw_finish:
2186 if (fw_ss51)
2187 {
2188 kfree(fw_ss51);
2189 }
2190 return FAIL;
2191 }
2192
2193 s32 gup_update_proc(void *dir)
2194 {
2195 s32 ret = 0;
2196 u8 retry = 0;
2197 s32 update_ret = FAIL;
2198 st_fw_head fw_head;
2199
2200 GTP_INFO("[update_proc]Begin update ......");
2201
2202 #if GTP_AUTO_UPDATE
2203 if (1 == searching_file)
2204 {
2205 u8 timeout = 0;
2206 searching_file = 0; // exit .bin update file searching
2207 GTP_INFO("Exiting searching file for auto update.");
2208 while ((show_len != 200) && (show_len != 100) && (timeout++ < 150)) // wait for auto update quitted completely
2209 {
2210 msleep(100);
2211 }
2212 }
2213 #endif
2214
2215 show_len = 1;
2216 total_len = 100;
2217
2218 #if GTP_COMPATIBLE_MODE
2219 if (CHIP_TYPE_GT9F == gtp_chip_type)
2220 {
2221 return gup_fw_download_proc(dir, GTP_FL_FW_BURN);
2222 }
2223 #endif
2224
2225 update_msg.file = NULL;
2226 ret = gup_check_update_file(i2c_client_point, &fw_head, (u8*)dir); //20121211
2227 if (FAIL == ret)
2228 {
2229 GTP_ERROR("[update_proc]check update file fail.");
2230 goto file_fail;
2231 }
2232
2233 //gtp_reset_guitar(i2c_client_point, 20);
2234 ret = gup_get_ic_fw_msg(i2c_client_point);
2235
2236 if (FAIL == ret)
2237 {
2238 GTP_ERROR("[update_proc]get ic message fail.");
2239 goto file_fail;
2240 }
2241
2242 ret = gup_enter_update_judge(&fw_head); //20121212
2243
2244 if (FAIL == ret)
2245 {
2246 GTP_ERROR("[update_proc]Check *.bin file fail.");
2247 goto file_fail;
2248 }
2249
2250 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
2251 #if GTP_ESD_PROTECT
2252 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
2253 #endif
2254 ret = gup_enter_update_mode(i2c_client_point);
2255
2256 if (FAIL == ret)
2257 {
2258 GTP_ERROR("[update_proc]enter update mode fail.");
2259 goto update_fail;
2260 }
2261
2262 while (retry++ < 5)
2263 {
2264 show_len = 10;
2265 total_len = 100;
2266 update_msg.fw_burned_len = 0;
2267 ret = gup_burn_dsp_isp(i2c_client_point);
2268 if(FAIL == ret)
2269 {
2270 GTP_ERROR("[update_proc]burn dsp isp fail.");
2271 continue;
2272 }
2273
2274 show_len = 20;
2275 ret = gup_burn_fw_ss51(i2c_client_point);
2276 if(FAIL == ret)
2277 {
2278 GTP_ERROR("[update_proc]burn ss51 firmware fail.");
2279 continue;
2280 }
2281
2282 show_len = 30;
2283 ret = gup_burn_fw_dsp(i2c_client_point);
2284 if(FAIL == ret)
2285 {
2286 GTP_ERROR("[update_proc]burn dsp firmware fail.");
2287 continue;
2288 }
2289
2290 show_len = 40;
2291 ret = gup_burn_fw_boot(i2c_client_point);
2292 if(FAIL == ret)
2293 {
2294 GTP_ERROR("[update_proc]burn bootloader firmware fail.");
2295 continue;
2296 }
2297 show_len = 50;
2298
2299 ret = gup_burn_fw_boot_isp(i2c_client_point);
2300 if (FAIL == ret)
2301 {
2302 GTP_ERROR("[update_proc]burn boot_isp firmware fail.");
2303 continue;
2304 }
2305
2306 show_len = 60;
2307 ret = gup_burn_fw_link(i2c_client_point);
2308 if (FAIL == ret)
2309 {
2310 GTP_ERROR("[update_proc]burn link firmware fail.");
2311 continue;
2312 }
2313
2314 show_len = 70;
2315 ret = gup_burn_fw_gwake(i2c_client_point);
2316 if (FAIL == ret)
2317 {
2318 GTP_ERROR("[update_proc]burn app_code firmware fail.");
2319 continue;
2320 }
2321 show_len = 80;
2322
2323 ret = gup_burn_fw_finish(i2c_client_point);
2324 if (FAIL == ret)
2325 {
2326 GTP_ERROR("[update_proc]burn finish fail.");
2327 continue;
2328 }
2329 show_len = 90;
2330 GTP_INFO("[update_proc]UPDATE SUCCESS.");
2331 retry = 0;
2332 break;
2333 }
2334
2335 if (retry >= 5)
2336 {
2337 GTP_ERROR("[update_proc]retry timeout,UPDATE FAIL.");
2338 update_ret = FAIL;
2339 }
2340 else
2341 {
2342 update_ret = SUCCESS;
2343 }
2344
2345 update_fail:
2346 GTP_DEBUG("[update_proc]leave update mode.");
2347 gup_leave_update_mode();
2348
2349 msleep(100);
2350
2351 if (SUCCESS == update_ret)
2352 {
2353 GTP_DEBUG("[update_proc]send config.");
2354 ret = gtp_send_cfg(i2c_client_point);
2355 if (ret < 0)
2356 {
2357 GTP_ERROR("[update_proc]send config fail.");
2358 }
2359 }
2360
2361 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
2362 #if GTP_ESD_PROTECT
2363 gtp_esd_switch(i2c_client_point, SWITCH_ON);
2364 #endif
2365
2366 file_fail:
2367
2368 if (update_msg.file && !IS_ERR(update_msg.file))
2369 {
2370 if (update_msg.old_fs)
2371 {
2372 set_fs(update_msg.old_fs);
2373 }
2374 filp_close(update_msg.file, NULL);
2375 }
2376 #if (GTP_AUTO_UPDATE && GTP_AUTO_UPDATE_CFG && GTP_HEADER_FW_UPDATE)
2377 if (NULL == dir)
2378 {
2379 gup_search_file(AUTO_SEARCH_CFG);
2380 if (got_file_flag & CFG_FILE_READY)
2381 {
2382 ret = gup_update_config(i2c_client_point);
2383 if(ret <= 0)
2384 {
2385 GTP_ERROR("Update config failed.");
2386 }
2387 _CLOSE_FILE(update_msg.cfg_file);
2388 msleep(500); //waiting config to be stored in FLASH.
2389 }
2390 }
2391 #endif
2392
2393 total_len = 100;
2394 if (SUCCESS == update_ret)
2395 {
2396 show_len = 100;
2397 return SUCCESS;
2398 }
2399 else
2400 {
2401 show_len = 200;
2402 return FAIL;
2403 }
2404 }
2405
2406 #if GTP_AUTO_UPDATE
2407 u8 gup_init_update_proc(struct i2c_client *client)
2408 {
2409 struct task_struct *thread = NULL;
2410
2411 GTP_INFO("Ready to run auto update thread");
2412
2413 #if GTP_COMPATIBLE_MODE
2414 if (CHIP_TYPE_GT9F == gtp_chip_type)
2415 {
2416 thread = kthread_run(gup_update_proc, "update", "fl_auto_update");
2417 }
2418 else
2419 #endif
2420 {
2421 thread = kthread_run(gup_update_proc, (void *)NULL, "guitar_update");
2422 }
2423 if (IS_ERR(thread))
2424 {
2425 GTP_ERROR("Failed to create update thread.\n");
2426 return -1;
2427 }
2428
2429 return 0;
2430 }
2431 #endif
2432
2433
2434 //******************* For GT9XXF Start ********************//
2435
2436 #define FL_UPDATE_PATH "/data/_fl_update_.bin"
2437 #define FL_UPDATE_PATH_SD "/sdcard/_fl_update_.bin"
2438
2439 #define FW_LITTLE_SS51_LENGTH (12 * 0x400) // 12K
2440
2441 #define GUP_FW_CHK_SIZE 256
2442 #define MAX_CHECK_TIMES 128 // max: 2 * (16 * 1024) / 256 = 128
2443
2444 //for clk cal
2445 #define PULSE_LENGTH (200)
2446 #define INIT_CLK_DAC (50)
2447 #define MAX_CLK_DAC (120)
2448 #define CLK_AVG_TIME (1)
2449 #define MILLION 1000000
2450
2451 #define _wRW_MISCTL__RG_DMY 0x4282
2452 #define _bRW_MISCTL__RG_OSC_CALIB 0x4268
2453 #define _fRW_MISCTL__GIO0 0x41e9
2454 #define _fRW_MISCTL__GIO1 0x41ed
2455 #define _fRW_MISCTL__GIO2 0x41f1
2456 #define _fRW_MISCTL__GIO3 0x41f5
2457 #define _fRW_MISCTL__GIO4 0x41f9
2458 #define _fRW_MISCTL__GIO5 0x41fd
2459 #define _fRW_MISCTL__GIO6 0x4201
2460 #define _fRW_MISCTL__GIO7 0x4205
2461 #define _fRW_MISCTL__GIO8 0x4209
2462 #define _fRW_MISCTL__GIO9 0x420d
2463 #define _fRW_MISCTL__MEA 0x41a0
2464 #define _bRW_MISCTL__MEA_MODE 0x41a1
2465 #define _wRW_MISCTL__MEA_MAX_NUM 0x41a4
2466 #define _dRO_MISCTL__MEA_VAL 0x41b0
2467 #define _bRW_MISCTL__MEA_SRCSEL 0x41a3
2468 #define _bRO_MISCTL__MEA_RDY 0x41a8
2469 #define _rRW_MISCTL__ANA_RXADC_B0_ 0x4250
2470 #define _bRW_MISCTL__RG_LDO_A18_PWD 0x426f
2471 #define _bRW_MISCTL__RG_BG_PWD 0x426a
2472 #define _bRW_MISCTL__RG_CLKGEN_PWD 0x4269
2473 #define _fRW_MISCTL__RG_RXADC_PWD 0x426a
2474 #define _bRW_MISCTL__OSC_CK_SEL 0x4030
2475 #define _rRW_MISCTL_RG_DMY83 0x4283
2476 #define _rRW_MISCTL__GIO1CTL_B2_ 0x41ee
2477 #define _rRW_MISCTL__GIO1CTL_B1_ 0x41ed
2478
2479 #if GTP_COMPATIBLE_MODE
2480
2481 u8 gup_check_fs_mounted(char *path_name)
2482 {
2483 struct path root_path;
2484 struct path path;
2485 int err;
2486 err = kern_path("/", LOOKUP_FOLLOW, &root_path);
2487
2488 if (err)
2489 return FAIL;
2490
2491 err = kern_path(path_name, LOOKUP_FOLLOW, &path);
2492
2493 if (err)
2494 return FAIL;
2495
2496 if (path.mnt->mnt_sb == root_path.mnt->mnt_sb)
2497 {
2498 //-- not mounted
2499 path_put(&path);
2500 path_put(&root_path);
2501 return FAIL;
2502 }
2503 else
2504 {
2505 path_put(&path);
2506 path_put(&root_path);
2507 return SUCCESS;
2508 }
2509 }
2510
2511 s32 gup_hold_ss51_dsp(struct i2c_client *client)
2512 {
2513 s32 ret = -1;
2514 s32 retry = 0;
2515 u8 rd_buf[3];
2516
2517 while(retry++ < 200)
2518 {
2519 #if GTP_FL_LITTLE_SYSTEM
2520 if (power_is_down)
2521 {
2522 GTP_DEBUG("System power is down, exit hold ss51 & dsp.");
2523 return FAIL;
2524 }
2525 #endif
2526 // step4:Hold ss51 & dsp
2527 ret = gup_set_ic_msg(client, _rRW_MISCTL__SWRST_B0_, 0x0C);
2528 if(ret <= 0)
2529 {
2530 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
2531 continue;
2532 }
2533
2534 // step5:Confirm hold
2535 ret = gup_get_ic_msg(client, _rRW_MISCTL__SWRST_B0_, rd_buf, 1);
2536 if (ret <= 0)
2537 {
2538 GTP_DEBUG("Hold ss51 & dsp I2C error,retry:%d", retry);
2539 continue;
2540 }
2541 if (0x0C == rd_buf[GTP_ADDR_LENGTH])
2542 {
2543 GTP_DEBUG("[enter_update_mode]Hold ss51 & dsp confirm SUCCESS");
2544 break;
2545 }
2546 GTP_DEBUG("Hold ss51 & dsp confirm 0x4180 failed,value:%d", rd_buf[GTP_ADDR_LENGTH]);
2547 }
2548 if(retry >= 200)
2549 {
2550 GTP_ERROR("Enter update Hold ss51 failed.");
2551 return FAIL;
2552 }
2553 //DSP_CK and DSP_ALU_CK PowerOn
2554 ret = gup_set_ic_msg(client, 0x4010, 0x00);
2555 if (ret <= 0)
2556 {
2557 GTP_ERROR("[enter_update_mode]DSP_CK and DSP_ALU_CK PowerOn fail.");
2558 return FAIL;
2559 }
2560
2561 //disable wdt
2562 ret = gup_set_ic_msg(client, _bRW_MISCTL__TMR0_EN, 0x00);
2563
2564 if (ret <= 0)
2565 {
2566 GTP_ERROR("[enter_update_mode]disable wdt fail.");
2567 return FAIL;
2568 }
2569
2570 //clear cache enable
2571 ret = gup_set_ic_msg(client, _bRW_MISCTL__CACHE_EN, 0x00);
2572
2573 if (ret <= 0)
2574 {
2575 GTP_ERROR("[enter_update_mode]clear cache enable fail.");
2576 return FAIL;
2577 }
2578
2579 //set boot from sram
2580 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOTCTL_B0_, 0x02);
2581
2582 if (ret <= 0)
2583 {
2584 GTP_ERROR("[enter_update_mode]set boot from sram fail.");
2585 return FAIL;
2586 }
2587
2588 //software reboot
2589 ret = gup_set_ic_msg(client, _bWO_MISCTL__CPU_SWRST_PULSE, 0x01);
2590 if (ret <= 0)
2591 {
2592 GTP_ERROR("[enter_update_mode]software reboot fail.");
2593 return FAIL;
2594 }
2595
2596 return SUCCESS;
2597 }
2598
2599 s32 gup_enter_update_mode_fl(struct i2c_client *client)
2600 {
2601 s32 ret = -1;
2602 //s32 retry = 0;
2603 //u8 rd_buf[3];
2604
2605 //step1:RST output low last at least 2ms
2606 GTP_GPIO_OUTPUT(GTP_RST_PORT, 0);
2607 msleep(2);
2608
2609 //step2:select I2C slave addr,INT:0--0xBA;1--0x28.
2610 GTP_GPIO_OUTPUT(GTP_INT_PORT, (client->addr == 0x14));
2611 msleep(2);
2612
2613 //step3:RST output high reset guitar
2614 GTP_GPIO_OUTPUT(GTP_RST_PORT, 1);
2615
2616 msleep(5);
2617
2618 //select addr & hold ss51_dsp
2619 ret = gup_hold_ss51_dsp(client);
2620 if (ret <= 0)
2621 {
2622 GTP_ERROR("[enter_update_mode]hold ss51 & dsp failed.");
2623 return FAIL;
2624 }
2625
2626 //clear control flag
2627 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_CTL_, 0x00);
2628
2629 if (ret <= 0)
2630 {
2631 GTP_ERROR("[enter_update_mode]clear control flag fail.");
2632 return FAIL;
2633 }
2634
2635 //set scramble
2636 ret = gup_set_ic_msg(client, _rRW_MISCTL__BOOT_OPT_B0_, 0x00);
2637
2638 if (ret <= 0)
2639 {
2640 GTP_ERROR("[enter_update_mode]set scramble fail.");
2641 return FAIL;
2642 }
2643
2644 //enable accessing code
2645 ret = gup_set_ic_msg(client, _bRW_MISCTL__MEM_CD_EN, 0x01);
2646
2647 if (ret <= 0)
2648 {
2649 GTP_ERROR("[enter_update_mode]enable accessing code fail.");
2650 return FAIL;
2651 }
2652
2653 return SUCCESS;
2654 }
2655
2656
2657 static s32 gup_prepare_fl_fw(char *path, st_fw_head *fw_head)
2658 {
2659 s32 i = 0;
2660 s32 ret = 0;
2661 s32 timeout = 0;
2662
2663 if (!memcmp(path, "update", 6))
2664 {
2665 GTP_INFO("Search for Flashless firmware file to update");
2666 searching_file = 1;
2667 for (i = 0; i < GUP_SEARCH_FILE_TIMES; ++i)
2668 {
2669 if (0 == searching_file)
2670 {
2671 GTP_INFO("Force terminate searching file auto update.");
2672 return FAIL;
2673 }
2674 update_msg.file = filp_open(FL_UPDATE_PATH, O_RDONLY, 0);
2675 if (IS_ERR(update_msg.file))
2676 {
2677 update_msg.file = filp_open(FL_UPDATE_PATH_SD, O_RDONLY, 0);
2678 if (IS_ERR(update_msg.file))
2679 {
2680 msleep(2000);
2681 continue;
2682 }
2683 else
2684 {
2685 path = FL_UPDATE_PATH_SD;
2686 break;
2687 }
2688 }
2689 else
2690 {
2691 path = FL_UPDATE_PATH;
2692 break;
2693 }
2694 }
2695 searching_file = 0;
2696 if (i >= 50)
2697 {
2698 GTP_ERROR("Search timeout, update aborted");
2699 return FAIL;
2700 }
2701 else
2702 {
2703 _CLOSE_FILE(update_msg.file);
2704 }
2705 while (rqst_processing && (timeout++ < 15))
2706 {
2707 GTP_INFO("wait for request process completed!");
2708 msleep(1000);
2709 }
2710 }
2711
2712 GTP_INFO("Firmware update file path: %s", path);
2713 update_msg.file = filp_open(path, O_RDONLY, 0);
2714
2715 if (IS_ERR(update_msg.file))
2716 {
2717 GTP_ERROR("Open update file(%s) error!", path);
2718 return FAIL;
2719 }
2720
2721 update_msg.old_fs = get_fs();
2722 set_fs(KERNEL_DS);
2723 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2724 update_msg.fw_total_len = update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_END);
2725 if (sizeof(gtp_default_FW_fl) != update_msg.fw_total_len)
2726 {
2727 GTP_ERROR("Inconsistent firmware size. File size: %d, default fw size: %d", update_msg.fw_total_len, sizeof(gtp_default_FW_fl));
2728 set_fs(update_msg.old_fs);
2729 _CLOSE_FILE(update_msg.file);
2730 return FAIL;
2731 }
2732
2733 GTP_DEBUG("Firmware size: %d", update_msg.fw_total_len);
2734 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2735 update_msg.file->f_op->read(update_msg.file, (char*)fw_head, FW_HEAD_LENGTH, &update_msg.file->f_pos);
2736
2737 update_msg.file->f_op->llseek(update_msg.file, 0, SEEK_SET);
2738 //copy fw file to gtp_default_FW_fl array
2739 ret = update_msg.file->f_op->read(update_msg.file,
2740 (char*)gtp_default_FW_fl,
2741 update_msg.fw_total_len,
2742 &update_msg.file->f_pos);
2743 if (ret < 0)
2744 {
2745 GTP_ERROR("Failed to read firmware data from %s, err-code: %d", path, ret);
2746 ret = FAIL;
2747 }
2748 else
2749 {
2750 ret = SUCCESS;
2751 }
2752 set_fs(update_msg.old_fs);
2753 _CLOSE_FILE(update_msg.file);
2754 return ret;
2755 }
2756
2757 static u8 gup_check_update_file_fl(struct i2c_client *client, st_fw_head *fw_head, char *path)
2758 {
2759 s32 i = 0;
2760 s32 fw_checksum = 0;
2761 s32 ret = 0;
2762
2763 if (NULL != path)
2764 {
2765 ret = gup_prepare_fl_fw(path, fw_head);
2766 if (ret == FAIL)
2767 {
2768 return FAIL;
2769 }
2770 }
2771
2772 memcpy(fw_head, gtp_default_FW_fl, FW_HEAD_LENGTH);
2773 GTP_INFO("FILE HARDWARE INFO:%02x%02x%02x%02x", fw_head->hw_info[0], fw_head->hw_info[1], fw_head->hw_info[2], fw_head->hw_info[3]);
2774 GTP_INFO("FILE PID:%s", fw_head->pid);
2775 fw_head->vid = ((fw_head->vid & 0xFF00) >> 8) + ((fw_head->vid & 0x00FF) << 8);
2776 GTP_INFO("FILE VID:%04x", fw_head->vid);
2777
2778 after_912_1020 = 0;
2779 if (!memcmp(fw_head->pid, "912", 3))
2780 {
2781 if (fw_head->vid > 0x1020)
2782 {
2783 after_912_1020 = 1;
2784 GTP_DEBUG("After 912_1020, config length set to 228");
2785 }
2786 }
2787
2788 //check firmware legality
2789 fw_checksum = 0;
2790 for (i = FW_HEAD_LENGTH; i < (FW_HEAD_LENGTH + update_msg.fw_total_len); i += 2)
2791 {
2792 fw_checksum = (gtp_default_FW_fl[i]<<8) + gtp_default_FW_fl[i+1];
2793 }
2794
2795 GTP_DEBUG("firmware checksum:%x", fw_checksum&0xFFFF);
2796 if(fw_checksum&0xFFFF)
2797 {
2798 GTP_ERROR("Illegal firmware file.");
2799 return FAIL;
2800 }
2801
2802 return SUCCESS;
2803 }
2804
2805 #if GTP_FL_LITTLE_SYSTEM
2806 // blocksize: 256Bytes
2807 u8 gup_burn_ss51_block(struct i2c_client *client, s32 block_section, s32 fw_block, u16 *fw_chksum)
2808 {
2809 s32 ret = 0;
2810 s32 index = 0;
2811 s32 i = 0;
2812
2813 GTP_DEBUG("Burn big ss51 block%d section%d (size: 256Bytes)", fw_block, block_section);
2814
2815 switch (fw_block)
2816 {
2817 case 1:
2818 case 2:
2819 case 3:
2820 case 4:
2821 case 5:
2822 case 6:
2823 case 7:
2824 case 8:
2825 index = FW_HEAD_LENGTH + (8 + fw_block-1)* 1024 * 2 + (block_section-1) * 256;
2826 break;
2827
2828 case 9:
2829 case 10:
2830 case 11:
2831 index = FW_HEAD_LENGTH + (16 - fw_block) * 1024 * 2 + (block_section-1) * 256;
2832 break;
2833 default:
2834 GTP_ERROR("Invalid firmware block: %d", fw_block);
2835 return FAIL;
2836 }
2837
2838 ret = i2c_write_bytes(client, GTP_REG_BUFFER + (block_section - 1) * 256,
2839 &gtp_default_FW_fl[index], 256);
2840
2841 if (ret < 0)
2842 {
2843 GTP_ERROR("Failed to burn ss51 block%d section%d (size: 256Bytes)!", fw_block, block_section);
2844 return FAIL;
2845 }
2846
2847 if (block_section == 1)
2848 {
2849 u16 chksum = 0;
2850
2851 for (i = 0; i < (2 * 1024); i += 2)
2852 {
2853 chksum += ((gtp_default_FW_fl[index + i]) << 8) + (gtp_default_FW_fl[index + i + 1]);
2854 }
2855 *fw_chksum = chksum;
2856 }
2857 return SUCCESS;
2858 }
2859
2860 u8 gup_burn_ss51_seg_b(struct i2c_client *client, s32 size, u16 *fw_chksum)
2861 {
2862 s32 ret = 0;
2863 s32 i = 0;
2864 u16 chksum = 0;
2865
2866 GTP_DEBUG("Burn big ss51 Seg B(size: %dK)", size);
2867
2868 ret = i2c_write_bytes(client, GTP_REG_SS51_SEG_B,
2869 &gtp_default_FW_fl[FW_HEAD_LENGTH], size * 1024);
2870
2871 if (ret < 0)
2872 {
2873 GTP_ERROR("Failed to Burn ss51 Seg B(size: %dK)", size);
2874 return FAIL;
2875 }
2876
2877 for (i = 0; i < (size * 1024); i += 2)
2878 {
2879 chksum += ((gtp_default_FW_fl[FW_HEAD_LENGTH + i]) << 8) + gtp_default_FW_fl[FW_HEAD_LENGTH + i + 1];
2880 }
2881 *fw_chksum = chksum;
2882 return SUCCESS;
2883 }
2884
2885 static u8 gup_download_fw_little_ss51(struct i2c_client *client)
2886 {
2887 s32 ret = 0;
2888 GTP_INFO("Download little ss51");
2889
2890 GTP_DEBUG("Select Bank0.");
2891
2892 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x00);
2893
2894 if (ret <= 0)
2895 {
2896 GTP_ERROR("Select bank0 fail.");
2897 return FAIL;
2898 }
2899
2900 // Just write
2901 ret = i2c_write_bytes(client, 0xC000,
2902 &gtp_default_FW_fl[FW_HEAD_LENGTH + FW_SS51_LENGTH + FW_DSP_LENGTH], FW_LITTLE_SS51_LENGTH);
2903
2904
2905 if (ret < 0)
2906 {
2907 GTP_ERROR("Failed to write little ss51.");
2908 return FAIL;
2909 }
2910
2911 return SUCCESS;
2912 }
2913
2914 #endif
2915
2916 static u8 gup_download_fw_ss51(struct i2c_client *client, u8 dwn_mode)
2917 {
2918 s32 ret = 0;
2919
2920 #if GTP_FL_LITTLE_SYSTEM
2921 if (GTP_FL_PWR_RESUME_BURN == dwn_mode)
2922 {
2923 return gup_download_fw_little_ss51(client);
2924 }
2925 #endif
2926
2927 if (GTP_FL_FW_BURN == dwn_mode)
2928 {
2929 GTP_DEBUG("[download_fw_ss51]Begin download ss51 firmware---->>");
2930 }
2931 else
2932 {
2933 GTP_DEBUG("[download_fw_ss51]Begin check ss51 firmware----->>");
2934 }
2935 //step1:download FW section 1
2936 GTP_DEBUG("[download_fw_ss51]step1:download FW section 1");
2937 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x00);
2938
2939 if (ret <= 0)
2940 {
2941 GTP_ERROR("[download_fw_ss51]select bank0 fail.");
2942 ret = FAIL;
2943 goto exit_download_fw_ss51;
2944 }
2945
2946
2947 ret = i2c_write_bytes(client, 0xC000,
2948 &gtp_default_FW_fl[FW_HEAD_LENGTH], FW_DOWNLOAD_LENGTH); // write the first bank
2949
2950 if (ret == -1)
2951 {
2952 GTP_ERROR("[download_fw_ss51]download FW section 1 fail.");
2953 ret = FAIL;
2954 goto exit_download_fw_ss51;
2955 }
2956
2957
2958 if (GTP_FL_FW_BURN == dwn_mode)
2959 {
2960 ret = gup_check_and_repair(i2c_client_point,
2961 0xC000,
2962 &gtp_default_FW_fl[FW_HEAD_LENGTH],
2963 FW_DOWNLOAD_LENGTH);
2964 if(FAIL == ret)
2965 {
2966 GTP_ERROR("[download_fw_ss51]Checked FW section 1 fail.");
2967 goto exit_download_fw_ss51;
2968 }
2969 }
2970
2971 //step2:download FW section 2
2972 GTP_DEBUG("[download_fw_ss51]step2:download FW section 1");
2973 ret = gup_set_ic_msg(i2c_client_point, _bRW_MISCTL__SRAM_BANK, 0x01);
2974
2975 if (ret <= 0)
2976 {
2977 GTP_ERROR("[download_fw_ss51]select bank1 fail.");
2978 ret = FAIL;
2979 goto exit_download_fw_ss51;
2980 }
2981
2982 ret = i2c_write_bytes(client, 0xC000, &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],FW_DOWNLOAD_LENGTH); // write the second bank
2983
2984 if (ret == -1)
2985 {
2986 GTP_ERROR("[download_fw_ss51]download FW section 2 fail.");
2987 ret = FAIL;
2988 goto exit_download_fw_ss51;
2989 }
2990
2991 if (GTP_FL_FW_BURN == dwn_mode)
2992 {
2993 ret = gup_check_and_repair(i2c_client_point,
2994 0xC000,
2995 &gtp_default_FW_fl[FW_HEAD_LENGTH+FW_DOWNLOAD_LENGTH],
2996 FW_DOWNLOAD_LENGTH);
2997
2998 if(FAIL == ret)
2999 {
3000 GTP_ERROR("[download_fw_ss51]Checked FW section 2 fail.");
3001 goto exit_download_fw_ss51;
3002 }
3003 }
3004 ret = SUCCESS;
3005
3006 exit_download_fw_ss51:
3007
3008 return ret;
3009 }
3010 #if (!GTP_SUPPORT_I2C_DMA)
3011 static s32 i2c_auto_read(struct i2c_client *client,u8 *rxbuf, int len)
3012 {
3013 u8 retry;
3014 u16 left = len;
3015 u16 offset = 0;
3016
3017 struct i2c_msg msg =
3018 {
3019 //.addr = ((client->addr &I2C_MASK_FLAG) | (I2C_ENEXT_FLAG)),
3020 .addr = ((client->addr &I2C_MASK_FLAG) | (I2C_PUSHPULL_FLAG)),
3021 .flags = I2C_M_RD,
3022 .timing = I2C_MASTER_CLOCK
3023 };
3024
3025 if(NULL == rxbuf)
3026 {
3027 return -1;
3028 }
3029
3030 while (left > 0)
3031 {
3032 msg.buf = &rxbuf[offset];
3033
3034 if (left > MAX_TRANSACTION_LENGTH)
3035 {
3036 msg.len = MAX_TRANSACTION_LENGTH;
3037 left -= MAX_TRANSACTION_LENGTH;
3038 offset += MAX_TRANSACTION_LENGTH;
3039 }
3040 else
3041 {
3042 msg.len = left;
3043 left = 0;
3044 }
3045
3046 retry = 0;
3047
3048 while (i2c_transfer(client->adapter, &msg, 1) != 1)
3049 {
3050 retry++;
3051
3052 if (retry == 20)
3053 {
3054 GTP_ERROR("I2C read 0x%X length=%d failed\n", offset, len);
3055 return -1;
3056 }
3057 }
3058 }
3059
3060 return 0;
3061 }
3062 #endif
3063
3064 static u8 gup_check_and_repair(struct i2c_client *client, s32 chk_start_addr, u8 *target_fw, u32 chk_total_length)
3065 {
3066 s32 ret = 0;
3067 u32 chked_len = 0;
3068 u8 chked_times = 0;
3069 u32 chk_addr = 0;
3070 u8 chk_buf[GUP_FW_CHK_SIZE];
3071 u32 rd_size = 0;
3072 u8 flag_err = 0;
3073 s32 i = 0;
3074
3075 chk_addr = chk_start_addr;
3076 while((chked_times < MAX_CHECK_TIMES) && (chked_len < chk_total_length))
3077 {
3078 rd_size = chk_total_length - chked_len;
3079 if(rd_size >= GUP_FW_CHK_SIZE)
3080 {
3081 rd_size = GUP_FW_CHK_SIZE;
3082 }
3083 #if GTP_SUPPORT_I2C_DMA
3084 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
3085 #else
3086 if (!i)
3087 {
3088 ret = i2c_read_bytes(client, chk_addr, chk_buf, rd_size);
3089 }
3090 else
3091 {
3092 ret = i2c_auto_read(client, chk_buf, rd_size);
3093 }
3094 #endif
3095
3096 if(-1 == ret)
3097 {
3098 GTP_ERROR("Read chk ram fw i2c error");
3099 chked_times++;
3100 continue;
3101 }
3102
3103 for(i=0; i<rd_size; i++)
3104 {
3105 if(chk_buf[i] != target_fw[i])
3106 {
3107 GTP_ERROR("Ram pos[0x%04x] checked failed,rewrite.", chk_addr + i);
3108 i2c_write_bytes(client, chk_addr+i, &target_fw[i], rd_size-i);
3109 flag_err = 1;
3110 i = 0;
3111 break;
3112 }
3113 }
3114
3115 if(!flag_err)
3116 {
3117 GTP_DEBUG("Ram pos[0x%04X] check pass!", chk_addr);
3118 chked_len += rd_size;
3119 target_fw += rd_size;
3120 chk_addr += rd_size;
3121 }
3122 else
3123 {
3124 flag_err = 0;
3125 chked_times++;
3126 }
3127 }
3128
3129 if(chked_times >= MAX_CHECK_TIMES)
3130 {
3131 GTP_ERROR("Ram data check failed.");
3132 return FAIL;
3133 }
3134 return SUCCESS;
3135 }
3136
3137 static u8 __gup_download_fw_dsp(struct i2c_client *client, u8 dwn_mode, int len)
3138 {
3139 s32 ret = 0;
3140
3141 if(GTP_FL_FW_BURN == dwn_mode)
3142 {
3143 GTP_DEBUG("[download_fw_dsp]Begin download dsp fw---->>");
3144 }
3145 else
3146 {
3147 GTP_DEBUG("[download_fw_dsp]Begin check dsp fw---->>");
3148 }
3149
3150 //step1:select bank2
3151 GTP_DEBUG("[download_fw_dsp]step1:select bank2");
3152 ret = gup_set_ic_msg(client, _bRW_MISCTL__SRAM_BANK, 0x02);
3153
3154 if (ret <= 0)
3155 {
3156 GTP_ERROR("[download_fw_dsp]select bank2 fail.");
3157 ret = FAIL;
3158 goto exit_download_fw_dsp;
3159 }
3160
3161 ret = i2c_write_bytes(client,
3162 0xC000,
3163 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
3164 len); // write the second bank
3165 if (ret == -1)
3166 {
3167 GTP_ERROR("[download_fw_dsp]download FW dsp fail.");
3168 ret = FAIL;
3169 goto exit_download_fw_dsp;
3170 }
3171
3172 if (GTP_FL_FW_BURN == dwn_mode)
3173 {
3174 ret = gup_check_and_repair(client,
3175 0xC000,
3176 &gtp_default_FW_fl[FW_HEAD_LENGTH+2*FW_DOWNLOAD_LENGTH],
3177 len);
3178
3179 if(FAIL == ret)
3180 {
3181 GTP_ERROR("[download_fw_dsp]Checked FW dsp fail.");
3182 goto exit_download_fw_dsp;
3183 }
3184
3185 }
3186 ret = SUCCESS;
3187
3188 exit_download_fw_dsp:
3189
3190 return ret;
3191 }
3192
3193 static u8 gup_download_fw_dsp(struct i2c_client *client, u8 dwn_mode)
3194 {
3195 return __gup_download_fw_dsp(client, dwn_mode, FW_DSP_LENGTH);
3196 }
3197
3198 s32 gup_fw_download_proc(void *dir, u8 dwn_mode)
3199 {
3200 s32 ret = 0;
3201 u8 retry = 0;
3202 st_fw_head fw_head;
3203
3204 #if GTP_FL_LITTLE_SYSTEM
3205 if (GTP_FL_PWR_RESUME_BURN == dwn_mode)
3206 {
3207 GTP_INFO("[fw_download_proc]Begin poweron resume little system download.....");
3208 }
3209 #endif
3210 if(GTP_FL_FW_BURN == dwn_mode)
3211 {
3212 GTP_INFO("[fw_download_proc]Begin fw download ......");
3213 }
3214 else
3215 {
3216 GTP_INFO("[fw_download_proc]Begin fw check ......");
3217 }
3218
3219 show_len = 0;
3220 total_len = 100;
3221
3222 ret = gup_check_update_file_fl(i2c_client_point, &fw_head, (char *)dir);
3223
3224 show_len = 10;
3225
3226 if (FAIL == ret)
3227 {
3228 GTP_ERROR("[fw_download_proc]check update file fail.");
3229 goto file_fail;
3230 }
3231
3232 if (!memcmp(fw_head.pid, "950", 3))
3233 {
3234 is_950 = 1;
3235 GTP_DEBUG("GT9XXF IC Type: gt950");
3236 }
3237 else
3238 {
3239 is_950 = 0;
3240 }
3241
3242 if (NULL != dir)
3243 {
3244 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
3245 #if GTP_ESD_PROTECT
3246 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
3247 #endif
3248 }
3249
3250 ret = gup_enter_update_mode_fl(i2c_client_point);
3251 show_len = 20;
3252
3253 if (FAIL == ret)
3254 {
3255 GTP_ERROR("[fw_download_proc]enter update mode fail.");
3256 goto download_fail;
3257 }
3258
3259 while (retry++ < 5)
3260 {
3261 ret = gup_download_fw_ss51(i2c_client_point, dwn_mode);
3262 show_len = 60;
3263 if (FAIL == ret)
3264 {
3265 GTP_ERROR("[fw_download_proc]burn ss51 firmware fail.");
3266 continue;
3267 }
3268
3269 ret = gup_download_fw_dsp(i2c_client_point, dwn_mode);
3270 show_len = 80;
3271 if (FAIL == ret)
3272 {
3273 GTP_ERROR("[fw_download_proc]burn dsp firmware fail.");
3274 continue;
3275 }
3276 GTP_INFO("[fw_download_proc]UPDATE SUCCESS.");
3277 retry = 0;
3278 break;
3279 }
3280
3281 if (retry >= 5)
3282 {
3283 GTP_ERROR("[fw_download_proc]retry timeout,UPDATE FAIL.");
3284 goto download_fail;
3285 }
3286
3287 if (NULL != dir)
3288 {
3289 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3290 gtp_fw_startup(i2c_client_point);
3291 #if GTP_ESD_PROTECT
3292 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3293 #endif
3294 }
3295 show_len = 100;
3296 return SUCCESS;
3297
3298 download_fail:
3299 if (NULL != dir)
3300 {
3301 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3302 gtp_fw_startup(i2c_client_point);
3303 #if GTP_ESD_PROTECT
3304 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3305 #endif
3306 }
3307
3308 file_fail:
3309 show_len = 200;
3310 return FAIL;
3311 }
3312
3313
3314 static void gup_bit_write(s32 addr, s32 bit, s32 val)
3315 {
3316 u8 buf;
3317 i2c_read_bytes(i2c_client_point, addr, &buf, 1);
3318
3319 buf = (buf & (~((u8)1 << bit))) | ((u8)val << bit);
3320
3321 i2c_write_bytes(i2c_client_point, addr, &buf, 1);
3322 }
3323
3324 static void gup_clk_count_init(s32 bCh, s32 bCNT)
3325 {
3326 u8 buf;
3327
3328 //_fRW_MISCTL__MEA_EN = 0; //Frequency measure enable
3329 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
3330 //_fRW_MISCTL__MEA_CLR = 1; //Frequency measure clear
3331 gup_bit_write(_fRW_MISCTL__MEA, 1, 1);
3332 //_bRW_MISCTL__MEA_MODE = 0; //Pulse mode
3333 buf = 0;
3334 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_MODE, &buf, 1);
3335 //_bRW_MISCTL__MEA_SRCSEL = 8 + bCh; //From GIO1
3336 buf = 8 + bCh;
3337 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__MEA_SRCSEL, &buf, 1);
3338 //_wRW_MISCTL__MEA_MAX_NUM = bCNT; //Set the Measure Counts = 1
3339 buf = bCNT;
3340 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__MEA_MAX_NUM, &buf, 1);
3341 //_fRW_MISCTL__MEA_CLR = 0; //Frequency measure not clear
3342 gup_bit_write(_fRW_MISCTL__MEA, 1, 0);
3343 //_fRW_MISCTL__MEA_EN = 1;
3344 gup_bit_write(_fRW_MISCTL__MEA, 0, 1);
3345 }
3346
3347 static u32 gup_clk_count_get(void)
3348 {
3349 s32 ready = 0;
3350 s32 temp;
3351 s8 buf[4];
3352
3353 while ((ready == 0)) //Wait for measurement complete
3354 {
3355 i2c_read_bytes(i2c_client_point, _bRO_MISCTL__MEA_RDY, buf, 1);
3356 ready = buf[0];
3357 }
3358
3359 udelay(50);
3360
3361 //_fRW_MISCTL__MEA_EN = 0;
3362 gup_bit_write(_fRW_MISCTL__MEA, 0, 0);
3363 i2c_read_bytes(i2c_client_point, _dRO_MISCTL__MEA_VAL, buf, 4);
3364 GTP_INFO("Clk_count 0: %2X", buf[0]);
3365 GTP_INFO("Clk_count 1: %2X", buf[1]);
3366 GTP_INFO("Clk_count 2: %2X", buf[2]);
3367 GTP_INFO("Clk_count 3: %2X", buf[3]);
3368
3369 temp = (s32)buf[0] + ((s32)buf[1] << 8) + ((s32)buf[2] << 16) + ((s32)buf[3] << 24);
3370 GTP_INFO("Clk_count : %d", temp);
3371 return temp;
3372 }
3373 u8 gup_clk_dac_setting(int dac)
3374 {
3375 s8 buf1, buf2;
3376
3377 i2c_read_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
3378 i2c_read_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
3379
3380 buf1 = (buf1 & 0xFFCF) | ((dac & 0x03) << 4);
3381 buf2 = (dac >> 2) & 0x3f;
3382
3383 i2c_write_bytes(i2c_client_point, _wRW_MISCTL__RG_DMY, &buf1, 1);
3384 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_OSC_CALIB, &buf2, 1);
3385
3386 return 0;
3387 }
3388
3389 static u8 gup_clk_calibration_pin_select(s32 bCh)
3390 {
3391 s32 i2c_addr;
3392
3393 switch (bCh)
3394 {
3395 case 0:
3396 i2c_addr = _fRW_MISCTL__GIO0;
3397 break;
3398
3399 case 1:
3400 i2c_addr = _fRW_MISCTL__GIO1;
3401 break;
3402
3403 case 2:
3404 i2c_addr = _fRW_MISCTL__GIO2;
3405 break;
3406
3407 case 3:
3408 i2c_addr = _fRW_MISCTL__GIO3;
3409 break;
3410
3411 case 4:
3412 i2c_addr = _fRW_MISCTL__GIO4;
3413 break;
3414
3415 case 5:
3416 i2c_addr = _fRW_MISCTL__GIO5;
3417 break;
3418
3419 case 6:
3420 i2c_addr = _fRW_MISCTL__GIO6;
3421 break;
3422
3423 case 7:
3424 i2c_addr = _fRW_MISCTL__GIO7;
3425 break;
3426
3427 case 8:
3428 i2c_addr = _fRW_MISCTL__GIO8;
3429 break;
3430
3431 case 9:
3432 i2c_addr = _fRW_MISCTL__GIO9;
3433 break;
3434 }
3435
3436 gup_bit_write(i2c_addr, 1, 0);
3437
3438 return 0;
3439 }
3440
3441 void gup_output_pulse(int t)
3442 {
3443 unsigned long flags;
3444 //s32 i;
3445
3446 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3447 udelay(10);
3448
3449 local_irq_save(flags);
3450
3451 mt_set_gpio_out(GTP_INT_PORT, 1);
3452 udelay(50);
3453 mt_set_gpio_out(GTP_INT_PORT, 0);
3454 udelay(t - 50);
3455 mt_set_gpio_out(GTP_INT_PORT, 1);
3456
3457 local_irq_restore(flags);
3458
3459 udelay(20);
3460 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3461 }
3462
3463 static void gup_sys_clk_init(void)
3464 {
3465 u8 buf;
3466
3467 //_fRW_MISCTL__RG_RXADC_CKMUX = 0;
3468 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 5, 0);
3469 //_bRW_MISCTL__RG_LDO_A18_PWD = 0; //DrvMISCTL_A18_PowerON
3470 buf = 0;
3471 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_LDO_A18_PWD, &buf, 1);
3472 //_bRW_MISCTL__RG_BG_PWD = 0; //DrvMISCTL_BG_PowerON
3473 buf = 0;
3474 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_BG_PWD, &buf, 1);
3475 //_bRW_MISCTL__RG_CLKGEN_PWD = 0; //DrvMISCTL_CLKGEN_PowerON
3476 buf = 0;
3477 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__RG_CLKGEN_PWD, &buf, 1);
3478 //_fRW_MISCTL__RG_RXADC_PWD = 0; //DrvMISCTL_RX_ADC_PowerON
3479 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 0, 0);
3480 //_fRW_MISCTL__RG_RXADC_REF_PWD = 0; //DrvMISCTL_RX_ADCREF_PowerON
3481 gup_bit_write(_rRW_MISCTL__ANA_RXADC_B0_, 1, 0);
3482 //gup_clk_dac_setting(60);
3483 //_bRW_MISCTL__OSC_CK_SEL = 1;;
3484 buf = 1;
3485 i2c_write_bytes(i2c_client_point, _bRW_MISCTL__OSC_CK_SEL, &buf, 1);
3486 }
3487
3488 u8 gup_clk_calibration(void)
3489 {
3490 //u8 buf;
3491 //u8 trigger;
3492 s32 i;
3493 struct timeval start, end;
3494 s32 count;
3495 s32 count_ref;
3496 s32 sec;
3497 s32 usec;
3498 s32 ret = 0;
3499 //unsigned long flags;
3500
3501 //buf = 0x0C; // hold ss51 and dsp
3502 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
3503 ret = gup_hold_ss51_dsp(i2c_client_point);
3504 if (ret <= 0)
3505 {
3506 GTP_ERROR("[gup_clk_calibration]hold ss51 & dsp failed.");
3507 return FAIL;
3508 }
3509
3510 //_fRW_MISCTL__CLK_BIAS = 0; //disable clock bias
3511 gup_bit_write(_rRW_MISCTL_RG_DMY83, 7, 0);
3512
3513 //_fRW_MISCTL__GIO1_PU = 0; //set TOUCH INT PIN MODE as input
3514 gup_bit_write(_rRW_MISCTL__GIO1CTL_B2_, 0, 0);
3515
3516 //_fRW_MISCTL__GIO1_OE = 0; //set TOUCH INT PIN MODE as input
3517 gup_bit_write(_rRW_MISCTL__GIO1CTL_B1_, 1, 0);
3518
3519 //buf = 0x00;
3520 //i2c_write_bytes(i2c_client_point, _rRW_MISCTL__SWRST_B0_, &buf, 1);
3521 //msleep(1000);
3522
3523 GTP_INFO("CLK calibration GO");
3524 gup_sys_clk_init();
3525 gup_clk_calibration_pin_select(1);//use GIO1 to do the calibration
3526
3527 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3528
3529 for (i = INIT_CLK_DAC; i < MAX_CLK_DAC; i++)
3530 {
3531 if (tpd_halt)
3532 {
3533 i = 72; //80; // if sleeping while calibrating main clock, set it default 80
3534 break;
3535 }
3536 GTP_INFO("CLK calibration DAC %d", i);
3537
3538 gup_clk_dac_setting(i);
3539 gup_clk_count_init(1, CLK_AVG_TIME);
3540
3541 #if 0
3542 gup_output_pulse(PULSE_LENGTH);
3543 count = gup_clk_count_get();
3544
3545 if (count > PULSE_LENGTH * 60)//60= 60Mhz * 1us
3546 {
3547 break;
3548 }
3549
3550 #else
3551 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3552
3553 //local_irq_save(flags);
3554 do_gettimeofday(&start);
3555 mt_set_gpio_out(GTP_INT_PORT, 1);
3556 //local_irq_restore(flags);
3557
3558 msleep(1);
3559 mt_set_gpio_out(GTP_INT_PORT, 0);
3560 msleep(1);
3561
3562 //local_irq_save(flags);
3563 do_gettimeofday(&end);
3564 mt_set_gpio_out(GTP_INT_PORT, 1);
3565 //local_irq_restore(flags);
3566
3567 count = gup_clk_count_get();
3568 udelay(20);
3569 GTP_GPIO_OUTPUT(GTP_INT_PORT, 0);
3570
3571 usec = end.tv_usec - start.tv_usec;
3572 sec = end.tv_sec - start.tv_sec;
3573 count_ref = 60 * (usec+ sec * MILLION);//60= 60Mhz * 1us
3574
3575 GTP_DEBUG("== time %d, %d, %d", sec, usec, count_ref);
3576
3577 if (count > count_ref)
3578 {
3579 GTP_DEBUG("== count_diff %d", count - count_ref);
3580 break;
3581 }
3582
3583 #endif
3584 }
3585
3586 //clk_dac = i;
3587
3588 //gtp_reset_guitar(i2c_client_point, 20);
3589
3590 #if 0//for debug
3591 //-- ouput clk to GPIO 4
3592 buf = 0x00;
3593 i2c_write_bytes(i2c_client_point, 0x41FA, &buf, 1);
3594 buf = 0x00;
3595 i2c_write_bytes(i2c_client_point, 0x4104, &buf, 1);
3596 buf = 0x00;
3597 i2c_write_bytes(i2c_client_point, 0x4105, &buf, 1);
3598 buf = 0x00;
3599 i2c_write_bytes(i2c_client_point, 0x4106, &buf, 1);
3600 buf = 0x01;
3601 i2c_write_bytes(i2c_client_point, 0x4107, &buf, 1);
3602 buf = 0x06;
3603 i2c_write_bytes(i2c_client_point, 0x41F8, &buf, 1);
3604 buf = 0x02;
3605 i2c_write_bytes(i2c_client_point, 0x41F9, &buf, 1);
3606 #endif
3607
3608 GTP_GPIO_AS_INT(GTP_INT_PORT);
3609 return i;
3610 }
3611
3612 int gup_reload_fw_dsp(void *dir, u8 dwn_mode)
3613 {
3614 s32 ret = 0;
3615 u8 retry = 0;
3616 u8 value = 0;
3617
3618 if (NULL != dir) {
3619 mt_eint_mask(CUST_EINT_TOUCH_PANEL_NUM);
3620 #if GTP_ESD_PROTECT
3621 gtp_esd_switch(i2c_client_point, SWITCH_OFF);
3622 #endif
3623 }
3624
3625 ret = gup_enter_update_mode_fl(i2c_client_point);
3626 if (FAIL == ret) {
3627 GTP_ERROR("[reload_fw_dsp]enter update mode fail.");
3628 goto download_fail;
3629 }
3630
3631 while (retry++ < 5) {
3632 ret = __gup_download_fw_dsp(i2c_client_point, dwn_mode, FW_DSP_LENGTH / 2); //reload 2k dsp code
3633 if (FAIL == ret){
3634 GTP_ERROR("[reload_fw_dsp]burn dsp firmware fail.");
3635 continue;
3636 }
3637 GTP_DEBUG("[reload_fw_dsp]UPDATE SUCCESS.");
3638 retry = 0;
3639 break;
3640 }
3641
3642 if (retry >= 5) {
3643 GTP_ERROR("[reload_fw_dsp]retry timeout,RELOAD FW DSP FAIL.");
3644 goto download_fail;
3645 }
3646
3647 if (NULL != dir) {
3648 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3649 gtp_fw_startup(i2c_client_point);
3650 #if GTP_ESD_PROTECT
3651 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3652 #endif
3653 }
3654 ret = i2c_write_bytes(i2c_client_point, 0x801F, &value, 1); // clear gesture mode reg
3655 if (ret == -1)
3656 return FAIL;
3657 else
3658 return SUCCESS;
3659
3660 download_fail:
3661 if (NULL != dir)
3662 {
3663 mt_eint_unmask(CUST_EINT_TOUCH_PANEL_NUM);
3664 gtp_fw_startup(i2c_client_point);
3665 #if GTP_ESD_PROTECT
3666 gtp_esd_switch(i2c_client_point, SWITCH_ON);
3667 #endif
3668 }
3669 return FAIL;
3670 }
3671 #endif
3672 //*************** For GT9XXF End ***********************//
kernel source for telekom puls (alcatel/mediatek)