1 #ifndef _MT6323_PMIC_UPMU_HW_H_
2 #define _MT6323_PMIC_UPMU_HW_H_
4 #include <mach/mt_typedefs.h>
7 #define PMIC_REG_BASE (0x0000)
9 #define CHR_CON0 ((UINT32)(PMIC_REG_BASE+0x0000))
10 #define CHR_CON1 ((UINT32)(PMIC_REG_BASE+0x0002))
11 #define CHR_CON2 ((UINT32)(PMIC_REG_BASE+0x0004))
12 #define CHR_CON3 ((UINT32)(PMIC_REG_BASE+0x0006))
13 #define CHR_CON4 ((UINT32)(PMIC_REG_BASE+0x0008))
14 #define CHR_CON5 ((UINT32)(PMIC_REG_BASE+0x000A))
15 #define CHR_CON6 ((UINT32)(PMIC_REG_BASE+0x000C))
16 #define CHR_CON7 ((UINT32)(PMIC_REG_BASE+0x000E))
17 #define CHR_CON8 ((UINT32)(PMIC_REG_BASE+0x0010))
18 #define CHR_CON9 ((UINT32)(PMIC_REG_BASE+0x0012))
19 #define CHR_CON10 ((UINT32)(PMIC_REG_BASE+0x0014))
20 #define CHR_CON11 ((UINT32)(PMIC_REG_BASE+0x0016))
21 #define CHR_CON12 ((UINT32)(PMIC_REG_BASE+0x0018))
22 #define CHR_CON13 ((UINT32)(PMIC_REG_BASE+0x001A))
23 #define CHR_CON14 ((UINT32)(PMIC_REG_BASE+0x001C))
24 #define CHR_CON15 ((UINT32)(PMIC_REG_BASE+0x001E))
25 #define CHR_CON16 ((UINT32)(PMIC_REG_BASE+0x0020))
26 #define CHR_CON17 ((UINT32)(PMIC_REG_BASE+0x0022))
27 #define CHR_CON18 ((UINT32)(PMIC_REG_BASE+0x0024))
28 #define CHR_CON19 ((UINT32)(PMIC_REG_BASE+0x0026))
29 #define CHR_CON20 ((UINT32)(PMIC_REG_BASE+0x0028))
30 #define CHR_CON21 ((UINT32)(PMIC_REG_BASE+0x002A))
31 #define CHR_CON22 ((UINT32)(PMIC_REG_BASE+0x002C))
32 #define CHR_CON23 ((UINT32)(PMIC_REG_BASE+0x002E))
33 #define CHR_CON24 ((UINT32)(PMIC_REG_BASE+0x0030))
34 #define CHR_CON25 ((UINT32)(PMIC_REG_BASE+0x0032))
35 #define CHR_CON26 ((UINT32)(PMIC_REG_BASE+0x0034))
36 #define CHR_CON27 ((UINT32)(PMIC_REG_BASE+0x0036))
37 #define CHR_CON28 ((UINT32)(PMIC_REG_BASE+0x0038))
38 #define CHR_CON29 ((UINT32)(PMIC_REG_BASE+0x003A))
39 #define STRUP_CON0 ((UINT32)(PMIC_REG_BASE+0x003C))
40 #define STRUP_CON2 ((UINT32)(PMIC_REG_BASE+0x003E))
41 #define STRUP_CON3 ((UINT32)(PMIC_REG_BASE+0x0040))
42 #define STRUP_CON4 ((UINT32)(PMIC_REG_BASE+0x0042))
43 #define STRUP_CON5 ((UINT32)(PMIC_REG_BASE+0x0044))
44 #define STRUP_CON6 ((UINT32)(PMIC_REG_BASE+0x0046))
45 #define STRUP_CON7 ((UINT32)(PMIC_REG_BASE+0x0048))
46 #define STRUP_CON8 ((UINT32)(PMIC_REG_BASE+0x004A))
47 #define STRUP_CON9 ((UINT32)(PMIC_REG_BASE+0x004C))
48 #define STRUP_CON10 ((UINT32)(PMIC_REG_BASE+0x004E))
49 #define STRUP_CON11 ((UINT32)(PMIC_REG_BASE+0x0050))
50 #define SPK_CON0 ((UINT32)(PMIC_REG_BASE+0x0052))
51 #define SPK_CON1 ((UINT32)(PMIC_REG_BASE+0x0054))
52 #define SPK_CON2 ((UINT32)(PMIC_REG_BASE+0x0056))
53 #define SPK_CON6 ((UINT32)(PMIC_REG_BASE+0x005E))
54 #define SPK_CON7 ((UINT32)(PMIC_REG_BASE+0x0060))
55 #define SPK_CON8 ((UINT32)(PMIC_REG_BASE+0x0062))
56 #define SPK_CON9 ((UINT32)(PMIC_REG_BASE+0x0064))
57 #define SPK_CON10 ((UINT32)(PMIC_REG_BASE+0x0066))
58 #define SPK_CON11 ((UINT32)(PMIC_REG_BASE+0x0068))
59 #define SPK_CON12 ((UINT32)(PMIC_REG_BASE+0x006A))
60 #define CID ((UINT32)(PMIC_REG_BASE+0x0100))
61 #define TOP_CKPDN0 ((UINT32)(PMIC_REG_BASE+0x0102))
62 #define TOP_CKPDN0_SET ((UINT32)(PMIC_REG_BASE+0x0104))
63 #define TOP_CKPDN0_CLR ((UINT32)(PMIC_REG_BASE+0x0106))
64 #define TOP_CKPDN1 ((UINT32)(PMIC_REG_BASE+0x0108))
65 #define TOP_CKPDN1_SET ((UINT32)(PMIC_REG_BASE+0x010A))
66 #define TOP_CKPDN1_CLR ((UINT32)(PMIC_REG_BASE+0x010C))
67 #define TOP_CKPDN2 ((UINT32)(PMIC_REG_BASE+0x010E))
68 #define TOP_CKPDN2_SET ((UINT32)(PMIC_REG_BASE+0x0110))
69 #define TOP_CKPDN2_CLR ((UINT32)(PMIC_REG_BASE+0x0112))
70 #define TOP_RST_CON ((UINT32)(PMIC_REG_BASE+0x0114))
71 #define TOP_RST_CON_SET ((UINT32)(PMIC_REG_BASE+0x0116))
72 #define TOP_RST_CON_CLR ((UINT32)(PMIC_REG_BASE+0x0118))
73 #define TOP_RST_MISC ((UINT32)(PMIC_REG_BASE+0x011A))
74 #define TOP_RST_MISC_SET ((UINT32)(PMIC_REG_BASE+0x011C))
75 #define TOP_RST_MISC_CLR ((UINT32)(PMIC_REG_BASE+0x011E))
76 #define TOP_CKCON0 ((UINT32)(PMIC_REG_BASE+0x0120))
77 #define TOP_CKCON0_SET ((UINT32)(PMIC_REG_BASE+0x0122))
78 #define TOP_CKCON0_CLR ((UINT32)(PMIC_REG_BASE+0x0124))
79 #define TOP_CKCON1 ((UINT32)(PMIC_REG_BASE+0x0126))
80 #define TOP_CKCON1_SET ((UINT32)(PMIC_REG_BASE+0x0128))
81 #define TOP_CKCON1_CLR ((UINT32)(PMIC_REG_BASE+0x012A))
82 #define TOP_CKTST0 ((UINT32)(PMIC_REG_BASE+0x012C))
83 #define TOP_CKTST1 ((UINT32)(PMIC_REG_BASE+0x012E))
84 #define TOP_CKTST2 ((UINT32)(PMIC_REG_BASE+0x0130))
85 #define TEST_OUT ((UINT32)(PMIC_REG_BASE+0x0132))
86 #define TEST_CON0 ((UINT32)(PMIC_REG_BASE+0x0134))
87 #define TEST_CON1 ((UINT32)(PMIC_REG_BASE+0x0136))
88 #define EN_STATUS0 ((UINT32)(PMIC_REG_BASE+0x0138))
89 #define EN_STATUS1 ((UINT32)(PMIC_REG_BASE+0x013A))
90 #define OCSTATUS0 ((UINT32)(PMIC_REG_BASE+0x013C))
91 #define OCSTATUS1 ((UINT32)(PMIC_REG_BASE+0x013E))
92 #define PGSTATUS ((UINT32)(PMIC_REG_BASE+0x0140))
93 #define CHRSTATUS ((UINT32)(PMIC_REG_BASE+0x0142))
94 #define TDSEL_CON ((UINT32)(PMIC_REG_BASE+0x0144))
95 #define RDSEL_CON ((UINT32)(PMIC_REG_BASE+0x0146))
96 #define SMT_CON0 ((UINT32)(PMIC_REG_BASE+0x0148))
97 #define SMT_CON1 ((UINT32)(PMIC_REG_BASE+0x014A))
98 #define SMT_CON2 ((UINT32)(PMIC_REG_BASE+0x014C))
99 #define SMT_CON3 ((UINT32)(PMIC_REG_BASE+0x014E))
100 #define SMT_CON4 ((UINT32)(PMIC_REG_BASE+0x0150))
101 #define DRV_CON0 ((UINT32)(PMIC_REG_BASE+0x0152))
102 #define DRV_CON1 ((UINT32)(PMIC_REG_BASE+0x0154))
103 #define DRV_CON2 ((UINT32)(PMIC_REG_BASE+0x0156))
104 #define DRV_CON3 ((UINT32)(PMIC_REG_BASE+0x0158))
105 #define DRV_CON4 ((UINT32)(PMIC_REG_BASE+0x015A))
106 #define SIMLS1_CON ((UINT32)(PMIC_REG_BASE+0x015C))
107 #define SIMLS2_CON ((UINT32)(PMIC_REG_BASE+0x015E))
108 #define INT_CON0 ((UINT32)(PMIC_REG_BASE+0x0160))
109 #define INT_CON0_SET ((UINT32)(PMIC_REG_BASE+0x0162))
110 #define INT_CON0_CLR ((UINT32)(PMIC_REG_BASE+0x0164))
111 #define INT_CON1 ((UINT32)(PMIC_REG_BASE+0x0166))
112 #define INT_CON1_SET ((UINT32)(PMIC_REG_BASE+0x0168))
113 #define INT_CON1_CLR ((UINT32)(PMIC_REG_BASE+0x016A))
114 #define INT_MISC_CON ((UINT32)(PMIC_REG_BASE+0x016C))
115 #define INT_MISC_CON_SET ((UINT32)(PMIC_REG_BASE+0x016E))
116 #define INT_MISC_CON_CLR ((UINT32)(PMIC_REG_BASE+0x0170))
117 #define INT_STATUS0 ((UINT32)(PMIC_REG_BASE+0x0172))
118 #define INT_STATUS1 ((UINT32)(PMIC_REG_BASE+0x0174))
119 #define OC_GEAR_0 ((UINT32)(PMIC_REG_BASE+0x0176))
120 #define OC_GEAR_1 ((UINT32)(PMIC_REG_BASE+0x0178))
121 #define OC_GEAR_2 ((UINT32)(PMIC_REG_BASE+0x017A))
122 #define OC_CTL_VPROC ((UINT32)(PMIC_REG_BASE+0x017C))
123 #define OC_CTL_VSYS ((UINT32)(PMIC_REG_BASE+0x017E))
124 #define OC_CTL_VPA ((UINT32)(PMIC_REG_BASE+0x0180))
125 #define FQMTR_CON0 ((UINT32)(PMIC_REG_BASE+0x0182))
126 #define FQMTR_CON1 ((UINT32)(PMIC_REG_BASE+0x0184))
127 #define FQMTR_CON2 ((UINT32)(PMIC_REG_BASE+0x0186))
128 #define RG_SPI_CON ((UINT32)(PMIC_REG_BASE+0x0188))
129 #define DEW_DIO_EN ((UINT32)(PMIC_REG_BASE+0x018A))
130 #define DEW_READ_TEST ((UINT32)(PMIC_REG_BASE+0x018C))
131 #define DEW_WRITE_TEST ((UINT32)(PMIC_REG_BASE+0x018E))
132 #define DEW_CRC_SWRST ((UINT32)(PMIC_REG_BASE+0x0190))
133 #define DEW_CRC_EN ((UINT32)(PMIC_REG_BASE+0x0192))
134 #define DEW_CRC_VAL ((UINT32)(PMIC_REG_BASE+0x0194))
135 #define DEW_DBG_MON_SEL ((UINT32)(PMIC_REG_BASE+0x0196))
136 #define DEW_CIPHER_KEY_SEL ((UINT32)(PMIC_REG_BASE+0x0198))
137 #define DEW_CIPHER_IV_SEL ((UINT32)(PMIC_REG_BASE+0x019A))
138 #define DEW_CIPHER_EN ((UINT32)(PMIC_REG_BASE+0x019C))
139 #define DEW_CIPHER_RDY ((UINT32)(PMIC_REG_BASE+0x019E))
140 #define DEW_CIPHER_MODE ((UINT32)(PMIC_REG_BASE+0x01A0))
141 #define DEW_CIPHER_SWRST ((UINT32)(PMIC_REG_BASE+0x01A2))
142 #define DEW_RDDMY_NO ((UINT32)(PMIC_REG_BASE+0x01A4))
143 #define DEW_RDATA_DLY_SEL ((UINT32)(PMIC_REG_BASE+0x01A6))
144 #define BUCK_CON0 ((UINT32)(PMIC_REG_BASE+0x0200))
145 #define BUCK_CON1 ((UINT32)(PMIC_REG_BASE+0x0202))
146 #define BUCK_CON2 ((UINT32)(PMIC_REG_BASE+0x0204))
147 #define BUCK_CON3 ((UINT32)(PMIC_REG_BASE+0x0206))
148 #define BUCK_CON4 ((UINT32)(PMIC_REG_BASE+0x0208))
149 #define BUCK_CON5 ((UINT32)(PMIC_REG_BASE+0x020A))
150 #define VPROC_CON0 ((UINT32)(PMIC_REG_BASE+0x020C))
151 #define VPROC_CON1 ((UINT32)(PMIC_REG_BASE+0x020E))
152 #define VPROC_CON2 ((UINT32)(PMIC_REG_BASE+0x0210))
153 #define VPROC_CON3 ((UINT32)(PMIC_REG_BASE+0x0212))
154 #define VPROC_CON4 ((UINT32)(PMIC_REG_BASE+0x0214))
155 #define VPROC_CON5 ((UINT32)(PMIC_REG_BASE+0x0216))
156 #define VPROC_CON7 ((UINT32)(PMIC_REG_BASE+0x021A))
157 #define VPROC_CON8 ((UINT32)(PMIC_REG_BASE+0x021C))
158 #define VPROC_CON9 ((UINT32)(PMIC_REG_BASE+0x021E))
159 #define VPROC_CON10 ((UINT32)(PMIC_REG_BASE+0x0220))
160 #define VPROC_CON11 ((UINT32)(PMIC_REG_BASE+0x0222))
161 #define VPROC_CON12 ((UINT32)(PMIC_REG_BASE+0x0224))
162 #define VPROC_CON13 ((UINT32)(PMIC_REG_BASE+0x0226))
163 #define VPROC_CON14 ((UINT32)(PMIC_REG_BASE+0x0228))
164 #define VPROC_CON15 ((UINT32)(PMIC_REG_BASE+0x022A))
165 #define VPROC_CON18 ((UINT32)(PMIC_REG_BASE+0x0230))
166 #define VSYS_CON0 ((UINT32)(PMIC_REG_BASE+0x0232))
167 #define VSYS_CON1 ((UINT32)(PMIC_REG_BASE+0x0234))
168 #define VSYS_CON2 ((UINT32)(PMIC_REG_BASE+0x0236))
169 #define VSYS_CON3 ((UINT32)(PMIC_REG_BASE+0x0238))
170 #define VSYS_CON4 ((UINT32)(PMIC_REG_BASE+0x023A))
171 #define VSYS_CON5 ((UINT32)(PMIC_REG_BASE+0x023C))
172 #define VSYS_CON7 ((UINT32)(PMIC_REG_BASE+0x0240))
173 #define VSYS_CON8 ((UINT32)(PMIC_REG_BASE+0x0242))
174 #define VSYS_CON9 ((UINT32)(PMIC_REG_BASE+0x0244))
175 #define VSYS_CON10 ((UINT32)(PMIC_REG_BASE+0x0246))
176 #define VSYS_CON11 ((UINT32)(PMIC_REG_BASE+0x0248))
177 #define VSYS_CON12 ((UINT32)(PMIC_REG_BASE+0x024A))
178 #define VSYS_CON13 ((UINT32)(PMIC_REG_BASE+0x024C))
179 #define VSYS_CON14 ((UINT32)(PMIC_REG_BASE+0x024E))
180 #define VSYS_CON15 ((UINT32)(PMIC_REG_BASE+0x0250))
181 #define VSYS_CON18 ((UINT32)(PMIC_REG_BASE+0x0256))
182 #define VPA_CON0 ((UINT32)(PMIC_REG_BASE+0x0300))
183 #define VPA_CON1 ((UINT32)(PMIC_REG_BASE+0x0302))
184 #define VPA_CON2 ((UINT32)(PMIC_REG_BASE+0x0304))
185 #define VPA_CON3 ((UINT32)(PMIC_REG_BASE+0x0306))
186 #define VPA_CON4 ((UINT32)(PMIC_REG_BASE+0x0308))
187 #define VPA_CON5 ((UINT32)(PMIC_REG_BASE+0x030A))
188 #define VPA_CON7 ((UINT32)(PMIC_REG_BASE+0x030E))
189 #define VPA_CON8 ((UINT32)(PMIC_REG_BASE+0x0310))
190 #define VPA_CON9 ((UINT32)(PMIC_REG_BASE+0x0312))
191 #define VPA_CON10 ((UINT32)(PMIC_REG_BASE+0x0314))
192 #define VPA_CON11 ((UINT32)(PMIC_REG_BASE+0x0316))
193 #define VPA_CON12 ((UINT32)(PMIC_REG_BASE+0x0318))
194 #define VPA_CON14 ((UINT32)(PMIC_REG_BASE+0x031C))
195 #define VPA_CON16 ((UINT32)(PMIC_REG_BASE+0x0320))
196 #define VPA_CON17 ((UINT32)(PMIC_REG_BASE+0x0322))
197 #define VPA_CON18 ((UINT32)(PMIC_REG_BASE+0x0324))
198 #define VPA_CON19 ((UINT32)(PMIC_REG_BASE+0x0326))
199 #define VPA_CON20 ((UINT32)(PMIC_REG_BASE+0x0328))
200 #define BUCK_K_CON0 ((UINT32)(PMIC_REG_BASE+0x032A))
201 #define BUCK_K_CON1 ((UINT32)(PMIC_REG_BASE+0x032C))
202 #define BUCK_K_CON2 ((UINT32)(PMIC_REG_BASE+0x032E))
203 #define ISINK0_CON0 ((UINT32)(PMIC_REG_BASE+0x0330))
204 #define ISINK0_CON1 ((UINT32)(PMIC_REG_BASE+0x0332))
205 #define ISINK0_CON2 ((UINT32)(PMIC_REG_BASE+0x0334))
206 #define ISINK0_CON3 ((UINT32)(PMIC_REG_BASE+0x0336))
207 #define ISINK1_CON0 ((UINT32)(PMIC_REG_BASE+0x0338))
208 #define ISINK1_CON1 ((UINT32)(PMIC_REG_BASE+0x033A))
209 #define ISINK1_CON2 ((UINT32)(PMIC_REG_BASE+0x033C))
210 #define ISINK1_CON3 ((UINT32)(PMIC_REG_BASE+0x033E))
211 #define ISINK2_CON0 ((UINT32)(PMIC_REG_BASE+0x0340))
212 #define ISINK2_CON1 ((UINT32)(PMIC_REG_BASE+0x0342))
213 #define ISINK2_CON2 ((UINT32)(PMIC_REG_BASE+0x0344))
214 #define ISINK2_CON3 ((UINT32)(PMIC_REG_BASE+0x0346))
215 #define ISINK3_CON0 ((UINT32)(PMIC_REG_BASE+0x0348))
216 #define ISINK3_CON1 ((UINT32)(PMIC_REG_BASE+0x034A))
217 #define ISINK3_CON2 ((UINT32)(PMIC_REG_BASE+0x034C))
218 #define ISINK3_CON3 ((UINT32)(PMIC_REG_BASE+0x034E))
219 #define ISINK_ANA0 ((UINT32)(PMIC_REG_BASE+0x0350))
220 #define ISINK_ANA1 ((UINT32)(PMIC_REG_BASE+0x0352))
221 #define ISINK_PHASE_DLY ((UINT32)(PMIC_REG_BASE+0x0354))
222 #define ISINK_EN_CTRL ((UINT32)(PMIC_REG_BASE+0x0356))
223 #define ANALDO_CON0 ((UINT32)(PMIC_REG_BASE+0x0400))
224 #define ANALDO_CON1 ((UINT32)(PMIC_REG_BASE+0x0402))
225 #define ANALDO_CON2 ((UINT32)(PMIC_REG_BASE+0x0404))
226 #define ANALDO_CON3 ((UINT32)(PMIC_REG_BASE+0x0406))
227 #define ANALDO_CON4 ((UINT32)(PMIC_REG_BASE+0x0408))
228 #define ANALDO_CON5 ((UINT32)(PMIC_REG_BASE+0x040A))
229 #define ANALDO_CON6 ((UINT32)(PMIC_REG_BASE+0x040C))
230 #define ANALDO_CON7 ((UINT32)(PMIC_REG_BASE+0x040E))
231 #define ANALDO_CON8 ((UINT32)(PMIC_REG_BASE+0x0410))
232 #define ANALDO_CON10 ((UINT32)(PMIC_REG_BASE+0x0412))
233 #define ANALDO_CON15 ((UINT32)(PMIC_REG_BASE+0x0414))
234 #define ANALDO_CON16 ((UINT32)(PMIC_REG_BASE+0x0416))
235 #define ANALDO_CON17 ((UINT32)(PMIC_REG_BASE+0x0418))
236 #define ANALDO_CON18 ((UINT32)(PMIC_REG_BASE+0x041A))
237 #define ANALDO_CON19 ((UINT32)(PMIC_REG_BASE+0x041C))
238 #define ANALDO_CON20 ((UINT32)(PMIC_REG_BASE+0x041E))
239 #define ANALDO_CON21 ((UINT32)(PMIC_REG_BASE+0x0420))
240 #define DIGLDO_CON0 ((UINT32)(PMIC_REG_BASE+0x0500))
241 #define DIGLDO_CON2 ((UINT32)(PMIC_REG_BASE+0x0502))
242 #define DIGLDO_CON3 ((UINT32)(PMIC_REG_BASE+0x0504))
243 #define DIGLDO_CON5 ((UINT32)(PMIC_REG_BASE+0x0506))
244 #define DIGLDO_CON6 ((UINT32)(PMIC_REG_BASE+0x0508))
245 #define DIGLDO_CON7 ((UINT32)(PMIC_REG_BASE+0x050A))
246 #define DIGLDO_CON8 ((UINT32)(PMIC_REG_BASE+0x050C))
247 #define DIGLDO_CON9 ((UINT32)(PMIC_REG_BASE+0x050E))
248 #define DIGLDO_CON10 ((UINT32)(PMIC_REG_BASE+0x0510))
249 #define DIGLDO_CON11 ((UINT32)(PMIC_REG_BASE+0x0512))
250 #define DIGLDO_CON12 ((UINT32)(PMIC_REG_BASE+0x0514))
251 #define DIGLDO_CON13 ((UINT32)(PMIC_REG_BASE+0x0516))
252 #define DIGLDO_CON14 ((UINT32)(PMIC_REG_BASE+0x0518))
253 #define DIGLDO_CON15 ((UINT32)(PMIC_REG_BASE+0x051A))
254 #define DIGLDO_CON16 ((UINT32)(PMIC_REG_BASE+0x051C))
255 #define DIGLDO_CON17 ((UINT32)(PMIC_REG_BASE+0x051E))
256 #define DIGLDO_CON18 ((UINT32)(PMIC_REG_BASE+0x0520))
257 #define DIGLDO_CON19 ((UINT32)(PMIC_REG_BASE+0x0522))
258 #define DIGLDO_CON20 ((UINT32)(PMIC_REG_BASE+0x0524))
259 #define DIGLDO_CON21 ((UINT32)(PMIC_REG_BASE+0x0526))
260 #define DIGLDO_CON23 ((UINT32)(PMIC_REG_BASE+0x0528))
261 #define DIGLDO_CON24 ((UINT32)(PMIC_REG_BASE+0x052A))
262 #define DIGLDO_CON26 ((UINT32)(PMIC_REG_BASE+0x052C))
263 #define DIGLDO_CON27 ((UINT32)(PMIC_REG_BASE+0x052E))
264 #define DIGLDO_CON28 ((UINT32)(PMIC_REG_BASE+0x0530))
265 #define DIGLDO_CON29 ((UINT32)(PMIC_REG_BASE+0x0532))
266 #define DIGLDO_CON30 ((UINT32)(PMIC_REG_BASE+0x0534))
267 #define DIGLDO_CON31 ((UINT32)(PMIC_REG_BASE+0x0536))
268 #define DIGLDO_CON32 ((UINT32)(PMIC_REG_BASE+0x0538))
269 #define DIGLDO_CON33 ((UINT32)(PMIC_REG_BASE+0x053A))
270 #define DIGLDO_CON34 ((UINT32)(PMIC_REG_BASE+0x053C))
271 #define DIGLDO_CON35 ((UINT32)(PMIC_REG_BASE+0x053E))
272 #define DIGLDO_CON36 ((UINT32)(PMIC_REG_BASE+0x0540))
273 #define DIGLDO_CON39 ((UINT32)(PMIC_REG_BASE+0x0542))
274 #define DIGLDO_CON40 ((UINT32)(PMIC_REG_BASE+0x0544))
275 #define DIGLDO_CON41 ((UINT32)(PMIC_REG_BASE+0x0546))
276 #define DIGLDO_CON42 ((UINT32)(PMIC_REG_BASE+0x0548))
277 #define DIGLDO_CON43 ((UINT32)(PMIC_REG_BASE+0x054A))
278 #define DIGLDO_CON44 ((UINT32)(PMIC_REG_BASE+0x054C))
279 #define DIGLDO_CON45 ((UINT32)(PMIC_REG_BASE+0x054E))
280 #define DIGLDO_CON46 ((UINT32)(PMIC_REG_BASE+0x0550))
281 #define DIGLDO_CON47 ((UINT32)(PMIC_REG_BASE+0x0552))
282 #define DIGLDO_CON48 ((UINT32)(PMIC_REG_BASE+0x0554))
283 #define DIGLDO_CON49 ((UINT32)(PMIC_REG_BASE+0x0556))
284 #define DIGLDO_CON50 ((UINT32)(PMIC_REG_BASE+0x0558))
285 #define DIGLDO_CON51 ((UINT32)(PMIC_REG_BASE+0x055A))
286 #define DIGLDO_CON52 ((UINT32)(PMIC_REG_BASE+0x055C))
287 #define DIGLDO_CON53 ((UINT32)(PMIC_REG_BASE+0x055E))
288 #define DIGLDO_CON54 ((UINT32)(PMIC_REG_BASE+0x0560))
289 #define EFUSE_CON0 ((UINT32)(PMIC_REG_BASE+0x0600))
290 #define EFUSE_CON1 ((UINT32)(PMIC_REG_BASE+0x0602))
291 #define EFUSE_CON2 ((UINT32)(PMIC_REG_BASE+0x0604))
292 #define EFUSE_CON3 ((UINT32)(PMIC_REG_BASE+0x0606))
293 #define EFUSE_CON4 ((UINT32)(PMIC_REG_BASE+0x0608))
294 #define EFUSE_CON5 ((UINT32)(PMIC_REG_BASE+0x060A))
295 #define EFUSE_CON6 ((UINT32)(PMIC_REG_BASE+0x060C))
296 #define EFUSE_VAL_0_15 ((UINT32)(PMIC_REG_BASE+0x060E))
297 #define EFUSE_VAL_16_31 ((UINT32)(PMIC_REG_BASE+0x0610))
298 #define EFUSE_VAL_32_47 ((UINT32)(PMIC_REG_BASE+0x0612))
299 #define EFUSE_VAL_48_63 ((UINT32)(PMIC_REG_BASE+0x0614))
300 #define EFUSE_VAL_64_79 ((UINT32)(PMIC_REG_BASE+0x0616))
301 #define EFUSE_VAL_80_95 ((UINT32)(PMIC_REG_BASE+0x0618))
302 #define EFUSE_VAL_96_111 ((UINT32)(PMIC_REG_BASE+0x061A))
303 #define EFUSE_VAL_112_127 ((UINT32)(PMIC_REG_BASE+0x061C))
304 #define EFUSE_VAL_128_143 ((UINT32)(PMIC_REG_BASE+0x061E))
305 #define EFUSE_VAL_144_159 ((UINT32)(PMIC_REG_BASE+0x0620))
306 #define EFUSE_VAL_160_175 ((UINT32)(PMIC_REG_BASE+0x0622))
307 #define EFUSE_VAL_176_191 ((UINT32)(PMIC_REG_BASE+0x0624))
308 #define EFUSE_DOUT_0_15 ((UINT32)(PMIC_REG_BASE+0x0626))
309 #define EFUSE_DOUT_16_31 ((UINT32)(PMIC_REG_BASE+0x0628))
310 #define EFUSE_DOUT_32_47 ((UINT32)(PMIC_REG_BASE+0x062A))
311 #define EFUSE_DOUT_48_63 ((UINT32)(PMIC_REG_BASE+0x062C))
312 #define EFUSE_DOUT_64_79 ((UINT32)(PMIC_REG_BASE+0x062E))
313 #define EFUSE_DOUT_80_95 ((UINT32)(PMIC_REG_BASE+0x0630))
314 #define EFUSE_DOUT_96_111 ((UINT32)(PMIC_REG_BASE+0x0632))
315 #define EFUSE_DOUT_112_127 ((UINT32)(PMIC_REG_BASE+0x0634))
316 #define EFUSE_DOUT_128_143 ((UINT32)(PMIC_REG_BASE+0x0636))
317 #define EFUSE_DOUT_144_159 ((UINT32)(PMIC_REG_BASE+0x0638))
318 #define EFUSE_DOUT_160_175 ((UINT32)(PMIC_REG_BASE+0x063A))
319 #define EFUSE_DOUT_176_191 ((UINT32)(PMIC_REG_BASE+0x063C))
320 #define EFUSE_CON7 ((UINT32)(PMIC_REG_BASE+0x063E))
321 #define EFUSE_CON8 ((UINT32)(PMIC_REG_BASE+0x0640))
322 #define EFUSE_CON9 ((UINT32)(PMIC_REG_BASE+0x0642))
323 #define RTC_MIX_CON0 ((UINT32)(PMIC_REG_BASE+0x0644))
324 #define RTC_MIX_CON1 ((UINT32)(PMIC_REG_BASE+0x0646))
325 #define AUDTOP_CON0 ((UINT32)(PMIC_REG_BASE+0x0700))
326 #define AUDTOP_CON1 ((UINT32)(PMIC_REG_BASE+0x0702))
327 #define AUDTOP_CON2 ((UINT32)(PMIC_REG_BASE+0x0704))
328 #define AUDTOP_CON3 ((UINT32)(PMIC_REG_BASE+0x0706))
329 #define AUDTOP_CON4 ((UINT32)(PMIC_REG_BASE+0x0708))
330 #define AUDTOP_CON5 ((UINT32)(PMIC_REG_BASE+0x070A))
331 #define AUDTOP_CON6 ((UINT32)(PMIC_REG_BASE+0x070C))
332 #define AUDTOP_CON7 ((UINT32)(PMIC_REG_BASE+0x070E))
333 #define AUDTOP_CON8 ((UINT32)(PMIC_REG_BASE+0x0710))
334 #define AUDTOP_CON9 ((UINT32)(PMIC_REG_BASE+0x0712))
335 #define AUXADC_ADC0 ((UINT32)(PMIC_REG_BASE+0x0714))
336 #define AUXADC_ADC1 ((UINT32)(PMIC_REG_BASE+0x0716))
337 #define AUXADC_ADC2 ((UINT32)(PMIC_REG_BASE+0x0718))
338 #define AUXADC_ADC3 ((UINT32)(PMIC_REG_BASE+0x071A))
339 #define AUXADC_ADC4 ((UINT32)(PMIC_REG_BASE+0x071C))
340 #define AUXADC_ADC5 ((UINT32)(PMIC_REG_BASE+0x071E))
341 #define AUXADC_ADC6 ((UINT32)(PMIC_REG_BASE+0x0720))
342 #define AUXADC_ADC7 ((UINT32)(PMIC_REG_BASE+0x0722))
343 #define AUXADC_ADC8 ((UINT32)(PMIC_REG_BASE+0x0724))
344 #define AUXADC_ADC9 ((UINT32)(PMIC_REG_BASE+0x0726))
345 #define AUXADC_ADC10 ((UINT32)(PMIC_REG_BASE+0x0728))
346 #define AUXADC_ADC11 ((UINT32)(PMIC_REG_BASE+0x072A))
347 #define AUXADC_ADC12 ((UINT32)(PMIC_REG_BASE+0x072C))
348 #define AUXADC_ADC13 ((UINT32)(PMIC_REG_BASE+0x072E))
349 #define AUXADC_ADC14 ((UINT32)(PMIC_REG_BASE+0x0730))
350 #define AUXADC_ADC15 ((UINT32)(PMIC_REG_BASE+0x0732))
351 #define AUXADC_ADC16 ((UINT32)(PMIC_REG_BASE+0x0734))
352 #define AUXADC_ADC17 ((UINT32)(PMIC_REG_BASE+0x0736))
353 #define AUXADC_ADC18 ((UINT32)(PMIC_REG_BASE+0x0738))
354 #define AUXADC_ADC19 ((UINT32)(PMIC_REG_BASE+0x073A))
355 #define AUXADC_ADC20 ((UINT32)(PMIC_REG_BASE+0x073C))
356 #define AUXADC_RSV1 ((UINT32)(PMIC_REG_BASE+0x073E))
357 #define AUXADC_RSV2 ((UINT32)(PMIC_REG_BASE+0x0740))
358 #define AUXADC_CON0 ((UINT32)(PMIC_REG_BASE+0x0742))
359 #define AUXADC_CON1 ((UINT32)(PMIC_REG_BASE+0x0744))
360 #define AUXADC_CON2 ((UINT32)(PMIC_REG_BASE+0x0746))
361 #define AUXADC_CON3 ((UINT32)(PMIC_REG_BASE+0x0748))
362 #define AUXADC_CON4 ((UINT32)(PMIC_REG_BASE+0x074A))
363 #define AUXADC_CON5 ((UINT32)(PMIC_REG_BASE+0x074C))
364 #define AUXADC_CON6 ((UINT32)(PMIC_REG_BASE+0x074E))
365 #define AUXADC_CON7 ((UINT32)(PMIC_REG_BASE+0x0750))
366 #define AUXADC_CON8 ((UINT32)(PMIC_REG_BASE+0x0752))
367 #define AUXADC_CON9 ((UINT32)(PMIC_REG_BASE+0x0754))
368 #define AUXADC_CON10 ((UINT32)(PMIC_REG_BASE+0x0756))
369 #define AUXADC_CON11 ((UINT32)(PMIC_REG_BASE+0x0758))
370 #define AUXADC_CON12 ((UINT32)(PMIC_REG_BASE+0x075A))
371 #define AUXADC_CON13 ((UINT32)(PMIC_REG_BASE+0x075C))
372 #define AUXADC_CON14 ((UINT32)(PMIC_REG_BASE+0x075E))
373 #define AUXADC_CON15 ((UINT32)(PMIC_REG_BASE+0x0760))
374 #define AUXADC_CON16 ((UINT32)(PMIC_REG_BASE+0x0762))
375 #define AUXADC_CON17 ((UINT32)(PMIC_REG_BASE+0x0764))
376 #define AUXADC_CON18 ((UINT32)(PMIC_REG_BASE+0x0766))
377 #define AUXADC_CON19 ((UINT32)(PMIC_REG_BASE+0x0768))
378 #define AUXADC_CON20 ((UINT32)(PMIC_REG_BASE+0x076A))
379 #define AUXADC_CON21 ((UINT32)(PMIC_REG_BASE+0x076C))
380 #define AUXADC_CON22 ((UINT32)(PMIC_REG_BASE+0x076E))
381 #define AUXADC_CON23 ((UINT32)(PMIC_REG_BASE+0x0770))
382 #define AUXADC_CON24 ((UINT32)(PMIC_REG_BASE+0x0772))
383 #define AUXADC_CON25 ((UINT32)(PMIC_REG_BASE+0x0774))
384 #define AUXADC_CON26 ((UINT32)(PMIC_REG_BASE+0x0776))
385 #define AUXADC_CON27 ((UINT32)(PMIC_REG_BASE+0x0778))
386 #define ACCDET_CON0 ((UINT32)(PMIC_REG_BASE+0x077A))
387 #define ACCDET_CON1 ((UINT32)(PMIC_REG_BASE+0x077C))
388 #define ACCDET_CON2 ((UINT32)(PMIC_REG_BASE+0x077E))
389 #define ACCDET_CON3 ((UINT32)(PMIC_REG_BASE+0x0780))
390 #define ACCDET_CON4 ((UINT32)(PMIC_REG_BASE+0x0782))
391 #define ACCDET_CON5 ((UINT32)(PMIC_REG_BASE+0x0784))
392 #define ACCDET_CON6 ((UINT32)(PMIC_REG_BASE+0x0786))
393 #define ACCDET_CON7 ((UINT32)(PMIC_REG_BASE+0x0788))
394 #define ACCDET_CON8 ((UINT32)(PMIC_REG_BASE+0x078A))
395 #define ACCDET_CON9 ((UINT32)(PMIC_REG_BASE+0x078C))
396 #define ACCDET_CON10 ((UINT32)(PMIC_REG_BASE+0x078E))
397 #define ACCDET_CON11 ((UINT32)(PMIC_REG_BASE+0x0790))
398 #define ACCDET_CON12 ((UINT32)(PMIC_REG_BASE+0x0792))
399 #define ACCDET_CON13 ((UINT32)(PMIC_REG_BASE+0x0794))
400 #define ACCDET_CON14 ((UINT32)(PMIC_REG_BASE+0x0796))
401 #define ACCDET_CON15 ((UINT32)(PMIC_REG_BASE+0x0798))
402 #define ACCDET_CON16 ((UINT32)(PMIC_REG_BASE+0x079A))
403 //mask is HEX; shift is Integer
404 #define PMIC_RG_VCDT_HV_EN_MASK 0x1
405 #define PMIC_RG_VCDT_HV_EN_SHIFT 0
406 #define PMIC_RGS_CHR_LDO_DET_MASK 0x1
407 #define PMIC_RGS_CHR_LDO_DET_SHIFT 1
408 #define PMIC_RG_PCHR_AUTOMODE_MASK 0x1
409 #define PMIC_RG_PCHR_AUTOMODE_SHIFT 2
410 #define PMIC_RG_CSDAC_EN_MASK 0x1
411 #define PMIC_RG_CSDAC_EN_SHIFT 3
412 #define PMIC_RG_CHR_EN_MASK 0x1
413 #define PMIC_RG_CHR_EN_SHIFT 4
414 #define PMIC_RGS_CHRDET_MASK 0x1
415 #define PMIC_RGS_CHRDET_SHIFT 5
416 #define PMIC_RGS_VCDT_LV_DET_MASK 0x1
417 #define PMIC_RGS_VCDT_LV_DET_SHIFT 6
418 #define PMIC_RGS_VCDT_HV_DET_MASK 0x1
419 #define PMIC_RGS_VCDT_HV_DET_SHIFT 7
420 #define PMIC_RG_VCDT_LV_VTH_MASK 0xF
421 #define PMIC_RG_VCDT_LV_VTH_SHIFT 0
422 #define PMIC_RG_VCDT_HV_VTH_MASK 0xF
423 #define PMIC_RG_VCDT_HV_VTH_SHIFT 4
424 #define PMIC_RG_VBAT_CV_EN_MASK 0x1
425 #define PMIC_RG_VBAT_CV_EN_SHIFT 1
426 #define PMIC_RG_VBAT_CC_EN_MASK 0x1
427 #define PMIC_RG_VBAT_CC_EN_SHIFT 2
428 #define PMIC_RG_CS_EN_MASK 0x1
429 #define PMIC_RG_CS_EN_SHIFT 3
430 #define PMIC_RGS_CS_DET_MASK 0x1
431 #define PMIC_RGS_CS_DET_SHIFT 5
432 #define PMIC_RGS_VBAT_CV_DET_MASK 0x1
433 #define PMIC_RGS_VBAT_CV_DET_SHIFT 6
434 #define PMIC_RGS_VBAT_CC_DET_MASK 0x1
435 #define PMIC_RGS_VBAT_CC_DET_SHIFT 7
436 #define PMIC_RG_VBAT_CV_VTH_MASK 0x1F
437 #define PMIC_RG_VBAT_CV_VTH_SHIFT 0
438 #define PMIC_RG_VBAT_CC_VTH_MASK 0x3
439 #define PMIC_RG_VBAT_CC_VTH_SHIFT 6
440 #define PMIC_RG_CS_VTH_MASK 0xF
441 #define PMIC_RG_CS_VTH_SHIFT 0
442 #define PMIC_RG_PCHR_TOHTC_MASK 0x7
443 #define PMIC_RG_PCHR_TOHTC_SHIFT 0
444 #define PMIC_RG_PCHR_TOLTC_MASK 0x7
445 #define PMIC_RG_PCHR_TOLTC_SHIFT 4
446 #define PMIC_RG_VBAT_OV_EN_MASK 0x1
447 #define PMIC_RG_VBAT_OV_EN_SHIFT 0
448 #define PMIC_RG_VBAT_OV_VTH_MASK 0x7
449 #define PMIC_RG_VBAT_OV_VTH_SHIFT 1
450 #define PMIC_RG_VBAT_OV_DEG_MASK 0x1
451 #define PMIC_RG_VBAT_OV_DEG_SHIFT 5
452 #define PMIC_RGS_VBAT_OV_DET_MASK 0x1
453 #define PMIC_RGS_VBAT_OV_DET_SHIFT 6
454 #define PMIC_RG_BATON_EN_MASK 0x1
455 #define PMIC_RG_BATON_EN_SHIFT 0
456 #define PMIC_RG_BATON_HT_EN_MASK 0x1
457 #define PMIC_RG_BATON_HT_EN_SHIFT 1
458 #define PMIC_BATON_TDET_EN_MASK 0x1
459 #define PMIC_BATON_TDET_EN_SHIFT 2
460 #define PMIC_RG_BATON_HT_TRIM_MASK 0x7
461 #define PMIC_RG_BATON_HT_TRIM_SHIFT 4
462 #define PMIC_RG_BATON_HT_TRIM_SET_MASK 0x1
463 #define PMIC_RG_BATON_HT_TRIM_SET_SHIFT 7
464 #define PMIC_RGS_BATON_UNDET_MASK 0x1
465 #define PMIC_RGS_BATON_UNDET_SHIFT 12
466 #define PMIC_RG_CSDAC_DATA_MASK 0x3FF
467 #define PMIC_RG_CSDAC_DATA_SHIFT 0
468 #define PMIC_RG_FRC_CSVTH_USBDL_MASK 0x1
469 #define PMIC_RG_FRC_CSVTH_USBDL_SHIFT 0
470 #define PMIC_RGS_PCHR_FLAG_OUT_MASK 0xF
471 #define PMIC_RGS_PCHR_FLAG_OUT_SHIFT 0
472 #define PMIC_RG_PCHR_FLAG_EN_MASK 0x1
473 #define PMIC_RG_PCHR_FLAG_EN_SHIFT 4
474 #define PMIC_RG_OTG_BVALID_EN_MASK 0x1
475 #define PMIC_RG_OTG_BVALID_EN_SHIFT 5
476 #define PMIC_RGS_OTG_BVALID_DET_MASK 0x1
477 #define PMIC_RGS_OTG_BVALID_DET_SHIFT 6
478 #define PMIC_RG_PCHR_FLAG_SEL_MASK 0x3F
479 #define PMIC_RG_PCHR_FLAG_SEL_SHIFT 0
480 #define PMIC_RG_PCHR_TESTMODE_MASK 0x1
481 #define PMIC_RG_PCHR_TESTMODE_SHIFT 0
482 #define PMIC_RG_CSDAC_TESTMODE_MASK 0x1
483 #define PMIC_RG_CSDAC_TESTMODE_SHIFT 1
484 #define PMIC_RG_PCHR_RST_MASK 0x1
485 #define PMIC_RG_PCHR_RST_SHIFT 2
486 #define PMIC_RG_PCHR_FT_CTRL_MASK 0x7
487 #define PMIC_RG_PCHR_FT_CTRL_SHIFT 4
488 #define PMIC_RG_CHRWDT_TD_MASK 0xF
489 #define PMIC_RG_CHRWDT_TD_SHIFT 0
490 #define PMIC_RG_CHRWDT_EN_MASK 0x1
491 #define PMIC_RG_CHRWDT_EN_SHIFT 4
492 #define PMIC_RG_CHRWDT_WR_MASK 0x1
493 #define PMIC_RG_CHRWDT_WR_SHIFT 8
494 #define PMIC_RG_PCHR_RV_MASK 0xFF
495 #define PMIC_RG_PCHR_RV_SHIFT 0
496 #define PMIC_RG_CHRWDT_INT_EN_MASK 0x1
497 #define PMIC_RG_CHRWDT_INT_EN_SHIFT 0
498 #define PMIC_RG_CHRWDT_FLAG_WR_MASK 0x1
499 #define PMIC_RG_CHRWDT_FLAG_WR_SHIFT 1
500 #define PMIC_RGS_CHRWDT_OUT_MASK 0x1
501 #define PMIC_RGS_CHRWDT_OUT_SHIFT 2
502 #define PMIC_RG_UVLO_VTHL_MASK 0x3
503 #define PMIC_RG_UVLO_VTHL_SHIFT 0
504 #define PMIC_RG_USBDL_RST_MASK 0x1
505 #define PMIC_RG_USBDL_RST_SHIFT 2
506 #define PMIC_RG_USBDL_SET_MASK 0x1
507 #define PMIC_RG_USBDL_SET_SHIFT 3
508 #define PMIC_ADCIN_VSEN_MUX_EN_MASK 0x1
509 #define PMIC_ADCIN_VSEN_MUX_EN_SHIFT 8
510 #define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_MASK 0x1
511 #define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT 9
512 #define PMIC_ADCIN_VBAT_EN_MASK 0x1
513 #define PMIC_ADCIN_VBAT_EN_SHIFT 10
514 #define PMIC_ADCIN_VSEN_EN_MASK 0x1
515 #define PMIC_ADCIN_VSEN_EN_SHIFT 11
516 #define PMIC_ADCIN_VCHR_EN_MASK 0x1
517 #define PMIC_ADCIN_VCHR_EN_SHIFT 12
518 #define PMIC_RG_BGR_RSEL_MASK 0x7
519 #define PMIC_RG_BGR_RSEL_SHIFT 0
520 #define PMIC_RG_BGR_UNCHOP_PH_MASK 0x1
521 #define PMIC_RG_BGR_UNCHOP_PH_SHIFT 4
522 #define PMIC_RG_BGR_UNCHOP_MASK 0x1
523 #define PMIC_RG_BGR_UNCHOP_SHIFT 5
524 #define PMIC_RG_BC11_BB_CTRL_MASK 0x1
525 #define PMIC_RG_BC11_BB_CTRL_SHIFT 0
526 #define PMIC_RG_BC11_RST_MASK 0x1
527 #define PMIC_RG_BC11_RST_SHIFT 1
528 #define PMIC_RG_BC11_VSRC_EN_MASK 0x3
529 #define PMIC_RG_BC11_VSRC_EN_SHIFT 2
530 #define PMIC_RGS_BC11_CMP_OUT_MASK 0x1
531 #define PMIC_RGS_BC11_CMP_OUT_SHIFT 7
532 #define PMIC_RG_BC11_VREF_VTH_MASK 0x3
533 #define PMIC_RG_BC11_VREF_VTH_SHIFT 0
534 #define PMIC_RG_BC11_CMP_EN_MASK 0x3
535 #define PMIC_RG_BC11_CMP_EN_SHIFT 2
536 #define PMIC_RG_BC11_IPD_EN_MASK 0x3
537 #define PMIC_RG_BC11_IPD_EN_SHIFT 4
538 #define PMIC_RG_BC11_IPU_EN_MASK 0x3
539 #define PMIC_RG_BC11_IPU_EN_SHIFT 6
540 #define PMIC_RG_BC11_BIAS_EN_MASK 0x1
541 #define PMIC_RG_BC11_BIAS_EN_SHIFT 8
542 #define PMIC_RG_CSDAC_STP_INC_MASK 0x7
543 #define PMIC_RG_CSDAC_STP_INC_SHIFT 0
544 #define PMIC_RG_CSDAC_STP_DEC_MASK 0x7
545 #define PMIC_RG_CSDAC_STP_DEC_SHIFT 4
546 #define PMIC_RG_CSDAC_DLY_MASK 0x7
547 #define PMIC_RG_CSDAC_DLY_SHIFT 0
548 #define PMIC_RG_CSDAC_STP_MASK 0x7
549 #define PMIC_RG_CSDAC_STP_SHIFT 4
550 #define PMIC_RG_LOW_ICH_DB_MASK 0x3F
551 #define PMIC_RG_LOW_ICH_DB_SHIFT 0
552 #define PMIC_RG_CHRIND_ON_MASK 0x1
553 #define PMIC_RG_CHRIND_ON_SHIFT 6
554 #define PMIC_RG_CHRIND_DIMMING_MASK 0x1
555 #define PMIC_RG_CHRIND_DIMMING_SHIFT 7
556 #define PMIC_RG_CV_MODE_MASK 0x1
557 #define PMIC_RG_CV_MODE_SHIFT 0
558 #define PMIC_RG_VCDT_MODE_MASK 0x1
559 #define PMIC_RG_VCDT_MODE_SHIFT 1
560 #define PMIC_RG_CSDAC_MODE_MASK 0x1
561 #define PMIC_RG_CSDAC_MODE_SHIFT 2
562 #define PMIC_RG_TRACKING_EN_MASK 0x1
563 #define PMIC_RG_TRACKING_EN_SHIFT 4
564 #define PMIC_RG_HWCV_EN_MASK 0x1
565 #define PMIC_RG_HWCV_EN_SHIFT 6
566 #define PMIC_RG_ULC_DET_EN_MASK 0x1
567 #define PMIC_RG_ULC_DET_EN_SHIFT 7
568 #define PMIC_RG_BGR_TRIM_EN_MASK 0x1
569 #define PMIC_RG_BGR_TRIM_EN_SHIFT 0
570 #define PMIC_RG_ICHRG_TRIM_MASK 0xF
571 #define PMIC_RG_ICHRG_TRIM_SHIFT 4
572 #define PMIC_RG_BGR_TRIM_MASK 0x1F
573 #define PMIC_RG_BGR_TRIM_SHIFT 0
574 #define PMIC_RG_OVP_TRIM_MASK 0xF
575 #define PMIC_RG_OVP_TRIM_SHIFT 0
576 #define PMIC_RG_CHR_OSC_TRIM_MASK 0x1F
577 #define PMIC_RG_CHR_OSC_TRIM_SHIFT 0
578 #define PMIC_QI_BGR_EXT_BUF_EN_MASK 0x1
579 #define PMIC_QI_BGR_EXT_BUF_EN_SHIFT 5
580 #define PMIC_RG_BGR_TEST_EN_MASK 0x1
581 #define PMIC_RG_BGR_TEST_EN_SHIFT 6
582 #define PMIC_RG_BGR_TEST_RSTB_MASK 0x1
583 #define PMIC_RG_BGR_TEST_RSTB_SHIFT 7
584 #define PMIC_RG_DAC_USBDL_MAX_MASK 0x3FF
585 #define PMIC_RG_DAC_USBDL_MAX_SHIFT 0
586 #define PMIC_RG_PCHR_RSV_MASK 0xFF
587 #define PMIC_RG_PCHR_RSV_SHIFT 0
588 #define PMIC_THR_DET_DIS_MASK 0x1
589 #define PMIC_THR_DET_DIS_SHIFT 0
590 #define PMIC_RG_THR_TMODE_MASK 0x1
591 #define PMIC_RG_THR_TMODE_SHIFT 1
592 #define PMIC_RG_THR_TEMP_SEL_MASK 0x1
593 #define PMIC_RG_THR_TEMP_SEL_SHIFT 2
594 #define PMIC_RG_STRUP_THR_SEL_MASK 0x3
595 #define PMIC_RG_STRUP_THR_SEL_SHIFT 3
596 #define PMIC_THR_HWPDN_EN_MASK 0x1
597 #define PMIC_THR_HWPDN_EN_SHIFT 5
598 #define PMIC_RG_THRDET_SEL_MASK 0x1
599 #define PMIC_RG_THRDET_SEL_SHIFT 6
600 #define PMIC_RG_STRUP_IREF_TRIM_MASK 0x1F
601 #define PMIC_RG_STRUP_IREF_TRIM_SHIFT 0
602 #define PMIC_RG_USBDL_EN_MASK 0x1
603 #define PMIC_RG_USBDL_EN_SHIFT 0
604 #define PMIC_RG_FCHR_KEYDET_EN_MASK 0x1
605 #define PMIC_RG_FCHR_KEYDET_EN_SHIFT 1
606 #define PMIC_RG_FCHR_PU_EN_MASK 0x1
607 #define PMIC_RG_FCHR_PU_EN_SHIFT 2
608 #define PMIC_RG_EN_DRVSEL_MASK 0x1
609 #define PMIC_RG_EN_DRVSEL_SHIFT 4
610 #define PMIC_RG_RST_DRVSEL_MASK 0x1
611 #define PMIC_RG_RST_DRVSEL_SHIFT 5
612 #define PMIC_RG_VREF_BG_MASK 0x7
613 #define PMIC_RG_VREF_BG_SHIFT 12
614 #define PMIC_RG_PMU_RSV_MASK 0xF
615 #define PMIC_RG_PMU_RSV_SHIFT 0
616 #define PMIC_THR_TEST_MASK 0x3
617 #define PMIC_THR_TEST_SHIFT 0
618 #define PMIC_PMU_THR_DEB_MASK 0x7
619 #define PMIC_PMU_THR_DEB_SHIFT 4
620 #define PMIC_PMU_THR_STATUS_MASK 0x7
621 #define PMIC_PMU_THR_STATUS_SHIFT 8
622 #define PMIC_DDUVLO_DEB_EN_MASK 0x1
623 #define PMIC_DDUVLO_DEB_EN_SHIFT 0
624 #define PMIC_PWRBB_DEB_EN_MASK 0x1
625 #define PMIC_PWRBB_DEB_EN_SHIFT 1
626 #define PMIC_STRUP_OSC_EN_MASK 0x1
627 #define PMIC_STRUP_OSC_EN_SHIFT 2
628 #define PMIC_STRUP_OSC_EN_SEL_MASK 0x1
629 #define PMIC_STRUP_OSC_EN_SEL_SHIFT 3
630 #define PMIC_STRUP_FT_CTRL_MASK 0x3
631 #define PMIC_STRUP_FT_CTRL_SHIFT 4
632 #define PMIC_STRUP_PWRON_FORCE_MASK 0x1
633 #define PMIC_STRUP_PWRON_FORCE_SHIFT 6
634 #define PMIC_BIAS_GEN_EN_FORCE_MASK 0x1
635 #define PMIC_BIAS_GEN_EN_FORCE_SHIFT 7
636 #define PMIC_STRUP_PWRON_MASK 0x1
637 #define PMIC_STRUP_PWRON_SHIFT 8
638 #define PMIC_STRUP_PWRON_SEL_MASK 0x1
639 #define PMIC_STRUP_PWRON_SEL_SHIFT 9
640 #define PMIC_BIAS_GEN_EN_MASK 0x1
641 #define PMIC_BIAS_GEN_EN_SHIFT 10
642 #define PMIC_BIAS_GEN_EN_SEL_MASK 0x1
643 #define PMIC_BIAS_GEN_EN_SEL_SHIFT 11
644 #define PMIC_RTC_XOSC32_ENB_SW_MASK 0x1
645 #define PMIC_RTC_XOSC32_ENB_SW_SHIFT 12
646 #define PMIC_RTC_XOSC32_ENB_SEL_MASK 0x1
647 #define PMIC_RTC_XOSC32_ENB_SEL_SHIFT 13
648 #define PMIC_STRUP_DIG_IO_PG_FORCE_MASK 0x1
649 #define PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT 15
650 #define PMIC_VPROC_PG_ENB_MASK 0x1
651 #define PMIC_VPROC_PG_ENB_SHIFT 0
652 #define PMIC_VSYS_PG_ENB_MASK 0x1
653 #define PMIC_VSYS_PG_ENB_SHIFT 1
654 #define PMIC_VM_PG_ENB_MASK 0x1
655 #define PMIC_VM_PG_ENB_SHIFT 2
656 #define PMIC_VIO18_PG_ENB_MASK 0x1
657 #define PMIC_VIO18_PG_ENB_SHIFT 3
658 #define PMIC_VTCXO_PG_ENB_MASK 0x1
659 #define PMIC_VTCXO_PG_ENB_SHIFT 4
660 #define PMIC_VA_PG_ENB_MASK 0x1
661 #define PMIC_VA_PG_ENB_SHIFT 5
662 #define PMIC_VIO28_PG_ENB_MASK 0x1
663 #define PMIC_VIO28_PG_ENB_SHIFT 6
664 #define PMIC_VGP2_PG_ENB_MASK 0x1
665 #define PMIC_VGP2_PG_ENB_SHIFT 7
666 #define PMIC_VPROC_PG_H2L_EN_MASK 0x1
667 #define PMIC_VPROC_PG_H2L_EN_SHIFT 8
668 #define PMIC_VSYS_PG_H2L_EN_MASK 0x1
669 #define PMIC_VSYS_PG_H2L_EN_SHIFT 9
670 #define PMIC_STRUP_CON6_RSV0_MASK 0x3
671 #define PMIC_STRUP_CON6_RSV0_SHIFT 10
672 #define PMIC_CLR_JUST_RST_MASK 0x1
673 #define PMIC_CLR_JUST_RST_SHIFT 4
674 #define PMIC_UVLO_L2H_DEB_EN_MASK 0x1
675 #define PMIC_UVLO_L2H_DEB_EN_SHIFT 5
676 #define PMIC_JUST_PWRKEY_RST_MASK 0x1
677 #define PMIC_JUST_PWRKEY_RST_SHIFT 14
678 #define PMIC_QI_OSC_EN_MASK 0x1
679 #define PMIC_QI_OSC_EN_SHIFT 15
680 #define PMIC_STRUP_EXT_PMIC_EN_MASK 0x1
681 #define PMIC_STRUP_EXT_PMIC_EN_SHIFT 0
682 #define PMIC_STRUP_EXT_PMIC_SEL_MASK 0x1
683 #define PMIC_STRUP_EXT_PMIC_SEL_SHIFT 1
684 #define PMIC_STRUP_CON8_RSV0_MASK 0x7F
685 #define PMIC_STRUP_CON8_RSV0_SHIFT 8
686 #define PMIC_QI_EXT_PMIC_EN_MASK 0x1
687 #define PMIC_QI_EXT_PMIC_EN_SHIFT 15
688 #define PMIC_STRUP_AUXADC_START_SW_MASK 0x1
689 #define PMIC_STRUP_AUXADC_START_SW_SHIFT 4
690 #define PMIC_STRUP_AUXADC_RSTB_SW_MASK 0x1
691 #define PMIC_STRUP_AUXADC_RSTB_SW_SHIFT 5
692 #define PMIC_STRUP_AUXADC_START_SEL_MASK 0x1
693 #define PMIC_STRUP_AUXADC_START_SEL_SHIFT 6
694 #define PMIC_STRUP_AUXADC_RSTB_SEL_MASK 0x1
695 #define PMIC_STRUP_AUXADC_RSTB_SEL_SHIFT 7
696 #define PMIC_STRUP_PWROFF_SEQ_EN_MASK 0x1
697 #define PMIC_STRUP_PWROFF_SEQ_EN_SHIFT 0
698 #define PMIC_STRUP_PWROFF_PREOFF_EN_MASK 0x1
699 #define PMIC_STRUP_PWROFF_PREOFF_EN_SHIFT 1
700 #define PMIC_SPK_EN_L_MASK 0x1
701 #define PMIC_SPK_EN_L_SHIFT 0
702 #define PMIC_SPKMODE_L_MASK 0x1
703 #define PMIC_SPKMODE_L_SHIFT 2
704 #define PMIC_SPK_TRIM_EN_L_MASK 0x1
705 #define PMIC_SPK_TRIM_EN_L_SHIFT 3
706 #define PMIC_SPK_OC_SHDN_DL_MASK 0x1
707 #define PMIC_SPK_OC_SHDN_DL_SHIFT 8
708 #define PMIC_SPK_THER_SHDN_L_EN_MASK 0x1
709 #define PMIC_SPK_THER_SHDN_L_EN_SHIFT 9
710 #define PMIC_RG_SPK_GAINL_MASK 0x3
711 #define PMIC_RG_SPK_GAINL_SHIFT 12
712 #define PMIC_DA_SPK_OFFSET_L_MASK 0x1F
713 #define PMIC_DA_SPK_OFFSET_L_SHIFT 0
714 #define PMIC_DA_SPK_LEAD_DGLH_L_MASK 0x1
715 #define PMIC_DA_SPK_LEAD_DGLH_L_SHIFT 5
716 #define PMIC_NI_SPK_LEAD_L_MASK 0x1
717 #define PMIC_NI_SPK_LEAD_L_SHIFT 6
718 #define PMIC_SPK_OFFSET_L_OV_MASK 0x1
719 #define PMIC_SPK_OFFSET_L_OV_SHIFT 7
720 #define PMIC_SPK_OFFSET_L_SW_MASK 0x1F
721 #define PMIC_SPK_OFFSET_L_SW_SHIFT 8
722 #define PMIC_SPK_LEAD_L_SW_MASK 0x1
723 #define PMIC_SPK_LEAD_L_SW_SHIFT 13
724 #define PMIC_SPK_OFFSET_L_MODE_MASK 0x1
725 #define PMIC_SPK_OFFSET_L_MODE_SHIFT 14
726 #define PMIC_SPK_TRIM_DONE_L_MASK 0x1
727 #define PMIC_SPK_TRIM_DONE_L_SHIFT 15
728 #define PMIC_RG_SPK_INTG_RST_L_MASK 0x1
729 #define PMIC_RG_SPK_INTG_RST_L_SHIFT 0
730 #define PMIC_RG_SPK_FORCE_EN_L_MASK 0x1
731 #define PMIC_RG_SPK_FORCE_EN_L_SHIFT 1
732 #define PMIC_RG_SPK_SLEW_L_MASK 0x3
733 #define PMIC_RG_SPK_SLEW_L_SHIFT 2
734 #define PMIC_RG_SPKAB_OBIAS_L_MASK 0x3
735 #define PMIC_RG_SPKAB_OBIAS_L_SHIFT 4
736 #define PMIC_RG_SPKRCV_EN_L_MASK 0x1
737 #define PMIC_RG_SPKRCV_EN_L_SHIFT 6
738 #define PMIC_RG_SPK_DRC_EN_L_MASK 0x1
739 #define PMIC_RG_SPK_DRC_EN_L_SHIFT 7
740 #define PMIC_RG_SPK_TEST_EN_L_MASK 0x1
741 #define PMIC_RG_SPK_TEST_EN_L_SHIFT 8
742 #define PMIC_RG_SPKAB_OC_EN_L_MASK 0x1
743 #define PMIC_RG_SPKAB_OC_EN_L_SHIFT 9
744 #define PMIC_RG_SPK_OC_EN_L_MASK 0x1
745 #define PMIC_RG_SPK_OC_EN_L_SHIFT 10
746 #define PMIC_SPK_TRIM_WND_MASK 0x7
747 #define PMIC_SPK_TRIM_WND_SHIFT 0
748 #define PMIC_SPK_TRIM_THD_MASK 0x3
749 #define PMIC_SPK_TRIM_THD_SHIFT 4
750 #define PMIC_SPK_OC_WND_MASK 0x3
751 #define PMIC_SPK_OC_WND_SHIFT 8
752 #define PMIC_SPK_OC_THD_MASK 0x3
753 #define PMIC_SPK_OC_THD_SHIFT 10
754 #define PMIC_SPK_D_OC_L_DEG_MASK 0x1
755 #define PMIC_SPK_D_OC_L_DEG_SHIFT 14
756 #define PMIC_SPK_AB_OC_L_DEG_MASK 0x1
757 #define PMIC_SPK_AB_OC_L_DEG_SHIFT 15
758 #define PMIC_SPK_TD1_MASK 0xF
759 #define PMIC_SPK_TD1_SHIFT 0
760 #define PMIC_SPK_TD2_MASK 0xF
761 #define PMIC_SPK_TD2_SHIFT 4
762 #define PMIC_SPK_TD3_MASK 0xF
763 #define PMIC_SPK_TD3_SHIFT 8
764 #define PMIC_SPK_TRIM_DIV_MASK 0x7
765 #define PMIC_SPK_TRIM_DIV_SHIFT 12
766 #define PMIC_RG_BTL_SET_MASK 0x3
767 #define PMIC_RG_BTL_SET_SHIFT 0
768 #define PMIC_RG_SPK_IBIAS_SEL_MASK 0x3
769 #define PMIC_RG_SPK_IBIAS_SEL_SHIFT 2
770 #define PMIC_RG_SPK_CCODE_MASK 0xF
771 #define PMIC_RG_SPK_CCODE_SHIFT 4
772 #define PMIC_RG_SPK_EN_VIEW_VCM_MASK 0x1
773 #define PMIC_RG_SPK_EN_VIEW_VCM_SHIFT 8
774 #define PMIC_RG_SPK_EN_VIEW_CLK_MASK 0x1
775 #define PMIC_RG_SPK_EN_VIEW_CLK_SHIFT 9
776 #define PMIC_RG_SPK_VCM_SEL_MASK 0x1
777 #define PMIC_RG_SPK_VCM_SEL_SHIFT 10
778 #define PMIC_RG_SPK_VCM_IBSEL_MASK 0x1
779 #define PMIC_RG_SPK_VCM_IBSEL_SHIFT 11
780 #define PMIC_RG_SPK_FBRC_EN_MASK 0x1
781 #define PMIC_RG_SPK_FBRC_EN_SHIFT 12
782 #define PMIC_RG_SPKAB_OVDRV_MASK 0x1
783 #define PMIC_RG_SPKAB_OVDRV_SHIFT 13
784 #define PMIC_RG_SPK_OCTH_D_MASK 0x1
785 #define PMIC_RG_SPK_OCTH_D_SHIFT 14
786 #define PMIC_RG_SPK_RSV_MASK 0xFF
787 #define PMIC_RG_SPK_RSV_SHIFT 0
788 #define PMIC_RG_SPKPGA_GAIN_MASK 0xF
789 #define PMIC_RG_SPKPGA_GAIN_SHIFT 8
790 #define PMIC_SPK_RSV0_MASK 0x1
791 #define PMIC_SPK_RSV0_SHIFT 12
792 #define PMIC_SPK_VCM_FAST_EN_MASK 0x1
793 #define PMIC_SPK_VCM_FAST_EN_SHIFT 13
794 #define PMIC_SPK_TEST_MODE0_MASK 0x1
795 #define PMIC_SPK_TEST_MODE0_SHIFT 14
796 #define PMIC_SPK_TEST_MODE1_MASK 0x1
797 #define PMIC_SPK_TEST_MODE1_SHIFT 15
798 #define PMIC_RG_SPK_ISENSE_REFSEL_MASK 0x7
799 #define PMIC_RG_SPK_ISENSE_REFSEL_SHIFT 0
800 #define PMIC_RG_SPK_ISENSE_GAINSEL_MASK 0x7
801 #define PMIC_RG_SPK_ISENSE_GAINSEL_SHIFT 4
802 #define PMIC_RG_ISENSE_PD_RESET_MASK 0x1
803 #define PMIC_RG_ISENSE_PD_RESET_SHIFT 8
804 #define PMIC_RG_SPK_ISENSE_EN_MASK 0x1
805 #define PMIC_RG_SPK_ISENSE_EN_SHIFT 9
806 #define PMIC_RG_SPK_ISENSE_TEST_EN_MASK 0x1
807 #define PMIC_RG_SPK_ISENSE_TEST_EN_SHIFT 10
808 #define PMIC_SPK_TD_WAIT_MASK 0x7
809 #define PMIC_SPK_TD_WAIT_SHIFT 0
810 #define PMIC_SPK_TD_DONE_MASK 0x7
811 #define PMIC_SPK_TD_DONE_SHIFT 4
812 #define PMIC_SPK_EN_MODE_MASK 0x1
813 #define PMIC_SPK_EN_MODE_SHIFT 0
814 #define PMIC_SPK_VCM_FAST_SW_MASK 0x1
815 #define PMIC_SPK_VCM_FAST_SW_SHIFT 1
816 #define PMIC_SPK_RST_L_SW_MASK 0x1
817 #define PMIC_SPK_RST_L_SW_SHIFT 3
818 #define PMIC_SPKMODE_L_SW_MASK 0x1
819 #define PMIC_SPKMODE_L_SW_SHIFT 5
820 #define PMIC_SPK_DEPOP_EN_L_SW_MASK 0x1
821 #define PMIC_SPK_DEPOP_EN_L_SW_SHIFT 7
822 #define PMIC_SPK_EN_L_SW_MASK 0x1
823 #define PMIC_SPK_EN_L_SW_SHIFT 9
824 #define PMIC_SPK_OUTSTG_EN_L_SW_MASK 0x1
825 #define PMIC_SPK_OUTSTG_EN_L_SW_SHIFT 11
826 #define PMIC_SPK_TRIM_EN_L_SW_MASK 0x1
827 #define PMIC_SPK_TRIM_EN_L_SW_SHIFT 13
828 #define PMIC_SPK_TRIM_STOP_L_SW_MASK 0x1
829 #define PMIC_SPK_TRIM_STOP_L_SW_SHIFT 15
830 #define PMIC_CID_MASK 0xFFFF
831 #define PMIC_CID_SHIFT 0
832 #define PMIC_RG_CLKSQ_EN_AUD_MASK 0x1
833 #define PMIC_RG_CLKSQ_EN_AUD_SHIFT 0
834 #define PMIC_RG_CLKSQ_EN_AUX_MASK 0x1
835 #define PMIC_RG_CLKSQ_EN_AUX_SHIFT 1
836 #define PMIC_RG_CLKSQ_EN_FQR_MASK 0x1
837 #define PMIC_RG_CLKSQ_EN_FQR_SHIFT 2
838 #define PMIC_RG_STRUP_75K_CK_PDN_MASK 0x1
839 #define PMIC_RG_STRUP_75K_CK_PDN_SHIFT 3
840 #define PMIC_RG_STRUP_32K_CK_PDN_MASK 0x1
841 #define PMIC_RG_STRUP_32K_CK_PDN_SHIFT 4
842 #define PMIC_RG_RTC_75K_DIV4_CK_PDN_MASK 0x1
843 #define PMIC_RG_RTC_75K_DIV4_CK_PDN_SHIFT 5
844 #define PMIC_RG_RTC_75K_CK_PDN_MASK 0x1
845 #define PMIC_RG_RTC_75K_CK_PDN_SHIFT 6
846 #define PMIC_RG_RTC_32K_CK_PDN_MASK 0x1
847 #define PMIC_RG_RTC_32K_CK_PDN_SHIFT 7
848 #define PMIC_RG_PCHR_32K_CK_PDN_MASK 0x1
849 #define PMIC_RG_PCHR_32K_CK_PDN_SHIFT 8
850 #define PMIC_RG_LDOSTB_1M_CK_PDN_MASK 0x1
851 #define PMIC_RG_LDOSTB_1M_CK_PDN_SHIFT 9
852 #define PMIC_RG_INTRP_CK_PDN_MASK 0x1
853 #define PMIC_RG_INTRP_CK_PDN_SHIFT 10
854 #define PMIC_RG_DRV_32K_CK_PDN_MASK 0x1
855 #define PMIC_RG_DRV_32K_CK_PDN_SHIFT 11
856 #define PMIC_RG_BUCK_1M_CK_PDN_MASK 0x1
857 #define PMIC_RG_BUCK_1M_CK_PDN_SHIFT 12
858 #define PMIC_RG_BUCK_CK_PDN_MASK 0x1
859 #define PMIC_RG_BUCK_CK_PDN_SHIFT 13
860 #define PMIC_RG_BUCK_ANA_CK_PDN_MASK 0x1
861 #define PMIC_RG_BUCK_ANA_CK_PDN_SHIFT 14
862 #define PMIC_RG_BUCK32K_PDN_MASK 0x1
863 #define PMIC_RG_BUCK32K_PDN_SHIFT 15
864 #define PMIC_TOP_CKPDN0_SET_MASK 0xFFFF
865 #define PMIC_TOP_CKPDN0_SET_SHIFT 0
866 #define PMIC_TOP_CKPDN0_CLR_MASK 0xFFFF
867 #define PMIC_TOP_CKPDN0_CLR_SHIFT 0
868 #define PMIC_RG_STRUP_6M_PDN_MASK 0x1
869 #define PMIC_RG_STRUP_6M_PDN_SHIFT 0
870 #define PMIC_RG_SPK_PWM_DIV_PDN_MASK 0x1
871 #define PMIC_RG_SPK_PWM_DIV_PDN_SHIFT 1
872 #define PMIC_RG_SPK_DIV_PDN_MASK 0x1
873 #define PMIC_RG_SPK_DIV_PDN_SHIFT 2
874 #define PMIC_RG_SPK_CK_PDN_MASK 0x1
875 #define PMIC_RG_SPK_CK_PDN_SHIFT 3
876 #define PMIC_RG_PWMOC_CK_PDN_MASK 0x1
877 #define PMIC_RG_PWMOC_CK_PDN_SHIFT 4
878 #define PMIC_RG_FQMTR_PDN_MASK 0x1
879 #define PMIC_RG_FQMTR_PDN_SHIFT 5
880 #define PMIC_RG_DRV_2M_CK_PDN_MASK 0x1
881 #define PMIC_RG_DRV_2M_CK_PDN_SHIFT 6
882 #define PMIC_RG_DRV_1M_CK_PDN_MASK 0x1
883 #define PMIC_RG_DRV_1M_CK_PDN_SHIFT 7
884 #define PMIC_RG_AUD_26M_PDN_MASK 0x1
885 #define PMIC_RG_AUD_26M_PDN_SHIFT 8
886 #define PMIC_RG_ACCDET_CK_PDN_MASK 0x1
887 #define PMIC_RG_ACCDET_CK_PDN_SHIFT 9
888 #define PMIC_RG_RTC_MCLK_PDN_MASK 0x1
889 #define PMIC_RG_RTC_MCLK_PDN_SHIFT 10
890 #define PMIC_RG_SMPS_CK_DIV_PDN_MASK 0x1
891 #define PMIC_RG_SMPS_CK_DIV_PDN_SHIFT 11
892 #define PMIC_RG_EFUSE_CK_PDN_MASK 0x1
893 #define PMIC_RG_EFUSE_CK_PDN_SHIFT 12
894 #define PMIC_RG_RTC32K_1V8_PDN_MASK 0x1
895 #define PMIC_RG_RTC32K_1V8_PDN_SHIFT 13
896 #define PMIC_RG_CLKSQ_EN_AUX_MD_MASK 0x1
897 #define PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT 14
898 #define PMIC_RG_AUXADC_SDM_CK_WAKE_PDN_MASK 0x1
899 #define PMIC_RG_AUXADC_SDM_CK_WAKE_PDN_SHIFT 15
900 #define PMIC_TOP_CKPDN1_SET_MASK 0xFFFF
901 #define PMIC_TOP_CKPDN1_SET_SHIFT 0
902 #define PMIC_TOP_CKPDN1_CLR_MASK 0xFFFF
903 #define PMIC_TOP_CKPDN1_CLR_SHIFT 0
904 #define PMIC_RG_ISINK0_CK_PDN_MASK 0x1
905 #define PMIC_RG_ISINK0_CK_PDN_SHIFT 0
906 #define PMIC_RG_ISINK1_CK_PDN_MASK 0x1
907 #define PMIC_RG_ISINK1_CK_PDN_SHIFT 1
908 #define PMIC_RG_ISINK2_CK_PDN_MASK 0x1
909 #define PMIC_RG_ISINK2_CK_PDN_SHIFT 2
910 #define PMIC_RG_ISINK3_CK_PDN_MASK 0x1
911 #define PMIC_RG_ISINK3_CK_PDN_SHIFT 3
912 #define PMIC_RG_AUXADC_SDM_CK_PDN_MASK 0x1
913 #define PMIC_RG_AUXADC_SDM_CK_PDN_SHIFT 4
914 #define PMIC_RG_AUXADC_CTL_CK_PDN_MASK 0x1
915 #define PMIC_RG_AUXADC_CTL_CK_PDN_SHIFT 5
916 #define PMIC_RG_AUXADC_32K_CK_PDN_MASK 0x1
917 #define PMIC_RG_AUXADC_32K_CK_PDN_SHIFT 6
918 #define PMIC_RG_AUD26M_DIV4_CK_PDN_MASK 0x1
919 #define PMIC_RG_AUD26M_DIV4_CK_PDN_SHIFT 7
920 #define PMIC_TOP_CKPDN2_SET_MASK 0xFFFF
921 #define PMIC_TOP_CKPDN2_SET_SHIFT 0
922 #define PMIC_TOP_CKPDN2_CLR_MASK 0xFFFF
923 #define PMIC_TOP_CKPDN2_CLR_SHIFT 0
924 #define PMIC_RG_EFUSE_MAN_RST_MASK 0x1
925 #define PMIC_RG_EFUSE_MAN_RST_SHIFT 0
926 #define PMIC_RG_AUXADC_RST_MASK 0x1
927 #define PMIC_RG_AUXADC_RST_SHIFT 1
928 #define PMIC_RG_AUDIO_RST_MASK 0x1
929 #define PMIC_RG_AUDIO_RST_SHIFT 2
930 #define PMIC_RG_ACCDET_RST_MASK 0x1
931 #define PMIC_RG_ACCDET_RST_SHIFT 4
932 #define PMIC_RG_SPK_RST_MASK 0x1
933 #define PMIC_RG_SPK_RST_SHIFT 5
934 #define PMIC_RG_DRIVER_RST_MASK 0x1
935 #define PMIC_RG_DRIVER_RST_SHIFT 6
936 #define PMIC_RG_RTC_RST_MASK 0x1
937 #define PMIC_RG_RTC_RST_SHIFT 7
938 #define PMIC_RG_FQMTR_RST_MASK 0x1
939 #define PMIC_RG_FQMTR_RST_SHIFT 8
940 #define PMIC_RG_TOP_RST_CON_RSV_15_9_MASK 0x7F
941 #define PMIC_RG_TOP_RST_CON_RSV_15_9_SHIFT 9
942 #define PMIC_TOP_RST_CON_SET_MASK 0xFFFF
943 #define PMIC_TOP_RST_CON_SET_SHIFT 0
944 #define PMIC_TOP_RST_CON_CLR_MASK 0xFFFF
945 #define PMIC_TOP_RST_CON_CLR_SHIFT 0
946 #define PMIC_RG_AP_RST_DIS_MASK 0x1
947 #define PMIC_RG_AP_RST_DIS_SHIFT 0
948 #define PMIC_RG_SYSRSTB_EN_MASK 0x1
949 #define PMIC_RG_SYSRSTB_EN_SHIFT 1
950 #define PMIC_RG_STRUP_MAN_RST_EN_MASK 0x1
951 #define PMIC_RG_STRUP_MAN_RST_EN_SHIFT 2
952 #define PMIC_RG_NEWLDO_RSTB_EN_MASK 0x1
953 #define PMIC_RG_NEWLDO_RSTB_EN_SHIFT 3
954 #define PMIC_RG_RST_PART_SEL_MASK 0x1
955 #define PMIC_RG_RST_PART_SEL_SHIFT 4
956 #define PMIC_RG_HOMEKEY_RST_EN_MASK 0x1
957 #define PMIC_RG_HOMEKEY_RST_EN_SHIFT 5
958 #define PMIC_RG_PWRKEY_RST_EN_MASK 0x1
959 #define PMIC_RG_PWRKEY_RST_EN_SHIFT 6
960 #define PMIC_RG_PWRRST_TMR_DIS_MASK 0x1
961 #define PMIC_RG_PWRRST_TMR_DIS_SHIFT 7
962 #define PMIC_RG_PWRKEY_RST_TD_MASK 0x3
963 #define PMIC_RG_PWRKEY_RST_TD_SHIFT 8
964 #define PMIC_TOP_RST_MISC_SET_MASK 0xFFFF
965 #define PMIC_TOP_RST_MISC_SET_SHIFT 0
966 #define PMIC_TOP_RST_MISC_CLR_MASK 0xFFFF
967 #define PMIC_TOP_RST_MISC_CLR_SHIFT 0
968 #define PMIC_RG_SRCLKEN_EN_MASK 0x1
969 #define PMIC_RG_SRCLKEN_EN_SHIFT 0
970 #define PMIC_RG_OSC_SEL_MASK 0x1
971 #define PMIC_RG_OSC_SEL_SHIFT 2
972 #define PMIC_RG_AUXADC_SDM_SEL_HW_MODE_MASK 0x1
973 #define PMIC_RG_AUXADC_SDM_SEL_HW_MODE_SHIFT 3
974 #define PMIC_RG_SRCLKEN_HW_MODE_MASK 0x1
975 #define PMIC_RG_SRCLKEN_HW_MODE_SHIFT 4
976 #define PMIC_RG_OSC_HW_MODE_MASK 0x1
977 #define PMIC_RG_OSC_HW_MODE_SHIFT 5
978 #define PMIC_RG_OSC_HW_SRC_SEL_MASK 0x1
979 #define PMIC_RG_OSC_HW_SRC_SEL_SHIFT 6
980 #define PMIC_RG_AUXADC_SDM_CK_HW_MODE_MASK 0x1
981 #define PMIC_RG_AUXADC_SDM_CK_HW_MODE_SHIFT 7
982 #define PMIC_RG_SMPS_AUTOFF_DIS_MASK 0x1
983 #define PMIC_RG_SMPS_AUTOFF_DIS_SHIFT 8
984 #define PMIC_RG_BUCK_1M_AUTOFF_DIS_MASK 0x1
985 #define PMIC_RG_BUCK_1M_AUTOFF_DIS_SHIFT 9
986 #define PMIC_RG_BUCK_ANA_AUTOFF_DIS_MASK 0x1
987 #define PMIC_RG_BUCK_ANA_AUTOFF_DIS_SHIFT 15
988 #define PMIC_TOP_CKCON0_SET_MASK 0xFFFF
989 #define PMIC_TOP_CKCON0_SET_SHIFT 0
990 #define PMIC_TOP_CKCON0_CLR_MASK 0xFFFF
991 #define PMIC_TOP_CKCON0_CLR_SHIFT 0
992 #define PMIC_RG_REGCK_SEL_MASK 0x3
993 #define PMIC_RG_REGCK_SEL_SHIFT 0
994 #define PMIC_RG_SPK_PWM_DIV_SEL_MASK 0x3
995 #define PMIC_RG_SPK_PWM_DIV_SEL_SHIFT 2
996 #define PMIC_RG_SPK_DIV_SEL_MASK 0x3
997 #define PMIC_RG_SPK_DIV_SEL_SHIFT 4
998 #define PMIC_RG_FQMTR_CKSEL_MASK 0x3
999 #define PMIC_RG_FQMTR_CKSEL_SHIFT 6
1000 #define PMIC_RG_ACCDET_CKSEL_MASK 0x3
1001 #define PMIC_RG_ACCDET_CKSEL_SHIFT 8
1002 #define PMIC_RG_ISINK0_CK_SEL_MASK 0x1
1003 #define PMIC_RG_ISINK0_CK_SEL_SHIFT 10
1004 #define PMIC_RG_ISINK1_CK_SEL_MASK 0x1
1005 #define PMIC_RG_ISINK1_CK_SEL_SHIFT 11
1006 #define PMIC_RG_ISINK2_CK_SEL_MASK 0x1
1007 #define PMIC_RG_ISINK2_CK_SEL_SHIFT 12
1008 #define PMIC_RG_ISINK3_CK_SEL_MASK 0x1
1009 #define PMIC_RG_ISINK3_CK_SEL_SHIFT 13
1010 #define PMIC_RG_AUXADC_SDM_CK_SEL_MASK 0x1
1011 #define PMIC_RG_AUXADC_SDM_CK_SEL_SHIFT 14
1012 #define PMIC_RG_AUDIO_CK_SEL_MASK 0x1
1013 #define PMIC_RG_AUDIO_CK_SEL_SHIFT 15
1014 #define PMIC_TOP_CKCON1_SET_MASK 0xFFFF
1015 #define PMIC_TOP_CKCON1_SET_SHIFT 0
1016 #define PMIC_TOP_CKCON1_CLR_MASK 0xFFFF
1017 #define PMIC_TOP_CKCON1_CLR_SHIFT 0
1018 #define PMIC_RG_RTC32K_TST_DIS_MASK 0x1
1019 #define PMIC_RG_RTC32K_TST_DIS_SHIFT 0
1020 #define PMIC_RG_SPK_TST_DIS_MASK 0x1
1021 #define PMIC_RG_SPK_TST_DIS_SHIFT 1
1022 #define PMIC_RG_SMPS_TST_DIS_MASK 0x1
1023 #define PMIC_RG_SMPS_TST_DIS_SHIFT 2
1024 #define PMIC_RG_PMU75K_TST_DIS_MASK 0x1
1025 #define PMIC_RG_PMU75K_TST_DIS_SHIFT 3
1026 #define PMIC_RG_AUD26M_TST_DIS_MASK 0x1
1027 #define PMIC_RG_AUD26M_TST_DIS_SHIFT 4
1028 #define PMIC_RG_SPK_TSTSEL_MASK 0x1
1029 #define PMIC_RG_SPK_TSTSEL_SHIFT 0
1030 #define PMIC_RG_SMPS_TSTSEL_MASK 0x1
1031 #define PMIC_RG_SMPS_TSTSEL_SHIFT 1
1032 #define PMIC_RG_RTC32K_TSTSEL_MASK 0x1
1033 #define PMIC_RG_RTC32K_TSTSEL_SHIFT 2
1034 #define PMIC_RG_PMU75K_TSTSEL_MASK 0x1
1035 #define PMIC_RG_PMU75K_TSTSEL_SHIFT 3
1036 #define PMIC_RG_AUD26M_TSTSEL_MASK 0x1
1037 #define PMIC_RG_AUD26M_TSTSEL_SHIFT 4
1038 #define PMIC_RG_RTCDET_TSTSEL_MASK 0x1
1039 #define PMIC_RG_RTCDET_TSTSEL_SHIFT 5
1040 #define PMIC_RG_PWMOC_TSTSEL_MASK 0x1
1041 #define PMIC_RG_PWMOC_TSTSEL_SHIFT 6
1042 #define PMIC_RG_LDOSTB_TSTSEL_MASK 0x1
1043 #define PMIC_RG_LDOSTB_TSTSEL_SHIFT 7
1044 #define PMIC_RG_ISINK_TSTSEL_MASK 0x1
1045 #define PMIC_RG_ISINK_TSTSEL_SHIFT 8
1046 #define PMIC_RG_FQMTR_TSTSEL_MASK 0x1
1047 #define PMIC_RG_FQMTR_TSTSEL_SHIFT 9
1048 #define PMIC_RG_CLASSD_TSTSEL_MASK 0x1
1049 #define PMIC_RG_CLASSD_TSTSEL_SHIFT 10
1050 #define PMIC_RG_AUXADC_SDM_TSTSEL_MASK 0x1
1051 #define PMIC_RG_AUXADC_SDM_TSTSEL_SHIFT 11
1052 #define PMIC_RG_AUD26M_DIV4_TSTSEL_MASK 0x1
1053 #define PMIC_RG_AUD26M_DIV4_TSTSEL_SHIFT 12
1054 #define PMIC_RG_AUDIF_TSTSEL_MASK 0x1
1055 #define PMIC_RG_AUDIF_TSTSEL_SHIFT 13
1056 #define PMIC_RG_BGR_TEST_CK_SEL_MASK 0x1
1057 #define PMIC_RG_BGR_TEST_CK_SEL_SHIFT 0
1058 #define PMIC_RG_PCHR_TEST_CK_SEL_MASK 0x1
1059 #define PMIC_RG_PCHR_TEST_CK_SEL_SHIFT 1
1060 #define PMIC_RG_STRUP_75K_26M_SEL_MASK 0x1
1061 #define PMIC_RG_STRUP_75K_26M_SEL_SHIFT 2
1062 #define PMIC_RG_BGR_TESTMODE_MASK 0x1
1063 #define PMIC_RG_BGR_TESTMODE_SHIFT 3
1064 #define PMIC_RG_TOP_CKTST2_RSV_15_8_MASK 0xFF
1065 #define PMIC_RG_TOP_CKTST2_RSV_15_8_SHIFT 8
1066 #define PMIC_TEST_OUT_MASK 0xF
1067 #define PMIC_TEST_OUT_SHIFT 0
1068 #define PMIC_RG_MON_FLAG_SEL_MASK 0xFF
1069 #define PMIC_RG_MON_FLAG_SEL_SHIFT 0
1070 #define PMIC_RG_MON_GRP_SEL_MASK 0xF
1071 #define PMIC_RG_MON_GRP_SEL_SHIFT 8
1072 #define PMIC_RG_TEST_DRIVER_MASK 0x1
1073 #define PMIC_RG_TEST_DRIVER_SHIFT 1
1074 #define PMIC_RG_TEST_CLASSD_MASK 0x1
1075 #define PMIC_RG_TEST_CLASSD_SHIFT 2
1076 #define PMIC_RG_TEST_AUD_MASK 0x1
1077 #define PMIC_RG_TEST_AUD_SHIFT 5
1078 #define PMIC_RG_TEST_AUXADC_MASK 0x1
1079 #define PMIC_RG_TEST_AUXADC_SHIFT 8
1080 #define PMIC_RG_NANDTREE_MODE_MASK 0x1
1081 #define PMIC_RG_NANDTREE_MODE_SHIFT 9
1082 #define PMIC_RG_EFUSE_MODE_MASK 0x1
1083 #define PMIC_RG_EFUSE_MODE_SHIFT 10
1084 #define PMIC_RG_TEST_STRUP_MASK 0x1
1085 #define PMIC_RG_TEST_STRUP_SHIFT 11
1086 #define PMIC_RG_TEST_SPK_MASK 0x1
1087 #define PMIC_RG_TEST_SPK_SHIFT 12
1088 #define PMIC_RG_TEST_SPK_PWM_MASK 0x1
1089 #define PMIC_RG_TEST_SPK_PWM_SHIFT 13
1090 #define PMIC_EN_STATUS_VPROC_MASK 0x1
1091 #define PMIC_EN_STATUS_VPROC_SHIFT 0
1092 #define PMIC_EN_STATUS_VSYS_MASK 0x1
1093 #define PMIC_EN_STATUS_VSYS_SHIFT 1
1094 #define PMIC_EN_STATUS_VPA_MASK 0x1
1095 #define PMIC_EN_STATUS_VPA_SHIFT 2
1096 #define PMIC_EN_STATUS_VRTC_MASK 0x1
1097 #define PMIC_EN_STATUS_VRTC_SHIFT 3
1098 #define PMIC_EN_STATUS_VA_MASK 0x1
1099 #define PMIC_EN_STATUS_VA_SHIFT 4
1100 #define PMIC_EN_STATUS_VCAMA_MASK 0x1
1101 #define PMIC_EN_STATUS_VCAMA_SHIFT 5
1102 #define PMIC_EN_STATUS_VCAMD_MASK 0x1
1103 #define PMIC_EN_STATUS_VCAMD_SHIFT 6
1104 #define PMIC_EN_STATUS_VCAM_AF_MASK 0x1
1105 #define PMIC_EN_STATUS_VCAM_AF_SHIFT 7
1106 #define PMIC_EN_STATUS_VCAM_IO_MASK 0x1
1107 #define PMIC_EN_STATUS_VCAM_IO_SHIFT 8
1108 #define PMIC_EN_STATUS_VCN28_MASK 0x1
1109 #define PMIC_EN_STATUS_VCN28_SHIFT 9
1110 #define PMIC_EN_STATUS_VCN33_MASK 0x1
1111 #define PMIC_EN_STATUS_VCN33_SHIFT 10
1112 #define PMIC_EN_STATUS_VCN_1V8_MASK 0x1
1113 #define PMIC_EN_STATUS_VCN_1V8_SHIFT 11
1114 #define PMIC_EN_STATUS_VEMC_3V3_MASK 0x1
1115 #define PMIC_EN_STATUS_VEMC_3V3_SHIFT 12
1116 #define PMIC_EN_STATUS_VGP1_MASK 0x1
1117 #define PMIC_EN_STATUS_VGP1_SHIFT 13
1118 #define PMIC_EN_STATUS_VGP2_MASK 0x1
1119 #define PMIC_EN_STATUS_VGP2_SHIFT 14
1120 #define PMIC_EN_STATUS_VGP3_MASK 0x1
1121 #define PMIC_EN_STATUS_VGP3_SHIFT 15
1122 #define PMIC_EN_STATUS_VIBR_MASK 0x1
1123 #define PMIC_EN_STATUS_VIBR_SHIFT 0
1124 #define PMIC_EN_STATUS_VIO18_MASK 0x1
1125 #define PMIC_EN_STATUS_VIO18_SHIFT 1
1126 #define PMIC_EN_STATUS_VIO28_MASK 0x1
1127 #define PMIC_EN_STATUS_VIO28_SHIFT 2
1128 #define PMIC_EN_STATUS_VM_MASK 0x1
1129 #define PMIC_EN_STATUS_VM_SHIFT 3
1130 #define PMIC_EN_STATUS_VMC_MASK 0x1
1131 #define PMIC_EN_STATUS_VMC_SHIFT 4
1132 #define PMIC_EN_STATUS_VMCH_MASK 0x1
1133 #define PMIC_EN_STATUS_VMCH_SHIFT 5
1134 #define PMIC_EN_STATUS_VRF18_MASK 0x1
1135 #define PMIC_EN_STATUS_VRF18_SHIFT 6
1136 #define PMIC_EN_STATUS_VSIM1_MASK 0x1
1137 #define PMIC_EN_STATUS_VSIM1_SHIFT 7
1138 #define PMIC_EN_STATUS_VSIM2_MASK 0x1
1139 #define PMIC_EN_STATUS_VSIM2_SHIFT 8
1140 #define PMIC_EN_STATUS_VTCXO_MASK 0x1
1141 #define PMIC_EN_STATUS_VTCXO_SHIFT 9
1142 #define PMIC_EN_STATUS_VUSB_MASK 0x1
1143 #define PMIC_EN_STATUS_VUSB_SHIFT 10
1144 #define PMIC_OC_STATUS_VPROC_MASK 0x1
1145 #define PMIC_OC_STATUS_VPROC_SHIFT 0
1146 #define PMIC_OC_STATUS_VSYS_MASK 0x1
1147 #define PMIC_OC_STATUS_VSYS_SHIFT 1
1148 #define PMIC_OC_STATUS_VPA_MASK 0x1
1149 #define PMIC_OC_STATUS_VPA_SHIFT 2
1150 #define PMIC_OC_STATUS_VA_MASK 0x1
1151 #define PMIC_OC_STATUS_VA_SHIFT 4
1152 #define PMIC_OC_STATUS_VCAMA_MASK 0x1
1153 #define PMIC_OC_STATUS_VCAMA_SHIFT 5
1154 #define PMIC_OC_STATUS_VCAMD_MASK 0x1
1155 #define PMIC_OC_STATUS_VCAMD_SHIFT 6
1156 #define PMIC_OC_STATUS_VCAM_AF_MASK 0x1
1157 #define PMIC_OC_STATUS_VCAM_AF_SHIFT 7
1158 #define PMIC_OC_STATUS_VCAM_IO_MASK 0x1
1159 #define PMIC_OC_STATUS_VCAM_IO_SHIFT 8
1160 #define PMIC_OC_STATUS_VCN28_MASK 0x1
1161 #define PMIC_OC_STATUS_VCN28_SHIFT 9
1162 #define PMIC_OC_STATUS_VCN33_MASK 0x1
1163 #define PMIC_OC_STATUS_VCN33_SHIFT 10
1164 #define PMIC_OC_STATUS_VCN_1V8_MASK 0x1
1165 #define PMIC_OC_STATUS_VCN_1V8_SHIFT 11
1166 #define PMIC_OC_STATUS_VEMC_3V3_MASK 0x1
1167 #define PMIC_OC_STATUS_VEMC_3V3_SHIFT 12
1168 #define PMIC_OC_STATUS_VGP1_MASK 0x1
1169 #define PMIC_OC_STATUS_VGP1_SHIFT 13
1170 #define PMIC_OC_STATUS_VGP2_MASK 0x1
1171 #define PMIC_OC_STATUS_VGP2_SHIFT 14
1172 #define PMIC_OC_STATUS_VGP3_MASK 0x1
1173 #define PMIC_OC_STATUS_VGP3_SHIFT 15
1174 #define PMIC_OC_STATUS_VIBR_MASK 0x1
1175 #define PMIC_OC_STATUS_VIBR_SHIFT 0
1176 #define PMIC_OC_STATUS_VIO18_MASK 0x1
1177 #define PMIC_OC_STATUS_VIO18_SHIFT 1
1178 #define PMIC_OC_STATUS_VIO28_MASK 0x1
1179 #define PMIC_OC_STATUS_VIO28_SHIFT 2
1180 #define PMIC_OC_STATUS_VM_MASK 0x1
1181 #define PMIC_OC_STATUS_VM_SHIFT 3
1182 #define PMIC_OC_STATUS_VMC_MASK 0x1
1183 #define PMIC_OC_STATUS_VMC_SHIFT 4
1184 #define PMIC_OC_STATUS_VMCH_MASK 0x1
1185 #define PMIC_OC_STATUS_VMCH_SHIFT 5
1186 #define PMIC_OC_STATUS_VRF18_MASK 0x1
1187 #define PMIC_OC_STATUS_VRF18_SHIFT 6
1188 #define PMIC_OC_STATUS_VSIM1_MASK 0x1
1189 #define PMIC_OC_STATUS_VSIM1_SHIFT 7
1190 #define PMIC_OC_STATUS_VSIM2_MASK 0x1
1191 #define PMIC_OC_STATUS_VSIM2_SHIFT 8
1192 #define PMIC_OC_STATUS_VTCXO_MASK 0x1
1193 #define PMIC_OC_STATUS_VTCXO_SHIFT 9
1194 #define PMIC_OC_STATUS_VUSB_MASK 0x1
1195 #define PMIC_OC_STATUS_VUSB_SHIFT 10
1196 #define PMIC_NI_SPK_OC_DET_D_L_MASK 0x1
1197 #define PMIC_NI_SPK_OC_DET_D_L_SHIFT 11
1198 #define PMIC_NI_SPK_OC_DET_AB_L_MASK 0x1
1199 #define PMIC_NI_SPK_OC_DET_AB_L_SHIFT 12
1200 #define PMIC_VPROC_PG_DEB_MASK 0x1
1201 #define PMIC_VPROC_PG_DEB_SHIFT 0
1202 #define PMIC_VSYS_PG_DEB_MASK 0x1
1203 #define PMIC_VSYS_PG_DEB_SHIFT 1
1204 #define PMIC_VM_PG_DEB_MASK 0x1
1205 #define PMIC_VM_PG_DEB_SHIFT 2
1206 #define PMIC_VIO18_PG_DEB_MASK 0x1
1207 #define PMIC_VIO18_PG_DEB_SHIFT 3
1208 #define PMIC_VTCXO_PG_DEB_MASK 0x1
1209 #define PMIC_VTCXO_PG_DEB_SHIFT 4
1210 #define PMIC_VA_PG_DEB_MASK 0x1
1211 #define PMIC_VA_PG_DEB_SHIFT 5
1212 #define PMIC_VIO28_PG_DEB_MASK 0x1
1213 #define PMIC_VIO28_PG_DEB_SHIFT 6
1214 #define PMIC_VGP2_PG_DEB_MASK 0x1
1215 #define PMIC_VGP2_PG_DEB_SHIFT 7
1216 #define PMIC_PMU_TEST_MODE_SCAN_MASK 0x1
1217 #define PMIC_PMU_TEST_MODE_SCAN_SHIFT 0
1218 #define PMIC_PWRKEY_DEB_MASK 0x1
1219 #define PMIC_PWRKEY_DEB_SHIFT 1
1220 #define PMIC_FCHRKEY_DEB_MASK 0x1
1221 #define PMIC_FCHRKEY_DEB_SHIFT 2
1222 #define PMIC_VBAT_OV_MASK 0x1
1223 #define PMIC_VBAT_OV_SHIFT 3
1224 #define PMIC_PCHR_CHRDET_MASK 0x1
1225 #define PMIC_PCHR_CHRDET_SHIFT 4
1226 #define PMIC_RO_BATON_UNDET_MASK 0x1
1227 #define PMIC_RO_BATON_UNDET_SHIFT 5
1228 #define PMIC_RTC_XTAL_DET_DONE_MASK 0x1
1229 #define PMIC_RTC_XTAL_DET_DONE_SHIFT 6
1230 #define PMIC_XOSC32_ENB_DET_MASK 0x1
1231 #define PMIC_XOSC32_ENB_DET_SHIFT 7
1232 #define PMIC_RTC_XTAL_DET_RSV_MASK 0xF
1233 #define PMIC_RTC_XTAL_DET_RSV_SHIFT 8
1234 #define PMIC_RG_SIMAP_TDSEL_MASK 0x1
1235 #define PMIC_RG_SIMAP_TDSEL_SHIFT 0
1236 #define PMIC_RG_AUD_TDSEL_MASK 0x1
1237 #define PMIC_RG_AUD_TDSEL_SHIFT 1
1238 #define PMIC_RG_SPI_TDSEL_MASK 0x1
1239 #define PMIC_RG_SPI_TDSEL_SHIFT 2
1240 #define PMIC_RG_PMU_TDSEL_MASK 0x1
1241 #define PMIC_RG_PMU_TDSEL_SHIFT 3
1242 #define PMIC_RG_SIMLS_TDSEL_MASK 0x3
1243 #define PMIC_RG_SIMLS_TDSEL_SHIFT 4
1244 #define PMIC_RG_SIMAP_RDSEL_MASK 0x1
1245 #define PMIC_RG_SIMAP_RDSEL_SHIFT 0
1246 #define PMIC_RG_AUD_RDSEL_MASK 0x1
1247 #define PMIC_RG_AUD_RDSEL_SHIFT 1
1248 #define PMIC_RG_SPI_RDSEL_MASK 0x1
1249 #define PMIC_RG_SPI_RDSEL_SHIFT 2
1250 #define PMIC_RG_PMU_RDSEL_MASK 0x1
1251 #define PMIC_RG_PMU_RDSEL_SHIFT 3
1252 #define PMIC_RG_SIMLS_RDSEL_MASK 0x3
1253 #define PMIC_RG_SIMLS_RDSEL_SHIFT 4
1254 #define PMIC_RG_SMT_SYSRSTB_MASK 0x1
1255 #define PMIC_RG_SMT_SYSRSTB_SHIFT 0
1256 #define PMIC_RG_SMT_INT_MASK 0x1
1257 #define PMIC_RG_SMT_INT_SHIFT 1
1258 #define PMIC_RG_SMT_SRCLKEN_MASK 0x1
1259 #define PMIC_RG_SMT_SRCLKEN_SHIFT 2
1260 #define PMIC_RG_SMT_RTC_32K1V8_MASK 0x1
1261 #define PMIC_RG_SMT_RTC_32K1V8_SHIFT 3
1262 #define PMIC_RG_SMT_SPI_CLK_MASK 0x1
1263 #define PMIC_RG_SMT_SPI_CLK_SHIFT 0
1264 #define PMIC_RG_SMT_SPI_CSN_MASK 0x1
1265 #define PMIC_RG_SMT_SPI_CSN_SHIFT 1
1266 #define PMIC_RG_SMT_SPI_MOSI_MASK 0x1
1267 #define PMIC_RG_SMT_SPI_MOSI_SHIFT 2
1268 #define PMIC_RG_SMT_SPI_MISO_MASK 0x1
1269 #define PMIC_RG_SMT_SPI_MISO_SHIFT 3
1270 #define PMIC_RG_SMT_AUD_CLK_MASK 0x1
1271 #define PMIC_RG_SMT_AUD_CLK_SHIFT 0
1272 #define PMIC_RG_SMT_AUD_MOSI_MASK 0x1
1273 #define PMIC_RG_SMT_AUD_MOSI_SHIFT 1
1274 #define PMIC_RG_SMT_AUD_MISO_MASK 0x1
1275 #define PMIC_RG_SMT_AUD_MISO_SHIFT 2
1276 #define PMIC_RG_SMT_SIM1_AP_SCLK_MASK 0x1
1277 #define PMIC_RG_SMT_SIM1_AP_SCLK_SHIFT 0
1278 #define PMIC_RG_SMT_SIM1_AP_SRST_MASK 0x1
1279 #define PMIC_RG_SMT_SIM1_AP_SRST_SHIFT 1
1280 #define PMIC_RG_SMT_SIMLS1_SCLK_MASK 0x1
1281 #define PMIC_RG_SMT_SIMLS1_SCLK_SHIFT 2
1282 #define PMIC_RG_SMT_SIMLS1_SRST_MASK 0x1
1283 #define PMIC_RG_SMT_SIMLS1_SRST_SHIFT 3
1284 #define PMIC_RG_SMT_SIM2_AP_SCLK_MASK 0x1
1285 #define PMIC_RG_SMT_SIM2_AP_SCLK_SHIFT 0
1286 #define PMIC_RG_SMT_SIM2_AP_SRST_MASK 0x1
1287 #define PMIC_RG_SMT_SIM2_AP_SRST_SHIFT 1
1288 #define PMIC_RG_SMT_SIMLS2_SCLK_MASK 0x1
1289 #define PMIC_RG_SMT_SIMLS2_SCLK_SHIFT 2
1290 #define PMIC_RG_SMT_SIMLS2_SRST_MASK 0x1
1291 #define PMIC_RG_SMT_SIMLS2_SRST_SHIFT 3
1292 #define PMIC_RG_OCTL_INT_MASK 0xF
1293 #define PMIC_RG_OCTL_INT_SHIFT 0
1294 #define PMIC_RG_OCTL_SRCLKEN_MASK 0xF
1295 #define PMIC_RG_OCTL_SRCLKEN_SHIFT 4
1296 #define PMIC_RG_OCTL_RTC_32K1V8_MASK 0xF
1297 #define PMIC_RG_OCTL_RTC_32K1V8_SHIFT 8
1298 #define PMIC_RG_OCTL_SPI_CLK_MASK 0xF
1299 #define PMIC_RG_OCTL_SPI_CLK_SHIFT 0
1300 #define PMIC_RG_OCTL_SPI_CSN_MASK 0xF
1301 #define PMIC_RG_OCTL_SPI_CSN_SHIFT 4
1302 #define PMIC_RG_OCTL_SPI_MOSI_MASK 0xF
1303 #define PMIC_RG_OCTL_SPI_MOSI_SHIFT 8
1304 #define PMIC_RG_OCTL_SPI_MISO_MASK 0xF
1305 #define PMIC_RG_OCTL_SPI_MISO_SHIFT 12
1306 #define PMIC_RG_OCTL_AUD_CLK_MASK 0xF
1307 #define PMIC_RG_OCTL_AUD_CLK_SHIFT 0
1308 #define PMIC_RG_OCTL_AUD_MOSI_MASK 0xF
1309 #define PMIC_RG_OCTL_AUD_MOSI_SHIFT 4
1310 #define PMIC_RG_OCTL_AUD_MISO_MASK 0xF
1311 #define PMIC_RG_OCTL_AUD_MISO_SHIFT 8
1312 #define PMIC_RG_OCTL_SIM1_AP_SCLK_MASK 0xF
1313 #define PMIC_RG_OCTL_SIM1_AP_SCLK_SHIFT 0
1314 #define PMIC_RG_OCTL_SIM1_AP_SRST_MASK 0xF
1315 #define PMIC_RG_OCTL_SIM1_AP_SRST_SHIFT 4
1316 #define PMIC_RG_OCTL_SIMLS1_SCLK_MASK 0xF
1317 #define PMIC_RG_OCTL_SIMLS1_SCLK_SHIFT 8
1318 #define PMIC_RG_OCTL_SIMLS1_SRST_MASK 0xF
1319 #define PMIC_RG_OCTL_SIMLS1_SRST_SHIFT 12
1320 #define PMIC_RG_OCTL_SIM2_AP_SCLK_MASK 0xF
1321 #define PMIC_RG_OCTL_SIM2_AP_SCLK_SHIFT 0
1322 #define PMIC_RG_OCTL_SIM2_AP_SRST_MASK 0xF
1323 #define PMIC_RG_OCTL_SIM2_AP_SRST_SHIFT 4
1324 #define PMIC_RG_OCTL_SIMLS2_SCLK_MASK 0xF
1325 #define PMIC_RG_OCTL_SIMLS2_SCLK_SHIFT 8
1326 #define PMIC_RG_OCTL_SIMLS2_SRST_MASK 0xF
1327 #define PMIC_RG_OCTL_SIMLS2_SRST_SHIFT 12
1328 #define PMIC_RG_SIMLS1_SCLK_CONF_MASK 0xF
1329 #define PMIC_RG_SIMLS1_SCLK_CONF_SHIFT 0
1330 #define PMIC_RG_SIMLS1_SRST_CONF_MASK 0xF
1331 #define PMIC_RG_SIMLS1_SRST_CONF_SHIFT 4
1332 #define PMIC_RG_SIMLS2_SCLK_CONF_MASK 0xF
1333 #define PMIC_RG_SIMLS2_SCLK_CONF_SHIFT 0
1334 #define PMIC_RG_SIMLS2_SRST_CONF_MASK 0xF
1335 #define PMIC_RG_SIMLS2_SRST_CONF_SHIFT 4
1336 #define PMIC_RG_INT_EN_SPKL_AB_MASK 0x1
1337 #define PMIC_RG_INT_EN_SPKL_AB_SHIFT 0
1338 #define PMIC_RG_INT_EN_SPKL_MASK 0x1
1339 #define PMIC_RG_INT_EN_SPKL_SHIFT 1
1340 #define PMIC_RG_INT_EN_BAT_L_MASK 0x1
1341 #define PMIC_RG_INT_EN_BAT_L_SHIFT 2
1342 #define PMIC_RG_INT_EN_BAT_H_MASK 0x1
1343 #define PMIC_RG_INT_EN_BAT_H_SHIFT 3
1344 #define PMIC_RG_INT_EN_WATCHDOG_MASK 0x1
1345 #define PMIC_RG_INT_EN_WATCHDOG_SHIFT 4
1346 #define PMIC_RG_INT_EN_PWRKEY_MASK 0x1
1347 #define PMIC_RG_INT_EN_PWRKEY_SHIFT 5
1348 #define PMIC_RG_INT_EN_THR_L_MASK 0x1
1349 #define PMIC_RG_INT_EN_THR_L_SHIFT 6
1350 #define PMIC_RG_INT_EN_THR_H_MASK 0x1
1351 #define PMIC_RG_INT_EN_THR_H_SHIFT 7
1352 #define PMIC_RG_INT_EN_VBATON_UNDET_MASK 0x1
1353 #define PMIC_RG_INT_EN_VBATON_UNDET_SHIFT 8
1354 #define PMIC_RG_INT_EN_BVALID_DET_MASK 0x1
1355 #define PMIC_RG_INT_EN_BVALID_DET_SHIFT 9
1356 #define PMIC_RG_INT_EN_CHRDET_MASK 0x1
1357 #define PMIC_RG_INT_EN_CHRDET_SHIFT 10
1358 #define PMIC_RG_INT_EN_OV_MASK 0x1
1359 #define PMIC_RG_INT_EN_OV_SHIFT 11
1360 #define PMIC_INT_CON0_SET_MASK 0xFFFF
1361 #define PMIC_INT_CON0_SET_SHIFT 0
1362 #define PMIC_INT_CON0_CLR_MASK 0xFFFF
1363 #define PMIC_INT_CON0_CLR_SHIFT 0
1364 #define PMIC_RG_INT_EN_LDO_MASK 0x1
1365 #define PMIC_RG_INT_EN_LDO_SHIFT 0
1366 #define PMIC_RG_INT_EN_FCHRKEY_MASK 0x1
1367 #define PMIC_RG_INT_EN_FCHRKEY_SHIFT 1
1368 #define PMIC_RG_INT_EN_ACCDET_MASK 0x1
1369 #define PMIC_RG_INT_EN_ACCDET_SHIFT 2
1370 #define PMIC_RG_INT_EN_AUDIO_MASK 0x1
1371 #define PMIC_RG_INT_EN_AUDIO_SHIFT 3
1372 #define PMIC_RG_INT_EN_RTC_MASK 0x1
1373 #define PMIC_RG_INT_EN_RTC_SHIFT 4
1374 #define PMIC_RG_INT_EN_VPROC_MASK 0x1
1375 #define PMIC_RG_INT_EN_VPROC_SHIFT 5
1376 #define PMIC_RG_INT_EN_VSYS_MASK 0x1
1377 #define PMIC_RG_INT_EN_VSYS_SHIFT 6
1378 #define PMIC_RG_INT_EN_VPA_MASK 0x1
1379 #define PMIC_RG_INT_EN_VPA_SHIFT 7
1380 #define PMIC_INT_CON1_SET_MASK 0xFFFF
1381 #define PMIC_INT_CON1_SET_SHIFT 0
1382 #define PMIC_INT_CON1_CLR_MASK 0xFFFF
1383 #define PMIC_INT_CON1_CLR_SHIFT 0
1384 #define PMIC_POLARITY_MASK 0x1
1385 #define PMIC_POLARITY_SHIFT 0
1386 #define PMIC_POLARITY_VBATON_UNDET_MASK 0x1
1387 #define PMIC_POLARITY_VBATON_UNDET_SHIFT 1
1388 #define PMIC_POLARITY_BVALID_DET_MASK 0x1
1389 #define PMIC_POLARITY_BVALID_DET_SHIFT 2
1390 #define PMIC_RG_FCHRKEY_INT_SEL_MASK 0x1
1391 #define PMIC_RG_FCHRKEY_INT_SEL_SHIFT 3
1392 #define PMIC_RG_PWRKEY_INT_SEL_MASK 0x1
1393 #define PMIC_RG_PWRKEY_INT_SEL_SHIFT 4
1394 #define PMIC_IVGEN_EXT_EN_MASK 0x1
1395 #define PMIC_IVGEN_EXT_EN_SHIFT 7
1396 #define PMIC_INT_MISC_CON_SET_MASK 0xFFFF
1397 #define PMIC_INT_MISC_CON_SET_SHIFT 0
1398 #define PMIC_INT_MISC_CON_CLR_MASK 0xFFFF
1399 #define PMIC_INT_MISC_CON_CLR_SHIFT 0
1400 #define PMIC_RG_INT_STATUS_SPKL_AB_MASK 0x1
1401 #define PMIC_RG_INT_STATUS_SPKL_AB_SHIFT 0
1402 #define PMIC_RG_INT_STATUS_SPKL_MASK 0x1
1403 #define PMIC_RG_INT_STATUS_SPKL_SHIFT 1
1404 #define PMIC_RG_INT_STATUS_BAT_L_MASK 0x1
1405 #define PMIC_RG_INT_STATUS_BAT_L_SHIFT 2
1406 #define PMIC_RG_INT_STATUS_BAT_H_MASK 0x1
1407 #define PMIC_RG_INT_STATUS_BAT_H_SHIFT 3
1408 #define PMIC_RG_INT_STATUS_WATCHDOG_MASK 0x1
1409 #define PMIC_RG_INT_STATUS_WATCHDOG_SHIFT 4
1410 #define PMIC_RG_INT_STATUS_PWRKEY_MASK 0x1
1411 #define PMIC_RG_INT_STATUS_PWRKEY_SHIFT 5
1412 #define PMIC_RG_INT_STATUS_THR_L_MASK 0x1
1413 #define PMIC_RG_INT_STATUS_THR_L_SHIFT 6
1414 #define PMIC_RG_INT_STATUS_THR_H_MASK 0x1
1415 #define PMIC_RG_INT_STATUS_THR_H_SHIFT 7
1416 #define PMIC_RG_INT_STATUS_VBATON_UNDET_MASK 0x1
1417 #define PMIC_RG_INT_STATUS_VBATON_UNDET_SHIFT 8
1418 #define PMIC_RG_INT_STATUS_BVALID_DET_MASK 0x1
1419 #define PMIC_RG_INT_STATUS_BVALID_DET_SHIFT 9
1420 #define PMIC_RG_INT_STATUS_CHRDET_MASK 0x1
1421 #define PMIC_RG_INT_STATUS_CHRDET_SHIFT 10
1422 #define PMIC_RG_INT_STATUS_OV_MASK 0x1
1423 #define PMIC_RG_INT_STATUS_OV_SHIFT 11
1424 #define PMIC_RG_INT_STATUS_LDO_MASK 0x1
1425 #define PMIC_RG_INT_STATUS_LDO_SHIFT 0
1426 #define PMIC_RG_INT_STATUS_FCHRKEY_MASK 0x1
1427 #define PMIC_RG_INT_STATUS_FCHRKEY_SHIFT 1
1428 #define PMIC_RG_INT_STATUS_ACCDET_MASK 0x1
1429 #define PMIC_RG_INT_STATUS_ACCDET_SHIFT 2
1430 #define PMIC_RG_INT_STATUS_AUDIO_MASK 0x1
1431 #define PMIC_RG_INT_STATUS_AUDIO_SHIFT 3
1432 #define PMIC_RG_INT_STATUS_RTC_MASK 0x1
1433 #define PMIC_RG_INT_STATUS_RTC_SHIFT 4
1434 #define PMIC_RG_INT_STATUS_VPROC_MASK 0x1
1435 #define PMIC_RG_INT_STATUS_VPROC_SHIFT 5
1436 #define PMIC_RG_INT_STATUS_VSYS_MASK 0x1
1437 #define PMIC_RG_INT_STATUS_VSYS_SHIFT 6
1438 #define PMIC_RG_INT_STATUS_VPA_MASK 0x1
1439 #define PMIC_RG_INT_STATUS_VPA_SHIFT 7
1440 #define PMIC_OC_GEAR_BVALID_DET_MASK 0x3
1441 #define PMIC_OC_GEAR_BVALID_DET_SHIFT 0
1442 #define PMIC_OC_GEAR_VBATON_UNDET_MASK 0x3
1443 #define PMIC_OC_GEAR_VBATON_UNDET_SHIFT 0
1444 #define PMIC_OC_GEAR_LDO_MASK 0x3
1445 #define PMIC_OC_GEAR_LDO_SHIFT 0
1446 #define PMIC_VPROC_OC_THD_MASK 0x3
1447 #define PMIC_VPROC_OC_THD_SHIFT 0
1448 #define PMIC_VPROC_OC_WND_MASK 0x3
1449 #define PMIC_VPROC_OC_WND_SHIFT 2
1450 #define PMIC_VPROC_DEG_EN_MASK 0x1
1451 #define PMIC_VPROC_DEG_EN_SHIFT 4
1452 #define PMIC_VSYS_OC_THD_MASK 0x3
1453 #define PMIC_VSYS_OC_THD_SHIFT 0
1454 #define PMIC_VSYS_OC_WND_MASK 0x3
1455 #define PMIC_VSYS_OC_WND_SHIFT 2
1456 #define PMIC_VSYS_DEG_EN_MASK 0x1
1457 #define PMIC_VSYS_DEG_EN_SHIFT 4
1458 #define PMIC_VPA_OC_THD_MASK 0x3
1459 #define PMIC_VPA_OC_THD_SHIFT 0
1460 #define PMIC_VPA_OC_WND_MASK 0x3
1461 #define PMIC_VPA_OC_WND_SHIFT 2
1462 #define PMIC_VPA_DEG_EN_MASK 0x1
1463 #define PMIC_VPA_DEG_EN_SHIFT 4
1464 #define PMIC_FQMTR_TCKSEL_MASK 0x7
1465 #define PMIC_FQMTR_TCKSEL_SHIFT 0
1466 #define PMIC_FQMTR_BUSY_MASK 0x1
1467 #define PMIC_FQMTR_BUSY_SHIFT 3
1468 #define PMIC_FQMTR_EN_MASK 0x1
1469 #define PMIC_FQMTR_EN_SHIFT 15
1470 #define PMIC_FQMTR_WINSET_MASK 0xFFFF
1471 #define PMIC_FQMTR_WINSET_SHIFT 0
1472 #define PMIC_FQMTR_DATA_MASK 0xFFFF
1473 #define PMIC_FQMTR_DATA_SHIFT 0
1474 #define PMIC_RG_SPI_CON_MASK 0x1
1475 #define PMIC_RG_SPI_CON_SHIFT 0
1476 #define PMIC_DEW_DIO_EN_MASK 0x1
1477 #define PMIC_DEW_DIO_EN_SHIFT 0
1478 #define PMIC_DEW_READ_TEST_MASK 0xFFFF
1479 #define PMIC_DEW_READ_TEST_SHIFT 0
1480 #define PMIC_DEW_WRITE_TEST_MASK 0xFFFF
1481 #define PMIC_DEW_WRITE_TEST_SHIFT 0
1482 #define PMIC_DEW_CRC_SWRST_MASK 0x1
1483 #define PMIC_DEW_CRC_SWRST_SHIFT 0
1484 #define PMIC_DEW_CRC_EN_MASK 0x1
1485 #define PMIC_DEW_CRC_EN_SHIFT 0
1486 #define PMIC_DEW_CRC_VAL_MASK 0xFF
1487 #define PMIC_DEW_CRC_VAL_SHIFT 0
1488 #define PMIC_DEW_DBG_MON_SEL_MASK 0xF
1489 #define PMIC_DEW_DBG_MON_SEL_SHIFT 0
1490 #define PMIC_DEW_CIPHER_KEY_SEL_MASK 0x3
1491 #define PMIC_DEW_CIPHER_KEY_SEL_SHIFT 0
1492 #define PMIC_DEW_CIPHER_IV_SEL_MASK 0x3
1493 #define PMIC_DEW_CIPHER_IV_SEL_SHIFT 0
1494 #define PMIC_DEW_CIPHER_EN_MASK 0x1
1495 #define PMIC_DEW_CIPHER_EN_SHIFT 0
1496 #define PMIC_DEW_CIPHER_RDY_MASK 0x1
1497 #define PMIC_DEW_CIPHER_RDY_SHIFT 0
1498 #define PMIC_DEW_CIPHER_MODE_MASK 0x1
1499 #define PMIC_DEW_CIPHER_MODE_SHIFT 0
1500 #define PMIC_DEW_CIPHER_SWRST_MASK 0x1
1501 #define PMIC_DEW_CIPHER_SWRST_SHIFT 0
1502 #define PMIC_DEW_RDDMY_NO_MASK 0xF
1503 #define PMIC_DEW_RDDMY_NO_SHIFT 0
1504 #define PMIC_DEW_RDATA_DLY_SEL_MASK 0x1
1505 #define PMIC_DEW_RDATA_DLY_SEL_SHIFT 0
1506 #define PMIC_RG_SMPS_TESTMODE_B_MASK 0xFF
1507 #define PMIC_RG_SMPS_TESTMODE_B_SHIFT 8
1508 #define PMIC_QI_VPROC_DIG_MON_MASK 0xF
1509 #define PMIC_QI_VPROC_DIG_MON_SHIFT 0
1510 #define PMIC_QI_VSYS_DIG_MON_MASK 0xF
1511 #define PMIC_QI_VSYS_DIG_MON_SHIFT 4
1512 #define PMIC_VSLEEP_SRC0_MASK 0x1FF
1513 #define PMIC_VSLEEP_SRC0_SHIFT 0
1514 #define PMIC_VSLEEP_SRC1_MASK 0xF
1515 #define PMIC_VSLEEP_SRC1_SHIFT 12
1516 #define PMIC_R2R_SRC0_MASK 0x1FF
1517 #define PMIC_R2R_SRC0_SHIFT 0
1518 #define PMIC_R2R_SRC1_MASK 0xF
1519 #define PMIC_R2R_SRC1_SHIFT 12
1520 #define PMIC_BUCK_OSC_SEL_SRC0_MASK 0x1FF
1521 #define PMIC_BUCK_OSC_SEL_SRC0_SHIFT 0
1522 #define PMIC_SRCLKEN_DLY_SRC1_MASK 0xF
1523 #define PMIC_SRCLKEN_DLY_SRC1_SHIFT 12
1524 #define PMIC_BUCK_CON5_RSV0_MASK 0xFFFF
1525 #define PMIC_BUCK_CON5_RSV0_SHIFT 0
1526 #define PMIC_RG_VPROC_TRIML_MASK 0x7
1527 #define PMIC_RG_VPROC_TRIML_SHIFT 0
1528 #define PMIC_RG_VPROC_TRIMH_MASK 0x7
1529 #define PMIC_RG_VPROC_TRIMH_SHIFT 3
1530 #define PMIC_RG_VPROC_CSM_MASK 0x7
1531 #define PMIC_RG_VPROC_CSM_SHIFT 6
1532 #define PMIC_RG_VPROC_ZXOS_TRIM_MASK 0x3F
1533 #define PMIC_RG_VPROC_ZXOS_TRIM_SHIFT 9
1534 #define PMIC_RG_VPROC_RZSEL_MASK 0x3
1535 #define PMIC_RG_VPROC_RZSEL_SHIFT 0
1536 #define PMIC_RG_VPROC_CC_MASK 0x3
1537 #define PMIC_RG_VPROC_CC_SHIFT 4
1538 #define PMIC_RG_VPROC_CSR_MASK 0x3
1539 #define PMIC_RG_VPROC_CSR_SHIFT 6
1540 #define PMIC_RG_VPROC_CSL_MASK 0x3
1541 #define PMIC_RG_VPROC_CSL_SHIFT 8
1542 #define PMIC_RG_VPROC_ZX_OS_MASK 0x3
1543 #define PMIC_RG_VPROC_ZX_OS_SHIFT 14
1544 #define PMIC_RG_VPROC_AVP_OS_MASK 0x7
1545 #define PMIC_RG_VPROC_AVP_OS_SHIFT 0
1546 #define PMIC_RG_VPROC_AVP_EN_MASK 0x1
1547 #define PMIC_RG_VPROC_AVP_EN_SHIFT 3
1548 #define PMIC_RG_VPROC_MODESET_MASK 0x1
1549 #define PMIC_RG_VPROC_MODESET_SHIFT 8
1550 #define PMIC_RG_VPROC_NDIS_EN_MASK 0x1
1551 #define PMIC_RG_VPROC_NDIS_EN_SHIFT 9
1552 #define PMIC_RG_VPROC_SLP_MASK 0x3
1553 #define PMIC_RG_VPROC_SLP_SHIFT 0
1554 #define PMIC_QI_VPROC_VSLEEP_MASK 0x3
1555 #define PMIC_QI_VPROC_VSLEEP_SHIFT 4
1556 #define PMIC_RG_VPROC_RSV_MASK 0xFF
1557 #define PMIC_RG_VPROC_RSV_SHIFT 0
1558 #define PMIC_VPROC_EN_CTRL_MASK 0x1
1559 #define PMIC_VPROC_EN_CTRL_SHIFT 0
1560 #define PMIC_VPROC_VOSEL_CTRL_MASK 0x1
1561 #define PMIC_VPROC_VOSEL_CTRL_SHIFT 1
1562 #define PMIC_VPROC_DLC_CTRL_MASK 0x1
1563 #define PMIC_VPROC_DLC_CTRL_SHIFT 2
1564 #define PMIC_VPROC_BURST_CTRL_MASK 0x1
1565 #define PMIC_VPROC_BURST_CTRL_SHIFT 3
1566 #define PMIC_VPROC_EN_MASK 0x1
1567 #define PMIC_VPROC_EN_SHIFT 0
1568 #define PMIC_QI_VPROC_STB_MASK 0x1
1569 #define PMIC_QI_VPROC_STB_SHIFT 12
1570 #define PMIC_QI_VPROC_EN_MASK 0x1
1571 #define PMIC_QI_VPROC_EN_SHIFT 13
1572 #define PMIC_QI_VPROC_OC_STATUS_MASK 0x1
1573 #define PMIC_QI_VPROC_OC_STATUS_SHIFT 15
1574 #define PMIC_VPROC_SFCHG_FRATE_MASK 0x7F
1575 #define PMIC_VPROC_SFCHG_FRATE_SHIFT 0
1576 #define PMIC_VPROC_SFCHG_FEN_MASK 0x1
1577 #define PMIC_VPROC_SFCHG_FEN_SHIFT 7
1578 #define PMIC_VPROC_SFCHG_RRATE_MASK 0x7F
1579 #define PMIC_VPROC_SFCHG_RRATE_SHIFT 8
1580 #define PMIC_VPROC_SFCHG_REN_MASK 0x1
1581 #define PMIC_VPROC_SFCHG_REN_SHIFT 15
1582 #define PMIC_VPROC_VOSEL_MASK 0x7F
1583 #define PMIC_VPROC_VOSEL_SHIFT 0
1584 #define PMIC_VPROC_VOSEL_ON_MASK 0x7F
1585 #define PMIC_VPROC_VOSEL_ON_SHIFT 0
1586 #define PMIC_VPROC_VOSEL_SLEEP_MASK 0x7F
1587 #define PMIC_VPROC_VOSEL_SLEEP_SHIFT 0
1588 #define PMIC_NI_VPROC_VOSEL_MASK 0x7F
1589 #define PMIC_NI_VPROC_VOSEL_SHIFT 0
1590 #define PMIC_VPROC_BURST_MASK 0x3
1591 #define PMIC_VPROC_BURST_SHIFT 0
1592 #define PMIC_VPROC_BURST_ON_MASK 0x3
1593 #define PMIC_VPROC_BURST_ON_SHIFT 4
1594 #define PMIC_VPROC_BURST_SLEEP_MASK 0x3
1595 #define PMIC_VPROC_BURST_SLEEP_SHIFT 8
1596 #define PMIC_QI_VPROC_BURST_MASK 0x3
1597 #define PMIC_QI_VPROC_BURST_SHIFT 12
1598 #define PMIC_VPROC_DLC_MASK 0x3
1599 #define PMIC_VPROC_DLC_SHIFT 0
1600 #define PMIC_VPROC_DLC_ON_MASK 0x3
1601 #define PMIC_VPROC_DLC_ON_SHIFT 4
1602 #define PMIC_VPROC_DLC_SLEEP_MASK 0x3
1603 #define PMIC_VPROC_DLC_SLEEP_SHIFT 8
1604 #define PMIC_QI_VPROC_DLC_MASK 0x3
1605 #define PMIC_QI_VPROC_DLC_SHIFT 12
1606 #define PMIC_VPROC_DLC_N_MASK 0x3
1607 #define PMIC_VPROC_DLC_N_SHIFT 0
1608 #define PMIC_VPROC_DLC_N_ON_MASK 0x3
1609 #define PMIC_VPROC_DLC_N_ON_SHIFT 4
1610 #define PMIC_VPROC_DLC_N_SLEEP_MASK 0x3
1611 #define PMIC_VPROC_DLC_N_SLEEP_SHIFT 8
1612 #define PMIC_QI_VPROC_DLC_N_MASK 0x3
1613 #define PMIC_QI_VPROC_DLC_N_SHIFT 12
1614 #define PMIC_VPROC_TRANSTD_MASK 0x3
1615 #define PMIC_VPROC_TRANSTD_SHIFT 0
1616 #define PMIC_VPROC_VOSEL_TRANS_EN_MASK 0x3
1617 #define PMIC_VPROC_VOSEL_TRANS_EN_SHIFT 4
1618 #define PMIC_VPROC_VOSEL_TRANS_ONCE_MASK 0x1
1619 #define PMIC_VPROC_VOSEL_TRANS_ONCE_SHIFT 6
1620 #define PMIC_NI_VPROC_VOSEL_TRANS_MASK 0x1
1621 #define PMIC_NI_VPROC_VOSEL_TRANS_SHIFT 7
1622 #define PMIC_VPROC_VSLEEP_EN_MASK 0x1
1623 #define PMIC_VPROC_VSLEEP_EN_SHIFT 8
1624 #define PMIC_VPROC_R2R_PDN_MASK 0x1
1625 #define PMIC_VPROC_R2R_PDN_SHIFT 10
1626 #define PMIC_VPROC_VSLEEP_SEL_MASK 0x1
1627 #define PMIC_VPROC_VSLEEP_SEL_SHIFT 11
1628 #define PMIC_NI_VPROC_R2R_PDN_MASK 0x1
1629 #define PMIC_NI_VPROC_R2R_PDN_SHIFT 14
1630 #define PMIC_NI_VPROC_VSLEEP_SEL_MASK 0x1
1631 #define PMIC_NI_VPROC_VSLEEP_SEL_SHIFT 15
1632 #define PMIC_RG_VSYS_TRIML_MASK 0x7
1633 #define PMIC_RG_VSYS_TRIML_SHIFT 0
1634 #define PMIC_RG_VSYS_TRIMH_MASK 0x7
1635 #define PMIC_RG_VSYS_TRIMH_SHIFT 3
1636 #define PMIC_RG_VSYS_CSM_MASK 0x7
1637 #define PMIC_RG_VSYS_CSM_SHIFT 6
1638 #define PMIC_RG_VSYS_ZXOS_TRIM_MASK 0x3F
1639 #define PMIC_RG_VSYS_ZXOS_TRIM_SHIFT 9
1640 #define PMIC_RG_VSYS_RZSEL_MASK 0x3
1641 #define PMIC_RG_VSYS_RZSEL_SHIFT 0
1642 #define PMIC_RG_VSYS_CC_MASK 0x3
1643 #define PMIC_RG_VSYS_CC_SHIFT 4
1644 #define PMIC_RG_VSYS_CSR_MASK 0x3
1645 #define PMIC_RG_VSYS_CSR_SHIFT 6
1646 #define PMIC_RG_VSYS_CSL_MASK 0x3
1647 #define PMIC_RG_VSYS_CSL_SHIFT 8
1648 #define PMIC_RG_VSYS_ZX_OS_MASK 0x3
1649 #define PMIC_RG_VSYS_ZX_OS_SHIFT 14
1650 #define PMIC_RG_VSYS_AVP_OS_MASK 0x7
1651 #define PMIC_RG_VSYS_AVP_OS_SHIFT 0
1652 #define PMIC_RG_VSYS_AVP_EN_MASK 0x1
1653 #define PMIC_RG_VSYS_AVP_EN_SHIFT 3
1654 #define PMIC_RG_VSYS_MODESET_MASK 0x1
1655 #define PMIC_RG_VSYS_MODESET_SHIFT 8
1656 #define PMIC_RG_VSYS_NDIS_EN_MASK 0x1
1657 #define PMIC_RG_VSYS_NDIS_EN_SHIFT 9
1658 #define PMIC_RG_VSYS_SLP_MASK 0x3
1659 #define PMIC_RG_VSYS_SLP_SHIFT 0
1660 #define PMIC_QI_VSYS_VSLEEP_MASK 0x3
1661 #define PMIC_QI_VSYS_VSLEEP_SHIFT 4
1662 #define PMIC_RG_VSYS_RSV_MASK 0xFF
1663 #define PMIC_RG_VSYS_RSV_SHIFT 0
1664 #define PMIC_VSYS_EN_CTRL_MASK 0x1
1665 #define PMIC_VSYS_EN_CTRL_SHIFT 0
1666 #define PMIC_VSYS_VOSEL_CTRL_MASK 0x1
1667 #define PMIC_VSYS_VOSEL_CTRL_SHIFT 1
1668 #define PMIC_VSYS_DLC_CTRL_MASK 0x1
1669 #define PMIC_VSYS_DLC_CTRL_SHIFT 2
1670 #define PMIC_VSYS_BURST_CTRL_MASK 0x1
1671 #define PMIC_VSYS_BURST_CTRL_SHIFT 3
1672 #define PMIC_VSYS_EN_MASK 0x1
1673 #define PMIC_VSYS_EN_SHIFT 0
1674 #define PMIC_QI_VSYS_STB_MASK 0x1
1675 #define PMIC_QI_VSYS_STB_SHIFT 12
1676 #define PMIC_QI_VSYS_EN_MASK 0x1
1677 #define PMIC_QI_VSYS_EN_SHIFT 13
1678 #define PMIC_QI_VSYS_OC_STATUS_MASK 0x1
1679 #define PMIC_QI_VSYS_OC_STATUS_SHIFT 15
1680 #define PMIC_VSYS_SFCHG_FRATE_MASK 0x7F
1681 #define PMIC_VSYS_SFCHG_FRATE_SHIFT 0
1682 #define PMIC_VSYS_SFCHG_FEN_MASK 0x1
1683 #define PMIC_VSYS_SFCHG_FEN_SHIFT 7
1684 #define PMIC_VSYS_SFCHG_RRATE_MASK 0x7F
1685 #define PMIC_VSYS_SFCHG_RRATE_SHIFT 8
1686 #define PMIC_VSYS_SFCHG_REN_MASK 0x1
1687 #define PMIC_VSYS_SFCHG_REN_SHIFT 15
1688 #define PMIC_VSYS_VOSEL_MASK 0x7F
1689 #define PMIC_VSYS_VOSEL_SHIFT 0
1690 #define PMIC_VSYS_VOSEL_ON_MASK 0x7F
1691 #define PMIC_VSYS_VOSEL_ON_SHIFT 0
1692 #define PMIC_VSYS_VOSEL_SLEEP_MASK 0x7F
1693 #define PMIC_VSYS_VOSEL_SLEEP_SHIFT 0
1694 #define PMIC_NI_VSYS_VOSEL_MASK 0x7F
1695 #define PMIC_NI_VSYS_VOSEL_SHIFT 0
1696 #define PMIC_VSYS_BURST_MASK 0x3
1697 #define PMIC_VSYS_BURST_SHIFT 0
1698 #define PMIC_VSYS_BURST_ON_MASK 0x3
1699 #define PMIC_VSYS_BURST_ON_SHIFT 4
1700 #define PMIC_VSYS_BURST_SLEEP_MASK 0x3
1701 #define PMIC_VSYS_BURST_SLEEP_SHIFT 8
1702 #define PMIC_QI_VSYS_BURST_MASK 0x3
1703 #define PMIC_QI_VSYS_BURST_SHIFT 12
1704 #define PMIC_VSYS_DLC_MASK 0x3
1705 #define PMIC_VSYS_DLC_SHIFT 0
1706 #define PMIC_VSYS_DLC_ON_MASK 0x3
1707 #define PMIC_VSYS_DLC_ON_SHIFT 4
1708 #define PMIC_VSYS_DLC_SLEEP_MASK 0x3
1709 #define PMIC_VSYS_DLC_SLEEP_SHIFT 8
1710 #define PMIC_QI_VSYS_DLC_MASK 0x3
1711 #define PMIC_QI_VSYS_DLC_SHIFT 12
1712 #define PMIC_VSYS_DLC_N_MASK 0x3
1713 #define PMIC_VSYS_DLC_N_SHIFT 0
1714 #define PMIC_VSYS_DLC_N_ON_MASK 0x3
1715 #define PMIC_VSYS_DLC_N_ON_SHIFT 4
1716 #define PMIC_VSYS_DLC_N_SLEEP_MASK 0x3
1717 #define PMIC_VSYS_DLC_N_SLEEP_SHIFT 8
1718 #define PMIC_QI_VSYS_DLC_N_MASK 0x3
1719 #define PMIC_QI_VSYS_DLC_N_SHIFT 12
1720 #define PMIC_VSYS_TRANSTD_MASK 0x3
1721 #define PMIC_VSYS_TRANSTD_SHIFT 0
1722 #define PMIC_VSYS_VOSEL_TRANS_EN_MASK 0x3
1723 #define PMIC_VSYS_VOSEL_TRANS_EN_SHIFT 4
1724 #define PMIC_VSYS_VOSEL_TRANS_ONCE_MASK 0x1
1725 #define PMIC_VSYS_VOSEL_TRANS_ONCE_SHIFT 6
1726 #define PMIC_NI_VSYS_VOSEL_TRANS_MASK 0x1
1727 #define PMIC_NI_VSYS_VOSEL_TRANS_SHIFT 7
1728 #define PMIC_VSYS_VSLEEP_EN_MASK 0x1
1729 #define PMIC_VSYS_VSLEEP_EN_SHIFT 8
1730 #define PMIC_VSYS_R2R_PDN_MASK 0x1
1731 #define PMIC_VSYS_R2R_PDN_SHIFT 10
1732 #define PMIC_VSYS_VSLEEP_SEL_MASK 0x1
1733 #define PMIC_VSYS_VSLEEP_SEL_SHIFT 11
1734 #define PMIC_NI_VSYS_R2R_PDN_MASK 0x1
1735 #define PMIC_NI_VSYS_R2R_PDN_SHIFT 14
1736 #define PMIC_NI_VSYS_VSLEEP_SEL_MASK 0x1
1737 #define PMIC_NI_VSYS_VSLEEP_SEL_SHIFT 15
1738 #define PMIC_RG_VPA_TRIML_MASK 0x7
1739 #define PMIC_RG_VPA_TRIML_SHIFT 0
1740 #define PMIC_RG_VPA_TRIMH_MASK 0x7
1741 #define PMIC_RG_VPA_TRIMH_SHIFT 3
1742 #define PMIC_RG_VPA_RZSEL_MASK 0x3
1743 #define PMIC_RG_VPA_RZSEL_SHIFT 0
1744 #define PMIC_RG_VPA_CC_MASK 0x3
1745 #define PMIC_RG_VPA_CC_SHIFT 4
1746 #define PMIC_RG_VPA_CSR_MASK 0x3
1747 #define PMIC_RG_VPA_CSR_SHIFT 6
1748 #define PMIC_RG_VPA_CSL_MASK 0x3
1749 #define PMIC_RG_VPA_CSL_SHIFT 8
1750 #define PMIC_RG_VPA_SLEW_NMOS_MASK 0x3
1751 #define PMIC_RG_VPA_SLEW_NMOS_SHIFT 10
1752 #define PMIC_RG_VPA_SLEW_MASK 0x3
1753 #define PMIC_RG_VPA_SLEW_SHIFT 12
1754 #define PMIC_RG_VPA_ZX_OS_MASK 0x3
1755 #define PMIC_RG_VPA_ZX_OS_SHIFT 14
1756 #define PMIC_RG_VPA_MODESET_MASK 0x1
1757 #define PMIC_RG_VPA_MODESET_SHIFT 8
1758 #define PMIC_RG_VPA_NDIS_EN_MASK 0x1
1759 #define PMIC_RG_VPA_NDIS_EN_SHIFT 9
1760 #define PMIC_RG_VPA_CSMIR_MASK 0x3
1761 #define PMIC_RG_VPA_CSMIR_SHIFT 12
1762 #define PMIC_RG_VPA_VBAT_DEL_MASK 0x3
1763 #define PMIC_RG_VPA_VBAT_DEL_SHIFT 14
1764 #define PMIC_RG_VPA_SLP_MASK 0x3
1765 #define PMIC_RG_VPA_SLP_SHIFT 0
1766 #define PMIC_RG_VPA_GPU_EN_MASK 0x1
1767 #define PMIC_RG_VPA_GPU_EN_SHIFT 6
1768 #define PMIC_RG_VPA_RSV_MASK 0xFFFF
1769 #define PMIC_RG_VPA_RSV_SHIFT 0
1770 #define PMIC_VPA_EN_CTRL_MASK 0x1
1771 #define PMIC_VPA_EN_CTRL_SHIFT 0
1772 #define PMIC_VPA_VOSEL_CTRL_MASK 0x1
1773 #define PMIC_VPA_VOSEL_CTRL_SHIFT 1
1774 #define PMIC_VPA_DLC_CTRL_MASK 0x1
1775 #define PMIC_VPA_DLC_CTRL_SHIFT 2
1776 #define PMIC_VPA_BURST_CTRL_MASK 0x1
1777 #define PMIC_VPA_BURST_CTRL_SHIFT 3
1778 #define PMIC_VPA_EN_MASK 0x1
1779 #define PMIC_VPA_EN_SHIFT 0
1780 #define PMIC_QI_VPA_STB_MASK 0x1
1781 #define PMIC_QI_VPA_STB_SHIFT 12
1782 #define PMIC_QI_VPA_EN_MASK 0x1
1783 #define PMIC_QI_VPA_EN_SHIFT 13
1784 #define PMIC_QI_VPA_OC_STATUS_MASK 0x1
1785 #define PMIC_QI_VPA_OC_STATUS_SHIFT 15
1786 #define PMIC_VPA_SFCHG_FRATE_MASK 0x7F
1787 #define PMIC_VPA_SFCHG_FRATE_SHIFT 0
1788 #define PMIC_VPA_SFCHG_FEN_MASK 0x1
1789 #define PMIC_VPA_SFCHG_FEN_SHIFT 7
1790 #define PMIC_VPA_SFCHG_RRATE_MASK 0x7F
1791 #define PMIC_VPA_SFCHG_RRATE_SHIFT 8
1792 #define PMIC_VPA_SFCHG_REN_MASK 0x1
1793 #define PMIC_VPA_SFCHG_REN_SHIFT 15
1794 #define PMIC_VPA_VOSEL_MASK 0x3F
1795 #define PMIC_VPA_VOSEL_SHIFT 0
1796 #define PMIC_VPA_VOSEL_ON_MASK 0x3F
1797 #define PMIC_VPA_VOSEL_ON_SHIFT 0
1798 #define PMIC_VPA_VOSEL_SLEEP_MASK 0x3F
1799 #define PMIC_VPA_VOSEL_SLEEP_SHIFT 0
1800 #define PMIC_NI_VPA_VOSEL_MASK 0x3F
1801 #define PMIC_NI_VPA_VOSEL_SHIFT 0
1802 #define PMIC_VPA_DLC_MASK 0x7
1803 #define PMIC_VPA_DLC_SHIFT 0
1804 #define PMIC_VPA_DLC_ON_MASK 0x7
1805 #define PMIC_VPA_DLC_ON_SHIFT 4
1806 #define PMIC_VPA_DLC_SLEEP_MASK 0x7
1807 #define PMIC_VPA_DLC_SLEEP_SHIFT 8
1808 #define PMIC_QI_VPA_DLC_MASK 0x7
1809 #define PMIC_QI_VPA_DLC_SHIFT 12
1810 #define PMIC_VPA_BURSTH_MASK 0x3
1811 #define PMIC_VPA_BURSTH_SHIFT 0
1812 #define PMIC_VPA_BURSTH_ON_MASK 0x3
1813 #define PMIC_VPA_BURSTH_ON_SHIFT 4
1814 #define PMIC_VPA_BURSTH_SLEEP_MASK 0x3
1815 #define PMIC_VPA_BURSTH_SLEEP_SHIFT 8
1816 #define PMIC_QI_VPA_BURSTH_MASK 0x3
1817 #define PMIC_QI_VPA_BURSTH_SHIFT 12
1818 #define PMIC_VPA_BURSTL_MASK 0x3
1819 #define PMIC_VPA_BURSTL_SHIFT 0
1820 #define PMIC_VPA_BURSTL_ON_MASK 0x3
1821 #define PMIC_VPA_BURSTL_ON_SHIFT 4
1822 #define PMIC_VPA_BURSTL_SLEEP_MASK 0x3
1823 #define PMIC_VPA_BURSTL_SLEEP_SHIFT 8
1824 #define PMIC_QI_VPA_BURSTL_MASK 0x3
1825 #define PMIC_QI_VPA_BURSTL_SHIFT 12
1826 #define PMIC_VPA_TRANSTD_MASK 0x3
1827 #define PMIC_VPA_TRANSTD_SHIFT 0
1828 #define PMIC_VPA_VOSEL_TRANS_EN_MASK 0x3
1829 #define PMIC_VPA_VOSEL_TRANS_EN_SHIFT 4
1830 #define PMIC_VPA_VOSEL_TRANS_ONCE_MASK 0x1
1831 #define PMIC_VPA_VOSEL_TRANS_ONCE_SHIFT 6
1832 #define PMIC_NI_VPA_DVS_BW_MASK 0x1
1833 #define PMIC_NI_VPA_DVS_BW_SHIFT 7
1834 #define PMIC_VPA_DLC_MAP_EN_MASK 0x1
1835 #define PMIC_VPA_DLC_MAP_EN_SHIFT 0
1836 #define PMIC_VPA_VOSEL_DLC001_MASK 0x3F
1837 #define PMIC_VPA_VOSEL_DLC001_SHIFT 8
1838 #define PMIC_VPA_VOSEL_DLC011_MASK 0x3F
1839 #define PMIC_VPA_VOSEL_DLC011_SHIFT 0
1840 #define PMIC_VPA_VOSEL_DLC111_MASK 0x3F
1841 #define PMIC_VPA_VOSEL_DLC111_SHIFT 8
1842 #define PMIC_K_RST_DONE_MASK 0x1
1843 #define PMIC_K_RST_DONE_SHIFT 0
1844 #define PMIC_K_MAP_SEL_MASK 0x1
1845 #define PMIC_K_MAP_SEL_SHIFT 1
1846 #define PMIC_K_ONCE_EN_MASK 0x1
1847 #define PMIC_K_ONCE_EN_SHIFT 2
1848 #define PMIC_K_ONCE_MASK 0x1
1849 #define PMIC_K_ONCE_SHIFT 3
1850 #define PMIC_K_START_MANUAL_MASK 0x1
1851 #define PMIC_K_START_MANUAL_SHIFT 4
1852 #define PMIC_K_SRC_SEL_MASK 0x1
1853 #define PMIC_K_SRC_SEL_SHIFT 5
1854 #define PMIC_K_AUTO_EN_MASK 0x1
1855 #define PMIC_K_AUTO_EN_SHIFT 6
1856 #define PMIC_K_INV_MASK 0x1
1857 #define PMIC_K_INV_SHIFT 7
1858 #define PMIC_K_CONTROL_SMPS_MASK 0x1F
1859 #define PMIC_K_CONTROL_SMPS_SHIFT 8
1860 #define PMIC_K_RESULT_MASK 0x1
1861 #define PMIC_K_RESULT_SHIFT 0
1862 #define PMIC_K_DONE_MASK 0x1
1863 #define PMIC_K_DONE_SHIFT 1
1864 #define PMIC_K_CONTROL_MASK 0x1F
1865 #define PMIC_K_CONTROL_SHIFT 3
1866 #define PMIC_QI_SMPS_OSC_CAL_MASK 0x1F
1867 #define PMIC_QI_SMPS_OSC_CAL_SHIFT 8
1868 #define PMIC_ISINK_CH0_MODE_MASK 0x3
1869 #define PMIC_ISINK_CH0_MODE_SHIFT 2
1870 #define PMIC_ISINK0_RSV1_MASK 0xF
1871 #define PMIC_ISINK0_RSV1_SHIFT 4
1872 #define PMIC_ISINK_DIM0_DUTY_MASK 0x1F
1873 #define PMIC_ISINK_DIM0_DUTY_SHIFT 8
1874 #define PMIC_ISINK0_RSV0_MASK 0x7
1875 #define PMIC_ISINK0_RSV0_SHIFT 13
1876 #define PMIC_ISINK_DIM0_FSEL_MASK 0xFFFF
1877 #define PMIC_ISINK_DIM0_FSEL_SHIFT 0
1878 #define PMIC_ISINK_SFSTR0_EN_MASK 0x1
1879 #define PMIC_ISINK_SFSTR0_EN_SHIFT 0
1880 #define PMIC_ISINK_SFSTR0_TC_MASK 0x3
1881 #define PMIC_ISINK_SFSTR0_TC_SHIFT 1
1882 #define PMIC_ISINK_CH0_STEP_MASK 0x7
1883 #define PMIC_ISINK_CH0_STEP_SHIFT 12
1884 #define PMIC_ISINK_BREATH0_TOFF_SEL_MASK 0xF
1885 #define PMIC_ISINK_BREATH0_TOFF_SEL_SHIFT 0
1886 #define PMIC_ISINK_BREATH0_TON_SEL_MASK 0xF
1887 #define PMIC_ISINK_BREATH0_TON_SEL_SHIFT 8
1888 #define PMIC_ISINK_BREATH0_TRF_SEL_MASK 0xF
1889 #define PMIC_ISINK_BREATH0_TRF_SEL_SHIFT 12
1890 #define PMIC_ISINK_CH1_MODE_MASK 0x3
1891 #define PMIC_ISINK_CH1_MODE_SHIFT 2
1892 #define PMIC_ISINK1_RSV1_MASK 0xF
1893 #define PMIC_ISINK1_RSV1_SHIFT 4
1894 #define PMIC_ISINK_DIM1_DUTY_MASK 0x1F
1895 #define PMIC_ISINK_DIM1_DUTY_SHIFT 8
1896 #define PMIC_ISINK1_RSV0_MASK 0x7
1897 #define PMIC_ISINK1_RSV0_SHIFT 13
1898 #define PMIC_ISINK_DIM1_FSEL_MASK 0xFFFF
1899 #define PMIC_ISINK_DIM1_FSEL_SHIFT 0
1900 #define PMIC_ISINK_SFSTR1_EN_MASK 0x1
1901 #define PMIC_ISINK_SFSTR1_EN_SHIFT 0
1902 #define PMIC_ISINK_SFSTR1_TC_MASK 0x3
1903 #define PMIC_ISINK_SFSTR1_TC_SHIFT 1
1904 #define PMIC_ISINK_CH1_STEP_MASK 0x7
1905 #define PMIC_ISINK_CH1_STEP_SHIFT 12
1906 #define PMIC_ISINK_BREATH1_TOFF_SEL_MASK 0xF
1907 #define PMIC_ISINK_BREATH1_TOFF_SEL_SHIFT 0
1908 #define PMIC_ISINK_BREATH1_TON_SEL_MASK 0xF
1909 #define PMIC_ISINK_BREATH1_TON_SEL_SHIFT 8
1910 #define PMIC_ISINK_BREATH1_TRF_SEL_MASK 0xF
1911 #define PMIC_ISINK_BREATH1_TRF_SEL_SHIFT 12
1912 #define PMIC_ISINK_CH2_MODE_MASK 0x3
1913 #define PMIC_ISINK_CH2_MODE_SHIFT 2
1914 #define PMIC_ISINK2_RSV1_MASK 0xF
1915 #define PMIC_ISINK2_RSV1_SHIFT 4
1916 #define PMIC_ISINK_DIM2_DUTY_MASK 0x1F
1917 #define PMIC_ISINK_DIM2_DUTY_SHIFT 8
1918 #define PMIC_ISINK2_RSV0_MASK 0x7
1919 #define PMIC_ISINK2_RSV0_SHIFT 13
1920 #define PMIC_ISINK_DIM2_FSEL_MASK 0xFFFF
1921 #define PMIC_ISINK_DIM2_FSEL_SHIFT 0
1922 #define PMIC_ISINK_SFSTR2_EN_MASK 0x1
1923 #define PMIC_ISINK_SFSTR2_EN_SHIFT 0
1924 #define PMIC_ISINK_SFSTR2_TC_MASK 0x3
1925 #define PMIC_ISINK_SFSTR2_TC_SHIFT 1
1926 #define PMIC_ISINK_CH2_STEP_MASK 0x7
1927 #define PMIC_ISINK_CH2_STEP_SHIFT 12
1928 #define PMIC_ISINK_BREATH2_TOFF_SEL_MASK 0xF
1929 #define PMIC_ISINK_BREATH2_TOFF_SEL_SHIFT 0
1930 #define PMIC_ISINK_BREATH2_TON_SEL_MASK 0xF
1931 #define PMIC_ISINK_BREATH2_TON_SEL_SHIFT 8
1932 #define PMIC_ISINK_BREATH2_TRF_SEL_MASK 0xF
1933 #define PMIC_ISINK_BREATH2_TRF_SEL_SHIFT 12
1934 #define PMIC_ISINK_CH3_MODE_MASK 0x3
1935 #define PMIC_ISINK_CH3_MODE_SHIFT 2
1936 #define PMIC_ISINK3_RSV1_MASK 0xF
1937 #define PMIC_ISINK3_RSV1_SHIFT 4
1938 #define PMIC_ISINK_DIM3_DUTY_MASK 0x1F
1939 #define PMIC_ISINK_DIM3_DUTY_SHIFT 8
1940 #define PMIC_ISINK3_RSV0_MASK 0x7
1941 #define PMIC_ISINK3_RSV0_SHIFT 13
1942 #define PMIC_ISINK_DIM3_FSEL_MASK 0xFFFF
1943 #define PMIC_ISINK_DIM3_FSEL_SHIFT 0
1944 #define PMIC_ISINK_SFSTR3_EN_MASK 0x1
1945 #define PMIC_ISINK_SFSTR3_EN_SHIFT 0
1946 #define PMIC_ISINK_SFSTR3_TC_MASK 0x3
1947 #define PMIC_ISINK_SFSTR3_TC_SHIFT 1
1948 #define PMIC_ISINK_CH3_STEP_MASK 0x7
1949 #define PMIC_ISINK_CH3_STEP_SHIFT 12
1950 #define PMIC_ISINK_BREATH3_TOFF_SEL_MASK 0xF
1951 #define PMIC_ISINK_BREATH3_TOFF_SEL_SHIFT 0
1952 #define PMIC_ISINK_BREATH3_TON_SEL_MASK 0xF
1953 #define PMIC_ISINK_BREATH3_TON_SEL_SHIFT 8
1954 #define PMIC_ISINK_BREATH3_TRF_SEL_MASK 0xF
1955 #define PMIC_ISINK_BREATH3_TRF_SEL_SHIFT 12
1956 #define PMIC_RG_ISINKS_RSV_MASK 0xFF
1957 #define PMIC_RG_ISINKS_RSV_SHIFT 0
1958 #define PMIC_RG_ISINK3_DOUBLE_EN_MASK 0x1
1959 #define PMIC_RG_ISINK3_DOUBLE_EN_SHIFT 8
1960 #define PMIC_RG_ISINK2_DOUBLE_EN_MASK 0x1
1961 #define PMIC_RG_ISINK2_DOUBLE_EN_SHIFT 9
1962 #define PMIC_RG_ISINK1_DOUBLE_EN_MASK 0x1
1963 #define PMIC_RG_ISINK1_DOUBLE_EN_SHIFT 10
1964 #define PMIC_RG_ISINK0_DOUBLE_EN_MASK 0x1
1965 #define PMIC_RG_ISINK0_DOUBLE_EN_SHIFT 11
1966 #define PMIC_RG_TRIM_SEL_MASK 0x7
1967 #define PMIC_RG_TRIM_SEL_SHIFT 12
1968 #define PMIC_RG_TRIM_EN_MASK 0x1
1969 #define PMIC_RG_TRIM_EN_SHIFT 15
1970 #define PMIC_NI_ISINK3_STATUS_MASK 0x1
1971 #define PMIC_NI_ISINK3_STATUS_SHIFT 0
1972 #define PMIC_NI_ISINK2_STATUS_MASK 0x1
1973 #define PMIC_NI_ISINK2_STATUS_SHIFT 1
1974 #define PMIC_NI_ISINK1_STATUS_MASK 0x1
1975 #define PMIC_NI_ISINK1_STATUS_SHIFT 2
1976 #define PMIC_NI_ISINK0_STATUS_MASK 0x1
1977 #define PMIC_NI_ISINK0_STATUS_SHIFT 3
1978 #define PMIC_ISINK_PHASE0_DLY_EN_MASK 0x1
1979 #define PMIC_ISINK_PHASE0_DLY_EN_SHIFT 0
1980 #define PMIC_ISINK_PHASE1_DLY_EN_MASK 0x1
1981 #define PMIC_ISINK_PHASE1_DLY_EN_SHIFT 1
1982 #define PMIC_ISINK_PHASE2_DLY_EN_MASK 0x1
1983 #define PMIC_ISINK_PHASE2_DLY_EN_SHIFT 2
1984 #define PMIC_ISINK_PHASE3_DLY_EN_MASK 0x1
1985 #define PMIC_ISINK_PHASE3_DLY_EN_SHIFT 3
1986 #define PMIC_ISINK_PHASE_DLY_TC_MASK 0x3
1987 #define PMIC_ISINK_PHASE_DLY_TC_SHIFT 4
1988 #define PMIC_ISINK_CH0_EN_MASK 0x1
1989 #define PMIC_ISINK_CH0_EN_SHIFT 0
1990 #define PMIC_ISINK_CH1_EN_MASK 0x1
1991 #define PMIC_ISINK_CH1_EN_SHIFT 1
1992 #define PMIC_ISINK_CH2_EN_MASK 0x1
1993 #define PMIC_ISINK_CH2_EN_SHIFT 2
1994 #define PMIC_ISINK_CH3_EN_MASK 0x1
1995 #define PMIC_ISINK_CH3_EN_SHIFT 3
1996 #define PMIC_ISINK_CHOP0_EN_MASK 0x1
1997 #define PMIC_ISINK_CHOP0_EN_SHIFT 4
1998 #define PMIC_ISINK_CHOP1_EN_MASK 0x1
1999 #define PMIC_ISINK_CHOP1_EN_SHIFT 5
2000 #define PMIC_ISINK_CHOP2_EN_MASK 0x1
2001 #define PMIC_ISINK_CHOP2_EN_SHIFT 6
2002 #define PMIC_ISINK_CHOP3_EN_MASK 0x1
2003 #define PMIC_ISINK_CHOP3_EN_SHIFT 7
2004 #define PMIC_RG_ANALDORSV1_MASK 0xFFFF
2005 #define PMIC_RG_ANALDORSV1_SHIFT 0
2006 #define PMIC_VTCXO_LP_SEL_MASK 0x1
2007 #define PMIC_VTCXO_LP_SEL_SHIFT 0
2008 #define PMIC_VTCXO_LP_SET_MASK 0x1
2009 #define PMIC_VTCXO_LP_SET_SHIFT 1
2010 #define PMIC_QI_VTCXO_MODE_MASK 0x1
2011 #define PMIC_QI_VTCXO_MODE_SHIFT 7
2012 #define PMIC_RG_VTCXO_STBTD_MASK 0x3
2013 #define PMIC_RG_VTCXO_STBTD_SHIFT 8
2014 #define PMIC_RG_VTCXO_EN_MASK 0x1
2015 #define PMIC_RG_VTCXO_EN_SHIFT 10
2016 #define PMIC_VTCXO_ON_CTRL_MASK 0x1
2017 #define PMIC_VTCXO_ON_CTRL_SHIFT 11
2018 #define PMIC_QI_VTCXO_EN_MASK 0x1
2019 #define PMIC_QI_VTCXO_EN_SHIFT 15
2020 #define PMIC_VA_LP_SEL_MASK 0x1
2021 #define PMIC_VA_LP_SEL_SHIFT 0
2022 #define PMIC_VA_LP_SET_MASK 0x1
2023 #define PMIC_VA_LP_SET_SHIFT 1
2024 #define PMIC_QI_VA_MODE_MASK 0x1
2025 #define PMIC_QI_VA_MODE_SHIFT 7
2026 #define PMIC_RG_VA_SENSE_SEL_MASK 0x3
2027 #define PMIC_RG_VA_SENSE_SEL_SHIFT 8
2028 #define PMIC_RG_VA_STBTD_MASK 0x3
2029 #define PMIC_RG_VA_STBTD_SHIFT 12
2030 #define PMIC_RG_VA_EN_MASK 0x1
2031 #define PMIC_RG_VA_EN_SHIFT 14
2032 #define PMIC_QI_VA_EN_MASK 0x1
2033 #define PMIC_QI_VA_EN_SHIFT 15
2034 #define PMIC_RG_ANALDORSV2_MASK 0xFFFF
2035 #define PMIC_RG_ANALDORSV2_SHIFT 0
2036 #define PMIC_RG_VCAMA_STBTD_MASK 0x3
2037 #define PMIC_RG_VCAMA_STBTD_SHIFT 12
2038 #define PMIC_RG_VCAMA_EN_MASK 0x1
2039 #define PMIC_RG_VCAMA_EN_SHIFT 15
2040 #define PMIC_RG_VCAMA_BIST_EN_MASK 0x1
2041 #define PMIC_RG_VCAMA_BIST_EN_SHIFT 0
2042 #define PMIC_RG_VA_BIST_EN_MASK 0x1
2043 #define PMIC_RG_VA_BIST_EN_SHIFT 3
2044 #define PMIC_RG_VTCXO_BIST_EN_MASK 0x1
2045 #define PMIC_RG_VTCXO_BIST_EN_SHIFT 5
2046 #define PMIC_QI_VCAMA_OC_STATUS_MASK 0x1
2047 #define PMIC_QI_VCAMA_OC_STATUS_SHIFT 8
2048 #define PMIC_QI_VA_OC_STATUS_MASK 0x1
2049 #define PMIC_QI_VA_OC_STATUS_SHIFT 11
2050 #define PMIC_QI_VTCXO_OC_STATUS_MASK 0x1
2051 #define PMIC_QI_VTCXO_OC_STATUS_SHIFT 13
2052 #define PMIC_RG_ANALDORSV3_MASK 0xFFFF
2053 #define PMIC_RG_ANALDORSV3_SHIFT 0
2054 #define PMIC_RG_VTCXO_NDIS_EN_MASK 0x1
2055 #define PMIC_RG_VTCXO_NDIS_EN_SHIFT 4
2056 #define PMIC_RG_VTCXO_OCFB_MASK 0x1
2057 #define PMIC_RG_VTCXO_OCFB_SHIFT 6
2058 #define PMIC_RG_VTCXO_CAL_MASK 0xF
2059 #define PMIC_RG_VTCXO_CAL_SHIFT 8
2060 #define PMIC_RG_VA_NDIS_EN_MASK 0x1
2061 #define PMIC_RG_VA_NDIS_EN_SHIFT 2
2062 #define PMIC_RG_VA_OCFB_MASK 0x1
2063 #define PMIC_RG_VA_OCFB_SHIFT 4
2064 #define PMIC_RG_VA_VOSEL_MASK 0x1
2065 #define PMIC_RG_VA_VOSEL_SHIFT 6
2066 #define PMIC_RG_VA_CAL_MASK 0xF
2067 #define PMIC_RG_VA_CAL_SHIFT 8
2068 #define PMIC_RG_VCAMA_FBSEL_MASK 0x3
2069 #define PMIC_RG_VCAMA_FBSEL_SHIFT 0
2070 #define PMIC_RG_VCAMA_NDIS_EN_MASK 0x1
2071 #define PMIC_RG_VCAMA_NDIS_EN_SHIFT 2
2072 #define PMIC_RG_VCAMA_OCFB_MASK 0x1
2073 #define PMIC_RG_VCAMA_OCFB_SHIFT 3
2074 #define PMIC_RG_VCAMA_STB_SEL_MASK 0x1
2075 #define PMIC_RG_VCAMA_STB_SEL_SHIFT 4
2076 #define PMIC_RG_VCAMA_VOSEL_MASK 0x3
2077 #define PMIC_RG_VCAMA_VOSEL_SHIFT 5
2078 #define PMIC_VCAMA_ON_CTRL_MASK 0x1
2079 #define PMIC_VCAMA_ON_CTRL_SHIFT 7
2080 #define PMIC_RG_VCAMA_CAL_MASK 0xF
2081 #define PMIC_RG_VCAMA_CAL_SHIFT 8
2082 #define PMIC_RG_RESERVE_STB_SEL_MASK 0xF
2083 #define PMIC_RG_RESERVE_STB_SEL_SHIFT 0
2084 #define PMIC_RG_ALDO_RESERVE_MASK 0xF
2085 #define PMIC_RG_ALDO_RESERVE_SHIFT 12
2086 #define PMIC_RG_VCN33_VOSEL_MASK 0x3
2087 #define PMIC_RG_VCN33_VOSEL_SHIFT 2
2088 #define PMIC_RG_VCN33_NDIS_EN_MASK 0x1
2089 #define PMIC_RG_VCN33_NDIS_EN_SHIFT 4
2090 #define PMIC_VCN33_ON_CTRL_BT_MASK 0x1
2091 #define PMIC_VCN33_ON_CTRL_BT_SHIFT 5
2092 #define PMIC_RG_VCN33_OCFB_MASK 0x1
2093 #define PMIC_RG_VCN33_OCFB_SHIFT 6
2094 #define PMIC_RG_VCN33_EN_BT_MASK 0x1
2095 #define PMIC_RG_VCN33_EN_BT_SHIFT 7
2096 #define PMIC_RG_VCN33_CAL_MASK 0xF
2097 #define PMIC_RG_VCN33_CAL_SHIFT 11
2098 #define PMIC_RG_VCN33_STBTD_MASK 0x3
2099 #define PMIC_RG_VCN33_STBTD_SHIFT 8
2100 #define PMIC_RG_VCN33_EN_WIFI_MASK 0x1
2101 #define PMIC_RG_VCN33_EN_WIFI_SHIFT 12
2102 #define PMIC_VCN33_ON_CTRL_WIFI_MASK 0x1
2103 #define PMIC_VCN33_ON_CTRL_WIFI_SHIFT 14
2104 #define PMIC_QI_VCN33_EN_MASK 0x1
2105 #define PMIC_QI_VCN33_EN_SHIFT 15
2106 #define PMIC_RG_VCN28_BIST_EN_MASK 0x1
2107 #define PMIC_RG_VCN28_BIST_EN_SHIFT 1
2108 #define PMIC_RG_VCN28_NDIS_EN_MASK 0x1
2109 #define PMIC_RG_VCN28_NDIS_EN_SHIFT 2
2110 #define PMIC_RG_VCN28_OCFB_MASK 0x1
2111 #define PMIC_RG_VCN28_OCFB_SHIFT 4
2112 #define PMIC_RG_VCN28_VOSEL_MASK 0x1
2113 #define PMIC_RG_VCN28_VOSEL_SHIFT 6
2114 #define PMIC_RG_VCN28_CAL_MASK 0xF
2115 #define PMIC_RG_VCN28_CAL_SHIFT 8
2116 #define PMIC_RG_VCN28_STBTD_MASK 0x3
2117 #define PMIC_RG_VCN28_STBTD_SHIFT 8
2118 #define PMIC_RG_VCN28_EN_MASK 0x1
2119 #define PMIC_RG_VCN28_EN_SHIFT 12
2120 #define PMIC_VCN28_ON_CTRL_MASK 0x1
2121 #define PMIC_VCN28_ON_CTRL_SHIFT 14
2122 #define PMIC_QI_VCN28_EN_MASK 0x1
2123 #define PMIC_QI_VCN28_EN_SHIFT 15
2124 #define PMIC_VCN28_LP_SEL_MASK 0x1
2125 #define PMIC_VCN28_LP_SEL_SHIFT 0
2126 #define PMIC_VCN28_LP_SET_MASK 0x1
2127 #define PMIC_VCN28_LP_SET_SHIFT 1
2128 #define PMIC_QI_VCN28_MODE_MASK 0x1
2129 #define PMIC_QI_VCN28_MODE_SHIFT 7
2130 #define PMIC_QI_VCN28_OC_STATUS_MASK 0x1
2131 #define PMIC_QI_VCN28_OC_STATUS_SHIFT 15
2132 #define PMIC_VCN33_LP_SEL_MASK 0x1
2133 #define PMIC_VCN33_LP_SEL_SHIFT 0
2134 #define PMIC_VCN33_LP_SET_MASK 0x1
2135 #define PMIC_VCN33_LP_SET_SHIFT 1
2136 #define PMIC_QI_VCN33_MODE_MASK 0x1
2137 #define PMIC_QI_VCN33_MODE_SHIFT 7
2138 #define PMIC_RG_VCN33_EN_MASK 0x1
2139 #define PMIC_RG_VCN33_EN_SHIFT 12
2140 #define PMIC_RG_VCN33_BIST_EN_MASK 0x1
2141 #define PMIC_RG_VCN33_BIST_EN_SHIFT 14
2142 #define PMIC_QI_VCN33_OC_STATUS_MASK 0x1
2143 #define PMIC_QI_VCN33_OC_STATUS_SHIFT 15
2144 #define PMIC_VIO28_LP_SEL_MASK 0x1
2145 #define PMIC_VIO28_LP_SEL_SHIFT 0
2146 #define PMIC_VIO28_LP_MODE_SET_MASK 0x1
2147 #define PMIC_VIO28_LP_MODE_SET_SHIFT 1
2148 #define PMIC_QI_VIO28_MODE_MASK 0x1
2149 #define PMIC_QI_VIO28_MODE_SHIFT 7
2150 #define PMIC_RG_VIO28_STBTD_MASK 0x3
2151 #define PMIC_RG_VIO28_STBTD_SHIFT 12
2152 #define PMIC_VIO28_EN_MASK 0x1
2153 #define PMIC_VIO28_EN_SHIFT 14
2154 #define PMIC_QI_VIO28_EN_MASK 0x1
2155 #define PMIC_QI_VIO28_EN_SHIFT 15
2156 #define PMIC_VUSB_LP_SEL_MASK 0x1
2157 #define PMIC_VUSB_LP_SEL_SHIFT 0
2158 #define PMIC_VUSB_LP_MODE_SET_MASK 0x1
2159 #define PMIC_VUSB_LP_MODE_SET_SHIFT 1
2160 #define PMIC_QI_VUSB_MODE_MASK 0x1
2161 #define PMIC_QI_VUSB_MODE_SHIFT 7
2162 #define PMIC_RG_VUSB_STBTD_MASK 0x3
2163 #define PMIC_RG_VUSB_STBTD_SHIFT 12
2164 #define PMIC_RG_VUSB_EN_MASK 0x1
2165 #define PMIC_RG_VUSB_EN_SHIFT 14
2166 #define PMIC_QI_VUSB_EN_MASK 0x1
2167 #define PMIC_QI_VUSB_EN_SHIFT 15
2168 #define PMIC_VMC_LP_SEL_MASK 0x1
2169 #define PMIC_VMC_LP_SEL_SHIFT 0
2170 #define PMIC_VMC_LP_MODE_SET_MASK 0x1
2171 #define PMIC_VMC_LP_MODE_SET_SHIFT 1
2172 #define PMIC_RG_STB_SEL_MASK 0x1
2173 #define PMIC_RG_STB_SEL_SHIFT 2
2174 #define PMIC_QI_VMC_MODE_MASK 0x1
2175 #define PMIC_QI_VMC_MODE_SHIFT 7
2176 #define PMIC_RG_VMC_STBTD_MASK 0x3
2177 #define PMIC_RG_VMC_STBTD_SHIFT 8
2178 #define PMIC_RG_VMC_EN_MASK 0x1
2179 #define PMIC_RG_VMC_EN_SHIFT 12
2180 #define PMIC_RG_VMC_INT_DIS_SEL_MASK 0x1
2181 #define PMIC_RG_VMC_INT_DIS_SEL_SHIFT 14
2182 #define PMIC_QI_VMC_EN_MASK 0x1
2183 #define PMIC_QI_VMC_EN_SHIFT 15
2184 #define PMIC_VMCH_LP_SEL_MASK 0x1
2185 #define PMIC_VMCH_LP_SEL_SHIFT 0
2186 #define PMIC_VMCH_LP_MODE_SET_MASK 0x1
2187 #define PMIC_VMCH_LP_MODE_SET_SHIFT 1
2188 #define PMIC_QI_VMCH_MODE_MASK 0x1
2189 #define PMIC_QI_VMCH_MODE_SHIFT 7
2190 #define PMIC_RG_VMCH_STBTD_MASK 0x3
2191 #define PMIC_RG_VMCH_STBTD_SHIFT 12
2192 #define PMIC_RG_VMCH_EN_MASK 0x1
2193 #define PMIC_RG_VMCH_EN_SHIFT 14
2194 #define PMIC_QI_VMCH_EN_MASK 0x1
2195 #define PMIC_QI_VMCH_EN_SHIFT 15
2196 #define PMIC_VEMC_3V3_LP_SEL_MASK 0x1
2197 #define PMIC_VEMC_3V3_LP_SEL_SHIFT 0
2198 #define PMIC_VEMC_3V3_LP_MODE_SET_MASK 0x1
2199 #define PMIC_VEMC_3V3_LP_MODE_SET_SHIFT 1
2200 #define PMIC_QI_VEMC_3V3_MODE_MASK 0x1
2201 #define PMIC_QI_VEMC_3V3_MODE_SHIFT 7
2202 #define PMIC_RG_VEMC_3V3_STBTD_MASK 0x3
2203 #define PMIC_RG_VEMC_3V3_STBTD_SHIFT 12
2204 #define PMIC_RG_VEMC_3V3_EN_MASK 0x1
2205 #define PMIC_RG_VEMC_3V3_EN_SHIFT 14
2206 #define PMIC_QI_VEMC_3V3_EN_MASK 0x1
2207 #define PMIC_QI_VEMC_3V3_EN_SHIFT 15
2208 #define PMIC_VGP1_LP_SEL_MASK 0x1
2209 #define PMIC_VGP1_LP_SEL_SHIFT 0
2210 #define PMIC_VGP1_LP_MODE_SET_MASK 0x1
2211 #define PMIC_VGP1_LP_MODE_SET_SHIFT 1
2212 #define PMIC_QI_VGP1_MODE_MASK 0x1
2213 #define PMIC_QI_VGP1_MODE_SHIFT 7
2214 #define PMIC_RG_VGP1_STBTD_MASK 0x3
2215 #define PMIC_RG_VGP1_STBTD_SHIFT 12
2216 #define PMIC_RG_VGP1_EN_MASK 0x1
2217 #define PMIC_RG_VGP1_EN_SHIFT 15
2218 #define PMIC_VGP2_LP_SEL_MASK 0x1
2219 #define PMIC_VGP2_LP_SEL_SHIFT 0
2220 #define PMIC_VGP2_LP_MODE_SET_MASK 0x1
2221 #define PMIC_VGP2_LP_MODE_SET_SHIFT 1
2222 #define PMIC_QI_VGP2_MODE_MASK 0x1
2223 #define PMIC_QI_VGP2_MODE_SHIFT 7
2224 #define PMIC_RG_VGP2_STBTD_MASK 0x3
2225 #define PMIC_RG_VGP2_STBTD_SHIFT 12
2226 #define PMIC_RG_VGP2_EN_MASK 0x1
2227 #define PMIC_RG_VGP2_EN_SHIFT 15
2228 #define PMIC_VGP3_LP_SEL_MASK 0x1
2229 #define PMIC_VGP3_LP_SEL_SHIFT 0
2230 #define PMIC_VGP3_LP_MODE_SET_MASK 0x1
2231 #define PMIC_VGP3_LP_MODE_SET_SHIFT 1
2232 #define PMIC_QI_VGP3_MODE_MASK 0x1
2233 #define PMIC_QI_VGP3_MODE_SHIFT 7
2234 #define PMIC_RG_VGP3_STBTD_MASK 0x3
2235 #define PMIC_RG_VGP3_STBTD_SHIFT 12
2236 #define PMIC_RG_VGP3_EN_MASK 0x1
2237 #define PMIC_RG_VGP3_EN_SHIFT 15
2238 #define PMIC_RG_VCN_1V8_NDIS_EN_MASK 0x1
2239 #define PMIC_RG_VCN_1V8_NDIS_EN_SHIFT 0
2240 #define PMIC_VCN_1V8_ON_CTRL_MASK 0x1
2241 #define PMIC_VCN_1V8_ON_CTRL_SHIFT 1
2242 #define PMIC_RG_VCN_1V8_OCFB_MASK 0x1
2243 #define PMIC_RG_VCN_1V8_OCFB_SHIFT 2
2244 #define PMIC_RG_VCN_1V8_STB_SEL_MASK 0x1
2245 #define PMIC_RG_VCN_1V8_STB_SEL_SHIFT 4
2246 #define PMIC_RG_VCN_1V8_CAL_MASK 0xF
2247 #define PMIC_RG_VCN_1V8_CAL_SHIFT 8
2248 #define PMIC_VCN_1V8_LP_SEL_MASK 0x1
2249 #define PMIC_VCN_1V8_LP_SEL_SHIFT 0
2250 #define PMIC_VCN_1V8_LP_MODE_SET_MASK 0x1
2251 #define PMIC_VCN_1V8_LP_MODE_SET_SHIFT 1
2252 #define PMIC_QI_VCN_1V8_MODE_MASK 0x1
2253 #define PMIC_QI_VCN_1V8_MODE_SHIFT 7
2254 #define PMIC_RG_VCN_1V8_STBTD_MASK 0x3
2255 #define PMIC_RG_VCN_1V8_STBTD_SHIFT 12
2256 #define PMIC_RG_VCN_1V8_EN_MASK 0x1
2257 #define PMIC_RG_VCN_1V8_EN_SHIFT 14
2258 #define PMIC_QI_VCN_1V8_EN_MASK 0x1
2259 #define PMIC_QI_VCN_1V8_EN_SHIFT 15
2260 #define PMIC_RG_STB_SIM1_SIO_MASK 0x1
2261 #define PMIC_RG_STB_SIM1_SIO_SHIFT 0
2262 #define PMIC_RE_DIGLDORSV1_MASK 0x7FFF
2263 #define PMIC_RE_DIGLDORSV1_SHIFT 1
2264 #define PMIC_VSIM1_LP_SEL_MASK 0x1
2265 #define PMIC_VSIM1_LP_SEL_SHIFT 0
2266 #define PMIC_VSIM1_LP_MODE_SET_MASK 0x1
2267 #define PMIC_VSIM1_LP_MODE_SET_SHIFT 1
2268 #define PMIC_QI_VSIM1_MODE_MASK 0x1
2269 #define PMIC_QI_VSIM1_MODE_SHIFT 7
2270 #define PMIC_RG_VSIM1_STBTD_MASK 0x3
2271 #define PMIC_RG_VSIM1_STBTD_SHIFT 12
2272 #define PMIC_RG_VSIM1_EN_MASK 0x1
2273 #define PMIC_RG_VSIM1_EN_SHIFT 15
2274 #define PMIC_VSIM2_LP_SEL_MASK 0x1
2275 #define PMIC_VSIM2_LP_SEL_SHIFT 0
2276 #define PMIC_VSIM2_LP_MODE_SET_MASK 0x1
2277 #define PMIC_VSIM2_LP_MODE_SET_SHIFT 1
2278 #define PMIC_VSIM2_THER_SHDN_EN_MASK 0x1
2279 #define PMIC_VSIM2_THER_SHDN_EN_SHIFT 2
2280 #define PMIC_QI_VSIM2_MODE_MASK 0x1
2281 #define PMIC_QI_VSIM2_MODE_SHIFT 7
2282 #define PMIC_RG_VSIM2_STBTD_MASK 0x3
2283 #define PMIC_RG_VSIM2_STBTD_SHIFT 12
2284 #define PMIC_RG_VSIM2_EN_MASK 0x1
2285 #define PMIC_RG_VSIM2_EN_SHIFT 15
2286 #define PMIC_RG_VRTC_FORCE_ON_MASK 0x1
2287 #define PMIC_RG_VRTC_FORCE_ON_SHIFT 0
2288 #define PMIC_VRTC_EN_MASK 0x1
2289 #define PMIC_VRTC_EN_SHIFT 8
2290 #define PMIC_QI_VRTC_EN_MASK 0x1
2291 #define PMIC_QI_VRTC_EN_SHIFT 15
2292 #define PMIC_RG_VEMC_3V3_BIST_EN_MASK 0x1
2293 #define PMIC_RG_VEMC_3V3_BIST_EN_SHIFT 3
2294 #define PMIC_RG_VMCH_BIST_EN_MASK 0x1
2295 #define PMIC_RG_VMCH_BIST_EN_SHIFT 6
2296 #define PMIC_RG_VMC_BIST_EN_MASK 0x1
2297 #define PMIC_RG_VMC_BIST_EN_SHIFT 10
2298 #define PMIC_RG_VUSB_BIST_EN_MASK 0x1
2299 #define PMIC_RG_VUSB_BIST_EN_SHIFT 11
2300 #define PMIC_RG_VIO28_BIST_EN_MASK 0x1
2301 #define PMIC_RG_VIO28_BIST_EN_SHIFT 15
2302 #define PMIC_RG_VRTC_BIST_EN_MASK 0x1
2303 #define PMIC_RG_VRTC_BIST_EN_SHIFT 0
2304 #define PMIC_RG_VSIM2_BIST_EN_MASK 0x1
2305 #define PMIC_RG_VSIM2_BIST_EN_SHIFT 2
2306 #define PMIC_RG_VSIM1_BIST_EN_MASK 0x1
2307 #define PMIC_RG_VSIM1_BIST_EN_SHIFT 3
2308 #define PMIC_RG_VIBR_BIST_EN_MASK 0x1
2309 #define PMIC_RG_VIBR_BIST_EN_SHIFT 5
2310 #define PMIC_RG_VGP3_BIST_EN_MASK 0x1
2311 #define PMIC_RG_VGP3_BIST_EN_SHIFT 11
2312 #define PMIC_RG_VGP2_BIST_EN_MASK 0x1
2313 #define PMIC_RG_VGP2_BIST_EN_SHIFT 14
2314 #define PMIC_RG_VGP1_BIST_EN_MASK 0x1
2315 #define PMIC_RG_VGP1_BIST_EN_SHIFT 15
2316 #define PMIC_QI_VEMC_3V3_OC_STATUS_MASK 0x1
2317 #define PMIC_QI_VEMC_3V3_OC_STATUS_SHIFT 3
2318 #define PMIC_QI_VMCH_OC_STATUS_MASK 0x1
2319 #define PMIC_QI_VMCH_OC_STATUS_SHIFT 6
2320 #define PMIC_QI_VMC_OC_STATUS_MASK 0x1
2321 #define PMIC_QI_VMC_OC_STATUS_SHIFT 10
2322 #define PMIC_QI_VUSB_OC_STATUS_MASK 0x1
2323 #define PMIC_QI_VUSB_OC_STATUS_SHIFT 11
2324 #define PMIC_QI_VIO28_OC_STATUS_MASK 0x1
2325 #define PMIC_QI_VIO28_OC_STATUS_SHIFT 15
2326 #define PMIC_QI_VSIM2_OC_STATUS_MASK 0x1
2327 #define PMIC_QI_VSIM2_OC_STATUS_SHIFT 2
2328 #define PMIC_QI_VSIM1_OC_STATUS_MASK 0x1
2329 #define PMIC_QI_VSIM1_OC_STATUS_SHIFT 3
2330 #define PMIC_QI_VIBR_OC_STATUS_MASK 0x1
2331 #define PMIC_QI_VIBR_OC_STATUS_SHIFT 5
2332 #define PMIC_QI_VGP3_OC_STATUS_MASK 0x1
2333 #define PMIC_QI_VGP3_OC_STATUS_SHIFT 11
2334 #define PMIC_QI_VGP2_OC_STATUS_MASK 0x1
2335 #define PMIC_QI_VGP2_OC_STATUS_SHIFT 14
2336 #define PMIC_QI_VGP1_OC_STATUS_MASK 0x1
2337 #define PMIC_QI_VGP1_OC_STATUS_SHIFT 15
2338 #define PMIC_RG_STB_SIM2_SIO_MASK 0x1
2339 #define PMIC_RG_STB_SIM2_SIO_SHIFT 0
2340 #define PMIC_RE_DIGLDORSV2_MASK 0x7FFF
2341 #define PMIC_RE_DIGLDORSV2_SHIFT 1
2342 #define PMIC_RG_VIO28_NDIS_EN_MASK 0x1
2343 #define PMIC_RG_VIO28_NDIS_EN_SHIFT 4
2344 #define PMIC_RG_VIO28_OCFB_MASK 0x1
2345 #define PMIC_RG_VIO28_OCFB_SHIFT 6
2346 #define PMIC_RG_VIO28_CAL_MASK 0xF
2347 #define PMIC_RG_VIO28_CAL_SHIFT 8
2348 #define PMIC_RG_VUSB_NDIS_EN_MASK 0x1
2349 #define PMIC_RG_VUSB_NDIS_EN_SHIFT 4
2350 #define PMIC_RG_VUSB_OCFB_MASK 0x1
2351 #define PMIC_RG_VUSB_OCFB_SHIFT 6
2352 #define PMIC_RG_VUSB_CAL_MASK 0xF
2353 #define PMIC_RG_VUSB_CAL_SHIFT 8
2354 #define PMIC_RG_VMC_NDIS_EN_MASK 0x1
2355 #define PMIC_RG_VMC_NDIS_EN_SHIFT 0
2356 #define PMIC_VMC_ON_CTRL_MASK 0x1
2357 #define PMIC_VMC_ON_CTRL_SHIFT 1
2358 #define PMIC_RG_VMC_OCFB_MASK 0x1
2359 #define PMIC_RG_VMC_OCFB_SHIFT 2
2360 #define PMIC_RG_VMC_VOSEL_MASK 0x1
2361 #define PMIC_RG_VMC_VOSEL_SHIFT 4
2362 #define PMIC_RG_VMC_STB_SEL_MASK 0x1
2363 #define PMIC_RG_VMC_STB_SEL_SHIFT 6
2364 #define PMIC_RG_VMC_STB_SEL_CAL_MASK 0x3
2365 #define PMIC_RG_VMC_STB_SEL_CAL_SHIFT 7
2366 #define PMIC_RG_VMC_CAL_MASK 0xF
2367 #define PMIC_RG_VMC_CAL_SHIFT 9
2368 #define PMIC_RG_VMCH_NDIS_EN_MASK 0x1
2369 #define PMIC_RG_VMCH_NDIS_EN_SHIFT 0
2370 #define PMIC_VMCH_ON_CTRL_MASK 0x1
2371 #define PMIC_VMCH_ON_CTRL_SHIFT 1
2372 #define PMIC_RG_VMCH_OCFB_MASK 0x1
2373 #define PMIC_RG_VMCH_OCFB_SHIFT 2
2374 #define PMIC_RG_VMCH_DB_EN_MASK 0x1
2375 #define PMIC_RG_VMCH_DB_EN_SHIFT 4
2376 #define PMIC_RG_VMCH_STB_SEL_MASK 0x1
2377 #define PMIC_RG_VMCH_STB_SEL_SHIFT 6
2378 #define PMIC_RG_VMCH_VOSEL_MASK 0x1
2379 #define PMIC_RG_VMCH_VOSEL_SHIFT 7
2380 #define PMIC_RG_VMCH_STB_SEL_CAL_MASK 0x3
2381 #define PMIC_RG_VMCH_STB_SEL_CAL_SHIFT 8
2382 #define PMIC_RG_VMCH_CAL_MASK 0xF
2383 #define PMIC_RG_VMCH_CAL_SHIFT 10
2384 #define PMIC_RG_VEMC_3V3_NDIS_EN_MASK 0x1
2385 #define PMIC_RG_VEMC_3V3_NDIS_EN_SHIFT 0
2386 #define PMIC_VEMC_3V3_ON_CTRL_MASK 0x1
2387 #define PMIC_VEMC_3V3_ON_CTRL_SHIFT 1
2388 #define PMIC_RG_VEMC_3V3_OCFB_MASK 0x1
2389 #define PMIC_RG_VEMC_3V3_OCFB_SHIFT 2
2390 #define PMIC_RG_VEMC_3V3_DL_EN_MASK 0x1
2391 #define PMIC_RG_VEMC_3V3_DL_EN_SHIFT 3
2392 #define PMIC_RG_VEMC_3V3_DB_EN_MASK 0x1
2393 #define PMIC_RG_VEMC_3V3_DB_EN_SHIFT 4
2394 #define PMIC_RG_VEMC_3V3_STB_SEL_MASK 0x1
2395 #define PMIC_RG_VEMC_3V3_STB_SEL_SHIFT 6
2396 #define PMIC_RG_VEMC_3V3_VOSEL_MASK 0x1
2397 #define PMIC_RG_VEMC_3V3_VOSEL_SHIFT 7
2398 #define PMIC_RG_VEMC_3V3_STB_SEL_CAL_MASK 0x3
2399 #define PMIC_RG_VEMC_3V3_STB_SEL_CAL_SHIFT 8
2400 #define PMIC_RG_VEMC_3V3_CAL_MASK 0xF
2401 #define PMIC_RG_VEMC_3V3_CAL_SHIFT 10
2402 #define PMIC_RG_VGP1_NDIS_EN_MASK 0x1
2403 #define PMIC_RG_VGP1_NDIS_EN_SHIFT 0
2404 #define PMIC_RG_VGP1_OCFB_MASK 0x1
2405 #define PMIC_RG_VGP1_OCFB_SHIFT 2
2406 #define PMIC_RG_VGP1_STB_SEL_MASK 0x1
2407 #define PMIC_RG_VGP1_STB_SEL_SHIFT 4
2408 #define PMIC_RG_VGP1_VOSEL_MASK 0x7
2409 #define PMIC_RG_VGP1_VOSEL_SHIFT 5
2410 #define PMIC_RG_VGP1_CAL_MASK 0xF
2411 #define PMIC_RG_VGP1_CAL_SHIFT 8
2412 #define PMIC_RG_VGP2_NDIS_EN_MASK 0x1
2413 #define PMIC_RG_VGP2_NDIS_EN_SHIFT 0
2414 #define PMIC_RG_VGP2_OCFB_MASK 0x1
2415 #define PMIC_RG_VGP2_OCFB_SHIFT 2
2416 #define PMIC_RG_VGP2_STB_SEL_MASK 0x1
2417 #define PMIC_RG_VGP2_STB_SEL_SHIFT 4
2418 #define PMIC_RG_VGP2_VOSEL_MASK 0x7
2419 #define PMIC_RG_VGP2_VOSEL_SHIFT 5
2420 #define PMIC_RG_VGP2_CAL_MASK 0xF
2421 #define PMIC_RG_VGP2_CAL_SHIFT 8
2422 #define PMIC_RG_VGP3_NDIS_EN_MASK 0x1
2423 #define PMIC_RG_VGP3_NDIS_EN_SHIFT 0
2424 #define PMIC_RG_VGP3_OCFB_MASK 0x1
2425 #define PMIC_RG_VGP3_OCFB_SHIFT 2
2426 #define PMIC_RG_VGP3_STB_SEL_MASK 0x1
2427 #define PMIC_RG_VGP3_STB_SEL_SHIFT 4
2428 #define PMIC_RG_VGP3_VOSEL_MASK 0x3
2429 #define PMIC_RG_VGP3_VOSEL_SHIFT 5
2430 #define PMIC_RG_VGP3_CAL_MASK 0xF
2431 #define PMIC_RG_VGP3_CAL_SHIFT 8
2432 #define PMIC_VCAM_AF_LP_SEL_MASK 0x1
2433 #define PMIC_VCAM_AF_LP_SEL_SHIFT 0
2434 #define PMIC_VCAM_AF_LP_MODE_SET_MASK 0x1
2435 #define PMIC_VCAM_AF_LP_MODE_SET_SHIFT 1
2436 #define PMIC_QI_VCAM_AF_MODE_MASK 0x1
2437 #define PMIC_QI_VCAM_AF_MODE_SHIFT 7
2438 #define PMIC_RG_VCAM_AF_STBTD_MASK 0x3
2439 #define PMIC_RG_VCAM_AF_STBTD_SHIFT 12
2440 #define PMIC_RG_VCAM_AF_EN_MASK 0x1
2441 #define PMIC_RG_VCAM_AF_EN_SHIFT 15
2442 #define PMIC_RG_VCAM_AF_NDIS_EN_MASK 0x1
2443 #define PMIC_RG_VCAM_AF_NDIS_EN_SHIFT 0
2444 #define PMIC_RG_VCAM_AF_OCFB_MASK 0x1
2445 #define PMIC_RG_VCAM_AF_OCFB_SHIFT 2
2446 #define PMIC_VCAM_AF_ON_CTRL_MASK 0x1
2447 #define PMIC_VCAM_AF_ON_CTRL_SHIFT 3
2448 #define PMIC_RG_VCAM_AF_STB_SEL_MASK 0x1
2449 #define PMIC_RG_VCAM_AF_STB_SEL_SHIFT 4
2450 #define PMIC_RG_VCAM_AF_VOSEL_MASK 0x7
2451 #define PMIC_RG_VCAM_AF_VOSEL_SHIFT 5
2452 #define PMIC_RG_VCAM_AF_CAL_MASK 0xF
2453 #define PMIC_RG_VCAM_AF_CAL_SHIFT 11
2454 #define PMIC_RE_DIGLDORSV3_MASK 0xFFFF
2455 #define PMIC_RE_DIGLDORSV3_SHIFT 0
2456 #define PMIC_RG_VSIM1_NDIS_EN_MASK 0x1
2457 #define PMIC_RG_VSIM1_NDIS_EN_SHIFT 0
2458 #define PMIC_RG_VSIM1_OCFB_MASK 0x1
2459 #define PMIC_RG_VSIM1_OCFB_SHIFT 2
2460 #define PMIC_RG_VSIM1_STB_SEL_MASK 0x1
2461 #define PMIC_RG_VSIM1_STB_SEL_SHIFT 4
2462 #define PMIC_RG_VSIM1_VOSEL_MASK 0x1
2463 #define PMIC_RG_VSIM1_VOSEL_SHIFT 5
2464 #define PMIC_RG_VSIM1_CAL_MASK 0xF
2465 #define PMIC_RG_VSIM1_CAL_SHIFT 8
2466 #define PMIC_RG_VSIM2_NDIS_EN_MASK 0x1
2467 #define PMIC_RG_VSIM2_NDIS_EN_SHIFT 0
2468 #define PMIC_RG_VSIM2_OCFB_MASK 0x1
2469 #define PMIC_RG_VSIM2_OCFB_SHIFT 2
2470 #define PMIC_RG_VSIM2_STB_SEL_MASK 0x1
2471 #define PMIC_RG_VSIM2_STB_SEL_SHIFT 4
2472 #define PMIC_RG_VSIM2_VOSEL_MASK 0x1
2473 #define PMIC_RG_VSIM2_VOSEL_SHIFT 5
2474 #define PMIC_RG_VSIM2_CAL_MASK 0xF
2475 #define PMIC_RG_VSIM2_CAL_SHIFT 8
2476 #define PMIC_RG_VSYSLDO_RESERVE_MASK 0x3
2477 #define PMIC_RG_VSYSLDO_RESERVE_SHIFT 0
2478 #define PMIC_VIBR_LP_SEL_MASK 0x1
2479 #define PMIC_VIBR_LP_SEL_SHIFT 0
2480 #define PMIC_VIBR_LP_MODE_SET_MASK 0x1
2481 #define PMIC_VIBR_LP_MODE_SET_SHIFT 1
2482 #define PMIC_VIBR_THER_SHEN_EN_MASK 0x1
2483 #define PMIC_VIBR_THER_SHEN_EN_SHIFT 2
2484 #define PMIC_QI_VIBR_MODE_MASK 0x1
2485 #define PMIC_QI_VIBR_MODE_SHIFT 7
2486 #define PMIC_RG_VIBR_STBTD_MASK 0x3
2487 #define PMIC_RG_VIBR_STBTD_SHIFT 12
2488 #define PMIC_RG_VIBR_EN_MASK 0x1
2489 #define PMIC_RG_VIBR_EN_SHIFT 15
2490 #define PMIC_RG_VIBR_NDIS_EN_MASK 0x1
2491 #define PMIC_RG_VIBR_NDIS_EN_SHIFT 0
2492 #define PMIC_RG_VIBR_OCFB_MASK 0x1
2493 #define PMIC_RG_VIBR_OCFB_SHIFT 2
2494 #define PMIC_RG_VIBR_STB_SEL_MASK 0x1
2495 #define PMIC_RG_VIBR_STB_SEL_SHIFT 4
2496 #define PMIC_RG_VIBR_VOSEL_MASK 0x7
2497 #define PMIC_RG_VIBR_VOSEL_SHIFT 5
2498 #define PMIC_RG_VIBR_STB_SEL_CAL_MASK 0x3
2499 #define PMIC_RG_VIBR_STB_SEL_CAL_SHIFT 8
2500 #define PMIC_RG_VIBR_CAL_MASK 0xF
2501 #define PMIC_RG_VIBR_CAL_SHIFT 10
2502 #define PMIC_DIGLDO_RSV1_MASK 0xFF
2503 #define PMIC_DIGLDO_RSV1_SHIFT 0
2504 #define PMIC_DIGLDO_RSV0_MASK 0xF
2505 #define PMIC_DIGLDO_RSV0_SHIFT 8
2506 #define PMIC_RG_LDO_FT_MASK 0x1
2507 #define PMIC_RG_LDO_FT_SHIFT 15
2508 #define PMIC_QI_VCAM_IO_OC_STATUS_MASK 0x1
2509 #define PMIC_QI_VCAM_IO_OC_STATUS_SHIFT 3
2510 #define PMIC_QI_VCAMD_OC_STATUS_MASK 0x1
2511 #define PMIC_QI_VCAMD_OC_STATUS_SHIFT 5
2512 #define PMIC_QI_VCN_1V8_OC_STATUS_MASK 0x1
2513 #define PMIC_QI_VCN_1V8_OC_STATUS_SHIFT 7
2514 #define PMIC_QI_VIO18_OC_STATUS_MASK 0x1
2515 #define PMIC_QI_VIO18_OC_STATUS_SHIFT 9
2516 #define PMIC_QI_VRF18_OC_STATUS_MASK 0x1
2517 #define PMIC_QI_VRF18_OC_STATUS_SHIFT 11
2518 #define PMIC_QI_VM_OC_STATUS_MASK 0x1
2519 #define PMIC_QI_VM_OC_STATUS_SHIFT 13
2520 #define PMIC_QI_VCAM_AF_OC_STATUS_MASK 0x1
2521 #define PMIC_QI_VCAM_AF_OC_STATUS_SHIFT 15
2522 #define PMIC_RG_VCAM_AF_BIST_EN_MASK 0x1
2523 #define PMIC_RG_VCAM_AF_BIST_EN_SHIFT 2
2524 #define PMIC_RG_VCAMD_IO_BIST_EN_MASK 0x1
2525 #define PMIC_RG_VCAMD_IO_BIST_EN_SHIFT 3
2526 #define PMIC_RG_VCN_1V8_BIST_EN_MASK 0x1
2527 #define PMIC_RG_VCN_1V8_BIST_EN_SHIFT 4
2528 #define PMIC_RG_VCAMD_BIST_EN_MASK 0x1
2529 #define PMIC_RG_VCAMD_BIST_EN_SHIFT 6
2530 #define PMIC_RG_VIO18_BIST_EN_MASK 0x1
2531 #define PMIC_RG_VIO18_BIST_EN_SHIFT 10
2532 #define PMIC_RG_VM_BIST_EN_MASK 0x1
2533 #define PMIC_RG_VM_BIST_EN_SHIFT 11
2534 #define PMIC_RG_VRF18_BIST_EN_MASK 0x1
2535 #define PMIC_RG_VRF18_BIST_EN_SHIFT 15
2536 #define PMIC_VIBR_ON_CTRL_MASK 0x1
2537 #define PMIC_VIBR_ON_CTRL_SHIFT 7
2538 #define PMIC_VSIM2_ON_CTRL_MASK 0x1
2539 #define PMIC_VSIM2_ON_CTRL_SHIFT 8
2540 #define PMIC_VSIM1_ON_CTRL_MASK 0x1
2541 #define PMIC_VSIM1_ON_CTRL_SHIFT 9
2542 #define PMIC_VGP3_ON_CTRL_MASK 0x1
2543 #define PMIC_VGP3_ON_CTRL_SHIFT 13
2544 #define PMIC_VGP2_ON_CTRL_MASK 0x1
2545 #define PMIC_VGP2_ON_CTRL_SHIFT 14
2546 #define PMIC_VGP1_ON_CTRL_MASK 0x1
2547 #define PMIC_VGP1_ON_CTRL_SHIFT 15
2548 #define PMIC_VRF18_LP_SEL_MASK 0x1
2549 #define PMIC_VRF18_LP_SEL_SHIFT 0
2550 #define PMIC_VRF18_LP_MODE_SET_MASK 0x1
2551 #define PMIC_VRF18_LP_MODE_SET_SHIFT 1
2552 #define PMIC_QI_VRF18_MODE_MASK 0x1
2553 #define PMIC_QI_VRF18_MODE_SHIFT 7
2554 #define PMIC_RG_VRF18_STBTD_MASK 0x3
2555 #define PMIC_RG_VRF18_STBTD_SHIFT 12
2556 #define PMIC_RG_VRF18_EN_MASK 0x1
2557 #define PMIC_RG_VRF18_EN_SHIFT 15
2558 #define PMIC_RG_VRF18_NDIS_EN_MASK 0x1
2559 #define PMIC_RG_VRF18_NDIS_EN_SHIFT 0
2560 #define PMIC_VRF18_ON_CTRL_MASK 0x1
2561 #define PMIC_VRF18_ON_CTRL_SHIFT 1
2562 #define PMIC_RG_VRF18_OCFB_MASK 0x1
2563 #define PMIC_RG_VRF18_OCFB_SHIFT 2
2564 #define PMIC_RG_VRF18_STB_SEL_MASK 0x1
2565 #define PMIC_RG_VRF18_STB_SEL_SHIFT 4
2566 #define PMIC_RG_VRF18_CAL_MASK 0xF
2567 #define PMIC_RG_VRF18_CAL_SHIFT 8
2568 #define PMIC_VM_LP_SEL_MASK 0x1
2569 #define PMIC_VM_LP_SEL_SHIFT 0
2570 #define PMIC_VM_LP_MODE_SET_MASK 0x1
2571 #define PMIC_VM_LP_MODE_SET_SHIFT 1
2572 #define PMIC_QI_VM_MODE_MASK 0x1
2573 #define PMIC_QI_VM_MODE_SHIFT 7
2574 #define PMIC_RG_VM_STBTD_MASK 0x3
2575 #define PMIC_RG_VM_STBTD_SHIFT 12
2576 #define PMIC_RG_VM_EN_MASK 0x1
2577 #define PMIC_RG_VM_EN_SHIFT 14
2578 #define PMIC_QI_VM_EN_MASK 0x1
2579 #define PMIC_QI_VM_EN_SHIFT 15
2580 #define PMIC_RG_VM_NDIS_EN_MASK 0x1
2581 #define PMIC_RG_VM_NDIS_EN_SHIFT 0
2582 #define PMIC_RG_VM_PLCUR_EN_MASK 0x1
2583 #define PMIC_RG_VM_PLCUR_EN_SHIFT 1
2584 #define PMIC_RG_VM_PLCUR_CAL_MASK 0x3
2585 #define PMIC_RG_VM_PLCUR_CAL_SHIFT 2
2586 #define PMIC_RG_VM_VOSEL_MASK 0x3
2587 #define PMIC_RG_VM_VOSEL_SHIFT 4
2588 #define PMIC_RG_VM_OCFB_MASK 0x1
2589 #define PMIC_RG_VM_OCFB_SHIFT 6
2590 #define PMIC_RG_VM_CAL_MASK 0xF
2591 #define PMIC_RG_VM_CAL_SHIFT 8
2592 #define PMIC_VIO18_LP_SEL_MASK 0x1
2593 #define PMIC_VIO18_LP_SEL_SHIFT 0
2594 #define PMIC_VIO18_LP_MODE_SET_MASK 0x1
2595 #define PMIC_VIO18_LP_MODE_SET_SHIFT 1
2596 #define PMIC_QI_VIO18_MODE_MASK 0x1
2597 #define PMIC_QI_VIO18_MODE_SHIFT 7
2598 #define PMIC_RG_VIO18_STBTD_MASK 0x3
2599 #define PMIC_RG_VIO18_STBTD_SHIFT 12
2600 #define PMIC_RG_VIO18_EN_MASK 0x1
2601 #define PMIC_RG_VIO18_EN_SHIFT 14
2602 #define PMIC_QI_VIO18_EN_MASK 0x1
2603 #define PMIC_QI_VIO18_EN_SHIFT 15
2604 #define PMIC_RG_VIO18_NDIS_EN_MASK 0x1
2605 #define PMIC_RG_VIO18_NDIS_EN_SHIFT 0
2606 #define PMIC_VIO18_ON_CTRL_MASK 0x1
2607 #define PMIC_VIO18_ON_CTRL_SHIFT 1
2608 #define PMIC_RG_VIO18_OCFB_MASK 0x1
2609 #define PMIC_RG_VIO18_OCFB_SHIFT 2
2610 #define PMIC_RG_VIO18_STB_SEL_MASK 0x1
2611 #define PMIC_RG_VIO18_STB_SEL_SHIFT 4
2612 #define PMIC_RG_VIO18_CAL_MASK 0xF
2613 #define PMIC_RG_VIO18_CAL_SHIFT 8
2614 #define PMIC_VCAMD_LP_SEL_MASK 0x1
2615 #define PMIC_VCAMD_LP_SEL_SHIFT 0
2616 #define PMIC_VCAMD_LP_MODE_SET_MASK 0x1
2617 #define PMIC_VCAMD_LP_MODE_SET_SHIFT 1
2618 #define PMIC_QI_VCAMD_MODE_MASK 0x1
2619 #define PMIC_QI_VCAMD_MODE_SHIFT 7
2620 #define PMIC_RG_VCAMD_STBTD_MASK 0x3
2621 #define PMIC_RG_VCAMD_STBTD_SHIFT 12
2622 #define PMIC_RG_VCAMD_EN_MASK 0x1
2623 #define PMIC_RG_VCAMD_EN_SHIFT 14
2624 #define PMIC_QI_VCAMD_EN_MASK 0x1
2625 #define PMIC_QI_VCAMD_EN_SHIFT 15
2626 #define PMIC_RG_VCAMD_NDIS_EN_MASK 0x1
2627 #define PMIC_RG_VCAMD_NDIS_EN_SHIFT 0
2628 #define PMIC_VCAMD_ON_CTRL_MASK 0x1
2629 #define PMIC_VCAMD_ON_CTRL_SHIFT 1
2630 #define PMIC_RG_VCAMD_OCFB_MASK 0x1
2631 #define PMIC_RG_VCAMD_OCFB_SHIFT 2
2632 #define PMIC_RG_VCAMD_STB_SEL_MASK 0x1
2633 #define PMIC_RG_VCAMD_STB_SEL_SHIFT 4
2634 #define PMIC_RG_VCAMD_VOSEL_MASK 0x3
2635 #define PMIC_RG_VCAMD_VOSEL_SHIFT 5
2636 #define PMIC_RG_VCAMD_CAL_MASK 0xF
2637 #define PMIC_RG_VCAMD_CAL_SHIFT 8
2638 #define PMIC_VCAM_IO_LP_SEL_MASK 0x1
2639 #define PMIC_VCAM_IO_LP_SEL_SHIFT 0
2640 #define PMIC_VCAM_IO_LP_MODE_SET_MASK 0x1
2641 #define PMIC_VCAM_IO_LP_MODE_SET_SHIFT 1
2642 #define PMIC_QI_VCAM_IO_MODE_MASK 0x1
2643 #define PMIC_QI_VCAM_IO_MODE_SHIFT 7
2644 #define PMIC_RG_VCAM_IO_STBTD_MASK 0x3
2645 #define PMIC_RG_VCAM_IO_STBTD_SHIFT 12
2646 #define PMIC_RG_VCAM_IO_EN_MASK 0x1
2647 #define PMIC_RG_VCAM_IO_EN_SHIFT 14
2648 #define PMIC_QI_VCAM_IO_EN_MASK 0x1
2649 #define PMIC_QI_VCAM_IO_EN_SHIFT 15
2650 #define PMIC_RG_VCAM_IO_NDIS_EN_MASK 0x1
2651 #define PMIC_RG_VCAM_IO_NDIS_EN_SHIFT 0
2652 #define PMIC_VCAM_IO_ON_CTRL_MASK 0x1
2653 #define PMIC_VCAM_IO_ON_CTRL_SHIFT 1
2654 #define PMIC_RG_VCAM_IO_OCFB_MASK 0x1
2655 #define PMIC_RG_VCAM_IO_OCFB_SHIFT 2
2656 #define PMIC_RG_VCAM_IO_STB_SEL_MASK 0x1
2657 #define PMIC_RG_VCAM_IO_STB_SEL_SHIFT 4
2658 #define PMIC_RG_VCAM_IO_CAL_MASK 0xF
2659 #define PMIC_RG_VCAM_IO_CAL_SHIFT 8
2660 #define PMIC_RG_EFUSE_ADDR_MASK 0x1F
2661 #define PMIC_RG_EFUSE_ADDR_SHIFT 0
2662 #define PMIC_RG_EFUSE_PROG_MASK 0x3F
2663 #define PMIC_RG_EFUSE_PROG_SHIFT 0
2664 #define PMIC_RG_EFUSE_EN_MASK 0x1
2665 #define PMIC_RG_EFUSE_EN_SHIFT 0
2666 #define PMIC_RG_EFUSE_PKEY_MASK 0xFFFF
2667 #define PMIC_RG_EFUSE_PKEY_SHIFT 0
2668 #define PMIC_RG_EFUSE_RD_TRIG_MASK 0x1
2669 #define PMIC_RG_EFUSE_RD_TRIG_SHIFT 0
2670 #define PMIC_RG_EFUSE_PROG_SRC_MASK 0x1
2671 #define PMIC_RG_EFUSE_PROG_SRC_SHIFT 0
2672 #define PMIC_RG_SKIP_EFUSE_OUT_MASK 0x1
2673 #define PMIC_RG_SKIP_EFUSE_OUT_SHIFT 2
2674 #define PMIC_RG_RD_RDY_BYPASS_MASK 0x1
2675 #define PMIC_RG_RD_RDY_BYPASS_SHIFT 4
2676 #define PMIC_RG_EFUSE_RD_ACK_MASK 0x1
2677 #define PMIC_RG_EFUSE_RD_ACK_SHIFT 0
2678 #define PMIC_RG_EFUSE_BUSY_MASK 0x1
2679 #define PMIC_RG_EFUSE_BUSY_SHIFT 2
2680 #define PMIC_RG_EFUSE_VAL_0_15_MASK 0xFFFF
2681 #define PMIC_RG_EFUSE_VAL_0_15_SHIFT 0
2682 #define PMIC_RG_EFUSE_VAL_16_31_MASK 0xFFFF
2683 #define PMIC_RG_EFUSE_VAL_16_31_SHIFT 0
2684 #define PMIC_RG_EFUSE_VAL_32_47_MASK 0xFFFF
2685 #define PMIC_RG_EFUSE_VAL_32_47_SHIFT 0
2686 #define PMIC_RG_EFUSE_VAL_48_63_MASK 0xFFFF
2687 #define PMIC_RG_EFUSE_VAL_48_63_SHIFT 0
2688 #define PMIC_RG_EFUSE_VAL_64_79_MASK 0xFFFF
2689 #define PMIC_RG_EFUSE_VAL_64_79_SHIFT 0
2690 #define PMIC_RG_EFUSE_VAL_80_95_MASK 0xFFFF
2691 #define PMIC_RG_EFUSE_VAL_80_95_SHIFT 0
2692 #define PMIC_RG_EFUSE_VAL_96_111_MASK 0xFFFF
2693 #define PMIC_RG_EFUSE_VAL_96_111_SHIFT 0
2694 #define PMIC_RG_EFUSE_VAL_112_127_MASK 0xFFFF
2695 #define PMIC_RG_EFUSE_VAL_112_127_SHIFT 0
2696 #define PMIC_RG_EFUSE_VAL_128_143_MASK 0xFFFF
2697 #define PMIC_RG_EFUSE_VAL_128_143_SHIFT 0
2698 #define PMIC_RG_EFUSE_VAL_144_159_MASK 0xFFFF
2699 #define PMIC_RG_EFUSE_VAL_144_159_SHIFT 0
2700 #define PMIC_RG_EFUSE_VAL_160_175_MASK 0xFFFF
2701 #define PMIC_RG_EFUSE_VAL_160_175_SHIFT 0
2702 #define PMIC_RG_EFUSE_VAL_176_191_MASK 0xFFFF
2703 #define PMIC_RG_EFUSE_VAL_176_191_SHIFT 0
2704 #define PMIC_RG_EFUSE_DOUT_0_15_MASK 0xFFFF
2705 #define PMIC_RG_EFUSE_DOUT_0_15_SHIFT 0
2706 #define PMIC_RG_EFUSE_DOUT_16_31_MASK 0xFFFF
2707 #define PMIC_RG_EFUSE_DOUT_16_31_SHIFT 0
2708 #define PMIC_RG_EFUSE_DOUT_32_47_MASK 0xFFFF
2709 #define PMIC_RG_EFUSE_DOUT_32_47_SHIFT 0
2710 #define PMIC_RG_EFUSE_DOUT_48_63_MASK 0xFFFF
2711 #define PMIC_RG_EFUSE_DOUT_48_63_SHIFT 0
2712 #define PMIC_RG_EFUSE_DOUT_64_79_MASK 0xFFFF
2713 #define PMIC_RG_EFUSE_DOUT_64_79_SHIFT 0
2714 #define PMIC_RG_EFUSE_DOUT_80_95_MASK 0xFFFF
2715 #define PMIC_RG_EFUSE_DOUT_80_95_SHIFT 0
2716 #define PMIC_RG_EFUSE_DOUT_96_111_MASK 0xFFFF
2717 #define PMIC_RG_EFUSE_DOUT_96_111_SHIFT 0
2718 #define PMIC_RG_EFUSE_DOUT_112_127_MASK 0xFFFF
2719 #define PMIC_RG_EFUSE_DOUT_112_127_SHIFT 0
2720 #define PMIC_RG_EFUSE_DOUT_128_143_MASK 0xFFFF
2721 #define PMIC_RG_EFUSE_DOUT_128_143_SHIFT 0
2722 #define PMIC_RG_EFUSE_DOUT_144_159_MASK 0xFFFF
2723 #define PMIC_RG_EFUSE_DOUT_144_159_SHIFT 0
2724 #define PMIC_RG_EFUSE_DOUT_160_175_MASK 0xFFFF
2725 #define PMIC_RG_EFUSE_DOUT_160_175_SHIFT 0
2726 #define PMIC_RG_EFUSE_DOUT_176_191_MASK 0xFFFF
2727 #define PMIC_RG_EFUSE_DOUT_176_191_SHIFT 0
2728 #define PMIC_RG_OTP_PA_MASK 0x3
2729 #define PMIC_RG_OTP_PA_SHIFT 0
2730 #define PMIC_RG_OTP_PDIN_MASK 0xFF
2731 #define PMIC_RG_OTP_PDIN_SHIFT 0
2732 #define PMIC_RG_OTP_PTM_MASK 0x3
2733 #define PMIC_RG_OTP_PTM_SHIFT 0
2734 #define PMIC_MIX_EOSC32_OPT_MASK 0x3
2735 #define PMIC_MIX_EOSC32_OPT_SHIFT 0
2736 #define PMIC_MIX_XOSC32_STP_CPDTB_MASK 0x1
2737 #define PMIC_MIX_XOSC32_STP_CPDTB_SHIFT 2
2738 #define PMIC_MIX_XOSC32_STP_PWDB_MASK 0x1
2739 #define PMIC_MIX_XOSC32_STP_PWDB_SHIFT 3
2740 #define PMIC_MIX_XOSC32_STP_LPDTB_MASK 0x1
2741 #define PMIC_MIX_XOSC32_STP_LPDTB_SHIFT 4
2742 #define PMIC_MIX_XOSC32_STP_LPDEN_MASK 0x1
2743 #define PMIC_MIX_XOSC32_STP_LPDEN_SHIFT 5
2744 #define PMIC_MIX_XOSC32_STP_LPDRST_MASK 0x1
2745 #define PMIC_MIX_XOSC32_STP_LPDRST_SHIFT 6
2746 #define PMIC_MIX_XOSC32_STP_CALI_MASK 0x1F
2747 #define PMIC_MIX_XOSC32_STP_CALI_SHIFT 7
2748 #define PMIC_STMP_MODE_MASK 0x1
2749 #define PMIC_STMP_MODE_SHIFT 12
2750 #define PMIC_MIX_EOSC32_STP_CHOP_EN_MASK 0x1
2751 #define PMIC_MIX_EOSC32_STP_CHOP_EN_SHIFT 0
2752 #define PMIC_MIX_DCXO_STP_LVSH_EN_MASK 0x1
2753 #define PMIC_MIX_DCXO_STP_LVSH_EN_SHIFT 1
2754 #define PMIC_MIX_PMU_STP_DDLO_VRTC_MASK 0x1
2755 #define PMIC_MIX_PMU_STP_DDLO_VRTC_SHIFT 2
2756 #define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_MASK 0x1
2757 #define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT 3
2758 #define PMIC_MIX_RTC_STP_XOSC32_ENB_MASK 0x1
2759 #define PMIC_MIX_RTC_STP_XOSC32_ENB_SHIFT 4
2760 #define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK 0x1
2761 #define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT 5
2762 #define PMIC_MIX_EOSC32_STP_RSV_MASK 0x3
2763 #define PMIC_MIX_EOSC32_STP_RSV_SHIFT 6
2764 #define PMIC_MIX_EOSC32_VCT_EN_MASK 0x1
2765 #define PMIC_MIX_EOSC32_VCT_EN_SHIFT 8
2766 #define PMIC_MIX_STP_BBWAKEUP_MASK 0x1
2767 #define PMIC_MIX_STP_BBWAKEUP_SHIFT 9
2768 #define PMIC_MIX_STP_RTC_DDLO_MASK 0x1
2769 #define PMIC_MIX_STP_RTC_DDLO_SHIFT 10
2770 #define PMIC_MIX_RTC_XOSC32_ENB_MASK 0x1
2771 #define PMIC_MIX_RTC_XOSC32_ENB_SHIFT 11
2772 #define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_MASK 0x1
2773 #define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT 12
2774 #define PMIC_RG_AUDULL_VCFG_MASK 0xF
2775 #define PMIC_RG_AUDULL_VCFG_SHIFT 0
2776 #define PMIC_RG_AUDULL_VUPG_MASK 0x7
2777 #define PMIC_RG_AUDULL_VUPG_SHIFT 4
2778 #define PMIC_RG_AUDULL_VPWDB_PGA_MASK 0x1
2779 #define PMIC_RG_AUDULL_VPWDB_PGA_SHIFT 7
2780 #define PMIC_RG_AUDULL_VPWDB_ADC_MASK 0x1
2781 #define PMIC_RG_AUDULL_VPWDB_ADC_SHIFT 8
2782 #define PMIC_RG_AUDULL_VADC_DENB_MASK 0x1
2783 #define PMIC_RG_AUDULL_VADC_DENB_SHIFT 9
2784 #define PMIC_RG_AUDULL_VADC_DVREF_CAL_MASK 0x1
2785 #define PMIC_RG_AUDULL_VADC_DVREF_CAL_SHIFT 10
2786 #define PMIC_RG_AUDULL_VREF24_EN_MASK 0x1
2787 #define PMIC_RG_AUDULL_VREF24_EN_SHIFT 11
2788 #define PMIC_RG_AUDULL_VCM14_EN_MASK 0x1
2789 #define PMIC_RG_AUDULL_VCM14_EN_SHIFT 12
2790 #define PMIC_RG_AUDULL_VCMSEL_MASK 0x1
2791 #define PMIC_RG_AUDULL_VCMSEL_SHIFT 13
2792 #define PMIC_RG_AUDULL_CHS_EN_MASK 0x1
2793 #define PMIC_RG_AUDULL_CHS_EN_SHIFT 14
2794 #define PMIC_RG_AUDULL_VCALI_MASK 0x7
2795 #define PMIC_RG_AUDULL_VCALI_SHIFT 0
2796 #define PMIC_RG_AUDULR_VCFG_MASK 0xF
2797 #define PMIC_RG_AUDULR_VCFG_SHIFT 4
2798 #define PMIC_RG_AUDULR_VUPG_MASK 0x7
2799 #define PMIC_RG_AUDULR_VUPG_SHIFT 8
2800 #define PMIC_RG_AUDULR_VPWDB_PGA_MASK 0x1
2801 #define PMIC_RG_AUDULR_VPWDB_PGA_SHIFT 0
2802 #define PMIC_RG_AUDULR_VPWDB_ADC_MASK 0x1
2803 #define PMIC_RG_AUDULR_VPWDB_ADC_SHIFT 1
2804 #define PMIC_RG_AUDULR_VADC_DENB_MASK 0x1
2805 #define PMIC_RG_AUDULR_VADC_DENB_SHIFT 2
2806 #define PMIC_RG_AUDULR_VADC_DVREF_CAL_MASK 0x1
2807 #define PMIC_RG_AUDULR_VADC_DVREF_CAL_SHIFT 3
2808 #define PMIC_RG_AUDULR_VREF24_EN_MASK 0x1
2809 #define PMIC_RG_AUDULR_VREF24_EN_SHIFT 4
2810 #define PMIC_RG_AUDULR_VCM14_EN_MASK 0x1
2811 #define PMIC_RG_AUDULR_VCM14_EN_SHIFT 5
2812 #define PMIC_RG_AUDULR_VCMSEL_MASK 0x1
2813 #define PMIC_RG_AUDULR_VCMSEL_SHIFT 6
2814 #define PMIC_RG_AUDULR_CHS_EN_MASK 0x1
2815 #define PMIC_RG_AUDULR_CHS_EN_SHIFT 7
2816 #define PMIC_RG_AUDULR_VCALI_MASK 0x7
2817 #define PMIC_RG_AUDULR_VCALI_SHIFT 0
2818 #define PMIC_RG_AUD_IGBIAS_CALI_MASK 0x3
2819 #define PMIC_RG_AUD_IGBIAS_CALI_SHIFT 4
2820 #define PMIC_RG_AUD_RSV_MASK 0xFF
2821 #define PMIC_RG_AUD_RSV_SHIFT 8
2822 #define PMIC_RG_AMUTER_MASK 0x1
2823 #define PMIC_RG_AMUTER_SHIFT 0
2824 #define PMIC_RG_AMUTEL_MASK 0x1
2825 #define PMIC_RG_AMUTEL_SHIFT 1
2826 #define PMIC_RG_ADACL_PWDB_MASK 0x1
2827 #define PMIC_RG_ADACL_PWDB_SHIFT 2
2828 #define PMIC_RG_ADACR_PWDB_MASK 0x1
2829 #define PMIC_RG_ADACR_PWDB_SHIFT 3
2830 #define PMIC_RG_ABIAS_PWDB_MASK 0x1
2831 #define PMIC_RG_ABIAS_PWDB_SHIFT 4
2832 #define PMIC_RG_AOUTL_PWDB_MASK 0x1
2833 #define PMIC_RG_AOUTL_PWDB_SHIFT 5
2834 #define PMIC_RG_AOUTR_PWDB_MASK 0x1
2835 #define PMIC_RG_AOUTR_PWDB_SHIFT 6
2836 #define PMIC_RG_ACALI_MASK 0x1F
2837 #define PMIC_RG_ACALI_SHIFT 0
2838 #define PMIC_RG_APGR_MASK 0x7
2839 #define PMIC_RG_APGR_SHIFT 8
2840 #define PMIC_RG_APGL_MASK 0x7
2841 #define PMIC_RG_APGL_SHIFT 12
2842 #define PMIC_RG_ABUF_BIAS_MASK 0x3
2843 #define PMIC_RG_ABUF_BIAS_SHIFT 0
2844 #define PMIC_RG_ABUF_INSHORT_MASK 0x1
2845 #define PMIC_RG_ABUF_INSHORT_SHIFT 2
2846 #define PMIC_RG_AHFMODE_MASK 0x1
2847 #define PMIC_RG_AHFMODE_SHIFT 3
2848 #define PMIC_RG_ADACCK_EN_MASK 0x1
2849 #define PMIC_RG_ADACCK_EN_SHIFT 4
2850 #define PMIC_RG_DACREF_MASK 0x1
2851 #define PMIC_RG_DACREF_SHIFT 5
2852 #define PMIC_RG_ADEPOPX_EN_MASK 0x1
2853 #define PMIC_RG_ADEPOPX_EN_SHIFT 6
2854 #define PMIC_RG_ADEPOPX_MASK 0x3
2855 #define PMIC_RG_ADEPOPX_SHIFT 7
2856 #define PMIC_RG_DEPOP_VCM_EN_MASK 0x1
2857 #define PMIC_RG_DEPOP_VCM_EN_SHIFT 9
2858 #define PMIC_RG_DEPOP_VCMSEL_MASK 0x1
2859 #define PMIC_RG_DEPOP_VCMSEL_SHIFT 10
2860 #define PMIC_RG_DEPOP_CURSEL_MASK 0x3
2861 #define PMIC_RG_DEPOP_CURSEL_SHIFT 11
2862 #define PMIC_RG_CHARGEOPTION_DEPOP_MASK 0x1
2863 #define PMIC_RG_CHARGEOPTION_DEPOP_SHIFT 13
2864 #define PMIC_RG_AVCMGEN_EN_MASK 0x1
2865 #define PMIC_RG_AVCMGEN_EN_SHIFT 14
2866 #define PMIC_RG_AUDDL_VREF24_EN_MASK 0x1
2867 #define PMIC_RG_AUDDL_VREF24_EN_SHIFT 15
2868 #define PMIC_RG_ABIRSV_MASK 0x3
2869 #define PMIC_RG_ABIRSV_SHIFT 0
2870 #define PMIC_RG_VBUF_FLOAT_MASK 0x1
2871 #define PMIC_RG_VBUF_FLOAT_SHIFT 2
2872 #define PMIC_RG_VDPG_MASK 0xF
2873 #define PMIC_RG_VDPG_SHIFT 4
2874 #define PMIC_RG_VBUF_PWDB_MASK 0x1
2875 #define PMIC_RG_VBUF_PWDB_SHIFT 8
2876 #define PMIC_RG_VBUF_BIAS_MASK 0x3
2877 #define PMIC_RG_VBUF_BIAS_SHIFT 9
2878 #define PMIC_RG_VDEPOP_MASK 0x1
2879 #define PMIC_RG_VDEPOP_SHIFT 11
2880 #define PMIC_RG_V2SPK_MASK 0x1
2881 #define PMIC_RG_V2SPK_SHIFT 12
2882 #define PMIC_RG_HSOUTSTBENH_MASK 0x1
2883 #define PMIC_RG_HSOUTSTBENH_SHIFT 13
2884 #define PMIC_AUDTOP_CON8_RSV_0_MASK 0x1
2885 #define PMIC_AUDTOP_CON8_RSV_0_SHIFT 0
2886 #define PMIC_RG_CLKSQ_MONEN_MASK 0x1
2887 #define PMIC_RG_CLKSQ_MONEN_SHIFT 1
2888 #define PMIC_RG_AUDDIGMICEN_MASK 0x1
2889 #define PMIC_RG_AUDDIGMICEN_SHIFT 2
2890 #define PMIC_RG_AUDPWDBMICBIAS_MASK 0x1
2891 #define PMIC_RG_AUDPWDBMICBIAS_SHIFT 3
2892 #define PMIC_RG_AUDDIGMICPDUTY_MASK 0x3
2893 #define PMIC_RG_AUDDIGMICPDUTY_SHIFT 4
2894 #define PMIC_RG_AUDDIGMICNDUTY_MASK 0x3
2895 #define PMIC_RG_AUDDIGMICNDUTY_SHIFT 6
2896 #define PMIC_RG_AUDDIGMICBIAS_MASK 0x3
2897 #define PMIC_RG_AUDDIGMICBIAS_SHIFT 8
2898 #define PMIC_RG_AUDMICBIASVREF_MASK 0x3
2899 #define PMIC_RG_AUDMICBIASVREF_SHIFT 10
2900 #define PMIC_RG_AUDSPAREVMIC_MASK 0xF
2901 #define PMIC_RG_AUDSPAREVMIC_SHIFT 12
2902 #define PMIC_RG_VBIRX_ZCD_EN_MASK 0x1
2903 #define PMIC_RG_VBIRX_ZCD_EN_SHIFT 0
2904 #define PMIC_RG_VBIRX_ZCD_CALI_MASK 0x3
2905 #define PMIC_RG_VBIRX_ZCD_CALI_SHIFT 1
2906 #define PMIC_RG_VBIRX_ZCD_HYS_ENB_MASK 0x1
2907 #define PMIC_RG_VBIRX_ZCD_HYS_ENB_SHIFT 3
2908 #define PMIC_RG_VBIRX_ZCD_STATUS_MASK 0xF
2909 #define PMIC_RG_VBIRX_ZCD_STATUS_SHIFT 4
2910 #define PMIC_RG_ADC_OUT_BATSNS_MASK 0x7FFF
2911 #define PMIC_RG_ADC_OUT_BATSNS_SHIFT 0
2912 #define PMIC_RG_ADC_RDY_BATSNS_MASK 0x1
2913 #define PMIC_RG_ADC_RDY_BATSNS_SHIFT 15
2914 #define PMIC_RG_ADC_OUT_ISENSE_MASK 0x7FFF
2915 #define PMIC_RG_ADC_OUT_ISENSE_SHIFT 0
2916 #define PMIC_RG_ADC_RDY_ISENSE_MASK 0x1
2917 #define PMIC_RG_ADC_RDY_ISENSE_SHIFT 15
2918 #define PMIC_RG_ADC_OUT_VCDT_MASK 0x7FFF
2919 #define PMIC_RG_ADC_OUT_VCDT_SHIFT 0
2920 #define PMIC_RG_ADC_RDY_VCDT_MASK 0x1
2921 #define PMIC_RG_ADC_RDY_VCDT_SHIFT 15
2922 #define PMIC_RG_ADC_OUT_BATON1_MASK 0x7FFF
2923 #define PMIC_RG_ADC_OUT_BATON1_SHIFT 0
2924 #define PMIC_RG_ADC_RDY_BATON1_MASK 0x1
2925 #define PMIC_RG_ADC_RDY_BATON1_SHIFT 15
2926 #define PMIC_RG_ADC_OUT_THR_SENSE1_MASK 0x7FFF
2927 #define PMIC_RG_ADC_OUT_THR_SENSE1_SHIFT 0
2928 #define PMIC_RG_ADC_RDY_THR_SENSE1_MASK 0x1
2929 #define PMIC_RG_ADC_RDY_THR_SENSE1_SHIFT 15
2930 #define PMIC_RG_ADC_OUT_THR_SENSE2_MASK 0x7FFF
2931 #define PMIC_RG_ADC_OUT_THR_SENSE2_SHIFT 0
2932 #define PMIC_RG_ADC_RDY_THR_SENSE2_MASK 0x1
2933 #define PMIC_RG_ADC_RDY_THR_SENSE2_SHIFT 15
2934 #define PMIC_RG_ADC_OUT_BATON2_MASK 0x7FFF
2935 #define PMIC_RG_ADC_OUT_BATON2_SHIFT 0
2936 #define PMIC_RG_ADC_RDY_BATON2_MASK 0x1
2937 #define PMIC_RG_ADC_RDY_BATON2_SHIFT 15
2938 #define PMIC_RG_ADC_OUT_CH5_MASK 0x7FFF
2939 #define PMIC_RG_ADC_OUT_CH5_SHIFT 0
2940 #define PMIC_RG_ADC_RDY_CH5_MASK 0x1
2941 #define PMIC_RG_ADC_RDY_CH5_SHIFT 15
2942 #define PMIC_RG_ADC_OUT_WAKEUP_PCHR_MASK 0x7FFF
2943 #define PMIC_RG_ADC_OUT_WAKEUP_PCHR_SHIFT 0
2944 #define PMIC_RG_ADC_RDY_WAKEUP_PCHR_MASK 0x1
2945 #define PMIC_RG_ADC_RDY_WAKEUP_PCHR_SHIFT 15
2946 #define PMIC_RG_ADC_OUT_WAKEUP_SWCHR_MASK 0x7FFF
2947 #define PMIC_RG_ADC_OUT_WAKEUP_SWCHR_SHIFT 0
2948 #define PMIC_RG_ADC_RDY_WAKEUP_SWCHR_MASK 0x1
2949 #define PMIC_RG_ADC_RDY_WAKEUP_SWCHR_SHIFT 15
2950 #define PMIC_RG_ADC_OUT_LBAT_MASK 0xFFF
2951 #define PMIC_RG_ADC_OUT_LBAT_SHIFT 0
2952 #define PMIC_RG_ADC_RDY_LBAT_MASK 0x1
2953 #define PMIC_RG_ADC_RDY_LBAT_SHIFT 15
2954 #define PMIC_RG_ADC_OUT_CH6_MASK 0x7FFF
2955 #define PMIC_RG_ADC_OUT_CH6_SHIFT 0
2956 #define PMIC_RG_ADC_RDY_CH6_MASK 0x1
2957 #define PMIC_RG_ADC_RDY_CH6_SHIFT 15
2958 #define PMIC_RG_ADC_RDY_GPS_MASK 0x1
2959 #define PMIC_RG_ADC_RDY_GPS_SHIFT 15
2960 #define PMIC_RG_ADC_OUT_GPS_MASK 0xFFFF
2961 #define PMIC_RG_ADC_OUT_GPS_SHIFT 0
2962 #define PMIC_RG_ADC_OUT_GPS_LSB_MASK 0x1
2963 #define PMIC_RG_ADC_OUT_GPS_LSB_SHIFT 15
2964 #define PMIC_RG_ADC_OUT_MD_MASK 0xFFFF
2965 #define PMIC_RG_ADC_OUT_MD_SHIFT 0
2966 #define PMIC_RG_ADC_OUT_MD_LSB_MASK 0x1
2967 #define PMIC_RG_ADC_OUT_MD_LSB_SHIFT 0
2968 #define PMIC_RG_ADC_RDY_MD_MASK 0x1
2969 #define PMIC_RG_ADC_RDY_MD_SHIFT 15
2970 #define PMIC_RG_ADC_OUT_INT_MASK 0x7FFF
2971 #define PMIC_RG_ADC_OUT_INT_SHIFT 0
2972 #define PMIC_RG_ADC_RDY_INT_MASK 0x1
2973 #define PMIC_RG_ADC_RDY_INT_SHIFT 15
2974 #define PMIC_RG_ADC_OUT_RSV1_MASK 0xFFFF
2975 #define PMIC_RG_ADC_OUT_RSV1_SHIFT 0
2976 #define PMIC_RG_ADC_OUT_RSV2_MASK 0xFFFF
2977 #define PMIC_RG_ADC_OUT_RSV2_SHIFT 0
2978 #define PMIC_RG_ADC_OUT_RSV3_MASK 0xFFFF
2979 #define PMIC_RG_ADC_OUT_RSV3_SHIFT 0
2980 #define PMIC_RG_SW_GAIN_TRIM_MASK 0xFFFF
2981 #define PMIC_RG_SW_GAIN_TRIM_SHIFT 0
2982 #define PMIC_RG_SW_OFFSET_TRIM_MASK 0xFFFF
2983 #define PMIC_RG_SW_OFFSET_TRIM_SHIFT 0
2984 #define PMIC_RG_ADC_PWDB_MASK 0x1
2985 #define PMIC_RG_ADC_PWDB_SHIFT 0
2986 #define PMIC_RG_ADC_PWDB_SWCTRL_MASK 0x1
2987 #define PMIC_RG_ADC_PWDB_SWCTRL_SHIFT 2
2988 #define PMIC_RG_ADC_CALI_RATE_MASK 0x3
2989 #define PMIC_RG_ADC_CALI_RATE_SHIFT 4
2990 #define PMIC_RG_ADC_CALI_EN_MASK 0x1
2991 #define PMIC_RG_ADC_CALI_EN_SHIFT 6
2992 #define PMIC_RG_ADC_CALI_FORCE_MASK 0x1
2993 #define PMIC_RG_ADC_CALI_FORCE_SHIFT 7
2994 #define PMIC_RG_ADC_AUTORST_RANGE_MASK 0x3
2995 #define PMIC_RG_ADC_AUTORST_RANGE_SHIFT 8
2996 #define PMIC_RG_ADC_AUTORST_EN_MASK 0x1
2997 #define PMIC_RG_ADC_AUTORST_EN_SHIFT 10
2998 #define PMIC_RG_ADC_LATCH_EDGE_MASK 0x1
2999 #define PMIC_RG_ADC_LATCH_EDGE_SHIFT 11
3000 #define PMIC_RG_ADC_FILTER_ORDER_MASK 0x1
3001 #define PMIC_RG_ADC_FILTER_ORDER_SHIFT 12
3002 #define PMIC_RG_ADC_SWCTRL_EN_MASK 0x1
3003 #define PMIC_RG_ADC_SWCTRL_EN_SHIFT 0
3004 #define PMIC_RG_ADCIN_VSEN_EN_MASK 0x1
3005 #define PMIC_RG_ADCIN_VSEN_EN_SHIFT 1
3006 #define PMIC_RG_ADCIN_VSEN_MUX_EN_MASK 0x1
3007 #define PMIC_RG_ADCIN_VSEN_MUX_EN_SHIFT 2
3008 #define PMIC_RG_ADCIN_VBAT_EN_MASK 0x1
3009 #define PMIC_RG_ADCIN_VBAT_EN_SHIFT 4
3010 #define PMIC_RG_ADCIN_CHR_EN_MASK 0x1
3011 #define PMIC_RG_ADCIN_CHR_EN_SHIFT 5
3012 #define PMIC_RG_AUXADC_CHSEL_MASK 0xF
3013 #define PMIC_RG_AUXADC_CHSEL_SHIFT 12
3014 #define PMIC_RG_LBAT_DEBT_MAX_MASK 0xFF
3015 #define PMIC_RG_LBAT_DEBT_MAX_SHIFT 0
3016 #define PMIC_RG_LBAT_DEBT_MIN_MASK 0xFF
3017 #define PMIC_RG_LBAT_DEBT_MIN_SHIFT 8
3018 #define PMIC_RG_LBAT_DET_PRD_15_0_MASK 0xFFFF
3019 #define PMIC_RG_LBAT_DET_PRD_15_0_SHIFT 0
3020 #define PMIC_RG_LBAT_DET_PRD_19_16_MASK 0xF
3021 #define PMIC_RG_LBAT_DET_PRD_19_16_SHIFT 0
3022 #define PMIC_RG_LBAT_VOLT_MAX_MASK 0xFFF
3023 #define PMIC_RG_LBAT_VOLT_MAX_SHIFT 0
3024 #define PMIC_RG_LBAT_IRQ_EN_MAX_MASK 0x1
3025 #define PMIC_RG_LBAT_IRQ_EN_MAX_SHIFT 12
3026 #define PMIC_RG_LBAT_EN_MAX_MASK 0x1
3027 #define PMIC_RG_LBAT_EN_MAX_SHIFT 13
3028 #define PMIC_RG_LBAT_MAX_IRQ_B_MASK 0x1
3029 #define PMIC_RG_LBAT_MAX_IRQ_B_SHIFT 15
3030 #define PMIC_RG_LBAT_VOLT_MIN_MASK 0xFFF
3031 #define PMIC_RG_LBAT_VOLT_MIN_SHIFT 0
3032 #define PMIC_RG_LBAT_IRQ_EN_MIN_MASK 0x1
3033 #define PMIC_RG_LBAT_IRQ_EN_MIN_SHIFT 12
3034 #define PMIC_RG_LBAT_EN_MIN_MASK 0x1
3035 #define PMIC_RG_LBAT_EN_MIN_SHIFT 13
3036 #define PMIC_RG_LBAT_MIN_IRQ_B_MASK 0x1
3037 #define PMIC_RG_LBAT_MIN_IRQ_B_SHIFT 15
3038 #define PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX_MASK 0x1FF
3039 #define PMIC_RG_LBAT_DEBOUNCE_COUNT_MAX_SHIFT 0
3040 #define PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN_MASK 0x1FF
3041 #define PMIC_RG_LBAT_DEBOUNCE_COUNT_MIN_SHIFT 0
3042 #define PMIC_RG_DATA_REUSE_SEL_MASK 0x3
3043 #define PMIC_RG_DATA_REUSE_SEL_SHIFT 3
3044 #define PMIC_RG_AUXADC_BIST_ENB_MASK 0x1
3045 #define PMIC_RG_AUXADC_BIST_ENB_SHIFT 5
3046 #define PMIC_RG_OSR_MASK 0x7
3047 #define PMIC_RG_OSR_SHIFT 10
3048 #define PMIC_RG_OSR_GPS_MASK 0x7
3049 #define PMIC_RG_OSR_GPS_SHIFT 13
3050 #define PMIC_RG_ADC_TRIM_CH7_SEL_MASK 0x3
3051 #define PMIC_RG_ADC_TRIM_CH7_SEL_SHIFT 0
3052 #define PMIC_RG_ADC_TRIM_CH6_SEL_MASK 0x3
3053 #define PMIC_RG_ADC_TRIM_CH6_SEL_SHIFT 2
3054 #define PMIC_RG_ADC_TRIM_CH5_SEL_MASK 0x3
3055 #define PMIC_RG_ADC_TRIM_CH5_SEL_SHIFT 4
3056 #define PMIC_RG_ADC_TRIM_CH4_SEL_MASK 0x3
3057 #define PMIC_RG_ADC_TRIM_CH4_SEL_SHIFT 6
3058 #define PMIC_RG_ADC_TRIM_CH3_SEL_MASK 0x3
3059 #define PMIC_RG_ADC_TRIM_CH3_SEL_SHIFT 8
3060 #define PMIC_RG_ADC_TRIM_CH2_SEL_MASK 0x3
3061 #define PMIC_RG_ADC_TRIM_CH2_SEL_SHIFT 10
3062 #define PMIC_RG_ADC_TRIM_CH0_SEL_MASK 0x3
3063 #define PMIC_RG_ADC_TRIM_CH0_SEL_SHIFT 14
3064 #define PMIC_RG_VBUF_CALEN_MASK 0x1
3065 #define PMIC_RG_VBUF_CALEN_SHIFT 0
3066 #define PMIC_RG_VBUF_EXTEN_MASK 0x1
3067 #define PMIC_RG_VBUF_EXTEN_SHIFT 1
3068 #define PMIC_RG_VBUF_BYP_MASK 0x1
3069 #define PMIC_RG_VBUF_BYP_SHIFT 2
3070 #define PMIC_RG_VBUF_EN_MASK 0x1
3071 #define PMIC_RG_VBUF_EN_SHIFT 4
3072 #define PMIC_RG_SOURCE_LBAT_SEL_MASK 0x1
3073 #define PMIC_RG_SOURCE_LBAT_SEL_SHIFT 15
3074 #define PMIC_EFUSE_GAIN_CH0_TRIM_MASK 0x1FF
3075 #define PMIC_EFUSE_GAIN_CH0_TRIM_SHIFT 0
3076 #define PMIC_EFUSE_OFFSET_CH0_TRIM_MASK 0xFF
3077 #define PMIC_EFUSE_OFFSET_CH0_TRIM_SHIFT 0
3078 #define PMIC_EFUSE_GAIN_CH4_TRIM_MASK 0x1FF
3079 #define PMIC_EFUSE_GAIN_CH4_TRIM_SHIFT 0
3080 #define PMIC_EFUSE_OFFSET_CH4_TRIM_MASK 0xFF
3081 #define PMIC_EFUSE_OFFSET_CH4_TRIM_SHIFT 0
3082 #define PMIC_EFUSE_GAIN_CH7_TRIM_MASK 0xFFFF
3083 #define PMIC_EFUSE_GAIN_CH7_TRIM_SHIFT 0
3084 #define PMIC_EFUSE_OFFSET_CH7_TRIM_MASK 0xFFFF
3085 #define PMIC_EFUSE_OFFSET_CH7_TRIM_SHIFT 0
3086 #define PMIC_RG_ADC_IBIAS_MASK 0x3
3087 #define PMIC_RG_ADC_IBIAS_SHIFT 0
3088 #define PMIC_RG_ADC_RST_MASK 0x1
3089 #define PMIC_RG_ADC_RST_SHIFT 2
3090 #define PMIC_RG_ADC_LP_EN_MASK 0x1
3091 #define PMIC_RG_ADC_LP_EN_SHIFT 3
3092 #define PMIC_RG_ADC_INPUT_SHORT_MASK 0x1
3093 #define PMIC_RG_ADC_INPUT_SHORT_SHIFT 4
3094 #define PMIC_RG_ADC_CHOPPER_EN_MASK 0x1
3095 #define PMIC_RG_ADC_CHOPPER_EN_SHIFT 5
3096 #define PMIC_RG_VPWDB_ADC_MASK 0x1
3097 #define PMIC_RG_VPWDB_ADC_SHIFT 6
3098 #define PMIC_RG_VREF18_EN_MASK 0x1
3099 #define PMIC_RG_VREF18_EN_SHIFT 7
3100 #define PMIC_RG_ADC_CHS_SEL_MASK 0x3
3101 #define PMIC_RG_ADC_CHS_SEL_SHIFT 8
3102 #define PMIC_RG_ADC_DVREF_CAL_MASK 0x1
3103 #define PMIC_RG_ADC_DVREF_CAL_SHIFT 14
3104 #define PMIC_RG_ADC_DENB_MASK 0x1
3105 #define PMIC_RG_ADC_DENB_SHIFT 15
3106 #define PMIC_RG_ADC_SLEEP_MODE_EN_MASK 0x1
3107 #define PMIC_RG_ADC_SLEEP_MODE_EN_SHIFT 0
3108 #define PMIC_RG_ADC_GPS_STATUS_MASK 0x1
3109 #define PMIC_RG_ADC_GPS_STATUS_SHIFT 1
3110 #define PMIC_RG_ADC_RSV_BIT_MASK 0x1
3111 #define PMIC_RG_ADC_RSV_BIT_SHIFT 2
3112 #define PMIC_RG_ADC_TEST_MODE_EN_MASK 0x1
3113 #define PMIC_RG_ADC_TEST_MODE_EN_SHIFT 3
3114 #define PMIC_RG_ADC_TEST_OUT_SEL_MASK 0x1
3115 #define PMIC_RG_ADC_TEST_OUT_SEL_SHIFT 4
3116 #define PMIC_RG_DECI_BYPASS_EN_MASK 0x1
3117 #define PMIC_RG_DECI_BYPASS_EN_SHIFT 5
3118 #define PMIC_RG_ADC_CLK_AON_MASK 0x1
3119 #define PMIC_RG_ADC_CLK_AON_SHIFT 7
3120 #define PMIC_RG_ADC_DECI_FORCE_MASK 0x1
3121 #define PMIC_RG_ADC_DECI_FORCE_SHIFT 12
3122 #define PMIC_RG_ADC_DECI_GDLY_MASK 0x3
3123 #define PMIC_RG_ADC_DECI_GDLY_SHIFT 14
3124 #define PMIC_RG_MD_RQST_MASK 0x1
3125 #define PMIC_RG_MD_RQST_SHIFT 15
3126 #define PMIC_RG_GPS_RQST_MASK 0x1
3127 #define PMIC_RG_GPS_RQST_SHIFT 15
3128 #define PMIC_RG_AP_RQST_LIST_MASK 0x1FF
3129 #define PMIC_RG_AP_RQST_LIST_SHIFT 0
3130 #define PMIC_RG_AP_RQST_MASK 0x1
3131 #define PMIC_RG_AP_RQST_SHIFT 15
3132 #define PMIC_RG_AP_RQST_LIST_RSV_MASK 0xFF
3133 #define PMIC_RG_AP_RQST_LIST_RSV_SHIFT 0
3134 #define PMIC_RG_ADC_OUT_TRIM_ENB_MASK 0x1
3135 #define PMIC_RG_ADC_OUT_TRIM_ENB_SHIFT 1
3136 #define PMIC_RG_ADC_TRIM_COMP_MASK 0x1
3137 #define PMIC_RG_ADC_TRIM_COMP_SHIFT 2
3138 #define PMIC_RG_ADC_2S_COMP_ENB_MASK 0x1
3139 #define PMIC_RG_ADC_2S_COMP_ENB_SHIFT 3
3140 #define PMIC_RG_CIC_OUT_RAW_MASK 0x1
3141 #define PMIC_RG_CIC_OUT_RAW_SHIFT 4
3142 #define PMIC_RG_DATA_SKIP_ENB_MASK 0x1
3143 #define PMIC_RG_DATA_SKIP_ENB_SHIFT 5
3144 #define PMIC_RG_DATA_SKIP_NUM_MASK 0x3
3145 #define PMIC_RG_DATA_SKIP_NUM_SHIFT 6
3146 #define PMIC_RG_ADC_REV_MASK 0xFF
3147 #define PMIC_RG_ADC_REV_SHIFT 0
3148 #define PMIC_RG_DECI_GDLY_SEL_MODE_MASK 0x1
3149 #define PMIC_RG_DECI_GDLY_SEL_MODE_SHIFT 0
3150 #define PMIC_RG_DECI_GDLY_VREF18_SELB_MASK 0x1
3151 #define PMIC_RG_DECI_GDLY_VREF18_SELB_SHIFT 1
3152 #define PMIC_RG_ADC_RSV1_MASK 0x1FFF
3153 #define PMIC_RG_ADC_RSV1_SHIFT 2
3154 #define PMIC_RG_VREF18_ENB_MASK 0x1
3155 #define PMIC_RG_VREF18_ENB_SHIFT 15
3156 #define PMIC_RG_ADC_MD_STATUS_MASK 0x1
3157 #define PMIC_RG_ADC_MD_STATUS_SHIFT 0
3158 #define PMIC_RG_ADC_RSV2_MASK 0x3FFF
3159 #define PMIC_RG_ADC_RSV2_SHIFT 1
3160 #define PMIC_RG_VREF18_ENB_MD_MASK 0x1
3161 #define PMIC_RG_VREF18_ENB_MD_SHIFT 15
3162 #define PMIC_RG_AUDACCDETVTHCAL_MASK 0x3
3163 #define PMIC_RG_AUDACCDETVTHCAL_SHIFT 0
3164 #define PMIC_RG_AUDACCDETSWCTRL_MASK 0x7
3165 #define PMIC_RG_AUDACCDETSWCTRL_SHIFT 4
3166 #define PMIC_RG_AUDACCDETTVDET_MASK 0x1
3167 #define PMIC_RG_AUDACCDETTVDET_SHIFT 8
3168 #define PMIC_RG_AUDACCDETVIN1PULLLOW_MASK 0x1
3169 #define PMIC_RG_AUDACCDETVIN1PULLLOW_SHIFT 9
3170 #define PMIC_AUDACCDETAUXADCSWCTRL_MASK 0x1
3171 #define PMIC_AUDACCDETAUXADCSWCTRL_SHIFT 10
3172 #define PMIC_AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1
3173 #define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 11
3174 #define PMIC_RG_AUDACCDETRSV_MASK 0xF
3175 #define PMIC_RG_AUDACCDETRSV_SHIFT 12
3176 #define PMIC_ACCDET_EN_MASK 0x1
3177 #define PMIC_ACCDET_EN_SHIFT 0
3178 #define PMIC_ACCDET_SEQ_INIT_MASK 0x1
3179 #define PMIC_ACCDET_SEQ_INIT_SHIFT 1
3180 #define PMIC_ACCDET_CMP_PWM_EN_MASK 0x1
3181 #define PMIC_ACCDET_CMP_PWM_EN_SHIFT 0
3182 #define PMIC_ACCDET_VTH_PWM_EN_MASK 0x1
3183 #define PMIC_ACCDET_VTH_PWM_EN_SHIFT 1
3184 #define PMIC_ACCDET_MBIAS_PWM_EN_MASK 0x1
3185 #define PMIC_ACCDET_MBIAS_PWM_EN_SHIFT 2
3186 #define PMIC_ACCDET_CMP_PWM_IDLE_MASK 0x1
3187 #define PMIC_ACCDET_CMP_PWM_IDLE_SHIFT 4
3188 #define PMIC_ACCDET_VTH_PWM_IDLE_MASK 0x1
3189 #define PMIC_ACCDET_VTH_PWM_IDLE_SHIFT 5
3190 #define PMIC_ACCDET_MBIAS_PWM_IDLE_MASK 0x1
3191 #define PMIC_ACCDET_MBIAS_PWM_IDLE_SHIFT 6
3192 #define PMIC_ACCDET_PWM_WIDTH_MASK 0xFFFF
3193 #define PMIC_ACCDET_PWM_WIDTH_SHIFT 0
3194 #define PMIC_ACCDET_PWM_THRESH_MASK 0xFFFF
3195 #define PMIC_ACCDET_PWM_THRESH_SHIFT 0
3196 #define PMIC_ACCDET_RISE_DELAY_MASK 0x7FFF
3197 #define PMIC_ACCDET_RISE_DELAY_SHIFT 0
3198 #define PMIC_ACCDET_FALL_DELAY_MASK 0x1
3199 #define PMIC_ACCDET_FALL_DELAY_SHIFT 15
3200 #define PMIC_ACCDET_DEBOUNCE0_MASK 0xFFFF
3201 #define PMIC_ACCDET_DEBOUNCE0_SHIFT 0
3202 #define PMIC_ACCDET_DEBOUNCE1_MASK 0xFFFF
3203 #define PMIC_ACCDET_DEBOUNCE1_SHIFT 0
3204 #define PMIC_ACCDET_DEBOUNCE2_MASK 0xFFFF
3205 #define PMIC_ACCDET_DEBOUNCE2_SHIFT 0
3206 #define PMIC_ACCDET_DEBOUNCE3_MASK 0xFFFF
3207 #define PMIC_ACCDET_DEBOUNCE3_SHIFT 0
3208 #define PMIC_ACCDET_IVAL_CUR_IN_MASK 0x3
3209 #define PMIC_ACCDET_IVAL_CUR_IN_SHIFT 0
3210 #define PMIC_ACCDET_IVAL_SAM_IN_MASK 0x3
3211 #define PMIC_ACCDET_IVAL_SAM_IN_SHIFT 4
3212 #define PMIC_ACCDET_IVAL_MEM_IN_MASK 0x3
3213 #define PMIC_ACCDET_IVAL_MEM_IN_SHIFT 8
3214 #define PMIC_ACCDET_IVAL_SEL_MASK 0x1
3215 #define PMIC_ACCDET_IVAL_SEL_SHIFT 15
3216 #define PMIC_ACCDET_IRQ_MASK 0x1
3217 #define PMIC_ACCDET_IRQ_SHIFT 0
3218 #define PMIC_ACCDET_IRQ_CLR_MASK 0x1
3219 #define PMIC_ACCDET_IRQ_CLR_SHIFT 8
3220 #define PMIC_ACCDET_TEST_MODE0_MASK 0x1
3221 #define PMIC_ACCDET_TEST_MODE0_SHIFT 0
3222 #define PMIC_ACCDET_TEST_MODE1_MASK 0x1
3223 #define PMIC_ACCDET_TEST_MODE1_SHIFT 1
3224 #define PMIC_ACCDET_TEST_MODE2_MASK 0x1
3225 #define PMIC_ACCDET_TEST_MODE2_SHIFT 2
3226 #define PMIC_ACCDET_TEST_MODE3_MASK 0x1
3227 #define PMIC_ACCDET_TEST_MODE3_SHIFT 3
3228 #define PMIC_ACCDET_TEST_MODE4_MASK 0x1
3229 #define PMIC_ACCDET_TEST_MODE4_SHIFT 4
3230 #define PMIC_ACCDET_TEST_MODE5_MASK 0x1
3231 #define PMIC_ACCDET_TEST_MODE5_SHIFT 5
3232 #define PMIC_ACCDET_PWM_SEL_MASK 0x3
3233 #define PMIC_ACCDET_PWM_SEL_SHIFT 6
3234 #define PMIC_ACCDET_IN_SW_MASK 0x3
3235 #define PMIC_ACCDET_IN_SW_SHIFT 8
3236 #define PMIC_ACCDET_CMP_EN_SW_MASK 0x1
3237 #define PMIC_ACCDET_CMP_EN_SW_SHIFT 12
3238 #define PMIC_ACCDET_VTH_EN_SW_MASK 0x1
3239 #define PMIC_ACCDET_VTH_EN_SW_SHIFT 13
3240 #define PMIC_ACCDET_MBIAS_EN_SW_MASK 0x1
3241 #define PMIC_ACCDET_MBIAS_EN_SW_SHIFT 14
3242 #define PMIC_ACCDET_PWM_EN_SW_MASK 0x1
3243 #define PMIC_ACCDET_PWM_EN_SW_SHIFT 15
3244 #define PMIC_ACCDET_IN_MASK 0x3
3245 #define PMIC_ACCDET_IN_SHIFT 0
3246 #define PMIC_ACCDET_CUR_IN_MASK 0x3
3247 #define PMIC_ACCDET_CUR_IN_SHIFT 2
3248 #define PMIC_ACCDET_SAM_IN_MASK 0x3
3249 #define PMIC_ACCDET_SAM_IN_SHIFT 4
3250 #define PMIC_ACCDET_MEM_IN_MASK 0x3
3251 #define PMIC_ACCDET_MEM_IN_SHIFT 6
3252 #define PMIC_ACCDET_STATE_MASK 0x7
3253 #define PMIC_ACCDET_STATE_SHIFT 8
3254 #define PMIC_ACCDET_MBIAS_CLK_MASK 0x1
3255 #define PMIC_ACCDET_MBIAS_CLK_SHIFT 12
3256 #define PMIC_ACCDET_VTH_CLK_MASK 0x1
3257 #define PMIC_ACCDET_VTH_CLK_SHIFT 13
3258 #define PMIC_ACCDET_CMP_CLK_MASK 0x1
3259 #define PMIC_ACCDET_CMP_CLK_SHIFT 14
3260 #define PMIC_DA_AUDACCDETAUXADCSWCTRL_MASK 0x1
3261 #define PMIC_DA_AUDACCDETAUXADCSWCTRL_SHIFT 15
3262 #define PMIC_ACCDET_CUR_DEB_MASK 0xFFFF
3263 #define PMIC_ACCDET_CUR_DEB_SHIFT 0
3264 #define PMIC_ACCDET_RSV_CON0_MASK 0xFFFF
3265 #define PMIC_ACCDET_RSV_CON0_SHIFT 0
3266 #define PMIC_ACCDET_RSV_CON1_MASK 0xFFFF
3267 #define PMIC_ACCDET_RSV_CON1_SHIFT 0
3270 #endif // _MT6323_PMIC_UPMU_HW_H_
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