arch/arm/mach-mt8127/include/mach/reg_accdet_mt6397.h

   1 #include <mach/mt_reg_base.h>
   2 //Register address define
   3 //#define PMIC_RESERVE_CON2 0xF0007500
   4
   5 #define ACCDET_BASE                 0x00000002
   6 #define TOP_RST_ACCDET           0x0114
   7 #define TOP_RST_ACCDET_SET               0x0116
   8 #define TOP_RST_ACCDET_CLR               0x0118
   9
  10 #define INT_CON_ACCDET           0x017E
  11 #define INT_CON_ACCDET_SET               0x0180  //6320 Design
  12 #define INT_CON_ACCDET_CLR       0x0182
  13
  14 #define INT_STATUS_ACCDET        0x0186
  15
  16 //6320 clock register
  17 #define TOP_CKPDN                0x0102
  18 #define TOP_CKPDN_SET            0x0104
  19 #define TOP_CKPDN_CLR            0x0106
  20
  21
  22 #define ACCDET_RSV               ACCDET_BASE + 0x0582
  23
  24 #define ACCDET_CTRL              ACCDET_BASE + 0x0584
  25 #define ACCDET_STATE_SWCTRL      ACCDET_BASE + 0x0586
  26 #define ACCDET_PWM_WIDTH                 ACCDET_BASE + 0x0588
  27 #define ACCDET_PWM_THRESH                ACCDET_BASE + 0x058A
  28 #define ACCDET_EN_DELAY_NUM      ACCDET_BASE + 0x058c
  29 #define ACCDET_DEBOUNCE0         ACCDET_BASE + 0x058E
  30 #define ACCDET_DEBOUNCE1         ACCDET_BASE + 0x0590
  31 #define ACCDET_DEBOUNCE2         ACCDET_BASE + 0x0592
  32 #define ACCDET_DEBOUNCE3         ACCDET_BASE + 0x0594
  33
  34 #define ACCDET_DEFAULT_STATE_RG  ACCDET_BASE + 0x0596
  35
  36
  37 #define ACCDET_IRQ_STS           ACCDET_BASE + 0x0598
  38
  39 #define ACCDET_CONTROL_RG        ACCDET_BASE + 0x059A
  40 #define ACCDET_STATE_RG          ACCDET_BASE + 0x059C
  41
  42 #define ACCDET_CUR_DEB                   ACCDET_BASE + 0x059E
  43 #define ACCDET_RSV_CON0                  ACCDET_BASE + 0x05A0
  44 #define ACCDET_RSV_CON1                  ACCDET_BASE + 0x05A2
  45
  46
  47 /*
  48 #define ACCDET_FSM_STATE         ACCDET_BASE + 0x50
  49 #define ACCDET_CURR_DEBDS        ACCDET_BASE + 0x54
  50 #define ACCDET_TV_START_LINE0    ACCDET_BASE + 0x58
  51 #define ACCDET_TV_END_LINE0      ACCDET_BASE + 0x5C
  52 #define ACCDET_TV_START_LINE1    ACCDET_BASE + 0x60
  53 #define ACCDET_TV_END_LINE1      ACCDET_BASE + 0x64
  54 #define ACCDET_TV_PRE_LINE       ACCDET_BASE + 0x68
  55 #define ACCDET_TV_START_PXL      ACCDET_BASE + 0x6C
  56 #define ACCDET_TV_END_PXL        ACCDET_BASE + 0x70
  57 #define ACCDET_TV_EN_DELAY_NUM   ACCDET_BASE + 0x74
  58 #define ACCDET_TV_DIV_RATE       ACCDET_BASE + 0x78
  59 */
  60
  61
  62
  63
  64 //Register value define
  65
  66
  67 #define ACCDET_CTRL_EN           (1<<0)
  68 #define ACCDET_MIC_PWM_IDLE      (1<<6)
  69 #define ACCDET_VTH_PWM_IDLE      (1<<5)
  70 #define ACCDET_CMP_PWM_IDLE      (1<<4)
  71 #define ACCDET_CMP_EN            (1<<0)
  72 #define ACCDET_VTH_EN            (1<<1)
  73 #define ACCDET_MICBIA_EN         (1<<2)
  74
  75
  76 #define ACCDET_ENABLE                    (1<<0)
  77 #define ACCDET_DISABLE                   (0<<0)
  78
  79 #define ACCDET_RESET_SET             (1<<4)
  80 #define ACCDET_RESET_CLR             (1<<4)
  81
  82 #define IRQ_CLR_BIT           0x100
  83 #define IRQ_STATUS_BIT        (1<<0)
  84
  85 #define RG_ACCDET_IRQ_SET        (1<<2)
  86 #define RG_ACCDET_IRQ_CLR        (1<<2)
  87 #define RG_ACCDET_IRQ_STATUS_CLR (1<<2)
  88
  89 //CLOCK
  90 #define RG_ACCDET_CLK_SET        (1<<14)
  91 #define RG_ACCDET_CLK_CLR        (1<<14)
  92
  93
  94 #define ACCDET_PWM_EN_SW         (1<<15)
  95 #define ACCDET_MIC_EN_SW         (1<<15)
  96 #define ACCDET_VTH_EN_SW         (1<<15)
  97 #define ACCDET_CMP_EN_SW         (1<<15)
  98
  99 #define ACCDET_SWCTRL_EN         0x07
 100
 101 #define ACCDET_IN_SW             0x10
 102
 103 #define ACCDET_PWM_SEL_CMP       0x00
 104 #define ACCDET_PWM_SEL_VTH       0x01
 105 #define ACCDET_PWM_SEL_MIC       0x10
 106 #define ACCDET_PWM_SEL_SW        0x11
 107 #define ACCDET_SWCTRL_IDLE_EN    (0x07<<4)
 108
 109
 110 #define ACCDET_TEST_MODE5_ACCDET_IN_GPI        (1<<5)
 111 #define ACCDET_TEST_MODE4_ACCDET_IN_SW        (1<<4)
 112 #define ACCDET_TEST_MODE3_MIC_SW        (1<<3)
 113 #define ACCDET_TEST_MODE2_VTH_SW        (1<<2)
 114 #define ACCDET_TEST_MODE1_CMP_SW        (1<<1)
 115 #define ACCDET_TEST_MODE0_GPI        (1<<0)
 116
 117 #define ACCDET_1V9_MODE_ON        0x10B0
 118 #define ACCDET_1V9_MODE_OFF       0x1090
 119 #define ACCDET_2V8_MODE_ON        0x01
 120 #define ACCDET_2V8_MODE_OFF       0x5090
 121
 122
 123 //#define ACCDET_DEFVAL_SEL        (1<<15)
 124
 125