arch/arm/mach-mt8127/include/mach/pmu_v7.h

   1 #ifndef _PMU_v7_H
   2 #define _PMU_V7_H
   3 #include<linux/threads.h>
   4
   5 /*
   6  * The cycle counter is ARMV7_CYCLE_COUNTER.
   7  * The first event counter is ARMV7_COUNTER0.
   8  * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
   9  */
  10 #define NUMBER_OF_EVENT                 4
  11 #define ARMV7_COUNTER0                  0
  12 #define ARMV7_COUNTER_LAST              (NUMBER_OF_EVENT - 1)
  13 #define ARMV7_CYCLE_COUNTER             (ARMV7_COUNTER_LAST + 1)
  14 #define NUMBER_OF_CPU  NR_CPUS
  15
  16 enum mtk_arm_perf_pmu_ids {
  17     ARM_PMU_ID_CA8 = 0,
  18     ARM_PMU_ID_CA9,
  19     ARM_PMU_ID_CA5,
  20     ARM_PMU_ID_CA15,
  21     ARM_PMU_ID_CA7,
  22     ARM_NUM_PMU_ID,
  23 };
  24
  25 #define EVENT_MASK  0x00000001
  26
  27 struct pmu_data{
  28     u32 cnt_val[NUMBER_OF_CPU][NUMBER_OF_EVENT + 1];  //Number of event counters + cycle event counter
  29     u32 overflow[NUMBER_OF_CPU];
  30 };
  31
  32 struct pmu_cfg{
  33     u32 event_cfg[NUMBER_OF_EVENT];
  34 };
  35
  36 struct arm_pmu {
  37     enum mtk_arm_perf_pmu_ids id;
  38     const char      *name;
  39     //irqreturn_t     (*handle_irq)(int irq_num, void *dev);
  40     void            (*enable)(void);
  41     //void            (*disable)(void);
  42     void             (*read_counter)(void);
  43     void            (*start)(void);
  44     void            (*stop)(void);
  45     void            (*reset)(void);
  46     int             num_events;
  47     struct pmu_data perf_data;
  48     struct pmu_cfg  perf_cfg;
  49     int                         multicore;
  50 };
  51
  52 enum mtk_armv7_perf_types {
  53     ARMV7_PMNC_SW_INCR              = 0x00,
  54     ARMV7_IFETCH_MISS               = 0x01,
  55     ARMV7_ITLB_MISS                 = 0x02,
  56     ARMV7_DCACHE_REFILL             = 0x03, /* L1 */
  57     ARMV7_DCACHE_ACCESS             = 0x04, /* L1 */
  58     ARMV7_DTLB_REFILL               = 0x05,
  59     ARMV7_DREAD                     = 0x06,
  60     ARMV7_DWRITE                    = 0x07,
  61     ARMV7_INSTR_EXECUTED            = 0x08,
  62     ARMV7_EXC_TAKEN                 = 0x09,
  63     ARMV7_EXC_EXECUTED              = 0x0A,
  64     ARMV7_CID_WRITE                 = 0x0B,
  65     /* ARMV7_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
  66      * It counts:
  67      *  - all branch instructions,
  68      *  - instructions that explicitly write the PC,
  69      *  - exception generating instructions.
  70      */
  71     ARMV7_PC_WRITE                  = 0x0C,
  72     ARMV7_PC_IMM_BRANCH             = 0x0D,
  73     ARMV7_PC_PROC_RETURN            = 0x0E,
  74     ARMV7_UNALIGNED_ACCESS          = 0x0F,
  75
  76     /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
  77     ARMV7_PC_BRANCH_MIS_PRED        = 0x10,
  78     ARMV7_CLOCK_CYCLES              = 0x11,
  79     ARMV7_PC_BRANCH_PRED            = 0x12,
  80     ARMV7_MEM_ACCESS                = 0x13,
  81     ARMV7_L1_ICACHE_ACCESS          = 0x14,
  82     ARMV7_L1_DCACHE_WB              = 0x15,
  83     ARMV7_L2_DCACHE_ACCESS          = 0x16,
  84     ARMV7_L2_DCACHE_REFILL          = 0x17,
  85     ARMV7_L2_DCACHE_WB              = 0x18,
  86     ARMV7_BUS_ACCESS                = 0x19,
  87     ARMV7_MEMORY_ERROR              = 0x1A,
  88     ARMV7_INSTR_SPEC                = 0x1B,
  89     ARMV7_TTBR_WRITE                = 0x1C,
  90     ARMV7_BUS_CYCLES                = 0x1D,
  91
  92     ARMV7_CPU_CYCLES                = 0xFF
  93 };
  94 /* ARMv7 Cortex-A9 specific event types */
  95 enum armv7_a9_perf_types {
  96     ARMV7_JAVA_HW_BYTECODE_EXEC     = 0x40,
  97     ARMV7_JAVA_SW_BYTECODE_EXEC     = 0x41,
  98     ARMV7_JAZELLE_BRANCH_EXEC       = 0x42,
  99
 100     ARMV7_COHERENT_LINE_MISS        = 0x50,
 101     ARMV7_COHERENT_LINE_HIT         = 0x51,
 102
 103     ARMV7_ICACHE_DEP_STALL_CYCLES   = 0x60,
 104     ARMV7_DCACHE_DEP_STALL_CYCLES   = 0x61,
 105     ARMV7_TLB_MISS_DEP_STALL_CYCLES = 0x62,
 106     ARMV7_STREX_EXECUTED_PASSED     = 0x63,
 107     ARMV7_STREX_EXECUTED_FAILED     = 0x64,
 108     ARMV7_DATA_EVICTION             = 0x65,
 109     ARMV7_ISSUE_STAGE_NO_INST       = 0x66,
 110     ARMV7_ISSUE_STAGE_EMPTY         = 0x67,
 111     ARMV7_INST_OUT_OF_RENAME_STAGE  = 0x68,
 112
 113     ARMV7_PREDICTABLE_FUNCT_RETURNS = 0x6E,
 114
 115     ARMV7_MAIN_UNIT_EXECUTED_INST   = 0x70,
 116     ARMV7_SECOND_UNIT_EXECUTED_INST = 0x71,
 117     ARMV7_LD_ST_UNIT_EXECUTED_INST  = 0x72,
 118     ARMV7_FP_EXECUTED_INST          = 0x73,
 119     ARMV7_NEON_EXECUTED_INST        = 0x74,
 120
 121     ARMV7_PLD_FULL_DEP_STALL_CYCLES = 0x80,
 122     ARMV7_DATA_WR_DEP_STALL_CYCLES  = 0x81,
 123     ARMV7_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
 124     ARMV7_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
 125     ARMV7_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
 126     ARMV7_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
 127     ARMV7_DMB_DEP_STALL_CYCLES      = 0x86,
 128
 129     ARMV7_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
 130     ARMV7_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
 131
 132     ARMV7_ISB_INST                  = 0x90,
 133     ARMV7_DSB_INST                  = 0x91,
 134     ARMV7_DMB_INST                  = 0x92,
 135     ARMV7_EXT_INTERRUPTS            = 0x93,
 136
 137     ARMV7_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
 138     ARMV7_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
 139     ARMV7_PLE_FIFO_FLUSH            = 0xA2,
 140     ARMV7_PLE_RQST_COMPLETED        = 0xA3,
 141     ARMV7_PLE_FIFO_OVERFLOW         = 0xA4,
 142     ARMV7_PLE_RQST_PROG             = 0xA5
 143 };
 144
 145 int register_pmu(struct arm_pmu **p_pmu);
 146 void unregister_pmu(struct arm_pmu **p_pmu);
 147
 148
 149
 150
 151 /*
 152  * Per-CPU PMNC: config reg
 153  */
 154 #define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
 155 #define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
 156 #define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
 157 #define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
 158 #define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
 159 #define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
 160 #define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
 161 #define ARMV7_PMNC_N_MASK       0x1f
 162 #define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
 163
 164 /*
 165  * Available counters
 166  */
 167 #define ARMV7_CNT0              0       /* First event counter */
 168 #define ARMV7_CCNT              31      /* Cycle counter */
 169
 170 /* Event to low level counters mapping */
 171 #define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
 172
 173 /*
 174  * CNTENS: counters enable reg
 175  */
 176 #define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
 177 #define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
 178
 179 /*
 180  * CNTENC: counters disable reg
 181  */
 182 #define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
 183 #define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
 184
 185 /*
 186  * INTENS: counters overflow interrupt enable reg
 187  */
 188 #define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
 189 #define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
 190
 191 /*
 192  * INTENC: counters overflow interrupt disable reg
 193  */
 194 #define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
 195 #define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
 196
 197 /*
 198  * EVTSEL: Event selection reg
 199  */
 200 #define ARMV7_EVTSEL_MASK       0xff            /* Mask for writable bits */
 201
 202 /*
 203  * SELECT: Counter selection reg
 204  */
 205 #define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
 206
 207 /*
 208  * FLAG: counters overflow flag status reg
 209  */
 210 #define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
 211 #define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
 212 #define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
 213 #define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
 214
 215 #endif