3 #ifndef MTK_EMMC_SUPPORT
4 #ifdef MTK_SPI_NAND_SUPPORT
5 #include <mach/snand_device_list.h>
7 #include <mach/nand_device_define.h>
11 /*******************************************************************************
12 * NFI Register Definition
13 *******************************************************************************/
15 #define NFI_CNFG_REG16 ((volatile P_U16)(NFI_BASE+0x0000))
16 #define NFI_PAGEFMT_REG16 ((volatile P_U16)(NFI_BASE+0x0004))
17 #define NFI_CON_REG16 ((volatile P_U32)(NFI_BASE+0x0008))
18 #define NFI_ACCCON_REG32 ((volatile P_U32)(NFI_BASE+0x000C))
19 #define NFI_INTR_EN_REG16 ((volatile P_U16)(NFI_BASE+0x0010))
20 #define NFI_INTR_REG16 ((volatile P_U16)(NFI_BASE+0x0014))
22 #define NFI_CMD_REG16 ((volatile P_U16)(NFI_BASE+0x0020))
24 #define NFI_ADDRNOB_REG16 ((volatile P_U16)(NFI_BASE+0x0030))
25 #define NFI_COLADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0034))
26 #define NFI_ROWADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0038))
28 #define NFI_STRDATA_REG16 ((volatile P_U16)(NFI_BASE+0x0040))
29 #define NFI_CNRNB_REG16 ((volatile P_U16)(NFI_BASE+0x0044))
32 #define NFI_DATAW_REG32 ((volatile P_U32)(NFI_BASE+0x0050))
33 #define NFI_DATAR_REG32 ((volatile P_U32)(NFI_BASE+0x0054))
34 #define NFI_PIO_DIRDY_REG16 ((volatile P_U16)(NFI_BASE+0x0058))
36 #define NFI_STA_REG32 ((volatile P_U32)(NFI_BASE+0x0060))
37 #define NFI_FIFOSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0064))
38 //#define NFI_LOCKSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0068))
40 #define NFI_ADDRCNTR_REG16 ((volatile P_U32)(NFI_BASE+0x0070))
42 #define NFI_STRADDR_REG32 ((volatile P_U32)(NFI_BASE+0x0080))
43 #define NFI_BYTELEN_REG16 ((volatile P_U32)(NFI_BASE+0x0084))
45 #define NFI_CSEL_REG16 ((volatile P_U16)(NFI_BASE+0x0090))
46 #define NFI_IOCON_REG16 ((volatile P_U16)(NFI_BASE+0x0094))
48 #define NFI_FDM0L_REG32 ((volatile P_U32)(NFI_BASE+0x00A0))
49 #define NFI_FDM0M_REG32 ((volatile P_U32)(NFI_BASE+0x00A4))
51 #define NFI_LOCK_REG16 ((volatile P_U16)(NFI_BASE+0x0100))
52 #define NFI_LOCKCON_REG32 ((volatile P_U32)(NFI_BASE+0x0104))
53 #define NFI_LOCKANOB_REG16 ((volatile P_U16)(NFI_BASE+0x0108))
54 #define NFI_LOCK00ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0110))
55 #define NFI_LOCK00FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0114))
56 #define NFI_LOCK01ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0118))
57 #define NFI_LOCK01FMT_REG32 ((volatile P_U32)(NFI_BASE+0x011C))
58 #define NFI_LOCK02ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0120))
59 #define NFI_LOCK02FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0124))
60 #define NFI_LOCK03ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0128))
61 #define NFI_LOCK03FMT_REG32 ((volatile P_U32)(NFI_BASE+0x012C))
62 #define NFI_LOCK04ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0130))
63 #define NFI_LOCK04FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0134))
64 #define NFI_LOCK05ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0138))
65 #define NFI_LOCK05FMT_REG32 ((volatile P_U32)(NFI_BASE+0x013C))
66 #define NFI_LOCK06ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0140))
67 #define NFI_LOCK06FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0144))
68 #define NFI_LOCK07ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0148))
69 #define NFI_LOCK07FMT_REG32 ((volatile P_U32)(NFI_BASE+0x014C))
70 #define NFI_LOCK08ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0150))
71 #define NFI_LOCK08FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0154))
72 #define NFI_LOCK09ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0158))
73 #define NFI_LOCK09FMT_REG32 ((volatile P_U32)(NFI_BASE+0x015C))
74 #define NFI_LOCK10ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0160))
75 #define NFI_LOCK10FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0164))
76 #define NFI_LOCK11ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0168))
77 #define NFI_LOCK11FMT_REG32 ((volatile P_U32)(NFI_BASE+0x016C))
78 #define NFI_LOCK12ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0170))
79 #define NFI_LOCK12FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0174))
80 #define NFI_LOCK13ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0178))
81 #define NFI_LOCK13FMT_REG32 ((volatile P_U32)(NFI_BASE+0x017C))
82 #define NFI_LOCK14ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0180))
83 #define NFI_LOCK14FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0184))
84 #define NFI_LOCK15ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0188))
85 #define NFI_LOCK15FMT_REG32 ((volatile P_U32)(NFI_BASE+0x018C))
87 #define NFI_FIFODATA0_REG32 ((volatile P_U32)(NFI_BASE+0x0190))
88 #define NFI_FIFODATA1_REG32 ((volatile P_U32)(NFI_BASE+0x0194))
89 #define NFI_FIFODATA2_REG32 ((volatile P_U32)(NFI_BASE+0x0198))
90 #define NFI_FIFODATA3_REG32 ((volatile P_U32)(NFI_BASE+0x019C))
91 #define NFI_DEBUG_CON1_REG16 ((volatile P_U16)(NFI_BASE+0x0220))
92 #define NFI_MASTERSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0224))
93 #define NFI_MASTERRST_REG32 ((volatile P_U16)(NFI_BASE+0x0228))
94 #define NFI_RANDOM_CNFG_REG32 ((volatile P_U32)(NFI_BASE+0x0238))
95 #define NFI_ENMPTY_THRESH_REG32 ((volatile P_U32)(NFI_BASE+0x023C))
96 #define NFI_NAND_TYPE_CNFG_REG32 ((volatile P_U32)(NFI_BASE+0x0240))
97 #define NFI_ACCCON1_REG3 ((volatile P_U32)(NFI_BASE+0x0244))
98 #define NFI_DLYCTRL_REG32 ((volatile P_U32)(NFI_BASE+0x0248))
100 #define NFI_RANDOM_ENSEED01_TS_REG32 ((volatile P_U32)(NFI_BASE+0x024C))
101 #define NFI_RANDOM_ENSEED02_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0250))
102 #define NFI_RANDOM_ENSEED03_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0254))
103 #define NFI_RANDOM_ENSEED04_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0258))
104 #define NFI_RANDOM_ENSEED05_TS_REG32 ((volatile P_U32)(NFI_BASE+0x025C))
105 #define NFI_RANDOM_ENSEED06_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0260))
107 #define NFI_RANDOM_DESEED01_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0264))
108 #define NFI_RANDOM_DESEED02_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0268))
109 #define NFI_RANDOM_DESEED03_TS_REG32 ((volatile P_U32)(NFI_BASE+0x026C))
110 #define NFI_RANDOM_DESEED04_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0270))
111 #define NFI_RANDOM_DESEED05_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0274))
112 #define NFI_RANDOM_DESEED06_TS_REG32 ((volatile P_U32)(NFI_BASE+0x0278))
116 /*******************************************************************************
117 * NFI Register Field Definition
118 *******************************************************************************/
121 #define DEBUG_CON1_BYPASS_MASTER_EN (0x8000)
123 #define MASTERSTA_MASK (0x0FFF)
126 #define CNFG_AHB (0x0001)
127 #define CNFG_READ_EN (0x0002)
128 #define CNFG_DMA_BURST_EN (0x0004)
129 #define CNFG_BYTE_RW (0x0040)
130 #define CNFG_HW_ECC_EN (0x0100)
131 #define CNFG_AUTO_FMT_EN (0x0200)
132 #define CNFG_OP_IDLE (0x0000)
133 #define CNFG_OP_READ (0x1000)
134 #define CNFG_OP_SRD (0x2000)
135 #define CNFG_OP_PRGM (0x3000)
136 #define CNFG_OP_ERASE (0x4000)
137 #define CNFG_OP_RESET (0x5000)
138 #define CNFG_OP_CUST (0x6000)
139 #define CNFG_OP_MODE_MASK (0x7000)
140 #define CNFG_OP_MODE_SHIFT (12)
143 #define PAGEFMT_512 (0x0000)
144 #define PAGEFMT_2K (0x0001)
145 #define PAGEFMT_4K (0x0002)
146 #define PAGEFMT_2K_1KS (0x0000)
147 #define PAGEFMT_4K_1KS (0x0001)
148 #define PAGEFMT_8K_1KS (0x0002)
149 #define PAGEFMT_16K_1KS (0x0003)
151 #define PAGEFMT_PAGE_MASK (0x0003)
152 #define PAGEFMT_SEC_SEL_512 (0x0004)
153 #define PAGEFMT_SECTOR_SEL (0x0004)
155 #define PAGEFMT_DBYTE_EN (0x0008)
157 #define PAGEFMT_SPARE_16 (0x0000)
158 #define PAGEFMT_SPARE_26 (0x0001)
159 #define PAGEFMT_SPARE_27 (0x0002)
160 #define PAGEFMT_SPARE_28 (0x0003)
161 #define PAGEFMT_SPARE_32 (0x0004)
162 #define PAGEFMT_SPARE_36 (0x0005)
163 #define PAGEFMT_SPARE_40 (0x0006)
164 #define PAGEFMT_SPARE_44 (0x0007)
165 #define PAGEFMT_SPARE_48 (0x0008)
166 #define PAGEFMT_SPARE_49 (0x0009)
167 #define PAGEFMT_SPARE_50 (0x000A)
168 #define PAGEFMT_SPARE_51 (0x000B)
169 #define PAGEFMT_SPARE_52 (0x000C)
170 #define PAGEFMT_SPARE_62 (0x000D)
171 #define PAGEFMT_SPARE_63 (0x000E)
172 #define PAGEFMT_SPARE_64 (0x000F)
174 #define PAGEFMT_SPARE_32_1KS (0x0000)
175 #define PAGEFMT_SPARE_52_1KS (0x0001)
176 #define PAGEFMT_SPARE_54_1KS (0x0002)
177 #define PAGEFMT_SPARE_56_1KS (0x0003)
178 #define PAGEFMT_SPARE_64_1KS (0x0004)
179 #define PAGEFMT_SPARE_72_1KS (0x0005)
180 #define PAGEFMT_SPARE_80_1KS (0x0006)
181 #define PAGEFMT_SPARE_88_1KS (0x0007)
182 #define PAGEFMT_SPARE_96_1KS (0x0008)
183 #define PAGEFMT_SPARE_98_1KS (0x0009)
184 #define PAGEFMT_SPARE_100_1KS (0x000A)
185 #define PAGEFMT_SPARE_102_1KS (0x000B)
186 #define PAGEFMT_SPARE_104_1KS (0x000C)
187 #define PAGEFMT_SPARE_124_1KS (0x000D)
188 #define PAGEFMT_SPARE_126_1KS (0x000E)
189 #define PAGEFMT_SPARE_128_1KS (0x000F)
191 #define PAGEFMT_SPARE_MASK (0x00F0)
192 #define PAGEFMT_SPARE_SHIFT (4)
194 #define PAGEFMT_FDM_MASK (0x0F00)
195 #define PAGEFMT_FDM_SHIFT (8)
197 #define PAGEFMT_FDM_ECC_MASK (0xF000)
198 #define PAGEFMT_FDM_ECC_SHIFT (12)
201 #define CON_FIFO_FLUSH (0x0001)
202 #define CON_NFI_RST (0x0002)
203 #define CON_NFI_SRD (0x0010)
205 #define CON_NFI_NOB_MASK (0x00E0)
206 #define CON_NFI_NOB_SHIFT (5)
208 #define CON_NFI_BRD (0x0100)
209 #define CON_NFI_BWR (0x0200)
211 #define CON_NFI_SEC_MASK (0x1F000)
212 #define CON_NFI_SEC_SHIFT (12)
215 #define SEED_MASK (0x7FFF)
216 #define EN_SEED_SHIFT (0x1)
217 #define DE_SEED_SHIFT (0x11)
218 #define CNFG_RAN_SEC (0x0010)
219 #define CNFG_RAN_SEL (0x0020)
220 #define RAN_CNFG_ENCODE_EN (1 << 0)
221 #define RAN_CNFG_DECODE_EN (1 << 16)
222 #define RAN_CNFG_ENCODE_SEED(x) (((U32)(x) & SEED_MASK) << 1)
223 #define RAN_CNFG_DECODE_SEED(x) (((U32)(x) & SEED_MASK) << 17)
227 #define ACCCON_SETTING ()
230 #define INTR_RD_DONE_EN (0x0001)
231 #define INTR_WR_DONE_EN (0x0002)
232 #define INTR_RST_DONE_EN (0x0004)
233 #define INTR_ERASE_DONE_EN (0x0008)
234 #define INTR_BSY_RTN_EN (0x0010)
235 #define INTR_ACC_LOCK_EN (0x0020)
236 #define INTR_AHB_DONE_EN (0x0040)
237 #define INTR_ALL_INTR_DE (0x0000)
238 #define INTR_ALL_INTR_EN (0x007F)
239 #define INTR_CUSTOM_PROG_DONE_INTR_EN (0x00000080)
240 #define INTR_AUTO_PROG_DONE_INTR_EN (0x00000200)
241 #define INTR_AUTO_BLKER_INTR_EN (0x00000800)
244 #define INTR_RD_DONE (0x0001)
245 #define INTR_WR_DONE (0x0002)
246 #define INTR_RST_DONE (0x0004)
247 #define INTR_ERASE_DONE (0x0008)
248 #define INTR_BSY_RTN (0x0010)
249 #define INTR_ACC_LOCK (0x0020)
250 #define INTR_AHB_DONE (0x0040)
253 #define ADDR_COL_NOB_MASK (0x0007)
254 #define ADDR_COL_NOB_SHIFT (0)
255 #define ADDR_ROW_NOB_MASK (0x0070)
256 #define ADDR_ROW_NOB_SHIFT (4)
259 #define STA_READ_EMPTY (0x00001000)
260 #define STA_ACC_LOCK (0x00000010)
261 #define STA_CMD_STATE (0x00000001)
262 #define STA_ADDR_STATE (0x00000002)
263 #define STA_DATAR_STATE (0x00000004)
264 #define STA_DATAW_STATE (0x00000008)
265 #define STA_FLASH_MACRO_IDLE (0x00000020)
268 #define STA_NAND_FSM_MASK (0x3F800000)
269 #define STA_NAND_BUSY (0x00000100)
270 #define STA_NAND_BUSY_RETURN (0x00000200)
271 #define STA_NFI_FSM_MASK (0x000F0000)
272 #define STA_NFI_OP_MASK (0x0000000F)
275 #define FIFO_RD_EMPTY (0x0040)
276 #define FIFO_RD_FULL (0x0080)
277 #define FIFO_WR_FULL (0x8000)
278 #define FIFO_WR_EMPTY (0x4000)
279 #define FIFO_RD_REMAIN(x) (0x1F&(x))
280 #define FIFO_WR_REMAIN(x) ((0x1F00&(x))>>8)
283 #define ADDRCNTR_CNTR(x) ((0x1F000&(x))>>12)
284 #define ADDRCNTR_OFFSET(x) (0x0FFF&(x))
287 #define NFI_LOCK_ON (0x0001)
290 #define PROG_RADD_NOB_MASK (0x7000)
291 #define PROG_RADD_NOB_SHIFT (12)
292 #define PROG_CADD_NOB_MASK (0x0300)
293 #define PROG_CADD_NOB_SHIFT (8)
294 #define ERASE_RADD_NOB_MASK (0x0070)
295 #define ERASE_RADD_NOB_SHIFT (4)
296 #define ERASE_CADD_NOB_MASK (0x0007)
297 #define ERASE_CADD_NOB_SHIFT (0)
300 #define HWDCM_SWCON_ON (1<<1)
301 #define WBUF_EN (1<<2)
302 #define NFI_BYPASS 0x8000
303 #define ECC_BYPASS 0x1
305 #define PAD_MACRO_RST 2
308 /*******************************************************************************
309 * ECC Register Definition
310 *******************************************************************************/
312 #define ECC_ENCCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0000))
313 #define ECC_ENCCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0004))
314 #define ECC_ENCDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0008))
315 #define ECC_ENCIDLE_REG32 ((volatile P_U32)(NFIECC_BASE+0x000C))
316 #define ECC_ENCPAR0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0010))
317 #define ECC_ENCPAR1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0014))
318 #define ECC_ENCPAR2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0018))
319 #define ECC_ENCPAR3_REG32 ((volatile P_U32)(NFIECC_BASE+0x001C))
320 #define ECC_ENCPAR4_REG32 ((volatile P_U32)(NFIECC_BASE+0x0020))
321 #define ECC_ENCPAR5_REG32 ((volatile P_U32)(NFIECC_BASE+0x0024))
322 #define ECC_ENCPAR6_REG32 ((volatile P_U32)(NFIECC_BASE+0x0028))
323 #define ECC_ENCSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x007C))
324 #define ECC_ENCIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0080))
325 #define ECC_ENCIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x0084))
327 #define ECC_DECCON_REG16 ((volatile P_U16)(NFIECC_BASE+0x0100))
328 #define ECC_DECCNFG_REG32 ((volatile P_U32)(NFIECC_BASE+0x0104))
329 #define ECC_DECDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0108))
330 #define ECC_DECIDLE_REG16 ((volatile P_U16)(NFIECC_BASE+0x010C))
331 #define ECC_DECFER_REG16 ((volatile P_U16)(NFIECC_BASE+0x0110))
332 #define ECC_DECENUM0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0114))
333 #define ECC_DECENUM1_REG32 ((volatile P_U32)(NFIECC_BASE+0x0118))
334 #define ECC_DECDONE_REG16 ((volatile P_U16)(NFIECC_BASE+0x0124))
335 #define ECC_DECEL0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0128))
336 #define ECC_DECEL1_REG32 ((volatile P_U32)(NFIECC_BASE+0x012C))
337 #define ECC_DECEL2_REG32 ((volatile P_U32)(NFIECC_BASE+0x0130))
338 #define ECC_DECEL3_REG32 ((volatile P_U32)(NFIECC_BASE+0x0134))
339 #define ECC_DECEL4_REG32 ((volatile P_U32)(NFIECC_BASE+0x0138))
340 #define ECC_DECEL5_REG32 ((volatile P_U32)(NFIECC_BASE+0x013C))
341 #define ECC_DECEL6_REG32 ((volatile P_U32)(NFIECC_BASE+0x0140))
342 #define ECC_DECEL7_REG32 ((volatile P_U32)(NFIECC_BASE+0x0144))
343 #define ECC_DECIRQEN_REG16 ((volatile P_U16)(NFIECC_BASE+0x0200))
344 #define ECC_DECIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x0204))
345 //#define ECC_FDMADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0148))
346 #define ECC_DECFSM_REG32 ((volatile P_U32)(NFIECC_BASE+0x0208))
347 #define ECC_BYPASS_REG32 ((volatile P_U32)(NFIECC_BASE+0x020C))
349 //#define ECC_SYNSTA_REG32 ((volatile P_U32)(NFIECC_BASE+0x0150))
350 //#define ECC_DECNFIDI_REG32 ((volatile P_U32)(NFIECC_BASE+0x0154))
351 //#define ECC_SYN0_REG32 ((volatile P_U32)(NFIECC_BASE+0x0158))
353 /*******************************************************************************
354 * ECC register definition
355 *******************************************************************************/
357 #define ECC_PARITY_BIT (14)
359 #define ENC_EN (0x0001)
360 #define ENC_DE (0x0000)
363 #define ECC_CNFG_ECC4 (0x0000)
364 #define ECC_CNFG_ECC6 (0x0001)
365 #define ECC_CNFG_ECC8 (0x0002)
366 #define ECC_CNFG_ECC10 (0x0003)
367 #define ECC_CNFG_ECC12 (0x0004)
368 #define ECC_CNFG_ECC14 (0x0005)
369 #define ECC_CNFG_ECC16 (0x0006)
370 #define ECC_CNFG_ECC18 (0x0007)
371 #define ECC_CNFG_ECC20 (0x0008)
372 #define ECC_CNFG_ECC22 (0x0009)
373 #define ECC_CNFG_ECC24 (0x000A)
374 #define ECC_CNFG_ECC28 (0x000B)
375 #define ECC_CNFG_ECC32 (0x000C)
376 #define ECC_CNFG_ECC36 (0x000D)
377 #define ECC_CNFG_ECC40 (0x000E)
378 #define ECC_CNFG_ECC44 (0x000F)
379 #define ECC_CNFG_ECC48 (0x0010)
380 #define ECC_CNFG_ECC52 (0x0011)
381 #define ECC_CNFG_ECC56 (0x0012)
382 #define ECC_CNFG_ECC60 (0x0013)
384 #define ECC_CNFG_ECC_MASK (0x0000001F)
386 #define ENC_CNFG_NFI (0x0020)
387 #define ENC_CNFG_MODE_MASK (0x0060)
389 #define ENC_CNFG_META6 (0x10300000)
390 #define ENC_CNFG_META8 (0x10400000)
392 #define ENC_CNFG_MSG_MASK (0x3FFF0000)
393 #define ENC_CNFG_MSG_SHIFT (0x10)
396 #define ENC_IDLE (0x0001)
399 #define STA_FSM (0x0007)
400 #define STA_COUNT_PS (0xFF10)
401 #define STA_COUNT_MS (0x3FFF0000)
404 #define ENC_IRQEN (0x0001)
407 #define ENC_IRQSTA (0x0001)
410 #define DEC_EN (0x0001)
411 #define DEC_DE (0x0000)
414 #define DEC_CNFG_ECC4 (0x0000)
415 //#define DEC_CNFG_ECC6 (0x0001)
416 //#define DEC_CNFG_ECC12 (0x0002)
418 #define DEC_CNFG_DEC_MODE_MASK (0x0060)
419 #define DEC_CNFG_AHB (0x0000)
420 #define DEC_CNFG_NFI (0x0020)
421 //#define DEC_CNFG_META6 (0x10300000)
422 //#define DEC_CNFG_META8 (0x10400000)
424 #define DEC_CNFG_FER (0x01000)
425 #define DEC_CNFG_EL (0x02000)
426 #define DEC_CNFG_CORRECT (0x03000)
427 #define DEC_CNFG_TYPE_MASK (0x03000)
429 #define DEC_CNFG_EMPTY_EN (0x80000000)
430 #define DEC_CNFG_DEC_BURST_EN (0x00000100)
432 #define DEC_CNFG_CODE_MASK (0x3FFF0000)
433 #define DEC_CNFG_CODE_SHIFT (0x10)
436 #define DEC_IDLE (0x0001)
439 #define DEC_FER0 (0x0001)
440 #define DEC_FER1 (0x0002)
441 #define DEC_FER2 (0x0004)
442 #define DEC_FER3 (0x0008)
443 #define DEC_FER4 (0x0010)
444 #define DEC_FER5 (0x0020)
445 #define DEC_FER6 (0x0040)
446 #define DEC_FER7 (0x0080)
449 #define ERR_NUM0 (0x0000003F)
450 #define ERR_NUM1 (0x00003F00)
451 #define ERR_NUM2 (0x003F0000)
452 #define ERR_NUM3 (0x3F000000)
453 #define ERR_NUM4 (0x0000003F)
454 #define ERR_NUM5 (0x00003F00)
455 #define ERR_NUM6 (0x003F0000)
456 #define ERR_NUM7 (0x3F000000)
459 #define DEC_DONE0 (0x0001)
460 #define DEC_DONE1 (0x0002)
461 #define DEC_DONE2 (0x0004)
462 #define DEC_DONE3 (0x0008)
463 #define DEC_DONE4 (0x0010)
464 #define DEC_DONE5 (0x0020)
465 #define DEC_DONE6 (0x0040)
466 #define DEC_DONE7 (0x0080)
469 #define DEC_IRQEN (0x0001)
472 #define DEC_IRQSTA (0x0001)
474 #define CHIPVER_ECO_1 (0x8a00)
475 #define CHIPVER_ECO_2 (0x8a01)
480 #define ECC_DECFSM_IDLE (0x01010101)
481 /*******************************************************************************
482 * Data Structure Definition
483 *******************************************************************************/
484 struct nfi_saved_para
488 u16 sNFI_PAGEFMT_REG16
;
490 u32 sNFI_ACCCON_REG32
;
491 u16 sNFI_INTR_EN_REG16
;
492 u16 sNFI_IOCON_REG16
;
494 u16 sNFI_DEBUG_CON1_REG16
;
496 u32 sECC_ENCCNFG_REG32
;
497 u32 sECC_FDMADDR_REG32
;
498 u32 sECC_DECCNFG_REG32
;
501 u32 sNFI_DLYCTRL_REG32
;
502 u32 sPERI_NFI_MAC_CTRL
;
503 u32 sNFI_NAND_TYPE_CNFG_REG32
;
504 u32 sNFI_ACCCON1_REG32
;
506 struct mtk_nand_pl_test
508 suseconds_t last_erase_time
;
509 suseconds_t last_prog_time
;
510 u32 nand_program_wdt_enable
;
511 u32 nand_erase_wdt_enable
;
515 struct nand_chip nand_chip
;
517 struct mtk_nand_host_hw
*hw
;
519 struct nfi_saved_para saved_para
;
521 #ifdef CONFIG_PWR_LOSS_MTK_SPOH
522 struct mtk_nand_pl_test pl
;
524 struct mtd_erase_region_info erase_region
[20];
541 * ECC layout control structure. Exported to userspace for
542 * diagnosis and to allow creation of raw images
543 struct nand_ecclayout {
547 struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
550 #define __DEBUG_NAND 1 /* Debug information on/off */
552 /* Debug message event */
553 #define DBG_EVT_NONE 0x00000000 /* No event */
554 #define DBG_EVT_INIT 0x00000001 /* Initial related event */
555 #define DBG_EVT_VERIFY 0x00000002 /* Verify buffer related event */
556 #define DBG_EVT_PERFORMANCE 0x00000004 /* Performance related event */
557 #define DBG_EVT_READ 0x00000008 /* Read related event */
558 #define DBG_EVT_WRITE 0x00000010 /* Write related event */
559 #define DBG_EVT_ERASE 0x00000020 /* Erase related event */
560 #define DBG_EVT_BADBLOCK 0x00000040 /* Badblock related event */
561 #define DBG_EVT_POWERCTL 0x00000080 /* Suspend/Resume related event */
562 #define DBG_EVT_OTP 0x00000100 /* OTP related event */
564 #define DBG_EVT_ALL 0xffffffff
566 #define DBG_EVT_MASK (DBG_EVT_INIT|DBG_EVT_POWERCTL)
569 #define MSG(evt, fmt, args...) \
571 if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
572 printk(fmt, ##args); \
576 #define MSG_FUNC_ENTRY(f) MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
578 #define MSG(evt, fmt, args...) do{}while(0)
579 #define MSG_FUNC_ENTRY(f) do{}while(0)