arch/arm/mach-mt8127/include/mach/mtk_mau.h

   1 #ifndef _MTK_MAU_H_
   2 #define _MTK_MAU_H_
   3
   4
   5
   6 #define MTK_MAU_MAJOR_NUMBER 190
   7
   8 #define MTK_IOW(num, dtype)     _IOW('O', num, dtype)
   9 #define MTK_IOR(num, dtype)     _IOR('O', num, dtype)
  10 #define MTK_IOWR(num, dtype)    _IOWR('O', num, dtype)
  11 #define MTK_IO(num)             _IO('O', num)
  12
  13 // --------------------------------------------------------------------------
  14 #define MTK_CONFIG_MM_MAU       MTK_IOW(10, unsigned long)
  15 #define MTK_CONFIG_MM_MPU       MTK_IOW(11, unsigned long)
  16 /*
  17 typedef enum {
  18     MAU0_MASK_RSV_0 = 0,
  19     MAU0_MASK_DEFECT,
  20     MAU0_MASK_JPE_ENC,
  21     MAU0_MASK_ROT_DMA0_OUT0,
  22     MAU0_MASK_ROT_DMA1_OUT0,
  23     MAU0_MASK_TV_ROT_OUT0,
  24     MAU0_MASK_CAM,
  25     MAU0_MASK_FD0,
  26     MAU0_MASK_FD2,
  27     MAU0_MASK_JPG_DEC0,
  28     MAU0_MASK_R_DMA0_OUT0,
  29     MAU0_MASK_R_DMA0_OUT1,
  30     MAU0_MASK_R_DMA0_OUT2,
  31     MAU0_MASK_FD1,
  32     MAU0_MASK_PCA,
  33     MAU0_MASK_JPGDMA_R,  // 15
  34     MAU0_MASK_JPGDMA_W,  // 15
  35     MAU0_MASK_ROT_DMA0_OUT1,// 15
  36     MAU0_MASK_ROT_DMA0_OUT2,// 15
  37     MAU0_MASK_ROT_DMA1_OUT1,// 15
  38     MAU0_MASK_ROT_DMA1_OUT2,// 15
  39     MAU0_MASK_TV_ROT_OUT1,  // no use
  40     MAU0_MASK_TV_ROT_OUT2,  // no use
  41     MAU0_MASK_R_DMA0_OUT3, // no use
  42     MAU0_MASK_JPG_DEC1,    // 15
  43
  44     MAU0_MASK_ALL,
  45
  46     MAU1_MASK_RSV_0 = MAU0_MASK_ALL,
  47     MAU1_MASK_OVL_MSK,    // 1
  48     MAU1_MASK_OVL_DCP,
  49     MAU1_MASK_DPI,
  50     MAU1_MASK_ROT_DMA2_OUT0,
  51     MAU1_MASK_ROT_DMA3_OUT0,
  52     MAU1_MASK_ROT_DMA4_OUT0,
  53     MAU1_MASK_TVC,
  54     MAU1_MASK_LCD_R,
  55     MAU1_MASK_LCD_W,
  56     MAU1_MASK_R_DMA1_OUT0,
  57     MAU1_MASK_R_DMA1_OUT1,
  58     MAU1_MASK_R_DMA1_OUT2,
  59     MAU1_MASK_SPI,
  60     MAU1_MASK_RSV_14,
  61     MAU1_MASK_DPI_HWC,
  62     MAU1_MASK_VRZ,            //16
  63     MAU1_MASK_ROT_DMA2_OUT1,  //20
  64     MAU1_MASK_ROT_DMA2_OUT2,  //20
  65     MAU1_MASK_ROT_DMA3_OUT1,  //20
  66     MAU1_MASK_ROT_DMA3_OUT2,  //20
  67     MAU1_MASK_ROT_DMA4_OUT1,  //20
  68     MAU1_MASK_ROT_DMA4_OUT2,  //20
  69     MAU1_MASK_GREQ_BLKW,      //17
  70     MAU1_MASK_GREQ_BLKR,      //18
  71     MAU1_MASK_TVC_PFH,      //no use
  72     MAU1_MASK_TVC_RESZ,      //no use
  73     MAU1_MASK_R_DMA1_OUT3,      //no use
  74     MAU1_MASK_EIS,          //19
  75
  76     MAU1_MASK_ALL,
  77
  78     MAU2_MASK_RSV_0 = MAU1_MASK_ALL,
  79     MAU2_MASK_VENC_MC,
  80     MAU2_MASK_VENC_BSDMA,
  81     MAU2_MASK_VENC_MVQP,
  82     MAU2_MASK_VENC_DMA,
  83     MAU2_MASK_VENC_REC,
  84     MAU2_MASK_VENC_POST0,
  85     MAU2_MASK_VENC_POST1,
  86
  87     MAU2_MASK_ALL,
  88
  89     MAU3_MASK_RSV_0 = MAU2_MASK_ALL,
  90     MAU3_MASK_G2D_R,
  91     MAU3_MASK_G2D_W,
  92     MAU3_MASK_AUDIO,
  93
  94     MAU3_MASK_ALL,
  95     MAU_MASK_ALL = MAU3_MASK_ALL
  96 }MTK_MAU0_MASK;
  97 */
  98
  99 typedef enum {
 100     MAU0_MASK_RSV_0 = 0,
 101     MAU0_MASK_DEFECT,
 102     MAU0_MASK_JPE_ENC,
 103     MAU0_MASK_ROT_DMA0_OUT0,
 104     MAU0_MASK_ROT_DMA1_OUT0,
 105     MAU0_MASK_TV_ROT_OUT0,
 106     MAU0_MASK_CAM,
 107     MAU0_MASK_FD0,
 108     MAU0_MASK_FD2,
 109     MAU0_MASK_JPG_DEC0,
 110     MAU0_MASK_R_DMA0_OUT0,
 111     MAU0_MASK_R_DMA0_OUT1,
 112     MAU0_MASK_R_DMA0_OUT2,
 113     MAU0_MASK_FD1,
 114     MAU0_MASK_PCA,
 115     MAU0_MASK_JPGDMA_R,  // 15
 116     MAU0_MASK_JPGDMA_W,  // 15
 117     MAU0_MASK_ROT_DMA0_OUT1,// 15
 118     MAU0_MASK_ROT_DMA0_OUT2,// 15
 119     MAU0_MASK_ROT_DMA1_OUT1,// 15
 120     MAU0_MASK_ROT_DMA1_OUT2,// 15
 121     MAU0_MASK_TV_ROT_OUT1,  // no use
 122     MAU0_MASK_TV_ROT_OUT2,  // no use
 123     MAU0_MASK_R_DMA0_OUT3, // no use
 124     MAU0_MASK_JPG_DEC1,    // 15
 125
 126     MAU0_MASK_ALL,
 127 }MTK_MAU0_MASK;
 128
 129 typedef enum {
 130     MAU1_MASK_RSV_0,
 131     MAU1_MASK_OVL_MSK,    // 1
 132     MAU1_MASK_OVL_DCP,
 133     MAU1_MASK_DPI,
 134     MAU1_MASK_ROT_DMA2_OUT0,
 135     MAU1_MASK_ROT_DMA3_OUT0,
 136     MAU1_MASK_ROT_DMA4_OUT0,
 137     MAU1_MASK_TVC,
 138     MAU1_MASK_LCD_R,
 139     MAU1_MASK_LCD_W,
 140     MAU1_MASK_R_DMA1_OUT0,
 141     MAU1_MASK_R_DMA1_OUT1,
 142     MAU1_MASK_R_DMA1_OUT2,
 143     MAU1_MASK_SPI,
 144     MAU1_MASK_RSV_14,
 145     MAU1_MASK_DPI_HWC,
 146     MAU1_MASK_VRZ,            //16
 147     MAU1_MASK_ROT_DMA2_OUT1,  //20
 148     MAU1_MASK_ROT_DMA2_OUT2,  //20
 149     MAU1_MASK_ROT_DMA3_OUT1,  //20
 150     MAU1_MASK_ROT_DMA3_OUT2,  //20
 151     MAU1_MASK_ROT_DMA4_OUT1,  //20
 152     MAU1_MASK_ROT_DMA4_OUT2,  //20
 153     MAU1_MASK_GREQ_BLKW,      //17
 154     MAU1_MASK_GREQ_BLKR,      //18
 155     MAU1_MASK_TVC_PFH,      //no use
 156     MAU1_MASK_TVC_RESZ,      //no use
 157     MAU1_MASK_R_DMA1_OUT3,      //no use
 158     MAU1_MASK_EIS,          //19
 159
 160     MAU1_MASK_ALL,
 161 }MTK_MAU1_MASK;
 162
 163
 164 typedef enum {
 165     MAU2_MASK_RSV_0,
 166     MAU2_MASK_VENC_MC,
 167     MAU2_MASK_VENC_BSDMA,
 168     MAU2_MASK_VENC_MVQP,
 169     MAU2_MASK_VENC_DMA,
 170     MAU2_MASK_VENC_REC,
 171     MAU2_MASK_VENC_POST0,
 172     MAU2_MASK_VENC_POST1,
 173
 174     MAU2_MASK_ALL,
 175
 176 }MTK_MAU2_MASK;
 177
 178 typedef enum {
 179     MAU3_MASK_RSV_0,
 180     MAU3_MASK_G2D_R,
 181     MAU3_MASK_G2D_W,
 182     MAU3_MASK_AUDIO,
 183
 184     MAU3_MASK_ALL,
 185 }MTK_MAU3_MASK;
 186
 187
 188
 189
 190
 191 typedef enum
 192 {
 193     MAU_PA,   //phsical address
 194     MAU_MVA       //m4u virtual addrss
 195 } MTK_MAU_MODE;
 196
 197
 198
 199 typedef enum
 200 {
 201     MAU_ENTRY_0 = 0,
 202     MAU_ENTRY_1,
 203     MAU_ENTRY_2,
 204     MAU_ENTRY_ALL
 205 } MTK_MAU_ENTRY;
 206
 207
 208 typedef struct
 209 {
 210     MTK_MAU_ENTRY   EntryID;                                                // Entry ID 0~2
 211     bool            Enable;
 212     MTK_MAU_MODE    Mode;
 213     unsigned int    InvalidMasterLARB0; // one bit represent one master, 1: allow, 0: not allow, usd by MAU and MPU
 214         unsigned int    InvalidMasterLARB1;    // one bit represent one master, 1: allow, 0: not allow, only used by MPU
 215     unsigned int    InvalidMasterLARB2;
 216     unsigned int    InvalidMasterLARB3;
 217         unsigned int    ReadEn;                                             // check read transaction, 1:enable, 0:disable
 218         unsigned int    WriteEn;                                      // check write transaction, 1:enable, 0:disable
 219         unsigned int    StartAddr;                                        // start address
 220         unsigned int    EndAddr;                                            // end address
 221 } MTK_MAU_CONFIG;
 222
 223
 224
 225
 226
 227
 228
 229
 230 typedef enum
 231 {
 232     MAU_ID_0,
 233     MAU_ID_1,
 234     MAU_ID_2,
 235     MAU_ID_3,
 236     MAU_ID_ALL
 237 } MTK_MAU_ID;
 238
 239
 240
 241
 242 int  MAU_Config(MTK_MAU_CONFIG* pMauConf);
 243 void MAU_PrintStatus(char* buf, unsigned int buf_len, unsigned int* num);
 244 void MAU_DumpReg(MTK_MAU_ID mauID);
 245 void MAU_LogSwitch(bool enable);
 246 void MAU_BackupReg(MTK_MAU_ID mauID);
 247 void MAU_RestoreReg(MTK_MAU_ID mauID);
 248 int MAU_get_port_with_m4u(unsigned  int start_addr, unsigned int end_addr);
 249
 250 int  MAU0_PowerOn(void);
 251 int  MAU0_PowerOff(void);
 252 int  MAU1_PowerOn(void);
 253 int  MAU1_PowerOff(void);
 254 int  MAU2_PowerOn(void);
 255 int  MAU2_PowerOff(void);
 256 int  MAU3_PowerOn(void);
 257 int  MAU3_PowerOff(void);
 258
 259
 260 #endif
 261