arch/arm/mach-mt8127/include/mach/mt_thermal.h

   1
   2 #ifndef _MT6589_THERMAL_H
   3 #define _MT6589_THERMAL_H
   4
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/spinlock.h>
   8 #include <linux/interrupt.h>
   9
  10 #include <asm/io.h>
  11 #include <asm/uaccess.h>
  12
  13 #include "mach/sync_write.h"
  14 #include "mach/mt_reg_base.h"
  15 #include "mach/mt_typedefs.h"
  16 //#include "mach/mt6575_auxadc_hw.h"
  17
  18
  19 /*******************************************************************************
  20  * AUXADC Register Definition
  21  ******************************************************************************/
  22 #define AUXADC_CON0_V       (AUXADC_BASE + 0x000)       //yes, 0x11003000
  23 #define AUXADC_CON1_V       (AUXADC_BASE + 0x004)
  24 #define AUXADC_CON1_SET_V   (AUXADC_BASE + 0x008)
  25 #define AUXADC_CON1_CLR_V   (AUXADC_BASE + 0x00C)
  26 #define AUXADC_CON2_V       (AUXADC_BASE + 0x010)
  27 //#define AUXADC_CON3_V       (AUXADC_BASE + 0x014)
  28 #define AUXADC_DAT0_V       (AUXADC_BASE + 0x014)
  29 #define AUXADC_DAT1_V       (AUXADC_BASE + 0x018)
  30 #define AUXADC_DAT2_V       (AUXADC_BASE + 0x01C)
  31 #define AUXADC_DAT3_V       (AUXADC_BASE + 0x020)
  32 #define AUXADC_DAT4_V       (AUXADC_BASE + 0x024)
  33 #define AUXADC_DAT5_V       (AUXADC_BASE + 0x028)
  34 #define AUXADC_DAT6_V       (AUXADC_BASE + 0x02C)
  35 #define AUXADC_DAT7_V       (AUXADC_BASE + 0x030)
  36 #define AUXADC_DAT8_V       (AUXADC_BASE + 0x034)
  37 #define AUXADC_DAT9_V       (AUXADC_BASE + 0x038)
  38 #define AUXADC_DAT10_V       (AUXADC_BASE + 0x03C)
  39 #define AUXADC_DAT11_V       (AUXADC_BASE + 0x040)
  40 #define AUXADC_MISC_V       (AUXADC_BASE + 0x094)
  41
  42 #define AUXADC_CON0_P       (AUXADC_BASE + 0x000 - 0xE0000000)
  43 #define AUXADC_CON1_P       (AUXADC_BASE + 0x004 - 0xE0000000)
  44 #define AUXADC_CON1_SET_P   (AUXADC_BASE + 0x008 - 0xE0000000)
  45 #define AUXADC_CON1_CLR_P   (AUXADC_BASE + 0x00C - 0xE0000000)
  46 #define AUXADC_CON2_P       (AUXADC_BASE + 0x010 - 0xE0000000)
  47 //#define AUXADC_CON3_P       (AUXADC_BASE + 0x014 - 0x30000000)
  48 #define AUXADC_DAT0_P       (AUXADC_BASE + 0x014 - 0xE0000000)
  49 #define AUXADC_DAT1_P       (AUXADC_BASE + 0x018 - 0xE0000000)
  50 #define AUXADC_DAT2_P       (AUXADC_BASE + 0x01C - 0xE0000000)
  51 #define AUXADC_DAT3_P       (AUXADC_BASE + 0x020 - 0xE0000000)
  52 #define AUXADC_DAT4_P       (AUXADC_BASE + 0x024 - 0xE0000000)
  53 #define AUXADC_DAT5_P       (AUXADC_BASE + 0x028 - 0xE0000000)
  54 #define AUXADC_DAT6_P       (AUXADC_BASE + 0x02C - 0xE0000000)
  55 #define AUXADC_DAT7_P       (AUXADC_BASE + 0x030 - 0xE0000000)
  56 #define AUXADC_DAT8_P       (AUXADC_BASE + 0x034 - 0xE0000000)
  57 #define AUXADC_DAT9_P       (AUXADC_BASE + 0x038 - 0xE0000000)
  58 #define AUXADC_DAT10_P       (AUXADC_BASE + 0x03C - 0xE0000000)
  59 #define AUXADC_DAT11_P       (AUXADC_BASE + 0x040 - 0xE0000000)
  60
  61 #define AUXADC_MISC_P       (AUXADC_BASE + 0x094 - 0xE0000000)
  62
  63 /*******************************************************************************
  64  * Peripheral Configuration Register Definition
  65  ******************************************************************************/
  66 #define PERI_GLOBALCON_RST0 (PERICFG_BASE + 0x000) //yes, 0x10003000
  67
  68 /*******************************************************************************
  69  * APMixedSys Configuration Register Definition
  70  ******************************************************************************/
  71  //Jerry ????
  72  #define TS_CON0             (APMIXEDSYS_BASE + 0x600) //yes 0x10209000
  73  #define TS_CON1             (APMIXEDSYS_BASE + 0x604)
  74  #define TS_CON0_P           (IO_VIRT_TO_PHYS(APMIXEDSYS_BASE) + 0x600)
  75  #define TS_CON1_P           (IO_VIRT_TO_PHYS(APMIXEDSYS_BASE) + 0x604)
  76 //#define TS_CON0             (APMIXED_BASE + 0x800)
  77 //#define TS_CON1             (APMIXED_BASE + 0x804)
  78 //#define TS_CON2             (APMIXED_BASE + 0x808)
  79 //#define TS_CON3             (APMIXED_BASE + 0x80C)
  80
  81 /*******************************************************************************
  82  * Thermal Controller Register Definition
  83  ******************************************************************************/
  84 #define TEMPMONCTL0         (THERMAL_BASE + 0x000) //yes 0x1100c000
  85 #define TEMPMONCTL1         (THERMAL_BASE + 0x004)
  86 #define TEMPMONCTL2         (THERMAL_BASE + 0x008)
  87 #define TEMPMONINT          (THERMAL_BASE + 0x00C)
  88 #define TEMPMONINTSTS       (THERMAL_BASE + 0x010)
  89 #define TEMPMONIDET0        (THERMAL_BASE + 0x014)
  90 #define TEMPMONIDET1        (THERMAL_BASE + 0x018)
  91 #define TEMPMONIDET2        (THERMAL_BASE + 0x01C)
  92 #define TEMPH2NTHRE         (THERMAL_BASE + 0x024)
  93 #define TEMPHTHRE           (THERMAL_BASE + 0x028)
  94 #define TEMPCTHRE           (THERMAL_BASE + 0x02C)
  95 #define TEMPOFFSETH         (THERMAL_BASE + 0x030)
  96 #define TEMPOFFSETL         (THERMAL_BASE + 0x034)
  97 #define TEMPMSRCTL0         (THERMAL_BASE + 0x038)
  98 #define TEMPMSRCTL1         (THERMAL_BASE + 0x03C)
  99 #define TEMPAHBPOLL         (THERMAL_BASE + 0x040)
 100 #define TEMPAHBTO           (THERMAL_BASE + 0x044)
 101 #define TEMPADCPNP0         (THERMAL_BASE + 0x048)
 102 #define TEMPADCPNP1         (THERMAL_BASE + 0x04C)
 103 #define TEMPADCPNP2         (THERMAL_BASE + 0x050)
 104 #define TEMPADCMUX          (THERMAL_BASE + 0x054)
 105 #define TEMPADCEXT          (THERMAL_BASE + 0x058)
 106 #define TEMPADCEXT1         (THERMAL_BASE + 0x05C)
 107 #define TEMPADCEN           (THERMAL_BASE + 0x060)
 108 #define TEMPPNPMUXADDR      (THERMAL_BASE + 0x064)
 109 #define TEMPADCMUXADDR      (THERMAL_BASE + 0x068)
 110 #define TEMPADCEXTADDR      (THERMAL_BASE + 0x06C)
 111 #define TEMPADCEXT1ADDR     (THERMAL_BASE + 0x070)
 112 #define TEMPADCENADDR       (THERMAL_BASE + 0x074)
 113 #define TEMPADCVALIDADDR    (THERMAL_BASE + 0x078)
 114 #define TEMPADCVOLTADDR     (THERMAL_BASE + 0x07C)
 115 #define TEMPRDCTRL          (THERMAL_BASE + 0x080)
 116 #define TEMPADCVALIDMASK    (THERMAL_BASE + 0x084)
 117 #define TEMPADCVOLTAGESHIFT (THERMAL_BASE + 0x088)
 118 #define TEMPADCWRITECTRL    (THERMAL_BASE + 0x08C)
 119 #define TEMPMSR0            (THERMAL_BASE + 0x090)
 120 #define TEMPMSR1            (THERMAL_BASE + 0x094)
 121 #define TEMPMSR2            (THERMAL_BASE + 0x098)
 122 #define TEMPIMMD0           (THERMAL_BASE + 0x0A0)
 123 #define TEMPIMMD1           (THERMAL_BASE + 0x0A4)
 124 #define TEMPIMMD2           (THERMAL_BASE + 0x0A8)
 125
 126 #define TEMPPROTCTL         (THERMAL_BASE + 0x0C0)
 127 #define TEMPPROTTA          (THERMAL_BASE + 0x0C4)
 128 #define TEMPPROTTB          (THERMAL_BASE + 0x0C8)
 129 #define TEMPPROTTC          (THERMAL_BASE + 0x0CC)
 130
 131 #define TEMPSPARE0          (THERMAL_BASE + 0x0F0)
 132 #define TEMPSPARE1          (THERMAL_BASE + 0x0F4)
 133 #define TEMPSPARE2          (THERMAL_BASE + 0x0F8)
 134 #define TEMPSPARE3          (THERMAL_BASE + 0x0FC)
 135
 136 /*******************************************************************************
 137  * Thermal Controller Register Mask Definition
 138  ******************************************************************************/
 139 #define THERMAL_ENABLE_SEN0     0x1
 140 #define THERMAL_ENABLE_SEN1     0x2
 141 #define THERMAL_ENABLE_SEN2     0x4
 142 #define THERMAL_MONCTL0_MASK    0x00000007
 143
 144 #define THERMAL_PUNT_MASK       0x00000FFF
 145 #define THERMAL_FSINTVL_MASK    0x03FF0000
 146 #define THERMAL_SPINTVL_MASK    0x000003FF
 147 #define THERMAL_MON_INT_MASK    0x0007FFFF
 148
 149 #define THERMAL_MON_CINTSTS0    0x000001
 150 #define THERMAL_MON_HINTSTS0    0x000002
 151 #define THERMAL_MON_LOINTSTS0   0x000004
 152 #define THERMAL_MON_HOINTSTS0   0x000008
 153 #define THERMAL_MON_NHINTSTS0   0x000010
 154 #define THERMAL_MON_CINTSTS1    0x000020
 155 #define THERMAL_MON_HINTSTS1    0x000040
 156 #define THERMAL_MON_LOINTSTS1   0x000080
 157 #define THERMAL_MON_HOINTSTS1   0x000100
 158 #define THERMAL_MON_NHINTSTS1   0x000200
 159 #define THERMAL_MON_CINTSTS2    0x000400
 160 #define THERMAL_MON_HINTSTS2    0x000800
 161 #define THERMAL_MON_LOINTSTS2   0x001000
 162 #define THERMAL_MON_HOINTSTS2   0x002000
 163 #define THERMAL_MON_NHINTSTS2   0x004000
 164 #define THERMAL_MON_TOINTSTS    0x008000
 165 #define THERMAL_MON_IMMDINTSTS0 0x010000
 166 #define THERMAL_MON_IMMDINTSTS1 0x020000
 167 #define THERMAL_MON_IMMDINTSTS2 0x040000
 168 #define THERMAL_MON_FILTINTSTS0 0x080000
 169 #define THERMAL_MON_FILTINTSTS1 0x100000
 170 #define THERMAL_MON_FILTINTSTS2 0x200000
 171
 172
 173 #define THERMAL_tri_SPM_State0  0x20000000
 174 #define THERMAL_tri_SPM_State1  0x40000000
 175 #define THERMAL_tri_SPM_State2  0x80000000
 176
 177
 178 #define THERMAL_MSRCTL0_MASK    0x00000007
 179 #define THERMAL_MSRCTL1_MASK    0x00000038
 180 #define THERMAL_MSRCTL2_MASK    0x000001C0
 181
 182 //extern int thermal_one_shot_handler(int times);
 183 struct TS_PTPOD
 184 {
 185         unsigned int ts_MTS;
 186         unsigned int ts_BTS;
 187 };
 188 extern void get_thermal_slope_intercept(struct TS_PTPOD *ts_info);
 189 extern void set_taklking_flag(bool flag);
 190 extern int mtktscpu_get_cpu_temp(void);
 191
 192 //#define THERMAL_WRAP_RD32(addr)            __raw_readl((void *)addr)
 193 #define THERMAL_WRAP_WR32(val,addr)        mt65xx_reg_sync_writel((val), ((void *)addr))
 194
 195 //#define THERMAL_WRAP_SET_BIT(BS,REG)       mt65xx_reg_sync_writel((__raw_readl((void *)REG) | (U32)(BS)), ((void *)REG))
 196 //#define THERMAL_WRAP_CLR_BIT(BS,REG)       mt65xx_reg_sync_writel((__raw_readl((void *)REG) & (~(U32)(BS))), ((void *)REG))
 197
 198
 199 #endif
 200