arch/arm/mach-mt8127/include/mach/mt_rtc_hw.h

   1 #ifndef __MT_RTC_HW_H__
   2 #define __MT_RTC_HW_H__
   3
   4 //#include <typedefs.h>
   5 //#include <platform.h>
   6 /*
   7 #define TOP_CKPDN               0x004E
   8 #define TOP_CKTST2      0x012E
   9 #define FQMTR_CON0      0x0188
  10 #define FQMTR_CON1      0x018A
  11 #define FQMTR_CON2      0x018C
  12 */
  13 /* RTC registers */
  14 //#define       RTC_BASE        (0x8000)
  15 /* RTC registers */
  16 #define RTC_BBPU                                        (RTC_BASE + 0x0000)
  17 #define RTC_BBPU_PWREN          (1U << 0)       /* BBPU = 1 when alarm occurs */
  18 #define RTC_BBPU_BBPU                   (1U << 2)       /* 1: power on, 0: power down */
  19 #define RTC_BBPU_AUTO                   (1U << 3)       /* BBPU = 0 when xreset_rstb goes low */
  20 #define RTC_BBPU_RELOAD         (1U << 5)
  21 #define RTC_BBPU_CBUSY          (1U << 6)
  22 #define RTC_BBPU_KEY                    (0x43 << 8)
  23
  24 #define RTC_IRQ_STA                             (RTC_BASE + 0x0002)
  25 #define RTC_IRQ_STA_AL          (1U << 0)
  26 #define RTC_IRQ_STA_LP          (1U << 3)
  27
  28 #define RTC_IRQ_EN                                      (RTC_BASE + 0x0004)
  29 #define RTC_IRQ_EN_AL                           (1U << 0)
  30 #define RTC_IRQ_EN_ONESHOT      (1U << 2)
  31 #define RTC_IRQ_EN_LP                           (1U << 3)
  32 #define RTC_IRQ_EN_ONESHOT_AL   (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
  33
  34 #define RTC_CII_EN                      (RTC_BASE + 0x0006)
  35 #define RTC_CII_SEC             (1U << 0)
  36 #define RTC_CII_MIN             (1U << 1)
  37 #define RTC_CII_HOU             (1U << 2)
  38 #define RTC_CII_DOM             (1U << 3)
  39 #define RTC_CII_DOW             (1U << 4)
  40 #define RTC_CII_MTH             (1U << 5)
  41 #define RTC_CII_YEA             (1U << 6)
  42 #define RTC_CII_1_2_SEC (1U << 7)
  43 #define RTC_CII_1_4_SEC (1U << 8)
  44 #define RTC_CII_1_8_SEC (1U << 9)
  45
  46 #define RTC_AL_MASK     (RTC_BASE + 0x0008)
  47 #define RTC_AL_MASK_SEC (1U << 0)
  48 #define RTC_AL_MASK_MIN (1U << 1)
  49 #define RTC_AL_MASK_HOU (1U << 2)
  50 #define RTC_AL_MASK_DOM (1U << 3)
  51 #define RTC_AL_MASK_DOW (1U << 4)
  52 #define RTC_AL_MASK_MTH (1U << 5)
  53 #define RTC_AL_MASK_YEA (1U << 6)
  54
  55 #define RTC_TC_SEC                      (RTC_BASE + 0x000a)
  56 #define RTC_TC_SEC_MASK 0x003f
  57
  58 #define RTC_TC_MIN                      (RTC_BASE + 0x000c)
  59 #define RTC_TC_MIN_MASK 0x003f
  60
  61 #define RTC_TC_HOU                      (RTC_BASE + 0x000e)
  62 #define RTC_TC_HOU_MASK 0x001f
  63
  64 #define RTC_TC_DOM                      (RTC_BASE + 0x0010)
  65 #define RTC_TC_DOM_MASK 0x001f
  66
  67 #define RTC_TC_DOW                      (RTC_BASE + 0x0012)
  68 #define RTC_TC_DOW_MASK 0x0007
  69
  70 #define RTC_TC_MTH                      (RTC_BASE + 0x0014)
  71 #define RTC_TC_MTH_MASK 0x000f
  72
  73 #define RTC_TC_YEA                      (RTC_BASE + 0x0016)
  74 #define RTC_TC_YEA_MASK 0x007f
  75
  76 #define RTC_AL_SEC                      (RTC_BASE + 0x0018)
  77 #define RTC_AL_SEC_MASK 0x003f
  78
  79 #define RTC_AL_MIN                      (RTC_BASE + 0x001a)
  80 #define RTC_AL_MIN_MASK 0x003f
  81
  82 /*
  83  * RTC_NEW_SPARE0: RTC_AL_HOU bit0~4
  84  *         bit 8 ~ 14 : Fuel Gauge
  85  *     bit 15     : reserved bits
  86  */
  87 #define RTC_AL_HOU                                                      (RTC_BASE + 0x001c)
  88 #define RTC_NEW_SPARE_FG_MASK           0xff00
  89 #define RTC_NEW_SPARE_FG_SHIFT  8
  90 #define RTC_AL_HOU_MASK                                 0x001f
  91
  92 /*
  93  * RTC_NEW_SPARE1: RTC_AL_DOM bit0~4
  94  *         bit 8 ~ 15 : reserved bits
  95  */
  96 #define RTC_AL_DOM                      (RTC_BASE + 0x001e)
  97 #define RTC_NEW_SPARE1  0xff00
  98 #define RTC_AL_DOM_MASK 0x001f
  99
 100 /*
 101  * RTC_NEW_SPARE2: RTC_AL_DOW bit0~2
 102  *         bit 8 ~ 15 : reserved bits
 103  */
 104 #define RTC_AL_DOW                      (RTC_BASE + 0x0020)
 105 #define RTC_NEW_SPARE2  0xff00
 106 #define RTC_AL_DOW_MASK 0x0007
 107
 108 /*
 109  * RTC_NEW_SPARE3: RTC_AL_MTH bit0~3
 110  *         bit 8 ~ 15 : reserved bits
 111  */
 112 #define RTC_AL_MTH                      (RTC_BASE + 0x0022)
 113 #define RTC_NEW_SPARE3  0xff00
 114 #define RTC_AL_MTH_MASK 0x000f
 115
 116 #define RTC_AL_YEA                      (RTC_BASE + 0x0024)
 117 #define RTC_AL_YEA_MASK 0x007f
 118
 119 #define RTC_OSC32CON                                                            (RTC_BASE + 0x0026)
 120 #define RTC_OSC32CON_UNLOCK1                            0x1a57
 121 #define RTC_OSC32CON_UNLOCK2                            0x2b68
 122 #define RTC_OSC32CON_XOSC32_ENB                 (1U << 13)
 123 #define RTC_OSC32CON_LNBUFEN                            (1U << 11)      /* ungate 32K to ABB */
 124 #define RTC_OSC32CON_EOSC32_CHOP_EN     (1U << 10)
 125 #define RTC_OSC32CON_EMBCK_SEL                  (1U << 7)
 126 #define RTC_OSC32CON_EMBCK_SEL_MODE     (1U << 6)
 127 #define RTC_OSC32CON_XOSCCALI_MASK      0x001f
 128
 129 #define RTC_XOSCCALI_START                                      0x0000
 130 #define RTC_XOSCCALI_END                                                0x001f
 131
 132 #define RTC_EOSC_CALI_LEFT      (RTC_OSC32CON_XOSC32_ENB | RTC_OSC32CON_EOSC32_CHOP_EN | RTC_OSC32CON_EMBCK_SEL | RTC_OSC32CON_EMBCK_SEL_MODE | RTC_XOSCCALI_START)
 133 #define RTC_EOSC_CALI_RIGHT     (RTC_OSC32CON_XOSC32_ENB | RTC_OSC32CON_EOSC32_CHOP_EN | RTC_OSC32CON_EMBCK_SEL | RTC_OSC32CON_EMBCK_SEL_MODE | RTC_XOSCCALI_END)
 134
 135 #define RTC_POWERKEY1   (RTC_BASE + 0x0028)
 136 #define RTC_POWERKEY2   (RTC_BASE + 0x002a)
 137 #define RTC_POWERKEY1_KEY       0xa357
 138 #define RTC_POWERKEY2_KEY       0x67d2
 139 /*
 140  * RTC_PDN1:
 141  *     bit 0 - 3  : Android bits
 142  *     bit 4 - 5  : Recovery bits (0x10: factory data reset)
 143  *     bit 6      : Bypass PWRKEY bit
 144  *     bit 7      : Power-On Time bit
 145  *     bit 8      : RTC_GPIO_USER_WIFI bit
 146  *     bit 9      : RTC_GPIO_USER_GPS bit
 147  *     bit 10     : RTC_GPIO_USER_BT bit
 148  *     bit 11     : RTC_GPIO_USER_FM bit
 149  *     bit 12     : RTC_GPIO_USER_PMIC bit
 150  *     bit 13     : Fast Boot
 151  *     bit 14     : Kernel Power Off Charging
 152  *     bit 15     : Debug bit
 153  */
 154 #define RTC_PDN1                                                                (RTC_BASE + 0x002c)
 155 #define RTC_PDN1_ANDROID_MASK           0x000f
 156 #define RTC_PDN1_RECOVERY_MASK  0x0030
 157 #define RTC_PDN1_FAC_RESET                      (1U << 4)
 158 #define RTC_PDN1_BYPASS_PWR                     (1U << 6)
 159 #define RTC_PDN1_PWRON_TIME                     (1U << 7)
 160 #define RTC_PDN1_GPIO_WIFI                      (1U << 8)
 161 #define RTC_PDN1_GPIO_GPS                               (1U << 9)
 162 #define RTC_PDN1_GPIO_BT                                (1U << 10)
 163 #define RTC_PDN1_GPIO_FM                                (1U << 11)
 164 #define RTC_PDN1_GPIO_PMIC                      (1U << 12)
 165 #define RTC_PDN1_FAST_BOOT                      (1U << 13)
 166 #define RTC_PDN1_KPOC                                           (1U << 14)
 167 #define RTC_PDN1_DEBUG                                  (1U << 15)
 168
 169 /*
 170  * RTC_PDN2:
 171  *     bit 0 - 3 : MTH in power-on time
 172  *     bit 4     : Power-On Alarm bit
 173  *     bit 5 - 6 : UART bits
 174  *     bit 7     : reserved bit
 175  *     bit 8 - 14: YEA in power-on time
 176  *     bit 15    : Power-On Logo bit
 177  */
 178 #define RTC_PDN2                                                                        (RTC_BASE + 0x002e)
 179 #define RTC_PDN2_PWRON_MTH_MASK         0x000f
 180 #define RTC_PDN2_PWRON_MTH_SHIFT        0
 181 #define RTC_PDN2_PWRON_ALARM                    (1U << 4)
 182 #define RTC_PDN2_UART_MASK                              0x0060
 183 #define RTC_PDN2_UART_SHIFT                             5
 184 #define RTC_PDN2_PWRON_YEA_MASK         0x7f00
 185 #define RTC_PDN2_AUTOBOOT         (1U << 7)
 186 #define RTC_PDN2_PWRON_YEA_SHIFT        8
 187 #define RTC_PDN2_PWRON_LOGO                             (1U << 15)
 188
 189 /*
 190  * RTC_SPAR0:
 191  *     bit 0 - 5 : SEC in power-on time
 192  *     bit 6     : 32K less bit. True:with 32K, False:Without 32K
 193  *     bit 7 - 15: reserved bits
 194  */
 195 #define RTC_SPAR0                                                                       (RTC_BASE + 0x0030)
 196 #define RTC_SPAR0_PWRON_SEC_MASK        0x003f
 197 #define RTC_SPAR0_PWRON_SEC_SHIFT       0
 198 #define RTC_SPAR0_32K_LESS                              (1U << 6)
 199 #define RTC_SPAR0_LP_DET                                        (1U << 7)
 200
 201 /*
 202  * RTC_SPAR1:
 203  *     bit 0 - 5  : MIN in power-on time
 204  *     bit 6 - 10 : HOU in power-on time
 205  *     bit 11 - 15: DOM in power-on time
 206  */
 207 #define RTC_SPAR1                                                                       (RTC_BASE + 0x0032)
 208 #define RTC_SPAR1_PWRON_MIN_MASK        0x003f
 209 #define RTC_SPAR1_PWRON_MIN_SHIFT       0
 210 #define RTC_SPAR1_PWRON_HOU_MASK        0x07c0
 211 #define RTC_SPAR1_PWRON_HOU_SHIFT       6
 212 #define RTC_SPAR1_PWRON_DOM_MASK        0xf800
 213 #define RTC_SPAR1_PWRON_DOM_SHIFT       11
 214
 215 #define RTC_PROT                                        (RTC_BASE + 0x0036)
 216 #define RTC_PROT_UNLOCK1        0x586a
 217 #define RTC_PROT_UNLOCK2        0x9136
 218
 219 #define RTC_DIFF        (RTC_BASE + 0x0038)
 220 #define RTC_CALI        (RTC_BASE + 0x003a)
 221 #define RTC_WRTGR       (RTC_BASE + 0x003c)
 222
 223 #define RTC_CON                                 (RTC_BASE + 0x003e)
 224 #define RTC_CON_LPEN            (1U << 2)
 225 #define RTC_CON_LPRST           (1U << 3)
 226 #define RTC_CON_CDBO            (1U << 4)
 227 #define RTC_CON_F32KOB          (1U << 5)       /* 0: RTC_GPIO exports 32K */
 228 #define RTC_CON_GPO             (1U << 6)
 229 #define RTC_CON_GOE             (1U << 7)       /* 1: GPO mode, 0: GPI mode */
 230 #define RTC_CON_GSR             (1U << 8)
 231 #define RTC_CON_GSMT            (1U << 9)
 232 #define RTC_CON_GPEN            (1U << 10)
 233 #define RTC_CON_GPU             (1U << 11)
 234 #define RTC_CON_GE4             (1U << 12)
 235 #define RTC_CON_GE8             (1U << 13)
 236 #define RTC_CON_GPI             (1U << 14)
 237 #define RTC_CON_LPSTA_RAW       (1U << 15)      /* 32K was stopped */
 238
 239 #endif /* __MT_RTC_HW_H__ */
 240