arch/arm/mach-mt8127/include/mach/mt_pwm_prv.h

   1 /*******************************************************************************
   2 * mt6575_pwm.h PWM Drvier
   3 *
   4 * Copyright (c) 2010, Media Teck.inc
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public Licence,
   8 * version 2, as publish by the Free Software Foundation.
   9 *
  10 * This program is distributed and in hope it will be useful, but WITHOUT
  11 * ANY WARRNTY; without even the implied warranty of MERCHANTABITLITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13 * more details.
  14 *
  15 *
  16 ********************************************************************************
  17 * Author : Chagnlei Gao (changlei.gao@mediatek.com)
  18 ********************************************************************************
  19 */
  20
  21 #ifndef __MT_PWM_PRV_H__
  22 #define __MT_PWM_PRV_H__
  23
  24 #ifdef OUTREG32
  25   #undef OUTREG32
  26   #define OUTREG32(x, y) mt65xx_reg_sync_writel(y, x)
  27 #endif
  28
  29 /***********************************
  30 * PWM register address             *
  31 ************************************/
  32 #define PWM_ENABLE (PWM_BASE+0x0000)
  33
  34 #define PWM4_DELAY (PWM_BASE+0x00004)
  35 #define PWM5_DELAY (PWM_BASE+0x00008)
  36
  37 #define PWM_3DLCM       (PWM_BASE+0x1D0)
  38 #define PWM_3DLCM_ENABLE_OFFSET 0
  39 #define PWM_3DLCM_2_INV 4
  40 #define PWM_3DLCM_1_INV 3
  41 #define PWM_3DLCM_0_INV 2
  42
  43 #define PWM_INT_ENABLE (PWM_BASE+0x0200)
  44 #define PWM_INT_STATUS (PWM_BASE+0x0204)
  45 #define PWM_INT_ACK (PWM_BASE+0x0208)
  46 #define PWM_EN_STATUS (PWM_BASE+0x020c)
  47
  48 /*PWM3,PWM4,PWM5_DELAY registers*/
  49 #define PWM_DELAY_DURATION_MASK 0x0000FFFF
  50 #define PWM_DELAY_CLK_MASK 0x00010000
  51
  52 #define PWM_ENABLE_SEQ_OFFSET 16
  53 #define PWM_ENABLE_TEST_SEL_OFFSET 17
  54
  55 /*PWM1~PWM7 control registers*/
  56 #define PWM_CON_CLKDIV_MASK 0x00000007
  57 #define PWM_CON_CLKDIV_OFFSET 0
  58 #define PWM_CON_CLKSEL_MASK 0x00000008
  59 #define PWM_CON_CLKSEL_OFFSET 3
  60
  61 #define PWM_CON_SRCSEL_MASK 0x00000020
  62 #define PWM_CON_SRCSEL_OFFSET 5
  63
  64 #define PWM_CON_MODE_MASK 0x00000040
  65 #define PWM_CON_MODE_OFFSET 6
  66
  67 #define PWM_CON_IDLE_VALUE_MASK 0x00000080
  68 #define PWM_CON_IDLE_VALUE_OFFSET 7
  69
  70 #define PWM_CON_GUARD_VALUE_MASK 0x00000100
  71 #define PWM_CON_GUARD_VALUE_OFFSET 8
  72
  73 #define PWM_CON_STOP_BITS_MASK 0x00007E00
  74 #define PWM_CON_STOP_BITS_OFFSET 9
  75 #define PWM_CON_OLD_MODE_MASK 0x00008000
  76 #define PWM_CON_OLD_MODE_OFFSET 15
  77
  78 #define BLOCK_CLK 65*1024*1024
  79
  80 #endif