arch/arm/mach-mt8127/include/mach/mt_musb_reg.h

   1 #ifndef __MT_MUSB_REG_H__
   2 #define __MT_MUSB_REG_H__
   3
   4 #define MUSB_EP0_FIFOSIZE       64      /* This is non-configurable */
   5
   6 /*
   7  * MUSB Register bits
   8  */
   9
  10 /* POWER */
  11 #define MUSB_POWER_ISOUPDATE    0x80
  12 #define MUSB_POWER_SOFTCONN     0x40
  13 #define MUSB_POWER_HSENAB       0x20
  14 #define MUSB_POWER_HSMODE       0x10
  15 #define MUSB_POWER_RESET        0x08
  16 #define MUSB_POWER_RESUME       0x04
  17 #define MUSB_POWER_SUSPENDM     0x02
  18 #define MUSB_POWER_ENSUSPEND    0x01
  19
  20 /* INTRUSB */
  21 #define MUSB_INTR_SUSPEND       0x01
  22 #define MUSB_INTR_RESUME        0x02
  23 #define MUSB_INTR_RESET         0x04
  24 #define MUSB_INTR_BABBLE        0x04
  25 #define MUSB_INTR_SOF           0x08
  26 #define MUSB_INTR_CONNECT       0x10
  27 #define MUSB_INTR_DISCONNECT    0x20
  28 #define MUSB_INTR_SESSREQ       0x40
  29 #define MUSB_INTR_VBUSERROR     0x80    /* For SESSION end */
  30
  31 /* DEVCTL */
  32 #define MUSB_DEVCTL_BDEVICE     0x80
  33 #define MUSB_DEVCTL_FSDEV       0x40
  34 #define MUSB_DEVCTL_LSDEV       0x20
  35 #define MUSB_DEVCTL_VBUS        0x18
  36 #define MUSB_DEVCTL_VBUS_SHIFT  3
  37 #define MUSB_DEVCTL_HM          0x04
  38 #define MUSB_DEVCTL_HR          0x02
  39 #define MUSB_DEVCTL_SESSION     0x01
  40
  41 /* MUSB ULPI VBUSCONTROL */
  42 #define MUSB_ULPI_USE_EXTVBUS   0x01
  43 #define MUSB_ULPI_USE_EXTVBUSIND 0x02
  44 /* ULPI_REG_CONTROL */
  45 #define MUSB_ULPI_REG_REQ       (1 << 0)
  46 #define MUSB_ULPI_REG_CMPLT     (1 << 1)
  47 #define MUSB_ULPI_RDN_WR        (1 << 2)
  48
  49 /* TESTMODE */
  50 #define MUSB_TEST_FORCE_HOST    0x80
  51 #define MUSB_TEST_FIFO_ACCESS   0x40
  52 #define MUSB_TEST_FORCE_FS      0x20
  53 #define MUSB_TEST_FORCE_HS      0x10
  54 #define MUSB_TEST_PACKET        0x08
  55 #define MUSB_TEST_K             0x04
  56 #define MUSB_TEST_J             0x02
  57 #define MUSB_TEST_SE0_NAK       0x01
  58
  59 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
  60 #define MUSB_FIFOSZ_DPB 0x10
  61 /* Allocation size (8, 16, 32, ... 4096) */
  62 #define MUSB_FIFOSZ_SIZE        0x0f
  63
  64 /* CSR0 */
  65 #define MUSB_CSR0_FLUSHFIFO     0x0100
  66 #define MUSB_CSR0_TXPKTRDY      0x0002
  67 #define MUSB_CSR0_RXPKTRDY      0x0001
  68
  69 /* CSR0 in Peripheral mode */
  70 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
  71 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
  72 #define MUSB_CSR0_P_SENDSTALL   0x0020
  73 #define MUSB_CSR0_P_SETUPEND    0x0010
  74 #define MUSB_CSR0_P_DATAEND     0x0008
  75 #define MUSB_CSR0_P_SENTSTALL   0x0004
  76
  77 /* CSR0 in Host mode */
  78 #define MUSB_CSR0_H_DIS_PING            0x0800
  79 #define MUSB_CSR0_H_WR_DATATOGGLE       0x0400  /* Set to allow setting: */
  80 #define MUSB_CSR0_H_DATATOGGLE          0x0200  /* Data toggle control */
  81 #define MUSB_CSR0_H_NAKTIMEOUT          0x0080
  82 #define MUSB_CSR0_H_STATUSPKT           0x0040
  83 #define MUSB_CSR0_H_REQPKT              0x0020
  84 #define MUSB_CSR0_H_ERROR               0x0010
  85 #define MUSB_CSR0_H_SETUPPKT            0x0008
  86 #define MUSB_CSR0_H_RXSTALL             0x0004
  87
  88 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
  89 #define MUSB_CSR0_P_WZC_BITS    \
  90         (MUSB_CSR0_P_SENTSTALL)
  91 #define MUSB_CSR0_H_WZC_BITS    \
  92         (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
  93         | MUSB_CSR0_RXPKTRDY)
  94
  95 /* TxType/RxType */
  96 #define MUSB_TYPE_SPEED         0xc0
  97 #define MUSB_TYPE_SPEED_SHIFT   6
  98 #define MUSB_TYPE_PROTO         0x30    /* Implicitly zero for ep0 */
  99 #define MUSB_TYPE_PROTO_SHIFT   4
 100 #define MUSB_TYPE_REMOTE_END    0xf     /* Implicitly zero for ep0 */
 101
 102 /* CONFIGDATA */
 103 #define MUSB_CONFIGDATA_MPRXE           0x80    /* Auto bulk pkt combining */
 104 #define MUSB_CONFIGDATA_MPTXE           0x40    /* Auto bulk pkt splitting */
 105 #define MUSB_CONFIGDATA_BIGENDIAN       0x20
 106 #define MUSB_CONFIGDATA_HBRXE           0x10    /* HB-ISO for RX */
 107 #define MUSB_CONFIGDATA_HBTXE           0x08    /* HB-ISO for TX */
 108 #define MUSB_CONFIGDATA_DYNFIFO         0x04    /* Dynamic FIFO sizing */
 109 #define MUSB_CONFIGDATA_SOFTCONE        0x02    /* SoftConnect */
 110 #define MUSB_CONFIGDATA_UTMIDW          0x01    /* Data width 0/1 => 8/16bits */
 111
 112 /* TXCSR in Peripheral and Host mode */
 113 #define MUSB_TXCSR_AUTOSET              0x8000
 114 #define MUSB_TXCSR_DMAENAB              0x1000
 115 #define MUSB_TXCSR_FRCDATATOG           0x0800
 116 #define MUSB_TXCSR_DMAMODE              0x0400
 117 #define MUSB_TXCSR_CLRDATATOG           0x0040
 118 #define MUSB_TXCSR_FLUSHFIFO            0x0008
 119 #define MUSB_TXCSR_FIFONOTEMPTY         0x0002
 120 #define MUSB_TXCSR_TXPKTRDY             0x0001
 121
 122 /* TXCSR in Peripheral mode */
 123 #define MUSB_TXCSR_P_ISO                0x4000
 124 #define MUSB_TXCSR_P_INCOMPTX           0x0080
 125 #define MUSB_TXCSR_P_SENTSTALL          0x0020
 126 #define MUSB_TXCSR_P_SENDSTALL          0x0010
 127 #define MUSB_TXCSR_P_UNDERRUN           0x0004
 128
 129 /* TXCSR in Host mode */
 130 #define MUSB_TXCSR_H_WR_DATATOGGLE      0x0200
 131 #define MUSB_TXCSR_H_DATATOGGLE         0x0100
 132 #define MUSB_TXCSR_H_NAKTIMEOUT         0x0080
 133 #define MUSB_TXCSR_H_RXSTALL            0x0020
 134 #define MUSB_TXCSR_H_ERROR              0x0004
 135
 136 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 137 #define MUSB_TXCSR_P_WZC_BITS   \
 138         (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
 139         | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
 140 #define MUSB_TXCSR_H_WZC_BITS   \
 141         (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
 142         | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
 143
 144 /* RXCSR in Peripheral and Host mode */
 145 #define MUSB_RXCSR_AUTOCLEAR            0x8000
 146 #define MUSB_RXCSR_DMAENAB              0x2000
 147 #define MUSB_RXCSR_DISNYET              0x1000
 148 #define MUSB_RXCSR_PID_ERR              0x1000
 149 #define MUSB_RXCSR_DMAMODE              0x0800
 150 #define MUSB_RXCSR_INCOMPRX             0x0100
 151 #define MUSB_RXCSR_CLRDATATOG           0x0080
 152 #define MUSB_RXCSR_FLUSHFIFO            0x0010
 153 #define MUSB_RXCSR_DATAERROR            0x0008
 154 #define MUSB_RXCSR_FIFOFULL             0x0002
 155 #define MUSB_RXCSR_RXPKTRDY             0x0001
 156
 157 //ALPS00798316, Enable DMA RxMode1
 158 #define MUSB_EP_RXPKTCOUNT              0x0300
 159 //ALPS00798316, Enable DMA RxMode1
 160
 161 /* RXCSR in Peripheral mode */
 162 #define MUSB_RXCSR_P_ISO                0x4000
 163 #define MUSB_RXCSR_P_SENTSTALL          0x0040
 164 #define MUSB_RXCSR_P_SENDSTALL          0x0020
 165 #define MUSB_RXCSR_P_OVERRUN            0x0004
 166
 167 /* RXCSR in Host mode */
 168 #define MUSB_RXCSR_H_AUTOREQ            0x4000
 169 #define MUSB_RXCSR_H_WR_DATATOGGLE      0x0400
 170 #define MUSB_RXCSR_H_DATATOGGLE         0x0200
 171 #define MUSB_RXCSR_H_RXSTALL            0x0040
 172 #define MUSB_RXCSR_H_REQPKT             0x0020
 173 #define MUSB_RXCSR_H_ERROR              0x0004
 174
 175 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 176 #define MUSB_RXCSR_P_WZC_BITS   \
 177         (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
 178         | MUSB_RXCSR_RXPKTRDY)
 179 #define MUSB_RXCSR_H_WZC_BITS   \
 180         (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
 181         | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
 182
 183 /* HUBADDR */
 184 #define MUSB_HUBADDR_MULTI_TT           0x80
 185
 186 /*
 187  * Common USB registers
 188  */
 189
 190 #define MUSB_FADDR              0x00    /* 8-bit */
 191 #define MUSB_POWER              0x01    /* 8-bit */
 192
 193 #define MUSB_INTRTX             0x02    /* 16-bit */
 194 #define MUSB_INTRRX             0x04
 195 #define MUSB_INTRTXE            0x06
 196 #define MUSB_INTRRXE            0x08
 197 #define MUSB_INTRUSB            0x0A    /* 8 bit */
 198 #define MUSB_INTRUSBE           0x0B    /* 8 bit */
 199 #define MUSB_FRAME              0x0C
 200 #define MUSB_INDEX              0x0E    /* 8 bit */
 201 #define MUSB_TESTMODE           0x0F    /* 8 bit */
 202
 203 #define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4))
 204
 205 /*
 206  * Additional Control Registers
 207  */
 208
 209 #define MUSB_DEVCTL             0x60    /* 8 bit */
 210
 211 #define MUSB_OPSTATE    0x620
 212 #define OTG_IDLE 0
 213
 214
 215 /* These are always controlled through the INDEX register */
 216 #define MUSB_TXFIFOSZ           0x62    /* 8-bit (see masks) */
 217 #define MUSB_RXFIFOSZ           0x63    /* 8-bit (see masks) */
 218 #define MUSB_TXFIFOADD          0x64    /* 16-bit offset shifted right 3 */
 219 #define MUSB_RXFIFOADD          0x66    /* 16-bit offset shifted right 3 */
 220
 221 /* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */
 222 #define MUSB_HWVERS             0x6C    /* 8 bit */
 223 #define MUSB_ULPI_BUSCONTROL    0x70    /* 8 bit */
 224 #define MUSB_ULPI_INT_MASK      0x72    /* 8 bit */
 225 #define MUSB_ULPI_INT_SRC       0x73    /* 8 bit */
 226 #define MUSB_ULPI_REG_DATA      0x74    /* 8 bit */
 227 #define MUSB_ULPI_REG_ADDR      0x75    /* 8 bit */
 228 #define MUSB_ULPI_REG_CONTROL   0x76    /* 8 bit */
 229 #define MUSB_ULPI_RAW_DATA      0x77    /* 8 bit */
 230
 231 #define MUSB_EPINFO             0x78    /* 8 bit */
 232 #define MUSB_RAMINFO            0x79    /* 8 bit */
 233 #define MUSB_LINKINFO           0x7a    /* 8 bit */
 234 #define MUSB_VPLEN              0x7b    /* 8 bit */
 235 #define MUSB_HS_EOF1            0x7c    /* 8 bit */
 236 #define MUSB_FS_EOF1            0x7d    /* 8 bit */
 237 #define MUSB_LS_EOF1            0x7e    /* 8 bit */
 238
 239 /* Offsets to endpoint registers */
 240 #define MUSB_TXMAXP             0x00
 241 #define MUSB_TXCSR              0x02
 242 #define MUSB_CSR0               MUSB_TXCSR      /* Re-used for EP0 */
 243 #define MUSB_RXMAXP             0x04
 244 #define MUSB_RXCSR              0x06
 245 #define MUSB_RXCOUNT            0x08
 246 #define MUSB_COUNT0             MUSB_RXCOUNT    /* Re-used for EP0 */
 247 #define MUSB_TXTYPE             0x0A
 248 #define MUSB_TYPE0              MUSB_TXTYPE     /* Re-used for EP0 */
 249 #define MUSB_TXINTERVAL         0x0B
 250 #define MUSB_NAKLIMIT0          MUSB_TXINTERVAL /* Re-used for EP0 */
 251 #define MUSB_RXTYPE             0x0C
 252 #define MUSB_RXINTERVAL         0x0D
 253 #define MUSB_FIFOSIZE           0x0F
 254 #define MUSB_CONFIGDATA         MUSB_FIFOSIZE   /* Re-used for EP0 */
 255
 256 /* Offsets to endpoint registers in indexed model (using INDEX register) */
 257 #define MUSB_INDEXED_OFFSET(_epnum, _offset)    \
 258         (0x10 + (_offset))
 259
 260
 261 #define MUSB_TXCSR_MODE                 0x2000
 262
 263 /* "bus control"/target registers, for host side multipoint (external hubs) */
 264 #define MUSB_TXFUNCADDR         0x0480
 265 #define MUSB_TXHUBADDR          0x0482
 266
 267 #define MUSB_RXFUNCADDR         0x0484
 268 #define MUSB_RXHUBADDR          0x0486
 269
 270 //Toggle registers
 271 #define MUSB_RXTOG          0x0080
 272 #define MUSB_RXTOGEN        0x0082
 273 #define MUSB_TXTOG          0x0084
 274 #define MUSB_TXTOGEN        0x0086
 275
 276 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \
 277         (0x80 + (8*(_epnum)) + (_offset))
 278
 279 /*
 280 MTK Software reset reg
 281 */
 282 #define MUSB_SWRST 0x74
 283 #define MUSB_SWRST_PHY_RST         (1<<7)
 284 #define MUSB_SWRST_PHYSIG_GATE_HS  (1<<6)
 285 #define MUSB_SWRST_PHYSIG_GATE_EN  (1<<5)
 286 #define MUSB_SWRST_REDUCE_DLY      (1<<4)
 287 #define MUSB_SWRST_UNDO_SRPFIX     (1<<3)
 288 #define MUSB_SWRST_FRC_VBUSVALID   (1<<2)
 289 #define MUSB_SWRST_SWRST           (1<<1)
 290 #define MUSB_SWRST_DISUSBRESET     (1<<0)
 291
 292 #define USB_L1INTS (0x00a0)  /* USB level 1 interrupt status register */
 293 #define USB_L1INTM (0x00a4)  /* USB level 1 interrupt mask register  */
 294 #define USB_L1INTP (0x00a8)  /* USB level 1 interrupt polarity register  */
 295
 296 #define DMA_INTR (USB_BASE + 0x0200)
 297 #define DMA_INTR_UNMASK_CLR_OFFSET (16)
 298 #define DMA_INTR_UNMASK_SET_OFFSET (24)
 299 #define USB_DMA_REALCOUNT(chan) (0x0280+0x10*(chan))
 300
 301
 302 /* ====================== */
 303 /* USB interrupt register */
 304 /* ====================== */
 305
 306 /* word access */
 307 #define TX_INT_STATUS        (1<<0)
 308 #define RX_INT_STATUS        (1<<1)
 309 #define USBCOM_INT_STATUS    (1<<2)
 310 #define DMA_INT_STATUS       (1<<3)
 311 #define PSR_INT_STATUS       (1<<4)
 312 #define QINT_STATUS          (1<<5)
 313 #define QHIF_INT_STATUS      (1<<6)
 314 #define DPDM_INT_STATUS      (1<<7)
 315 #define VBUSVALID_INT_STATUS (1<<8)
 316 #define IDDIG_INT_STATUS     (1<<9)
 317 #define DRVVBUS_INT_STATUS   (1<<10)
 318
 319 #define VBUSVALID_INT_POL    (1<<8)
 320 #define IDDIG_INT_POL        (1<<9)
 321 #define DRVVBUS_INT_POL      (1<<10)
 322
 323 static inline void musb_write_txfifosz(void __iomem *mbase, u8 c_size)
 324 {
 325         musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
 326 }
 327
 328 static inline void musb_write_txfifoadd(void __iomem *mbase, u16 c_off)
 329 {
 330         musb_writew(mbase, MUSB_TXFIFOADD, c_off);
 331 }
 332
 333 static inline void musb_write_rxfifosz(void __iomem *mbase, u8 c_size)
 334 {
 335         musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
 336 }
 337
 338 static inline void  musb_write_rxfifoadd(void __iomem *mbase, u16 c_off)
 339 {
 340         musb_writew(mbase, MUSB_RXFIFOADD, c_off);
 341 }
 342
 343 static inline void musb_write_ulpi_buscontrol(void __iomem *mbase, u8 val)
 344 {
 345         musb_writeb(mbase, MUSB_ULPI_BUSCONTROL, val);
 346 }
 347
 348 static inline u8 musb_read_txfifosz(void __iomem *mbase)
 349 {
 350         return musb_readb(mbase, MUSB_TXFIFOSZ);
 351 }
 352
 353 static inline u16 musb_read_txfifoadd(void __iomem *mbase)
 354 {
 355         return musb_readw(mbase, MUSB_TXFIFOADD);
 356 }
 357
 358 static inline u8 musb_read_rxfifosz(void __iomem *mbase)
 359 {
 360         return musb_readb(mbase, MUSB_RXFIFOSZ);
 361 }
 362
 363 static inline u16  musb_read_rxfifoadd(void __iomem *mbase)
 364 {
 365         return musb_readw(mbase, MUSB_RXFIFOADD);
 366 }
 367
 368 static inline u8 musb_read_ulpi_buscontrol(void __iomem *mbase)
 369 {
 370         return musb_readb(mbase, MUSB_ULPI_BUSCONTROL);
 371 }
 372
 373 static inline u8 musb_read_configdata(void __iomem *mbase)
 374 {
 375         musb_writeb(mbase, MUSB_INDEX, 0);
 376         return musb_readb(mbase, 0x10 + MUSB_CONFIGDATA);
 377 }
 378
 379 static inline u16 musb_read_hwvers(void __iomem *mbase)
 380 {
 381         return musb_readw(mbase, MUSB_HWVERS);
 382 }
 383
 384 static inline void musb_write_rxfunaddr(void __iomem *mbase, u8 epnum,
 385                 u8 qh_addr_reg)
 386 {
 387         musb_writew(mbase, MUSB_RXFUNCADDR+8*epnum, qh_addr_reg);
 388 }
 389
 390 static inline void musb_write_rxhubaddr(void __iomem *mbase, u8 epnum,
 391                 u8 qh_h_addr_reg)
 392 {
 393     u16 rx_hub_port_addr = musb_readw(mbase,0x0486+8*epnum);
 394     rx_hub_port_addr &= 0xff00;
 395     rx_hub_port_addr |= qh_h_addr_reg;
 396         musb_writew(mbase, MUSB_RXHUBADDR+8*epnum, rx_hub_port_addr);
 397 }
 398
 399 static inline void musb_write_rxhubport(void __iomem *mbase, u8 epnum,
 400                 u8 qh_h_port_reg)
 401 {
 402         u16 rx_hub_port_addr = musb_readw(mbase,0x0486+8*epnum);
 403     u16 rx_port_addr = (u16)qh_h_port_reg;
 404     rx_hub_port_addr &= 0x00ff;
 405     rx_hub_port_addr |= (rx_port_addr<<8);
 406         musb_writew(mbase, MUSB_RXHUBADDR+8*epnum, rx_hub_port_addr);
 407 }
 408
 409 static inline void  musb_write_txfunaddr(void __iomem *mbase, u8 epnum,
 410                 u8 qh_addr_reg)
 411 {
 412         musb_writew(mbase, MUSB_TXFUNCADDR+8*epnum, qh_addr_reg);
 413 }
 414
 415 static inline void  musb_write_txhubaddr(void __iomem *mbase, u8 epnum,
 416                 u8 qh_h_addr_reg)
 417 {
 418         u16 tx_hub_port_addr = musb_readw(mbase,0x0482+8*epnum);
 419     tx_hub_port_addr &= 0xff00;
 420     tx_hub_port_addr |= qh_h_addr_reg;
 421         musb_writew(mbase, MUSB_TXHUBADDR+8*epnum, tx_hub_port_addr);
 422 }
 423
 424 static inline void  musb_write_txhubport(void __iomem *mbase, u8 epnum,
 425                 u8 qh_h_port_reg)
 426 {
 427         u16 tx_hub_port_addr = musb_readw(mbase,0x0482+8*epnum);
 428     u16 tx_port_addr = (u16)qh_h_port_reg;
 429     tx_hub_port_addr &= 0x00ff;
 430     tx_hub_port_addr |= (tx_port_addr<<8);
 431         musb_writew(mbase, MUSB_TXHUBADDR+8*epnum, tx_hub_port_addr);
 432 }
 433
 434 #endif  /* __MUSB_REGS_H__ */