arch/arm/mach-mt8127/include/mach/mt_mcu.h

   1 #ifndef __MCU_H__
   2 #define __MCU_H__
   3
   4 /*
   5  * Define hardware registers.
   6  */
   7 #define MCU_BIU_CON             (MCU_BIU_BASE + 0x0)
   8 #define MCU_BIU_PMCR            (MCU_BIU_BASE + 0x14)
   9 #define MCU_BIU_CCR             (MCU_BIU_BASE + 0x40)
  10 #define MCU_BIU_CCR_CON         (MCU_BIU_BASE + 0x44)
  11 #define MCU_BIU_CCR_OVFL        (MCU_BIU_BASE + 0x48)
  12 #define MCU_BIU_EVENT0_SEL      (MCU_BIU_BASE + 0x50)
  13 #define MCU_BIU_EVENT0_CNT      (MCU_BIU_BASE + 0x54)
  14 #define MCU_BIU_EVENT0_CON      (MCU_BIU_BASE + 0x58)
  15 #define MCU_BIU_EVENT0_OVFL     (MCU_BIU_BASE + 0x5C)
  16 #define MCU_BIU_EVENT1_SEL      (MCU_BIU_BASE + 0x60)
  17 #define MCU_BIU_EVENT1_CNT      (MCU_BIU_BASE + 0x64)
  18 #define MCU_BIU_EVENT1_CON      (MCU_BIU_BASE + 0x68)
  19 #define MCU_BIU_EVENT1_OVFL     (MCU_BIU_BASE + 0x6C)
  20
  21 #define MCUSYS_CA7_CACHE_CONFIG         (MCUSYS_CFGREG_BASE + 0x000)
  22 #define MCUSYS_CPU0_MEM_DELSEL          (MCUSYS_CFGREG_BASE + 0x004)
  23 #define MCUSYS_CPU1_MEM_DELSEL          (MCUSYS_CFGREG_BASE + 0x008)
  24 #define MCUSYS_CPU2_MEM_DELSEL          (MCUSYS_CFGREG_BASE + 0x00C)
  25 #define MCUSYS_CPU3_MEM_DELSEL          (MCUSYS_CFGREG_BASE + 0x010)
  26 #define MCUSYS_CACHE_MEM_DELSEL         (MCUSYS_CFGREG_BASE + 0x014)
  27 #define MCUSYS_AXI_CONFIG               (MCUSYS_CFGREG_BASE + 0x020)
  28 #define MCUSYS_MISC_CONFIG0             (MCUSYS_CFGREG_BASE + 0x024)
  29 #define MCUSYS_MISC_CONFIG1             (MCUSYS_CFGREG_BASE + 0x028)
  30 #define MCUSYS_CA7_CFG_DIS              (MCUSYS_CFGREG_BASE + 0x050)
  31 #define MCUSYS_CA7_CLKEN_CTRL           (MCUSYS_CFGREG_BASE + 0x054)
  32 #define MCUSYS_CA7_RST_CTRL             (MCUSYS_CFGREG_BASE + 0x058)
  33 #define MCUSYS_CA7_MISC_CONFIG          (MCUSYS_CFGREG_BASE + 0x05C)
  34 #define MCUSYS_ACLKEN_DIV               (MCUSYS_CFGREG_BASE + 0x060)
  35 #define MCUSYS_PCLKEN_DIV               (MCUSYS_CFGREG_BASE + 0x064)
  36 #define MCUSYS_MEM_PWR_CTRL             (MCUSYS_CFGREG_BASE + 0x068)
  37 #define MCUSYS_ARMPLL_DIV_CTRL          (MCUSYS_CFGREG_BASE + 0x06C)
  38 #define MCUSYS_RST_STATUS               (MCUSYS_CFGREG_BASE + 0x070)
  39 #define MCUSYS_DBG_CTRL                 (MCUSYS_CFGREG_BASE + 0x080)
  40 #define MCUSYS_DBG_FLAG                 (MCUSYS_CFGREG_BASE + 0x084)
  41 #define MCUSYS_AP_BANK4_MAP_UPDATE      (MCUSYS_CFGREG_BASE + 0x090)
  42 #define MCUSYS_RW_RSVD1                 (MCUSYS_CFGREG_BASE + 0x094)
  43 #define MCUSYS_RO_RSVD                  (MCUSYS_CFGREG_BASE + 0x098)
  44 #define MCUSYS_INT_POL_CTL0             (MCUSYS_CFGREG_BASE + 0x100)
  45 #define MCUSYS_INT_POL_CTL1             (MCUSYS_CFGREG_BASE + 0x104)
  46 #define MCUSYS_INT_POL_CTL2             (MCUSYS_CFGREG_BASE + 0x108)
  47 #define MCUSYS_INT_POL_CTL3             (MCUSYS_CFGREG_BASE + 0x10C)
  48 #define MCUSYS_INT_POL_CTL4             (MCUSYS_CFGREG_BASE + 0x110)
  49 #define MCUSYS_INT_POL_CTL5             (MCUSYS_CFGREG_BASE + 0x114)
  50 #define MCUSYS_INT_POL_CTL6             (MCUSYS_CFGREG_BASE + 0x118)
  51 #define MCUSYS_AP_BANK4_MAP0            (MCUSYS_CFGREG_BASE + 0x200)
  52 #define MCUSYS_AP_BANK4_MAP1            (MCUSYS_CFGREG_BASE + 0x204)
  53 #define MCUSYS_BUS_SYNC_SEL             (MCUSYS_CFGREG_BASE + 0x208)
  54 #define MCUSYS_CA7_IR_MON               (MCUSYS_CFGREG_BASE + 0x20C)
  55 #define MCUSYS_DBG_CORE0_PC             (MCUSYS_CFGREG_BASE + 0x300)
  56 #define MCUSYS_DBG_CORE0_FP             (MCUSYS_CFGREG_BASE + 0x304)
  57 #define MCUSYS_DBG_CORE0_SP             (MCUSYS_CFGREG_BASE + 0x308)
  58 #define MCUSYS_DBG_CORE1_PC             (MCUSYS_CFGREG_BASE + 0x310)
  59 #define MCUSYS_DBG_CORE1_FP             (MCUSYS_CFGREG_BASE + 0x314)
  60 #define MCUSYS_DBG_CORE1_SP             (MCUSYS_CFGREG_BASE + 0x318)
  61 #define MCUSYS_DBG_CORE2_PC             (MCUSYS_CFGREG_BASE + 0x320)
  62 #define MCUSYS_DBG_CORE2_FP             (MCUSYS_CFGREG_BASE + 0x324)
  63 #define MCUSYS_DBG_CORE2_SP             (MCUSYS_CFGREG_BASE + 0x328)
  64 #define MCUSYS_DBG_CORE3_PC             (MCUSYS_CFGREG_BASE + 0x330)
  65 #define MCUSYS_DBG_CORE3_FP             (MCUSYS_CFGREG_BASE + 0x334)
  66 #define MCUSYS_DBG_CORE3_SP             (MCUSYS_CFGREG_BASE + 0x338)
  67 #define MCUSYS_DFD_CTRL                 (MCUSYS_CFGREG_BASE + 0x400)
  68 #define MCUSYS_DFD_CNT_L                (MCUSYS_CFGREG_BASE + 0x404)
  69 #define MCUSYS_DFD_CNT_H                (MCUSYS_CFGREG_BASE + 0x408)
  70
  71 /*
  72  * Define constants.
  73  */
  74
  75
  76 /*
  77  * Define function prototypes.
  78  */
  79 #endif  /*!__MCU_H__ */