import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / include / mach / mt_gpufreq.h
1 #ifndef _MT_GPUFREQ_H
2 #define _MT_GPUFREQ_H
3
4 #include <linux/module.h>
5
6 /*********************
7 * Clock Mux Register
8 **********************/
9 #define CLK26CALI (0xF00001C0) // FIX ME, No this register
10 #define CLK_MISC_CFG_0 (0xF0000210)
11 #define CLK_MISC_CFG_1 (0xF0000214)
12 #define CLK26CALI_0 (0xF0000220)
13 #define CLK26CALI_1 (0xF0000224)
14 #define CLK26CALI_2 (0xF0000228)
15 #define MBIST_CFG_0 (0xF0000308)
16 #define MBIST_CFG_1 (0xF000030C)
17 #define MBIST_CFG_2 (0xF0000310)
18 #define MBIST_CFG_3 (0xF0000314)
19
20 /*********************
21 * GPU Frequency List
22 **********************/
23 #define GPU_DVFS_F1 (476666) // KHz
24 #define GPU_DVFS_F2 (403000) // KHz
25 #define GPU_DVFS_F3 (357500) // KHz
26 #define GPU_DVFS_F4 (312000) // KHz
27 #define GPU_DVFS_F5 (286000) // KHz
28 #define GPU_DVFS_F6 (268666) // KHz
29 #define GPU_DVFS_F7 (238333) // KHz
30 #define GPU_DVFS_F8 (156000) // KHz
31
32 /**************************
33 * MFG Clock Mux Selection
34 ***************************/
35 #define GPU_MMPLL_D3 (GPU_DVFS_F1)
36 #define GPU_SYSPLL_D2 (GPU_DVFS_F2)
37 #define GPU_MMPLL_D4 (GPU_DVFS_F3)
38 #define GPU_UNIVPLL1_D2 (GPU_DVFS_F4)
39 #define GPU_MMPLL_D5 (GPU_DVFS_F5)
40 #define GPU_SYSPLL_D3 (GPU_DVFS_F6)
41 #define GPU_MMPLL_D6 (GPU_DVFS_F7)
42 #define GPU_UNIVPLL1_D4 (GPU_DVFS_F8)
43
44 /******************************
45 * MFG Power Voltage Selection
46 *******************************/
47 #define GPU_POWER_VCORE_1_05V (64)
48 #define GPU_POWER_VRF18_1_05V (0)
49 #define GPU_POWER_VRF18_1_10V (2)
50 #define GPU_POWER_VRF18_1_15V (4)
51
52 /*****************************************
53 * PMIC settle time, should not be changed
54 ******************************************/
55 #define PMIC_SETTLE_TIME (40) // us
56
57
58 /****************************************************************
59 * enable this option to calculate clock on ration in period time.
60 *****************************************************************/
61 #define GPU_CLOCK_RATIO
62 #ifdef GPU_CLOCK_RATIO
63 #define GPU_COUNT_OVERFLOW 1000000 // 1 sec
64 #endif
65
66 /****************************************************************
67 * Default disable gpu dvfs.
68 *****************************************************************/
69 //#define GPU_DVFS_DEFAULT_DISABLED
70
71
72 /********************************************
73 * enable this option to adjust buck voltage
74 *********************************************/
75 #define MT_BUCK_ADJUST
76
77 struct mt_gpufreq_info
78 {
79 unsigned int gpufreq_khz;
80 unsigned int gpufreq_lower_bound;
81 unsigned int gpufreq_upper_bound;
82 unsigned int gpufreq_volt;
83 unsigned int gpufreq_remap;
84 };
85
86 struct mt_gpufreq_power_info
87 {
88 unsigned int gpufreq_khz;
89 unsigned int gpufreq_power;
90 };
91
92 #ifdef GPU_CLOCK_RATIO
93 /* GPU DVFS clock on ratio */
94 enum mt_gpufreq_clock_ratio {
95 GPU_DVFS_CLOCK_RATIO_OFF = 0, /* GPU clock turned off */
96 GPU_DVFS_CLOCK_RATIO_ON , /* GPU clock turned on */
97 GPU_DVFS_CLOCK_RATIO_GET /* Get GPU clock on ratio in a period time */
98 };
99 #endif
100
101 /*****************
102 * extern function
103 ******************/
104 extern int mt_gpufreq_state_set(int enabled);
105 extern void mt_gpufreq_thermal_protect(unsigned int limited_power);
106 extern int mt_gpufreq_register(struct mt_gpufreq_info *freqs, int num);
107 extern bool mt_gpufreq_is_registered_get(void);
108 #ifdef GPU_CLOCK_RATIO
109 extern unsigned int mt_gpufreq_gpu_clock_ratio(enum mt_gpufreq_clock_ratio act);
110 #endif
111 extern unsigned int mt_gpufreq_cur_freq(void);
112 extern unsigned int mt_gpufreq_cur_load(void);
113 extern int mt_gpufreq_non_register(void);
114 extern void mt_gpufreq_set_initial(unsigned int freq_new, unsigned int volt_new);
115 #endif