arch/arm/mach-mt8127/include/mach/mt_fhreg.h

   1 #ifndef __MT_FHREG_H__
   2 #define __MT_FHREG_H__
   3
   4 #include <linux/bitops.h>
   5 #include <mach/mt_reg_base.h>
   6
   7
   8 /*--------------------------------------------------------------------------*/
   9 /* Common Macro                                                             */
  10 /*--------------------------------------------------------------------------*/
  11 //#define REG_ADDR(x)                 ((volatile u32*)(FHCTL_BASE + OFFSET_##x))
  12 #define REG_ADDR(x)                 (FHCTL_BASE + OFFSET_##x)
  13
  14
  15 #define OFFSET_FHDMA_CFG                   0x0000
  16 #define OFFSET_FHDMA_2G1BASE           0x0004
  17 #define OFFSET_FHDMA_2G2BASE           0x0008
  18 #define OFFSET_FHDMA_INTMDBASE         0x000C
  19 #define OFFSET_FHDMA_EXTMDBASE         0x0010
  20 #define OFFSET_FHDMA_BTBASE            0x0014
  21 #define OFFSET_FHDMA_WFBASE            0x0018
  22 #define OFFSET_FHDMA_FMBASE            0x001C
  23 #define OFFSET_FHSRAM_CON                  0x0020
  24 #define OFFSET_FHSRAM_WR               0x0024
  25 #define OFFSET_FHSRAM_RD               0x0028
  26 #define OFFSET_FHCTL_CFG                   0x002C
  27
  28 #define OFFSET_FHCTL_CON                   0x0030
  29
  30 #define OFFSET_FHCTL_2G1_CH            0x0034
  31 #define OFFSET_FHCTL_2G2_CH            0x0038
  32 #define OFFSET_FHCTL_INTMD_CH          0x003C
  33 #define OFFSET_FHCTL_EXTMD_CH          0x0040
  34 #define OFFSET_FHCTL_BT_CH             0x0044
  35 #define OFFSET_FHCTL_WF_CH             0x0048
  36 #define OFFSET_FHCTL_FM_CH             0x004C
  37 #define OFFSET_FHCTL0_CFG                  0x0050
  38 #define OFFSET_FHCTL0_UPDNLMT          0x0054
  39 #define OFFSET_FHCTL0_DDS                  0x0058
  40 #define OFFSET_FHCTL0_DVFS                 0x005C
  41 #define OFFSET_FHCTL0_MON                  0x0060
  42
  43 #define OFFSET_FHCTL1_CFG                  0x0064
  44 #define OFFSET_FHCTL1_UPDNLMT          0x0068
  45 #define OFFSET_FHCTL1_DDS                  0x006C
  46 #define OFFSET_FHCTL1_DVFS                 0x0070
  47 #define OFFSET_FHCTL1_MON                  0x0074
  48
  49 #define OFFSET_FHCTL2_CFG                  0x0078
  50 #define OFFSET_FHCTL2_UPDNLMT          0x007C
  51 #define OFFSET_FHCTL2_DDS                  0x0080
  52 #define OFFSET_FHCTL2_DVFS                 0x0084
  53 #define OFFSET_FHCTL2_MON                  0x0088
  54
  55 #define OFFSET_FHCTL3_CFG                  0x008C
  56 #define OFFSET_FHCTL3_UPDNLMT          0x0090
  57 #define OFFSET_FHCTL3_DDS                  0x0094
  58 #define OFFSET_FHCTL3_DVFS                 0x0098
  59 #define OFFSET_FHCTL3_MON                  0x009C
  60
  61 #define OFFSET_FHCTL4_CFG                  0x00A0
  62 #define OFFSET_FHCTL4_UPDNLMT          0x00A4
  63 #define OFFSET_FHCTL4_DDS                  0x00A8
  64 #define OFFSET_FHCTL4_DVFS                 0x00AC
  65 #define OFFSET_FHCTL4_MON                  0x00B0
  66
  67 #define OFFSET_FHCTL5_CFG                  0x00B4
  68 #define OFFSET_FHCTL5_UPDNLMT          0x00B8
  69 #define OFFSET_FHCTL5_DDS                  0x00BC
  70 #define OFFSET_FHCTL5_DVFS                 0x00C0
  71 #define OFFSET_FHCTL5_MON              0x00C4
  72
  73 /* 8127 FHCTL MB */
  74 #define OFFSET_FHCTL6_CFG                  0x00C8
  75 #define OFFSET_FHCTL6_UPDNLMT          0x00CC
  76 #define OFFSET_FHCTL6_DDS                  0x00D0
  77 #define OFFSET_FHCTL6_DVFS                 0x00D4
  78 #define OFFSET_FHCTL6_MON              0x00D8
  79
  80 #define OFFSET_FHCTL7_CFG                  0x00DC
  81 #define OFFSET_FHCTL7_UPDNLMT          0x00E0
  82 #define OFFSET_FHCTL7_DDS                  0x00E4
  83 #define OFFSET_FHCTL7_DVFS                 0x00E8
  84 #define OFFSET_FHCTL7_MON              0x00EC
  85 /* 8127 FHCTL ME */
  86
  87 #define FH_SFSTRX_DYS  (0xFU<<20)
  88 #define FH_SFSTRX_DTS  (0xFU<<16)
  89 #define FH_FHCTLX_SRHMODE  (0x1U<<5)
  90 #define FH_SFSTRX_BP  (0x1U<<4)
  91 #define FH_SFSTRX_EN  (0x1U<<2)
  92 #define FH_FRDDSX_EN  (0x1U<<1)
  93 #define FH_FHCTLX_EN  (0x1U<<0)
  94 #define FH_FRDDSX_DNLMT   (0xFFU<<16)
  95 #define FH_FRDDSX_UPLMT  (0xFFU)
  96 #define FH_FHCTLX_PLL_TGL_ORG  (0x1U<<31)
  97 #define FH_FHCTLX_PLL_ORG  (0xFFFFFU)
  98 #define FH_FHCTLX_PAUSE  (0x1U<<31)
  99 #define FH_FHCTLX_PRD  (0x1U<<30)
 100 #define FH_SFSTRX_PRD  (0x1U<<29)
 101 #define FH_FRDDSX_PRD (0x1U<<28)
 102 #define FH_FHCTLX_STATE  (0xFU<<24)
 103 #define FH_FHCTLX_PLL_CHG  (0x1U<<21)
 104 #define FH_FHCTLX_PLL_DDS  (0xFFFFFU)
 105
 106 #define REG_FHDMA_CFG              REG_ADDR(FHDMA_CFG)
 107 #define REG_FHDMA_2G1BASE        REG_ADDR(FHDMA_2G1BASE)
 108 #define REG_FHDMA_2G2BASE        REG_ADDR(FHDMA_2G2BASE)
 109 #define REG_FHDMA_INTMDBASE      REG_ADDR(FHDMA_INTMDBASE)
 110 #define REG_FHDMA_EXTMDBASE      REG_ADDR(FHDMA_EXTMDBASE)
 111 #define REG_FHDMA_BTBASE         REG_ADDR(FHDMA_BTBASE)
 112 #define REG_FHDMA_WFBASE         REG_ADDR(FHDMA_WFBASE)
 113 #define REG_FHDMA_FMBASE         REG_ADDR(FHDMA_FMBASE)
 114 #define REG_FHSRAM_CON           REG_ADDR(FHSRAM_CON)
 115 #define REG_FHSRAM_WR            REG_ADDR(FHSRAM_WR)
 116 #define REG_FHSRAM_RD            REG_ADDR(FHSRAM_RD)
 117 #define REG_FHCTL_CFG              REG_ADDR(FHCTL_CFG)
 118 #define REG_FHCTL_CON              REG_ADDR(FHCTL_CON)
 119 #define REG_FHCTL_2G1_CH         REG_ADDR(FHCTL_2G1_CH)
 120 #define REG_FHCTL_2G2_CH         REG_ADDR(FHCTL_2G2_CH)
 121 #define REG_FHCTL_INTMD_CH       REG_ADDR(FHCTL_INTMD_CH)
 122 #define REG_FHCTL_EXTMD_CH       REG_ADDR(FHCTL_EXTMD_CH)
 123 #define REG_FHCTL_BT_CH          REG_ADDR(FHCTL_BT_CH)
 124 #define REG_FHCTL_WF_CH          REG_ADDR(FHCTL_WF_CH)
 125 #define REG_FHCTL_FM_CH          REG_ADDR(FHCTL_FM_CH)
 126 #define REG_FHCTL0_CFG           REG_ADDR(FHCTL0_CFG)
 127 #define REG_FHCTL0_UPDNLMT           REG_ADDR(FHCTL0_UPDNLMT)
 128 #define REG_FHCTL0_DDS           REG_ADDR(FHCTL0_DDS)
 129 #define REG_FHCTL0_DVFS          REG_ADDR(FHCTL0_DVFS)
 130 #define REG_FHCTL0_MON           REG_ADDR(FHCTL0_MON)
 131 #define REG_FHCTL1_CFG           REG_ADDR(FHCTL1_CFG)
 132 #define REG_FHCTL1_UPDNLMT           REG_ADDR(FHCTL1_UPDNLMT)
 133 #define REG_FHCTL1_DDS           REG_ADDR(FHCTL1_DDS)
 134 #define REG_FHCTL1_DVFS          REG_ADDR(FHCTL1_DVFS)
 135 #define REG_FHCTL1_MON           REG_ADDR(FHCTL1_MON)
 136 #define REG_FHCTL2_CFG           REG_ADDR(FHCTL2_CFG)
 137 #define REG_FHCTL2_UPDNLMT           REG_ADDR(FHCTL2_UPDNLMT)
 138 #define REG_FHCTL2_DDS           REG_ADDR(FHCTL2_DDS)
 139 #define REG_FHCTL2_DVFS          REG_ADDR(FHCTL2_DVFS)
 140 #define REG_FHCTL2_MON           REG_ADDR(FHCTL2_MON)
 141 #define REG_FHCTL3_CFG           REG_ADDR(FHCTL3_CFG)
 142 #define REG_FHCTL3_UPDNLMT           REG_ADDR(FHCTL3_UPDNLMT)
 143 #define REG_FHCTL3_DDS           REG_ADDR(FHCTL3_DDS)
 144 #define REG_FHCTL3_DVFS          REG_ADDR(FHCTL3_DVFS)
 145 #define REG_FHCTL3_MON           REG_ADDR(FHCTL3_MON)
 146 #define REG_FHCTL4_CFG           REG_ADDR(FHCTL4_CFG)
 147 #define REG_FHCTL4_UPDNLMT       REG_ADDR(FHCTL4_UPDNLMT)
 148 #define REG_FHCTL4_DDS           REG_ADDR(FHCTL4_DDS)
 149 #define REG_FHCTL4_DVFS          REG_ADDR(FHCTL4_DVFS)
 150 #define REG_FHCTL4_MON           REG_ADDR(FHCTL4_MON)
 151 #define REG_FHCTL5_CFG           REG_ADDR(FHCTL5_CFG)
 152 #define REG_FHCTL5_UPDNLMT           REG_ADDR(FHCTL5_UPDNLMT)
 153 #define REG_FHCTL5_DDS           REG_ADDR(FHCTL5_DDS)
 154 #define REG_FHCTL5_DVFS          REG_ADDR(FHCTL5_DVFS)
 155 #define REG_FHCTL5_MON           REG_ADDR(FHCTL5_MON)
 156 /* 8127 FHCTL MB */
 157 #define REG_FHCTL6_CFG           REG_ADDR(FHCTL6_CFG)
 158 #define REG_FHCTL6_UPDNLMT           REG_ADDR(FHCTL6_UPDNLMT)
 159 #define REG_FHCTL6_DDS           REG_ADDR(FHCTL6_DDS)
 160 #define REG_FHCTL6_DVFS          REG_ADDR(FHCTL6_DVFS)
 161 #define REG_FHCTL6_MON           REG_ADDR(FHCTL6_MON)
 162 #define REG_FHCTL7_CFG           REG_ADDR(FHCTL7_CFG)
 163 #define REG_FHCTL7_UPDNLMT           REG_ADDR(FHCTL7_UPDNLMT)
 164 #define REG_FHCTL7_DDS           REG_ADDR(FHCTL7_DDS)
 165 #define REG_FHCTL7_DVFS          REG_ADDR(FHCTL7_DVFS)
 166 #define REG_FHCTL7_MON           REG_ADDR(FHCTL7_MON)
 167 /* 8127 FHCTL ME */
 168
 169 static inline unsigned int uffs(unsigned int x)
 170 {
 171     unsigned int r = 1;
 172
 173     if (!x)
 174         return 0;
 175     if (!(x & 0xffff)) {
 176         x >>= 16;
 177         r += 16;
 178     }
 179     if (!(x & 0xff)) {
 180         x >>= 8;
 181         r += 8;
 182     }
 183     if (!(x & 0xf)) {
 184         x >>= 4;
 185         r += 4;
 186     }
 187     if (!(x & 3)) {
 188         x >>= 2;
 189         r += 2;
 190     }
 191     if (!(x & 1)) {
 192         x >>= 1;
 193         r += 1;
 194     }
 195     return r;
 196 }
 197 #define fh_read8(reg)           readb(reg)
 198 #define fh_read16(reg)          readw(reg)
 199 #define fh_read32(reg)          readl((void __iomem *)reg)
 200 #define fh_write8(reg,val)      mt65xx_reg_sync_writeb((val),(reg))
 201 #define fh_write16(reg,val)     mt65xx_reg_sync_writew((val),(reg))
 202 #define fh_write32(reg,val)     mt65xx_reg_sync_writel((val),(reg))
 203
 204 //#define fh_set_bits(reg,bs)     ((*(volatile u32*)(reg)) |= (u32)(bs))
 205 //#define fh_clr_bits(reg,bs)     ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
 206
 207 #define fh_set_field(reg,field,val) \
 208     do {        \
 209         volatile unsigned int tv = fh_read32(reg);      \
 210         tv &= ~(field); \
 211         tv |= ((val) << (uffs((unsigned int)field) - 1)); \
 212         fh_write32(reg,tv); \
 213     } while(0)
 214 #define fh_get_field(reg,field,val) \
 215     do {        \
 216         volatile unsigned int tv = fh_read32(reg);      \
 217         val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
 218     } while(0)
 219
 220
 221
 222 #endif //#ifndef __MT_FHREG_H__
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