arch/arm/mach-mt8127/include/mach/mt_emi_bwl.h

   1 #ifndef __MT6575_EMI_BW_LIMITER__
   2 #define __MT6575_EMI_BW_LIMITER__
   3
   4 /*
   5  * Define EMI hardware registers.
   6  */
   7
   8 #define EMI_CONA    (EMI_BASE + 0x0000)
   9 #define EMI_CONB    (EMI_BASE + 0x0008)
  10 #define EMI_CONC    (EMI_BASE + 0x0010)
  11 #define EMI_COND    (EMI_BASE + 0x0018)
  12 #define EMI_CONE    (EMI_BASE + 0x0020)
  13 #define EMI_ARBA    (EMI_BASE + 0x0100)
  14 #define EMI_ARBB    (EMI_BASE + 0x0108)
  15 #define EMI_ARBC    (EMI_BASE + 0x0110)
  16 #define EMI_ARBD    (EMI_BASE + 0x0118)
  17 #define EMI_ARBE    (EMI_BASE + 0x0120)
  18 #define EMI_ARBF    (EMI_BASE + 0x0128)
  19 #define EMI_ARBG    (EMI_BASE + 0x0130)
  20 #define EMI_ARBI    (EMI_BASE + 0x0140)
  21 #define EMI_ARBJ    (EMI_BASE + 0x0148)
  22 #define EMI_ARBK    (EMI_BASE + 0x0150)
  23 #define EMI_SLCT    (EMI_BASE + 0x0158)
  24
  25 /*
  26  * Define constants.
  27  */
  28
  29 /* define concurrency scenario ID */
  30 enum
  31 {
  32 #define X_CON_SCE(con_sce, arba, arbc, arbd, arbe, arbf, arbg) con_sce,
  33 #include "mach/mt6575_con_sce.h"
  34 #undef X_CON_SCE
  35     NR_CON_SCE
  36 };
  37
  38 /* define control operation */
  39 enum
  40 {
  41     ENABLE_CON_SCE = 0,
  42     DISABLE_CON_SCE = 1
  43 };
  44
  45 #define EN_CON_SCE_STR "ON"
  46 #define DIS_CON_SCE_STR "OFF"
  47
  48 /*
  49  * Define data structures.
  50  */
  51
  52 /* define control table entry */
  53 struct emi_bwl_ctrl
  54 {
  55     unsigned int ref_cnt;
  56 };
  57
  58 /*
  59  * Define function prototype.
  60  */
  61
  62 extern int mtk_mem_bw_ctrl(int sce, int op);
  63
  64 #endif  /* !__MT6575_EMI_BWL_H__ */
  65