4 #include "mach/mt_reg_base.h"
7 #define CAM_BASE 0xF5004000
11 #define PERI_USB0_DCM (USB_BASE+0x700)
14 #define MSDC0_IP_DCM (MSDC_0_BASE + 0x00B4)
17 #define MSDC1_IP_DCM (MSDC_1_BASE + 0x00B4)
20 #define MSDC2_IP_DCM (MSDC_2_BASE + 0x00B4)
22 /* APB Module pmic_wrap */
23 #define PMIC_WRAP_DCM_EN (PWRAP_BASE+0x13C)
27 #define I2C0_I2CREG_HW_CG_EN ((I2C0_BASE+0x054))
30 #define I2C1_I2CREG_HW_CG_EN ((I2C1_BASE+0x054))
33 #define I2C2_I2CREG_HW_CG_EN ((I2C2_BASE+0x054))
37 #define CA7_MISC_CONFIG (MCUSYS_CFGREG_BASE + 0x005C)
38 #define MCU_BIU_CON (MCUSYS_CFGREG_BASE + 0x8000)
42 #define DCM_CFG (INFRA_BASE + 0x0004)
43 #define CLK_SCP_CFG_0 (INFRA_BASE + 0x0200)
44 #define CLK_SCP_CFG_1 (INFRA_BASE + 0x0204)
47 #define TOP_CKDIV1 (INFRACFG_AO_BASE + 0x0008)
48 #define TOP_DCMCTL (INFRACFG_AO_BASE + 0x0010)
49 #define TOP_DCMDBC (INFRACFG_AO_BASE + 0x0014)
52 #define INFRA_DCMCTL (INFRACFG_AO_BASE + 0x0050)
53 #define INFRA_DCMDBC (INFRACFG_AO_BASE + 0x0054)
54 #define INFRA_DCMFSEL (INFRACFG_AO_BASE + 0x0058)
58 #define PERI_GLOBALCON_DCMCTL (PERICFG_BASE + 0x0050)
59 #define PERI_GLOBALCON_DCMDBC (PERICFG_BASE + 0x0054)
60 #define PERI_GLOBALCON_DCMFSEL (PERICFG_BASE + 0x0058)
63 #define DRAMC_PD_CTRL (DRAMC0_BASE + 0x01DC)
66 #define MMU_DCM (SMI_MMU_TOP_BASE+0x5f0)
69 #define SMI_DCM_CONTROL 0xF4011300
73 #define SMI_COMMON_AO_SMI_CON (SMI1_BASE+0x010)
74 #define SMI_COMMON_AO_SMI_CON_SET (SMI1_BASE+0x014)
75 #define SMI_COMMON_AO_SMI_CON_CLR (SMI1_BASE+0x018)
79 /* APB Module smi_larb */
80 #define SMILARB0_DCM_STA (SMI_LARB0_BASE + 0x00)
81 #define SMILARB0_DCM_CON (SMI_LARB0_BASE + 0x10)
82 #define SMILARB0_DCM_SET (SMI_LARB0_BASE + 0x14)
83 #define SMILARB0_DCM_CLR (SMI_LARB0_BASE + 0x18)
85 #define SMILARB1_DCM_STA (SMI_LARB1_BASE + 0x00)
86 #define SMILARB1_DCM_CON (SMI_LARB1_BASE + 0x10)
87 #define SMILARB1_DCM_SET (SMI_LARB1_BASE + 0x14)
88 #define SMILARB1_DCM_CLR (SMI_LARB1_BASE + 0x18)
90 #define SMILARB2_DCM_STA (SMI_LARB3_BASE + 0x00)
91 #define SMILARB2_DCM_CON (SMI_LARB3_BASE + 0x10)
92 #define SMILARB2_DCM_SET (SMI_LARB3_BASE + 0x14)
93 #define SMILARB2_DCM_CLR (SMI_LARB3_BASE + 0x18)
97 #define MFG_DCM_CON_0 (G3D_CONFIG_BASE + 0x10)
100 #define CAM_CTL_RAW_DCM (CAM_BASE + 0x190)
101 #define CAM_CTL_RGB_DCM (CAM_BASE + 0x194)
102 #define CAM_CTL_YUV_DCM (CAM_BASE + 0x198)
103 #define CAM_CTL_CDP_DCM (CAM_BASE + 0x19C)
104 #define CAM_CTL_DMA_DCM (CAM_BASE + 0x1B0)
106 #define CAM_CTL_RAW_DCM_STA (CAM_BASE + 0x1A0)
107 #define CAM_CTL_RGB_DCM_STA (CAM_BASE + 0x1A4)
108 #define CAM_CTL_YUV_DCM_STA (CAM_BASE + 0x1A8)
109 #define CAM_CTL_CDP_DCM_STA (CAM_BASE + 0x1AC)
110 #define CAM_CTL_DMA_DCM_STA (CAM_BASE + 0x1B4)
113 #define JPGENC_DCM_CTRL (JPGENC_BASE + 0x300)
117 #define DISP_HW_DCM_DIS0 (DISPSYS_BASE + 0x120)
118 #define DISP_HW_DCM_DIS_SET0 (DISPSYS_BASE + 0x124)
119 #define DISP_HW_DCM_DIS_CLR0 (DISPSYS_BASE + 0x128)
121 #define DISP_HW_DCM_DIS1 (DISPSYS_BASE + 0x12C)
122 #define DISP_HW_DCM_DIS_SET1 (DISPSYS_BASE + 0x130)
123 #define DISP_HW_DCM_DIS_CLR1 (DISPSYS_BASE + 0x134)
126 #define VENC_CE (VENC_BASE + 0xEC)
127 #define VENC_CLK_DCM_CTRL (VENC_BASE + 0xF4)
128 #define VENC_CLK_CG_CTRL (VENC_BASE + 0x94)
131 #define VDEC_DCM_CON (VDEC_GCON_BASE + 0x18)
134 #define CPU_DCM (1U << 0)
135 #define IFR_DCM (1U << 1)
136 #define PER_DCM (1U << 2)
137 #define SMI_DCM (1U << 3)
138 #define MFG_DCM (1U << 4)
139 #define DIS_DCM (1U << 5)
140 #define ISP_DCM (1U << 6)
141 #define VDE_DCM (1U << 7)
142 #define TOPCKGEN_DCM (1U << 8)
143 #define ALL_DCM (CPU_DCM|IFR_DCM|PER_DCM|SMI_DCM|MFG_DCM|DIS_DCM|ISP_DCM|VDE_DCM|TOPCKGEN_DCM)
144 #define NR_DCMS (0x9)
147 extern void dcm_enable(unsigned int type
);
148 extern void dcm_disable(unsigned int type
);
150 extern void bus_dcm_enable(void);
151 extern void bus_dcm_disable(void);
153 extern void disable_infra_dcm(void);
154 extern void restore_infra_dcm(void);
156 extern void disable_peri_dcm(void);
157 extern void restore_peri_dcm(void);
159 extern void mt_dcm_init(void);