arch/arm/mach-mt8127/include/mach/mt_cpufreq.h

   1 #ifndef _MT_CPUFREQ_H
   2 #define _MT_CPUFREQ_H
   3
   4 #include <linux/module.h>
   5
   6 /*********************
   7 * Clock Mux Register
   8 **********************/
   9 #define TOP_CKMUXSEL    (0xF0001000)
  10 #define TOP_CKDIV1_CPU  (0xF0001008)
  11
  12 /****************************
  13 * PMIC Wrapper DVFS Register
  14 *****************************/
  15 #define PWRAP_BASE              (0xF000D000)
  16 #define PMIC_WRAP_DVFS_ADR0     (PWRAP_BASE + 0xE4)
  17 #define PMIC_WRAP_DVFS_WDATA0   (PWRAP_BASE + 0xE8)
  18 #define PMIC_WRAP_DVFS_ADR1     (PWRAP_BASE + 0xEC)
  19 #define PMIC_WRAP_DVFS_WDATA1   (PWRAP_BASE + 0xF0)
  20 #define PMIC_WRAP_DVFS_ADR2     (PWRAP_BASE + 0xF4)
  21 #define PMIC_WRAP_DVFS_WDATA2   (PWRAP_BASE + 0xF8)
  22 #define PMIC_WRAP_DVFS_ADR3     (PWRAP_BASE + 0xFC)
  23 #define PMIC_WRAP_DVFS_WDATA3   (PWRAP_BASE + 0x100)
  24 #define PMIC_WRAP_DVFS_ADR4     (PWRAP_BASE + 0x104)
  25 #define PMIC_WRAP_DVFS_WDATA4   (PWRAP_BASE + 0x108)
  26 #define PMIC_WRAP_DVFS_ADR5     (PWRAP_BASE + 0x10C)
  27 #define PMIC_WRAP_DVFS_WDATA5   (PWRAP_BASE + 0x110)
  28 #define PMIC_WRAP_DVFS_ADR6     (PWRAP_BASE + 0x114)
  29 #define PMIC_WRAP_DVFS_WDATA6   (PWRAP_BASE + 0x118)
  30 #define PMIC_WRAP_DVFS_ADR7     (PWRAP_BASE + 0x11C)
  31 #define PMIC_WRAP_DVFS_WDATA7   (PWRAP_BASE + 0x120)
  32
  33 /*****************
  34 * extern function
  35 ******************/
  36 extern int mt_cpufreq_state_set(int enabled);
  37 extern void mt_cpufreq_thermal_protect(unsigned int limited_power);
  38 void mt_cpufreq_enable_by_ptpod(void);
  39 unsigned int mt_cpufreq_disable_by_ptpod(void);
  40 extern unsigned int mt_cpufreq_max_frequency_by_DVS(unsigned int num);
  41 void mt_cpufreq_return_default_DVS_by_ptpod(void);
  42 extern bool mt_cpufreq_earlysuspend_status_get(void);
  43
  44
  45 /*****************
  46 * dummy type define for kernel 3.10
  47 ******************/
  48 enum mt_cpu_dvfs_id {
  49
  50 #ifdef MTK_FORCE_CLUSTER1
  51         MT_CPU_DVFS_BIG,
  52         MT_CPU_DVFS_LITTLE,
  53 #else
  54         MT_CPU_DVFS_LITTLE,
  55         MT_CPU_DVFS_BIG,
  56 #endif
  57
  58         NR_MT_CPU_DVFS,
  59 };
  60
  61 #endif