arch/arm/mach-mt8127/include/mach/mt_clkmgr.h

   1 #ifndef _MT_CLKMGR_H
   2 #define _MT_CLKMGR_H
   3
   4
   5 /* clkmgr constants */
   6
   7 enum {
   8         CG_PERI0,
   9         CG_PERI1,
  10         CG_INFRA,
  11         CG_TOPCK,
  12         CG_DISP0,
  13         CG_DISP1,
  14         CG_IMAGE,
  15         CG_MFG,
  16         CG_AUDIO,
  17         CG_VDEC0,
  18         CG_VDEC1,
  19         NR_GRPS,
  20 };
  21
  22
  23 enum cg_clk_id {
  24         MT_CG_PERI_NFI,
  25         MT_CG_PERI_THERM,
  26         MT_CG_PERI_PWM1,
  27         MT_CG_PERI_PWM2,
  28         MT_CG_PERI_PWM3,
  29         MT_CG_PERI_PWM4,
  30         MT_CG_PERI_PWM5,
  31         MT_CG_PERI_PWM6,
  32         MT_CG_PERI_PWM7,
  33         MT_CG_PERI_PWM,
  34         MT_CG_PERI_USB0,
  35         MT_CG_PERI_USB1,
  36         MT_CG_PERI_AP_DMA,
  37         MT_CG_PERI_MSDC30_0,
  38         MT_CG_PERI_MSDC30_1,
  39         MT_CG_PERI_MSDC30_2,
  40         MT_CG_PERI_NLI,
  41         MT_CG_PERI_UART0,
  42         MT_CG_PERI_UART1,
  43         MT_CG_PERI_UART2,
  44         MT_CG_PERI_UART3,
  45         MT_CG_PERI_BTIF,
  46         MT_CG_PERI_I2C0,
  47         MT_CG_PERI_I2C1,
  48         MT_CG_PERI_I2C2,
  49         MT_CG_PERI_I2C3,
  50         MT_CG_PERI_AUXADC,
  51         MT_CG_PERI_SPI0,
  52         MT_CG_PERI_ETH,
  53         MT_CG_PERI_USB0_MCU,
  54         MT_CG_PERI_USB1_MCU,
  55         MT_CG_PERI_USB_SLV,
  56
  57         MT_CG_PERI_GCPU,
  58         MT_CG_PERI_NFI_ECC,
  59         MT_CG_PERI_NFIPAD,
  60
  61         MT_CG_INFRA_DBGCLK,
  62         MT_CG_INFRA_SMI,
  63         MT_CG_INFRA_AUDIO,
  64         MT_CG_INFRA_EFUSE,
  65         MT_CG_INFRA_L2C_SRAM,
  66         MT_CG_INFRA_M4U,
  67         MT_CG_INFRA_CONNMCU,
  68         MT_CG_INFRA_TRNG,
  69         MT_CG_INFRA_CPUM,
  70         MT_CG_INFRA_KP,
  71         MT_CG_INFRA_CEC,
  72         MT_CG_INFRA_IRRX,
  73         MT_CG_INFRA_PMICSPI_SHARE,
  74         MT_CG_INFRA_PMICWRAP,
  75
  76         MT_CG_TOPCK_PMICSPI,
  77
  78         MT_CG_DISP0_SMI_COMMON,
  79         MT_CG_DISP0_SMI_LARB0,
  80         MT_CG_DISP0_MM_CMDQ,
  81         MT_CG_DISP0_MUTEX,
  82         MT_CG_DISP0_DISP_COLOR,
  83         MT_CG_DISP0_DISP_BLS,
  84         MT_CG_DISP0_DISP_WDMA,
  85         MT_CG_DISP0_DISP_RDMA,
  86         MT_CG_DISP0_DISP_OVL,
  87         MT_CG_DISP0_MDP_TDSHP,
  88         MT_CG_DISP0_MDP_WROT,
  89         MT_CG_DISP0_MDP_WDMA,
  90         MT_CG_DISP0_MDP_RSZ1,
  91         MT_CG_DISP0_MDP_RSZ0,
  92         MT_CG_DISP0_MDP_RDMA,
  93         MT_CG_DISP0_MDP_BLS_26M,
  94         MT_CG_DISP0_CAM_MDP,
  95         MT_CG_DISP0_FAKE_ENG,
  96         MT_CG_DISP0_MUTEX_32K,
  97         MT_CG_DISP0_DISP_RMDA1,
  98         MT_CG_DISP0_DISP_UFOE,
  99
 100         MT_CG_DISP1_DSI_ENGINE,
 101         MT_CG_DISP1_DSI_DIGITAL,
 102         MT_CG_DISP1_DPI_DIGITAL_LANE,
 103         MT_CG_DISP1_DPI_ENGINE,
 104         MT_CG_DISP1_DPI1_DIGITAL_LANE,
 105         MT_CG_DISP1_DPI1_ENGINE,
 106         MT_CG_DISP1_TVE_OUTPUT_CLOCK,
 107         MT_CG_DISP1_TVE_INPUT_CLOCK,
 108         MT_CG_DISP1_HDMI_PIXEL_CLOCK,
 109         MT_CG_DISP1_HDMI_PLL_CLOCK,
 110         MT_CG_DISP1_HDMI_AUDIO_CLOCK,
 111         MT_CG_DISP1_HDMI_SPDIF_CLOCK,
 112         MT_CG_DISP1_LVDS_PIXEL_CLOCK,
 113         MT_CG_DISP1_LVDS_CTS_CLOCK,
 114
 115         MT_CG_IMAGE_LARB2_SMI,
 116         MT_CG_IMAGE_CAM_SMI,
 117         MT_CG_IMAGE_CAM_CAM,
 118         MT_CG_IMAGE_SEN_TG,
 119         MT_CG_IMAGE_SEN_CAM,
 120         MT_CG_IMAGE_VENC_JPENC,
 121
 122         MT_CG_MFG_G3D,
 123
 124         MT_CG_AUDIO_AFE,
 125         MT_CG_AUDIO_I2S,
 126         MT_CG_AUDIO_APLL_TUNER_CK,
 127         MT_CG_AUDIO_HDMI_CK,
 128         MT_CG_AUDIO_SPDF_CK,
 129         MT_CG_AUDIO_SPDF2_CK,
 130
 131         MT_CG_VDEC0_VDEC,
 132
 133         MT_CG_VDEC1_LARB,
 134
 135         NR_CLKS,
 136 };
 137
 138
 139 enum {
 140         /* CLK_CFG_0 */
 141         MT_MUX_MM,
 142         MT_MUX_DDRPHYCFG,
 143         MT_MUX_MEM,
 144         MT_MUX_AXI,
 145
 146         /* CLK_CFG_1 */
 147         MT_MUX_CAMTG,
 148         MT_MUX_MFG,
 149         MT_MUX_VDEC,
 150         MT_MUX_PWM,
 151
 152         /* CLK_CFG_2 */
 153         MT_MUX_MSDC30_0,
 154         MT_MUX_USB20,
 155         MT_MUX_SPI,
 156         MT_MUX_UART,
 157
 158         /* CLK_CFG_3 */
 159         MT_MUX_AUDINTBUS,
 160         MT_MUX_AUDIO,
 161         MT_MUX_MSDC30_2,
 162         MT_MUX_MSDC30_1,
 163
 164         /* CLK_CFG_4 */
 165         MT_MUX_DPI1,
 166         MT_MUX_DPI0,
 167         MT_MUX_SCP,
 168         MT_MUX_PMICSPI,
 169
 170         /* CLK_CFG_5 */
 171         MT_MUX_DPILVDS,
 172         MT_MUX_APLL,
 173         MT_MUX_HDMI,
 174         MT_MUX_TVE,
 175
 176         /* CLK_CFG_6 */
 177         MT_MUX_ETH_50M,
 178         MT_MUX_NFI2X,
 179         MT_MUX_RTC,
 180
 181         NR_MUXS,
 182 };
 183
 184 enum {
 185         ARMPLL,
 186         MAINPLL,
 187         MSDCPLL,
 188         UNIVPLL,
 189         MMPLL,
 190         VENCPLL,
 191         TVDPLL,
 192         LVDSPLL,
 193         AUDPLL,
 194
 195         NR_PLLS,
 196 };
 197
 198
 199 enum {
 200         SYS_CONN,
 201         SYS_DPY,
 202         SYS_DIS,
 203         SYS_MFG,
 204         SYS_ISP,
 205         SYS_IFR,
 206         SYS_VDE,
 207
 208         NR_SYSS,
 209 };
 210
 211
 212 #ifdef __KERNEL__
 213
 214 /* the following definition / declaration are only enabled in Linux kernel */
 215
 216
 217 #include <linux/list.h>
 218 #include "mach/mt_reg_base.h"
 219 #include "mach/mt_typedefs.h"
 220
 221
 222 #define CLKMGR_8127             1
 223 #define CLKMGR_EXT              0
 224 #define CLKMGR_CLKM0            0
 225
 226
 227 #define AP_PLL_CON0         (APMIXEDSYS_BASE + 0x0000)
 228 #define AP_PLL_CON1         (APMIXEDSYS_BASE + 0x0004)
 229 #define AP_PLL_CON2         (APMIXEDSYS_BASE + 0x0008)
 230
 231 #define PLL_HP_CON0         (APMIXEDSYS_BASE + 0x0014)
 232
 233 #define ARMPLL_CON0         (APMIXEDSYS_BASE + 0x0200)
 234 #define ARMPLL_CON1         (APMIXEDSYS_BASE + 0x0204)
 235 #define ARMPLL_PWR_CON0     (APMIXEDSYS_BASE + 0x020C)
 236
 237 #define MAINPLL_CON0        (APMIXEDSYS_BASE + 0x0210)
 238 #define MAINPLL_CON1        (APMIXEDSYS_BASE + 0x0214)
 239 #define MAINPLL_PWR_CON0    (APMIXEDSYS_BASE + 0x021C)
 240
 241 #define UNIVPLL_CON0        (APMIXEDSYS_BASE + 0x0220)
 242 #define UNIVPLL_CON1        (APMIXEDSYS_BASE + 0x0224)
 243 #define UNIVPLL_PWR_CON0    (APMIXEDSYS_BASE + 0x022C)
 244
 245 #define MMPLL_CON0          (APMIXEDSYS_BASE + 0x0230)
 246 #define MMPLL_CON1          (APMIXEDSYS_BASE + 0x0234)
 247 #define MMPLL_PWR_CON0      (APMIXEDSYS_BASE + 0x023C)
 248
 249 #define MSDCPLL_CON0        (APMIXEDSYS_BASE + 0x0240)
 250 #define MSDCPLL_CON1        (APMIXEDSYS_BASE + 0x0244)
 251 #define MSDCPLL_PWR_CON0    (APMIXEDSYS_BASE + 0x024C)
 252
 253 #define AUDPLL_CON0         (APMIXEDSYS_BASE + 0x0250)
 254 #define AUDPLL_CON1         (APMIXEDSYS_BASE + 0x0254)
 255 #define AUDPLL_PWR_CON0     (APMIXEDSYS_BASE + 0x025C)
 256
 257 #define VENCPLL_CON0        (DDRPHY_BASE + 0x800)
 258 #define VENCPLL_CON1        (DDRPHY_BASE + 0x804)
 259 #define VENCPLL_PWR_CON0    (DDRPHY_BASE + 0x80C)
 260
 261 #define TVDPLL_CON0         (APMIXEDSYS_BASE + 0x0260)
 262 #define TVDPLL_CON1         (APMIXEDSYS_BASE + 0x0264)
 263 #define TVDPLL_PWR_CON0     (APMIXEDSYS_BASE + 0x026C)
 264
 265 #define LVDSPLL_CON0        (APMIXEDSYS_BASE + 0x0270)
 266 #define LVDSPLL_CON1        (APMIXEDSYS_BASE + 0x0274)
 267 #define LVDSPLL_PWR_CON0    (APMIXEDSYS_BASE + 0x027C)
 268
 269 #define CLK_DSI_PLL_CON0    (MIPI_CONFIG_BASE + 0x50)
 270
 271 #define CLK_CFG_0           (INFRA_BASE + 0x0040)
 272 #define CLK_CFG_1           (INFRA_BASE + 0x0050)
 273 #define CLK_CFG_2           (INFRA_BASE + 0x0060)
 274 #define CLK_CFG_3           (INFRA_BASE + 0x0070)
 275 #define CLK_CFG_4           (INFRA_BASE + 0x0080)
 276 #define CLK_CFG_4_SET       (INFRA_BASE + 0x0084)
 277 #define CLK_CFG_4_CLR       (INFRA_BASE + 0x0088)
 278 #define CLK_CFG_5           (INFRA_BASE + 0x0090)
 279 #define CLK_CFG_6           (INFRA_BASE + 0x00A0)
 280 #define CLK_CFG_8           (INFRA_BASE + 0x0100)
 281 #define CLK_CFG_9           (INFRA_BASE + 0x0104)
 282 #define CLK_CFG_10          (INFRA_BASE + 0x0108)
 283 #define CLK_CFG_11          (INFRA_BASE + 0x010C)
 284 #define CLK_SCP_CFG_0       (INFRA_BASE + 0x0200)
 285 #define CLK_SCP_CFG_1       (INFRA_BASE + 0x0204)
 286
 287 #define INFRA_PDN_SET       (INFRACFG_AO_BASE + 0x0040)
 288 #define INFRA_PDN_CLR       (INFRACFG_AO_BASE + 0x0044)
 289 #define INFRA_PDN_STA       (INFRACFG_AO_BASE + 0x0048)
 290
 291 #define TOPAXI_PROT_EN      (INFRACFG_AO_BASE + 0x0220)
 292 #define TOPAXI_PROT_STA1    (INFRACFG_AO_BASE + 0x0228)
 293
 294 #define PERI_PDN0_SET       (PERICFG_BASE + 0x0008)
 295 #define PERI_PDN0_CLR       (PERICFG_BASE + 0x0010)
 296 #define PERI_PDN0_STA       (PERICFG_BASE + 0x0018)
 297
 298 #define PERI_PDN1_SET       (PERICFG_BASE + 0x000C)
 299 #define PERI_PDN1_CLR       (PERICFG_BASE + 0x0014)
 300 #define PERI_PDN1_STA       (PERICFG_BASE + 0x001C)
 301
 302 #define AUDIO_TOP_CON0      (AUDIO_REG_BASE + 0x0000)
 303
 304 #define MFG_CG_CON          (G3D_CONFIG_BASE + 0x0000)
 305 #define MFG_CG_SET          (G3D_CONFIG_BASE + 0x0004)
 306 #define MFG_CG_CLR          (G3D_CONFIG_BASE + 0x0008)
 307
 308 #define DISP_CG_CON0        (DISPSYS_BASE + 0x100)
 309 #define DISP_CG_SET0        (DISPSYS_BASE + 0x104)
 310 #define DISP_CG_CLR0        (DISPSYS_BASE + 0x108)
 311 #define DISP_CG_CON1        (DISPSYS_BASE + 0x110)
 312 #define DISP_CG_SET1        (DISPSYS_BASE + 0x114)
 313 #define DISP_CG_CLR1        (DISPSYS_BASE + 0x118)
 314
 315 #define IMG_CG_CON          (IMGSYS_CONFG_BASE + 0x0000)
 316 #define IMG_CG_SET          (IMGSYS_CONFG_BASE + 0x0004)
 317 #define IMG_CG_CLR          (IMGSYS_CONFG_BASE + 0x0008)
 318
 319 #define VDEC_CKEN_SET       (VDEC_GCON_BASE + 0x0000)
 320 #define VDEC_CKEN_CLR       (VDEC_GCON_BASE + 0x0004)
 321 #define LARB_CKEN_SET       (VDEC_GCON_BASE + 0x0008)
 322 #define LARB_CKEN_CLR       (VDEC_GCON_BASE + 0x000C)
 323
 324
 325 enum {
 326         MT_LARB_DISP = 0,
 327         MT_LARB_VDEC = 1,
 328         MT_LARB_IMG  = 2,
 329 };
 330
 331
 332 /* larb monitor mechanism definition */
 333 enum {
 334         LARB_MONITOR_LEVEL_HIGH     = 10,
 335         LARB_MONITOR_LEVEL_MEDIUM   = 20,
 336         LARB_MONITOR_LEVEL_LOW      = 30,
 337 };
 338
 339 struct larb_monitor {
 340         struct list_head link;
 341         int level;
 342         void (*backup)(struct larb_monitor *h, int larb_idx);       /* called before disable larb clock */
 343         void (*restore)(struct larb_monitor *h, int larb_idx);      /* called after enable larb clock */
 344 };
 345
 346
 347 #if CLKMGR_CLKM0
 348
 349
 350 enum monitor_clk_sel_0{
 351         no_clk_0             = 0,
 352         AD_UNIV_624M_CK      = 5,
 353         AD_UNIV_416M_CK      = 6,
 354         AD_UNIV_249P6M_CK    = 7,
 355         AD_UNIV_178P3M_CK_0  = 8,
 356         AD_UNIV_48M_CK       = 9,
 357         AD_USB_48M_CK        = 10,
 358         rtc32k_ck_i_0        = 20,
 359         AD_SYS_26M_CK_0      = 21,
 360 };
 361
 362
 363 #endif /* CLKMGR_CLKM0 */
 364
 365
 366 enum monitor_clk_sel {
 367         no_clk               = 0,
 368         AD_SYS_26M_CK        = 1,
 369         rtc32k_ck_i          = 2,
 370         clkph_MCLK_o         = 7,
 371         AD_DPICLK            = 8,
 372         AD_MSDCPLL_CK        = 9,
 373         AD_MMPLL_CK          = 10,
 374         AD_UNIV_178P3M_CK    = 11,
 375         AD_MAIN_H156M_CK     = 12,
 376         AD_VENCPLL_CK        = 13,
 377 };
 378
 379
 380 enum ckmon_sel {
 381 #if CLKMGR_CLKM0
 382         clk_ckmon0           = 0,
 383 #endif
 384         clk_ckmon1           = 1,
 385         clk_ckmon2           = 2,
 386         clk_ckmon3           = 3,
 387 };
 388
 389
 390 enum ABIST_CLK {
 391         ABIST_CLK_NULL,
 392
 393         ABIST_AD_MAIN_H546M_CK            =  1,
 394         ABIST_AD_MAIN_H364M_CK            =  2,
 395         ABIST_AD_MAIN_H218P4M_CK          =  3,
 396         ABIST_AD_MAIN_H156M_CK            =  4,
 397         ABIST_AD_UNIV_624M_CK             =  5,
 398         ABIST_AD_UNIV_416M_CK             =  6,
 399         ABIST_AD_UNIV_249P6M_CK           =  7,
 400         ABIST_AD_UNIV_178P3M_CK           =  8,
 401         ABIST_AD_UNIV_48M_CK              =  9,
 402         ABIST_AD_USB_48M_CK               = 10,
 403         ABIST_AD_MMPLL_CK                 = 11,
 404         ABIST_AD_MSDCPLL_CK               = 12,
 405         ABIST_AD_DPICLK                   = 13,
 406         ABIST_CLKPH_MCK_O                 = 14,
 407         ABIST_AD_MEMPLL2_CKOUT0_PRE_ISO   = 15,
 408         ABIST_AD_MCUPLL1_H481M_CK         = 16,
 409         ABIST_AD_MDPLL1_416M_CK           = 17,
 410         ABIST_AD_WPLL_CK                  = 18,
 411         ABIST_AD_WHPLL_CK                 = 19,
 412         ABIST_RTC32K_CK_I                 = 20,
 413         ABIST_AD_SYS_26M_CK               = 21,
 414         ABIST_AD_VENCPLL_CK               = 22,
 415         ABIST_AD_MIPI_26M_CK              = 33,
 416         ABIST_AD_MEM_26M_CK               = 35,
 417         ABIST_AD_PLLGP_TST_CK             = 36,
 418         ABIST_AD_DSI0_LNTC_DSICLK         = 37,
 419         ABIST_AD_MPPLL_TST_CK             = 38,
 420         ABIST_ARMPLL_OCC_MON              = 39,
 421         ABIST_AD_MEM2MIPI_26M_CK          = 40,
 422         ABIST_AD_MEMPLL_MONCLK            = 41,
 423         ABIST_AD_MEMPLL2_MONCLK           = 42,
 424         ABIST_AD_MEMPLL3_MONCLK           = 43,
 425         ABIST_AD_MEMPLL4_MONCLK           = 44,
 426         ABIST_AD_MEMPLL_REFCLK            = 45,
 427         ABIST_AD_MEMPLL_FBCLK             = 46,
 428         ABIST_AD_MEMPLL2_REFCLK           = 47,
 429         ABIST_AD_MEMPLL2_FBCLK            = 48,
 430         ABIST_AD_MEMPLL3_REFCLK           = 49,
 431         ABIST_AD_MEMPLL3_FBCLK            = 50,
 432         ABIST_AD_MEMPLL4_REFCLK           = 51,
 433         ABIST_AD_MEMPLL4_FBCLK            = 52,
 434         ABIST_AD_MEMPLL_TSTDIV2_CK        = 53,
 435         ABIST_AD_LVDSPLL_CK               = 54,
 436         ABIST_AD_LVDSTX_MONCLK            = 55,
 437         ABIST_AD_HDMITX_MONCLK            = 56,
 438         ABIST_AD_USB20_C240M              = 57,
 439         ABIST_AD_USB20_C240M_1P           = 58,
 440         ABIST_AD_MONREF_CK                = 59,
 441         ABIST_AD_MONFBK_CK                = 60,
 442         ABIST_AD_TVDPLL_CK                = 61,
 443         ABIST_AD_AUDPLL_CK                = 62,
 444         ABIST_AD_LVDSPLL_ETH_CK           = 63,
 445
 446         ABIST_CLK_END,
 447 };
 448
 449
 450 enum CKGEN_CLK {
 451         CKGEN_CLK_NULL,
 452
 453         CKGEN_HF_FAXI_CK          =  1,
 454         CKGEN_HD_FAXI_CK          =  2,
 455         CKGEN_HF_FNFI2X_CK        =  3,
 456         CKGEN_HF_FDDRPHYCFG_CK    =  4,
 457         CKGEN_HF_FMM_CK           =  5,
 458         CKGEN_F_FPWM_CK           =  6,
 459         CKGEN_HF_FVDEC_CK         =  7,
 460         CKGEN_HF_FMFG_CK          =  8,
 461         CKGEN_HF_FCAMTG_CK        =  9,
 462         CKGEN_F_FUART_CK          = 10,
 463         CKGEN_HF_FSPI_CK          = 11,
 464         CKGEN_F_FUSB20_CK         = 12,
 465         CKGEN_HF_FMSDC30_0_CK     = 13,
 466         CKGEN_HF_FMSDC30_1_CK     = 14,
 467         CKGEN_HF_FMSDC30_2_CK     = 15,
 468         CKGEN_HF_FAUDIO_CK        = 16,
 469         CKGEN_HF_FAUD_INTBUS_CK   = 17,
 470         CKGEN_HF_FPMICSPI_CK      = 18,
 471         CKGEN_F_FRTC_CK           = 19,
 472         CKGEN_F_F26M_CK           = 20,
 473         CKGEN_F_F32K_MD1_CK       = 21,
 474         CKGEN_F_FRTC_CONN_CK      = 22,
 475         CKGEN_HF_FETH_50M_CK      = 23,
 476         CKGEN_HD_HAXI_NLI_CK      = 25,
 477         CKGEN_HD_QAXIDCM_CK       = 26,
 478         CKGEN_F_FFPC_CK           = 27,
 479         CKGEN_HF_FDPI0_CK         = 28,
 480         CKGEN_F_FCKBUS_CK_SCAN    = 29,
 481         CKGEN_F_FCKRTC_CK_SCAN    = 30,
 482         CKGEN_HF_FDPILVDS_CK      = 31,
 483
 484         CKGEN_CLK_END,
 485 };
 486
 487
 488 #if CLKMGR_EXT
 489
 490 /* Measure clock frequency (in KHz) by frequency meter. */
 491 extern uint32_t measure_abist_freq(enum ABIST_CLK clk);
 492 extern uint32_t measure_ckgen_freq(enum CKGEN_CLK clk);
 493
 494 #endif /* CLKMGR_EXT */
 495
 496
 497 extern void register_larb_monitor(struct larb_monitor *handler);
 498 extern void unregister_larb_monitor(struct larb_monitor *handler);
 499
 500 /* clock API */
 501 extern int enable_clock(enum cg_clk_id id, char *mod_name);
 502 extern int disable_clock(enum cg_clk_id id, char *mod_name);
 503 extern int mt_enable_clock(enum cg_clk_id id, char *mod_name);
 504 extern int mt_disable_clock(enum cg_clk_id id, char *mod_name);
 505
 506 extern int clock_is_on(int id);
 507
 508 extern int clkmux_sel(int id, unsigned int clksrc, char *name);
 509 extern void enable_mux(int id, char *name);
 510 extern void disable_mux(int id, char *name);
 511
 512 extern void clk_set_force_on(int id);
 513 extern void clk_clr_force_on(int id);
 514 extern int clk_is_force_on(int id);
 515
 516 /* pll API */
 517 extern int enable_pll(int id, char *mod_name);
 518 extern int disable_pll(int id, char *mod_name);
 519
 520 extern int pll_hp_switch_on(int id, int hp_on);
 521 extern int pll_hp_switch_off(int id, int hp_off);
 522
 523 #if CLKMGR_8127
 524
 525 /* set/get PLL frequency in KHz. */
 526 extern unsigned int pll_get_freq(int id);
 527 extern unsigned int pll_set_freq(int id, unsigned int freq_khz);
 528
 529 #endif /* CLKMGR_8127 */
 530
 531 extern int pll_fsel(int id, unsigned int value);
 532 extern int pll_is_on(int id);
 533
 534 /* subsys API */
 535 extern int enable_subsys(int id, char *mod_name);
 536 extern int disable_subsys(int id, char *mod_name);
 537 extern int subsys_is_on(int id);
 538
 539 extern bool isp_vdec_on_off(void);
 540
 541 extern int conn_power_on(void);
 542 extern int conn_power_off(void);
 543
 544 /* other API */
 545 const char *grp_get_name(int id);
 546 int clk_id_to_grp_id(enum cg_clk_id id);
 547 unsigned int clk_id_to_mask(enum cg_clk_id id);
 548
 549
 550 /* init */
 551 extern void mt_clkmgr_init(void);
 552
 553 extern void CLKM_32K(bool flag);
 554 extern int CLK_Monitor(enum ckmon_sel ckmon, enum monitor_clk_sel sel, int div);
 555
 556 #if CLKMGR_CLKM0
 557 extern int CLK_Monitor_0(enum ckmon_sel ckmon, enum monitor_clk_sel_0 sel, int div);
 558 #endif /* CLKMGR_CLKM0 */
 559
 560
 561 #if !CLKMGR_8127
 562
 563
 564 /* deprecated or unused in MT8127 */
 565
 566 extern int enable_clock_ext_locked(int id, char *mod_name);
 567 extern int disable_clock_ext_locked(int id, char *mod_name);
 568
 569 extern int enable_pll_spec(int id, char *mod_name);
 570 extern int disable_pll_spec(int id, char *mod_name);
 571
 572 extern int md_power_on(int id);
 573 extern int md_power_off(int id, unsigned int timeout);
 574
 575 extern void enable_clksq1(void);
 576 extern void disable_clksq1(void);
 577
 578 extern void clksq1_sw2hw(void);
 579 extern void clksq1_hw2sw(void);
 580
 581 extern int clkmgr_is_locked(void);
 582
 583
 584 #endif /* !CLKMGR_8127 */
 585
 586
 587 #ifdef __MT_CLKMGR_C__
 588
 589 /* clkmgr internal use only */
 590
 591 #ifdef CONFIG_MTK_MMC
 592 extern void msdc_clk_status(int *status);
 593 #endif
 594
 595 #endif /* __MT_CLKMGR_C__ */
 596
 597
 598 #endif /* __KERNEL__ */
 599
 600
 601 #endif