1 /*****************************************************************************
18 ****************************************************************************/
23 #define PMIC6333_E1_CID_CODE 0x1093
24 #define PMIC6333_E2_CID_CODE 0x2093
25 #define PMIC6333_E3_CID_CODE 0x3093
27 #define MT6333_POWER_BUCK_DEFAULT 0
28 #define MT6333_POWER_BUCK_VCORE 1
29 #define MT6333_POWER_BUCK_VMEM 2
30 #define MT6333_POWER_BUCK_VRF18 3
32 /**********************************************************
36 *********************************************************/
37 #define SWCHR_BASE (0x00000000)
39 #define MT6333_CID0 ((UINT32)(SWCHR_BASE+0x00))
40 #define MT6333_PERP_CON0 ((UINT32)(SWCHR_BASE+0x01))
41 #define MT6333_PERP_CON1 ((UINT32)(SWCHR_BASE+0x02))
42 #define MT6333_PERP_CON2 ((UINT32)(SWCHR_BASE+0x03))
43 #define MT6333_PERP_CON3 ((UINT32)(SWCHR_BASE+0x04))
44 #define MT6333_PERP_CON4 ((UINT32)(SWCHR_BASE+0x05))
45 #define MT6333_PERP_CON5 ((UINT32)(SWCHR_BASE+0x06))
46 #define MT6333_PERP_CON6 ((UINT32)(SWCHR_BASE+0x07))
47 #define MT6333_PERP_CON7 ((UINT32)(SWCHR_BASE+0x08))
48 #define MT6333_PERP_CON8 ((UINT32)(SWCHR_BASE+0x09))
49 #define MT6333_PERP_CON9 ((UINT32)(SWCHR_BASE+0x0A))
50 #define MT6333_PERP_CON10 ((UINT32)(SWCHR_BASE+0x0B))
51 #define MT6333_PERP_CON11 ((UINT32)(SWCHR_BASE+0x0C))
52 #define MT6333_CORE_CON0 ((UINT32)(SWCHR_BASE+0x0D))
53 #define MT6333_CORE_CON1 ((UINT32)(SWCHR_BASE+0x0E))
54 #define MT6333_CORE_CON2 ((UINT32)(SWCHR_BASE+0x0F))
55 #define MT6333_CORE_CON3 ((UINT32)(SWCHR_BASE+0x10))
56 #define MT6333_CORE_CON4 ((UINT32)(SWCHR_BASE+0x11))
57 #define MT6333_CORE_CON5 ((UINT32)(SWCHR_BASE+0x12))
58 #define MT6333_CORE_CON6 ((UINT32)(SWCHR_BASE+0x13))
59 #define MT6333_CORE_CON7 ((UINT32)(SWCHR_BASE+0x14))
60 #define MT6333_CORE_CON8 ((UINT32)(SWCHR_BASE+0x15))
61 #define MT6333_CORE_CON9 ((UINT32)(SWCHR_BASE+0x16))
62 #define MT6333_CORE_CON10 ((UINT32)(SWCHR_BASE+0x17))
63 #define MT6333_CORE_CON11 ((UINT32)(SWCHR_BASE+0x18))
64 #define MT6333_STA_CON0 ((UINT32)(SWCHR_BASE+0x19))
65 #define MT6333_STA_CON1 ((UINT32)(SWCHR_BASE+0x1A))
66 #define MT6333_STA_CON2 ((UINT32)(SWCHR_BASE+0x1B))
67 #define MT6333_STA_CON3 ((UINT32)(SWCHR_BASE+0x1C))
68 #define MT6333_STA_CON4 ((UINT32)(SWCHR_BASE+0x1D))
69 #define MT6333_STA_CON5 ((UINT32)(SWCHR_BASE+0x1E))
70 #define MT6333_STA_CON6 ((UINT32)(SWCHR_BASE+0x1F))
71 #define MT6333_STA_CON7 ((UINT32)(SWCHR_BASE+0x20))
72 #define MT6333_STA_CON8 ((UINT32)(SWCHR_BASE+0x21))
73 #define MT6333_STA_CON9 ((UINT32)(SWCHR_BASE+0x22))
74 #define MT6333_STA_CON10 ((UINT32)(SWCHR_BASE+0x23))
75 #define MT6333_STA_CON11 ((UINT32)(SWCHR_BASE+0x24))
76 #define MT6333_STA_CON12 ((UINT32)(SWCHR_BASE+0x25))
77 #define MT6333_STA_CON13 ((UINT32)(SWCHR_BASE+0x26))
78 #define MT6333_STA_CON14 ((UINT32)(SWCHR_BASE+0x27))
79 #define MT6333_STA_CON15 ((UINT32)(SWCHR_BASE+0x28))
80 #define MT6333_DIG_CON0 ((UINT32)(SWCHR_BASE+0x29))
81 #define MT6333_DIG_CON1 ((UINT32)(SWCHR_BASE+0x2A))
82 #define MT6333_DIG_CON2 ((UINT32)(SWCHR_BASE+0x2B))
83 #define MT6333_DIG_CON3 ((UINT32)(SWCHR_BASE+0x2C))
84 #define MT6333_DIG_CON4 ((UINT32)(SWCHR_BASE+0x2D))
85 #define MT6333_DIG_CON5 ((UINT32)(SWCHR_BASE+0x2E))
86 #define MT6333_DIG_CON6 ((UINT32)(SWCHR_BASE+0x2F))
87 #define MT6333_DIG_CON7 ((UINT32)(SWCHR_BASE+0x30))
88 #define MT6333_DIG_CON8 ((UINT32)(SWCHR_BASE+0x31))
89 #define MT6333_DIG_CON9 ((UINT32)(SWCHR_BASE+0x32))
90 #define MT6333_DIG_CON10 ((UINT32)(SWCHR_BASE+0x33))
91 #define MT6333_DIG_CON11 ((UINT32)(SWCHR_BASE+0x34))
92 #define MT6333_DIG_CON12 ((UINT32)(SWCHR_BASE+0x35))
93 #define MT6333_DIG_CON13 ((UINT32)(SWCHR_BASE+0x36))
94 #define MT6333_DIG_CON14 ((UINT32)(SWCHR_BASE+0x37))
95 #define MT6333_DIG_CON15 ((UINT32)(SWCHR_BASE+0x38))
96 #define MT6333_DIG_CON16 ((UINT32)(SWCHR_BASE+0x39))
97 #define MT6333_DIG_CON17 ((UINT32)(SWCHR_BASE+0x3A))
98 #define MT6333_DIG_CON18 ((UINT32)(SWCHR_BASE+0x3B))
99 #define MT6333_GPIO_CON0 ((UINT32)(SWCHR_BASE+0x3C))
100 #define MT6333_GPIO_CON1 ((UINT32)(SWCHR_BASE+0x3D))
101 #define MT6333_GPIO_CON2 ((UINT32)(SWCHR_BASE+0x3E))
102 #define MT6333_CLK_CON0 ((UINT32)(SWCHR_BASE+0x3F))
103 #define MT6333_CLK_CON0_SET ((UINT32)(SWCHR_BASE+0x40))
104 #define MT6333_CLK_CON0_CLR ((UINT32)(SWCHR_BASE+0x41))
105 #define MT6333_CLK_CON1 ((UINT32)(SWCHR_BASE+0x42))
106 #define MT6333_CLK_CON2 ((UINT32)(SWCHR_BASE+0x43))
107 #define MT6333_INT_CON0 ((UINT32)(SWCHR_BASE+0x44))
108 #define MT6333_INT_CON0_SET ((UINT32)(SWCHR_BASE+0x45))
109 #define MT6333_INT_CON0_CLR ((UINT32)(SWCHR_BASE+0x46))
110 #define MT6333_INT_CON1 ((UINT32)(SWCHR_BASE+0x47))
111 #define MT6333_INT_CON1_SET ((UINT32)(SWCHR_BASE+0x48))
112 #define MT6333_INT_CON1_CLR ((UINT32)(SWCHR_BASE+0x49))
113 #define MT6333_INT_CON2 ((UINT32)(SWCHR_BASE+0x4A))
114 #define MT6333_INT_CON2_SET ((UINT32)(SWCHR_BASE+0x4B))
115 #define MT6333_INT_CON2_CLR ((UINT32)(SWCHR_BASE+0x4C))
116 #define MT6333_CHRWDT_CON0 ((UINT32)(SWCHR_BASE+0x4D))
117 #define MT6333_CHRWDT_STATUS0 ((UINT32)(SWCHR_BASE+0x4E))
118 #define MT6333_INT_STATUS0 ((UINT32)(SWCHR_BASE+0x4F))
119 #define MT6333_INT_STATUS1 ((UINT32)(SWCHR_BASE+0x50))
120 #define MT6333_INT_STATUS2 ((UINT32)(SWCHR_BASE+0x51))
121 #define MT6333_OC_CTL_VCORE ((UINT32)(SWCHR_BASE+0x52))
122 #define MT6333_OC_CTL_VMEM ((UINT32)(SWCHR_BASE+0x53))
123 #define MT6333_OC_CTL_VRF18 ((UINT32)(SWCHR_BASE+0x54))
124 #define MT6333_INT_MISC_CON ((UINT32)(SWCHR_BASE+0x55))
125 #define MT6333_BUCK_CON0 ((UINT32)(SWCHR_BASE+0x56))
126 #define MT6333_VCORE_CON0 ((UINT32)(SWCHR_BASE+0x57))
127 #define MT6333_VCORE_CON1 ((UINT32)(SWCHR_BASE+0x58))
128 #define MT6333_VCORE_CON2 ((UINT32)(SWCHR_BASE+0x59))
129 #define MT6333_VCORE_CON3 ((UINT32)(SWCHR_BASE+0x5A))
130 #define MT6333_VCORE_CON4 ((UINT32)(SWCHR_BASE+0x5B))
131 #define MT6333_VCORE_CON5 ((UINT32)(SWCHR_BASE+0x5C))
132 #define MT6333_VCORE_CON6 ((UINT32)(SWCHR_BASE+0x5D))
133 #define MT6333_VCORE_CON7 ((UINT32)(SWCHR_BASE+0x5E))
134 #define MT6333_VCORE_CON8 ((UINT32)(SWCHR_BASE+0x5F))
135 #define MT6333_VCORE_CON9 ((UINT32)(SWCHR_BASE+0x60))
136 #define MT6333_VCORE_CON10 ((UINT32)(SWCHR_BASE+0x61))
137 #define MT6333_VCORE_CON11 ((UINT32)(SWCHR_BASE+0x62))
138 #define MT6333_VCORE_CON12 ((UINT32)(SWCHR_BASE+0x63))
139 #define MT6333_VCORE_CON13 ((UINT32)(SWCHR_BASE+0x64))
140 #define MT6333_VCORE_CON14 ((UINT32)(SWCHR_BASE+0x65))
141 #define MT6333_VCORE_CON15 ((UINT32)(SWCHR_BASE+0x66))
142 #define MT6333_VCORE_CON16 ((UINT32)(SWCHR_BASE+0x67))
143 #define MT6333_VCORE_CON17 ((UINT32)(SWCHR_BASE+0x68))
144 #define MT6333_VCORE_CON18 ((UINT32)(SWCHR_BASE+0x69))
145 #define MT6333_VCORE_CON19 ((UINT32)(SWCHR_BASE+0x6A))
146 #define MT6333_VCORE_CON20 ((UINT32)(SWCHR_BASE+0x6B))
147 #define MT6333_VCORE_CON21 ((UINT32)(SWCHR_BASE+0x6C))
148 #define MT6333_VCORE_CON22 ((UINT32)(SWCHR_BASE+0x6D))
149 #define MT6333_VCORE_CON23 ((UINT32)(SWCHR_BASE+0x6E))
150 #define MT6333_VCORE_CON24 ((UINT32)(SWCHR_BASE+0x6F))
151 #define MT6333_VCORE_CON25 ((UINT32)(SWCHR_BASE+0x70))
152 #define MT6333_VCORE_CON26 ((UINT32)(SWCHR_BASE+0x71))
153 #define MT6333_VCORE_CON27 ((UINT32)(SWCHR_BASE+0x72))
154 #define MT6333_VCORE_CON28 ((UINT32)(SWCHR_BASE+0x73))
155 #define MT6333_VCORE_CON29 ((UINT32)(SWCHR_BASE+0x74))
156 #define MT6333_VCORE_CON30 ((UINT32)(SWCHR_BASE+0x75))
157 #define MT6333_VMEM_RSV0 ((UINT32)(SWCHR_BASE+0x76))
158 #define MT6333_VMEM_CON0 ((UINT32)(SWCHR_BASE+0x77))
159 #define MT6333_VMEM_CON1 ((UINT32)(SWCHR_BASE+0x78))
160 #define MT6333_VMEM_CON2 ((UINT32)(SWCHR_BASE+0x79))
161 #define MT6333_VMEM_CON3 ((UINT32)(SWCHR_BASE+0x7A))
162 #define MT6333_VMEM_CON4 ((UINT32)(SWCHR_BASE+0x7B))
163 #define MT6333_VMEM_CON5 ((UINT32)(SWCHR_BASE+0x7C))
164 #define MT6333_VMEM_CON6 ((UINT32)(SWCHR_BASE+0x7D))
165 #define MT6333_VMEM_CON7 ((UINT32)(SWCHR_BASE+0x7E))
166 #define MT6333_VMEM_CON8 ((UINT32)(SWCHR_BASE+0x7F))
167 #define MT6333_VMEM_CON9 ((UINT32)(SWCHR_BASE+0x80))
168 #define MT6333_VMEM_CON12 ((UINT32)(SWCHR_BASE+0x81))
169 #define MT6333_VMEM_CON13 ((UINT32)(SWCHR_BASE+0x82))
170 #define MT6333_VMEM_CON14 ((UINT32)(SWCHR_BASE+0x83))
171 #define MT6333_VMEM_CON15 ((UINT32)(SWCHR_BASE+0x84))
172 #define MT6333_VMEM_CON16 ((UINT32)(SWCHR_BASE+0x85))
173 #define MT6333_VMEM_CON17 ((UINT32)(SWCHR_BASE+0x86))
174 #define MT6333_VMEM_CON18 ((UINT32)(SWCHR_BASE+0x87))
175 #define MT6333_VMEM_CON19 ((UINT32)(SWCHR_BASE+0x88))
176 #define MT6333_VMEM_CON20 ((UINT32)(SWCHR_BASE+0x89))
177 #define MT6333_VMEM_CON21 ((UINT32)(SWCHR_BASE+0x8A))
178 #define MT6333_VMEM_CON22 ((UINT32)(SWCHR_BASE+0x8B))
179 #define MT6333_VRF18_RSV0 ((UINT32)(SWCHR_BASE+0x8C))
180 #define MT6333_VRF18_CON0 ((UINT32)(SWCHR_BASE+0x8D))
181 #define MT6333_VRF18_CON1 ((UINT32)(SWCHR_BASE+0x8E))
182 #define MT6333_VRF18_CON2 ((UINT32)(SWCHR_BASE+0x8F))
183 #define MT6333_VRF18_CON3 ((UINT32)(SWCHR_BASE+0x90))
184 #define MT6333_VRF18_CON4 ((UINT32)(SWCHR_BASE+0x91))
185 #define MT6333_VRF18_CON6 ((UINT32)(SWCHR_BASE+0x92))
186 #define MT6333_VRF18_CON7 ((UINT32)(SWCHR_BASE+0x93))
187 #define MT6333_VRF18_CON8 ((UINT32)(SWCHR_BASE+0x94))
188 #define MT6333_VRF18_CON9 ((UINT32)(SWCHR_BASE+0x95))
189 #define MT6333_VRF18_CON12 ((UINT32)(SWCHR_BASE+0x96))
190 #define MT6333_VRF18_CON13 ((UINT32)(SWCHR_BASE+0x97))
191 #define MT6333_VRF18_CON14 ((UINT32)(SWCHR_BASE+0x98))
192 #define MT6333_VRF18_CON15 ((UINT32)(SWCHR_BASE+0x99))
193 #define MT6333_VRF18_CON16 ((UINT32)(SWCHR_BASE+0x9A))
194 #define MT6333_VRF18_CON17 ((UINT32)(SWCHR_BASE+0x9B))
195 #define MT6333_VRF18_CON18 ((UINT32)(SWCHR_BASE+0x9C))
196 #define MT6333_VRF18_CON19 ((UINT32)(SWCHR_BASE+0x9D))
197 #define MT6333_VRF18_CON20 ((UINT32)(SWCHR_BASE+0x9E))
198 #define MT6333_VRF18_CON21 ((UINT32)(SWCHR_BASE+0x9F))
199 #define MT6333_VRF18_CON22 ((UINT32)(SWCHR_BASE+0xA0))
200 #define MT6333_BUCK_K_CON0 ((UINT32)(SWCHR_BASE+0xA1))
201 #define MT6333_BUCK_K_CON1 ((UINT32)(SWCHR_BASE+0xA2))
202 #define MT6333_BUCK_K_CON2 ((UINT32)(SWCHR_BASE+0xA3))
203 #define MT6333_BUCK_K_CON3 ((UINT32)(SWCHR_BASE+0xA4))
204 #define MT6333_BUCK_K_CON4 ((UINT32)(SWCHR_BASE+0xA5))
205 #define MT6333_BUCK_K_CON5 ((UINT32)(SWCHR_BASE+0xA6))
206 #define MT6333_STRUP_CON0 ((UINT32)(SWCHR_BASE+0xA7))
207 #define MT6333_STRUP_CON1 ((UINT32)(SWCHR_BASE+0xA8))
208 #define MT6333_STRUP_CON2 ((UINT32)(SWCHR_BASE+0xA9))
209 #define MT6333_EFUSE_CON0 ((UINT32)(SWCHR_BASE+0xAA))
210 #define MT6333_EFUSE_CON1 ((UINT32)(SWCHR_BASE+0xAB))
211 #define MT6333_EFUSE_CON2 ((UINT32)(SWCHR_BASE+0xAC))
212 #define MT6333_EFUSE_CON3 ((UINT32)(SWCHR_BASE+0xAD))
213 #define MT6333_EFUSE_CON4 ((UINT32)(SWCHR_BASE+0xAE))
214 #define MT6333_EFUSE_CON5 ((UINT32)(SWCHR_BASE+0xAF))
215 #define MT6333_EFUSE_CON6 ((UINT32)(SWCHR_BASE+0xB0))
216 #define MT6333_EFUSE_CON7 ((UINT32)(SWCHR_BASE+0xB1))
217 #define MT6333_EFUSE_CON8 ((UINT32)(SWCHR_BASE+0xB2))
218 #define MT6333_EFUSE_CON9 ((UINT32)(SWCHR_BASE+0xB3))
219 #define MT6333_EFUSE_CON10 ((UINT32)(SWCHR_BASE+0xB4))
220 #define MT6333_EFUSE_CON11 ((UINT32)(SWCHR_BASE+0xB5))
221 #define MT6333_EFUSE_CON12 ((UINT32)(SWCHR_BASE+0xB6))
222 #define MT6333_EFUSE_DOUT_0_7 ((UINT32)(SWCHR_BASE+0xB7))
223 #define MT6333_EFUSE_DOUT_8_15 ((UINT32)(SWCHR_BASE+0xB8))
224 #define MT6333_EFUSE_DOUT_16_23 ((UINT32)(SWCHR_BASE+0xB9))
225 #define MT6333_EFUSE_DOUT_24_31 ((UINT32)(SWCHR_BASE+0xBA))
226 #define MT6333_EFUSE_DOUT_32_39 ((UINT32)(SWCHR_BASE+0xBB))
227 #define MT6333_EFUSE_DOUT_40_47 ((UINT32)(SWCHR_BASE+0xBC))
228 #define MT6333_EFUSE_DOUT_48_55 ((UINT32)(SWCHR_BASE+0xBD))
229 #define MT6333_EFUSE_DOUT_56_63 ((UINT32)(SWCHR_BASE+0xBE))
230 #define MT6333_TESTI_CON0 ((UINT32)(SWCHR_BASE+0xE0))
231 #define MT6333_TESTI_CON1 ((UINT32)(SWCHR_BASE+0xE1))
232 #define MT6333_TESTI_CON2 ((UINT32)(SWCHR_BASE+0xE2))
233 #define MT6333_TESTI_CON3 ((UINT32)(SWCHR_BASE+0xE3))
234 #define MT6333_TESTI_CON4 ((UINT32)(SWCHR_BASE+0xE4))
235 #define MT6333_TESTI_CON5 ((UINT32)(SWCHR_BASE+0xE5))
236 #define MT6333_TESTI_CON6 ((UINT32)(SWCHR_BASE+0xE6))
237 #define MT6333_TESTI_CON7 ((UINT32)(SWCHR_BASE+0xE7))
238 #define MT6333_TESTI_CON8 ((UINT32)(SWCHR_BASE+0xE8))
239 #define MT6333_TESTI_MUX_CON0 ((UINT32)(SWCHR_BASE+0xE9))
240 #define MT6333_TESTI_MUX_CON1 ((UINT32)(SWCHR_BASE+0xEA))
241 #define MT6333_TESTI_MUX_CON2 ((UINT32)(SWCHR_BASE+0xEB))
242 #define MT6333_TESTI_MUX_CON3 ((UINT32)(SWCHR_BASE+0xEC))
243 #define MT6333_TESTI_MUX_CON4 ((UINT32)(SWCHR_BASE+0xED))
244 #define MT6333_TESTI_MUX_CON5 ((UINT32)(SWCHR_BASE+0xEE))
245 #define MT6333_TESTI_MUX_CON6 ((UINT32)(SWCHR_BASE+0xEF))
246 #define MT6333_TESTI_MUX_CON7 ((UINT32)(SWCHR_BASE+0xF0))
247 #define MT6333_TESTI_MUX_CON8 ((UINT32)(SWCHR_BASE+0xF1))
248 #define MT6333_TESTO_CON0 ((UINT32)(SWCHR_BASE+0xF2))
249 #define MT6333_TESTO_CON1 ((UINT32)(SWCHR_BASE+0xF3))
250 #define MT6333_TESTO_CON2 ((UINT32)(SWCHR_BASE+0xF4))
251 #define MT6333_TESTO_CON3 ((UINT32)(SWCHR_BASE+0xF5))
252 #define MT6333_TEST_OMUX_CON0 ((UINT32)(SWCHR_BASE+0xF6))
253 #define MT6333_TEST_OMUX_CON1 ((UINT32)(SWCHR_BASE+0xF7))
254 #define MT6333_TEST_OMUX_CON2 ((UINT32)(SWCHR_BASE+0xF8))
255 #define MT6333_TEST_OMUX_CON3 ((UINT32)(SWCHR_BASE+0xF9))
256 #define MT6333_DEBUG_CON0 ((UINT32)(SWCHR_BASE+0xFA))
257 #define MT6333_DEBUG_CON1 ((UINT32)(SWCHR_BASE+0xFB))
258 #define MT6333_DEBUG_CON2 ((UINT32)(SWCHR_BASE+0xFC))
259 #define MT6333_CID1 ((UINT32)(SWCHR_BASE+0xFD))
260 //mask is HEX; shift is Integer
261 #define MT6333_PMIC_CID0_MASK 0xFF
262 #define MT6333_PMIC_CID0_SHIFT 0
263 #define MT6333_PMIC_RG_BGR_RSEL_MASK 0x7
264 #define MT6333_PMIC_RG_BGR_RSEL_SHIFT 0
265 #define MT6333_PMIC_RG_BGR_UNCHOP_MASK 0x1
266 #define MT6333_PMIC_RG_BGR_UNCHOP_SHIFT 4
267 #define MT6333_PMIC_RG_BGR_UNCHOP_PH_MASK 0x1
268 #define MT6333_PMIC_RG_BGR_UNCHOP_PH_SHIFT 5
269 #define MT6333_PMIC_RG_BGR_TRIM_MASK 0x1F
270 #define MT6333_PMIC_RG_BGR_TRIM_SHIFT 0
271 #define MT6333_PMIC_RG_BGR_TRIM_EN_MASK 0x1
272 #define MT6333_PMIC_RG_BGR_TRIM_EN_SHIFT 7
273 #define MT6333_PMIC_RG_BGR_TEST_EN_MASK 0x1
274 #define MT6333_PMIC_RG_BGR_TEST_EN_SHIFT 0
275 #define MT6333_PMIC_RG_BGR_TEST_RSTB_MASK 0x1
276 #define MT6333_PMIC_RG_BGR_TEST_RSTB_SHIFT 1
277 #define MT6333_PMIC_RG_BGR_TEST_CKIN_MASK 0x1
278 #define MT6333_PMIC_RG_BGR_TEST_CKIN_SHIFT 2
279 #define MT6333_PMIC_RG_CHR_EN_MASK 0x1
280 #define MT6333_PMIC_RG_CHR_EN_SHIFT 0
281 #define MT6333_PMIC_RG_VBOUT_EN_MASK 0x1
282 #define MT6333_PMIC_RG_VBOUT_EN_SHIFT 0
283 #define MT6333_PMIC_RG_ADCIN_VBAT_EN_MASK 0x1
284 #define MT6333_PMIC_RG_ADCIN_VBAT_EN_SHIFT 1
285 #define MT6333_PMIC_RG_ADCIN_CHRIN_EN_MASK 0x1
286 #define MT6333_PMIC_RG_ADCIN_CHRIN_EN_SHIFT 2
287 #define MT6333_PMIC_RG_ADCIN_BATON_EN_MASK 0x1
288 #define MT6333_PMIC_RG_ADCIN_BATON_EN_SHIFT 3
289 #define MT6333_PMIC_RG_BAT_ON_OPEN_VTH_MASK 0x1
290 #define MT6333_PMIC_RG_BAT_ON_OPEN_VTH_SHIFT 4
291 #define MT6333_PMIC_RG_BAT_ON_PULL_HIGH_EN_MASK 0x1
292 #define MT6333_PMIC_RG_BAT_ON_PULL_HIGH_EN_SHIFT 5
293 #define MT6333_PMIC_RG_INT_PH_ENB_MASK 0x1
294 #define MT6333_PMIC_RG_INT_PH_ENB_SHIFT 0
295 #define MT6333_PMIC_RG_SCL_PH_ENB_MASK 0x1
296 #define MT6333_PMIC_RG_SCL_PH_ENB_SHIFT 1
297 #define MT6333_PMIC_RG_SDA_PH_ENB_MASK 0x1
298 #define MT6333_PMIC_RG_SDA_PH_ENB_SHIFT 2
299 #define MT6333_PMIC_RG_VDRV_RDIVSEL_MASK 0x3
300 #define MT6333_PMIC_RG_VDRV_RDIVSEL_SHIFT 0
301 #define MT6333_PMIC_RG_SWCHR_RV1_MASK 0xFF
302 #define MT6333_PMIC_RG_SWCHR_RV1_SHIFT 0
303 #define MT6333_PMIC_RG_CHR_OTG_LV_TH_MASK 0x1
304 #define MT6333_PMIC_RG_CHR_OTG_LV_TH_SHIFT 0
305 #define MT6333_PMIC_RG_CHR_OTG_HV_TH_MASK 0x1
306 #define MT6333_PMIC_RG_CHR_OTG_HV_TH_SHIFT 2
307 #define MT6333_PMIC_RG_STRUP_THER_RG_TH_MASK 0xF
308 #define MT6333_PMIC_RG_STRUP_THER_RG_TH_SHIFT 0
309 #define MT6333_PMIC_RG_STRUP_RSV_MASK 0xF
310 #define MT6333_PMIC_RG_STRUP_RSV_SHIFT 4
311 #define MT6333_PMIC_RG_SWCHR_ANA_TEST_MODE_MASK 0x1
312 #define MT6333_PMIC_RG_SWCHR_ANA_TEST_MODE_SHIFT 0
313 #define MT6333_PMIC_RG_SWCHR_ANA_TEST_MODE_SEL_MASK 0x7
314 #define MT6333_PMIC_RG_SWCHR_ANA_TEST_MODE_SEL_SHIFT 2
315 #define MT6333_PMIC_RG_CSA_OTG_SEL_MASK 0x3
316 #define MT6333_PMIC_RG_CSA_OTG_SEL_SHIFT 0
317 #define MT6333_PMIC_RG_OTG_CS_SLP_EN_MASK 0x1
318 #define MT6333_PMIC_RG_OTG_CS_SLP_EN_SHIFT 3
319 #define MT6333_PMIC_RG_SLP_OTG_SEL_MASK 0x3
320 #define MT6333_PMIC_RG_SLP_OTG_SEL_SHIFT 5
321 #define MT6333_PMIC_RG_ITERM_SEL_MASK 0x7
322 #define MT6333_PMIC_RG_ITERM_SEL_SHIFT 0
323 #define MT6333_PMIC_RG_ICS_LOOP_MASK 0x3
324 #define MT6333_PMIC_RG_ICS_LOOP_SHIFT 4
325 #define MT6333_PMIC_RG_ZXGM_TUNE_MASK 0x3
326 #define MT6333_PMIC_RG_ZXGM_TUNE_SHIFT 0
327 #define MT6333_PMIC_RG_CHOP_EN_MASK 0x1
328 #define MT6333_PMIC_RG_CHOP_EN_SHIFT 4
329 #define MT6333_PMIC_RG_FORCE_NON_OC_MASK 0x1
330 #define MT6333_PMIC_RG_FORCE_NON_OC_SHIFT 5
331 #define MT6333_PMIC_RG_FORCE_NON_OV_MASK 0x1
332 #define MT6333_PMIC_RG_FORCE_NON_OV_SHIFT 6
333 #define MT6333_PMIC_RG_GDRI_MINOFF_EN_MASK 0x1
334 #define MT6333_PMIC_RG_GDRI_MINOFF_EN_SHIFT 7
335 #define MT6333_PMIC_RG_SYS_VREFTRIM_MASK 0x3F
336 #define MT6333_PMIC_RG_SYS_VREFTRIM_SHIFT 0
337 #define MT6333_PMIC_RG_CS_VREFTRIM_MASK 0x3F
338 #define MT6333_PMIC_RG_CS_VREFTRIM_SHIFT 0
339 #define MT6333_PMIC_RG_OSC_TRIM_MASK 0x3F
340 #define MT6333_PMIC_RG_OSC_TRIM_SHIFT 0
341 #define MT6333_PMIC_RG_VSYS_OV_TRIM_MASK 0x1F
342 #define MT6333_PMIC_RG_VSYS_OV_TRIM_SHIFT 0
343 #define MT6333_PMIC_RG_SWCHR_RV2_MASK 0xFF
344 #define MT6333_PMIC_RG_SWCHR_RV2_SHIFT 0
345 #define MT6333_PMIC_RG_INPUT_CC_REG_MASK 0x1
346 #define MT6333_PMIC_RG_INPUT_CC_REG_SHIFT 0
347 #define MT6333_PMIC_RG_OTG_CHRIN_VOL_MASK 0x7
348 #define MT6333_PMIC_RG_OTG_CHRIN_VOL_SHIFT 3
349 #define MT6333_PMIC_RG_FORCE_OTG_NON_OV_MASK 0x1
350 #define MT6333_PMIC_RG_FORCE_OTG_NON_OV_SHIFT 7
351 #define MT6333_PMIC_RG_INOUT_CSREG_SEL_MASK 0x1
352 #define MT6333_PMIC_RG_INOUT_CSREG_SEL_SHIFT 0
353 #define MT6333_PMIC_RG_CHOPFREQ_SEL_MASK 0x1
354 #define MT6333_PMIC_RG_CHOPFREQ_SEL_SHIFT 4
355 #define MT6333_PMIC_RG_CHGPREG_SEL_MASK 0x3
356 #define MT6333_PMIC_RG_CHGPREG_SEL_SHIFT 6
357 #define MT6333_PMIC_RG_FLASH_DRV_EN_MASK 0x1
358 #define MT6333_PMIC_RG_FLASH_DRV_EN_SHIFT 0
359 #define MT6333_PMIC_RG_FPWM_OTG_MASK 0x1
360 #define MT6333_PMIC_RG_FPWM_OTG_SHIFT 0
361 #define MT6333_PMIC_RG_OTG_ZX_TESTMODE_MASK 0x1
362 #define MT6333_PMIC_RG_OTG_ZX_TESTMODE_SHIFT 2
363 #define MT6333_PMIC_RG_SWCHR_ZX_TESTMODE_MASK 0x1
364 #define MT6333_PMIC_RG_SWCHR_ZX_TESTMODE_SHIFT 4
365 #define MT6333_PMIC_RG_ZX_TRIM_MASK 0x7
366 #define MT6333_PMIC_RG_ZX_TRIM_SHIFT 0
367 #define MT6333_PMIC_RG_ZX_TRIM_OTG_MASK 0x7
368 #define MT6333_PMIC_RG_ZX_TRIM_OTG_SHIFT 4
369 #define MT6333_PMIC_RGS_AUTO_RECHARGE_MASK 0x1
370 #define MT6333_PMIC_RGS_AUTO_RECHARGE_SHIFT 0
371 #define MT6333_PMIC_RGS_CHARGE_COMPLETE_HW_MASK 0x1
372 #define MT6333_PMIC_RGS_CHARGE_COMPLETE_HW_SHIFT 1
373 #define MT6333_PMIC_RGS_PWM_OC_DET_MASK 0x1
374 #define MT6333_PMIC_RGS_PWM_OC_DET_SHIFT 2
375 #define MT6333_PMIC_RGS_VSYS_OV_DET_MASK 0x1
376 #define MT6333_PMIC_RGS_VSYS_OV_DET_SHIFT 3
377 #define MT6333_PMIC_RGS_POWER_PATH_MASK 0x1
378 #define MT6333_PMIC_RGS_POWER_PATH_SHIFT 4
379 #define MT6333_PMIC_RGS_FORCE_NO_PP_CONFIG_MASK 0x1
380 #define MT6333_PMIC_RGS_FORCE_NO_PP_CONFIG_SHIFT 5
381 #define MT6333_PMIC_RGS_CHRG_STATUS_MASK 0x1
382 #define MT6333_PMIC_RGS_CHRG_STATUS_SHIFT 6
383 #define MT6333_PMIC_RGS_BAT_ST_RECC_MASK 0x1
384 #define MT6333_PMIC_RGS_BAT_ST_RECC_SHIFT 0
385 #define MT6333_PMIC_RGS_SYS_GT_CV_MASK 0x1
386 #define MT6333_PMIC_RGS_SYS_GT_CV_SHIFT 1
387 #define MT6333_PMIC_RGS_BAT_GT_CC_MASK 0x1
388 #define MT6333_PMIC_RGS_BAT_GT_CC_SHIFT 2
389 #define MT6333_PMIC_RGS_BAT_GT_30_MASK 0x1
390 #define MT6333_PMIC_RGS_BAT_GT_30_SHIFT 3
391 #define MT6333_PMIC_RGS_BAT_GT_22_MASK 0x1
392 #define MT6333_PMIC_RGS_BAT_GT_22_SHIFT 4
393 #define MT6333_PMIC_RGS_BUCK_MODE_MASK 0x1
394 #define MT6333_PMIC_RGS_BUCK_MODE_SHIFT 0
395 #define MT6333_PMIC_RGS_BUCK_PRECC_MODE_MASK 0x1
396 #define MT6333_PMIC_RGS_BUCK_PRECC_MODE_SHIFT 1
397 #define MT6333_PMIC_RGS_CHRDET_MASK 0x1
398 #define MT6333_PMIC_RGS_CHRDET_SHIFT 2
399 #define MT6333_PMIC_RGS_CHR_HV_DET_MASK 0x1
400 #define MT6333_PMIC_RGS_CHR_HV_DET_SHIFT 3
401 #define MT6333_PMIC_RGS_CHR_PLUG_IN_MASK 0x1
402 #define MT6333_PMIC_RGS_CHR_PLUG_IN_SHIFT 4
403 #define MT6333_PMIC_RGS_BATON_UNDET_MASK 0x1
404 #define MT6333_PMIC_RGS_BATON_UNDET_SHIFT 5
405 #define MT6333_PMIC_RGS_CHRIN_LV_DET_MASK 0x1
406 #define MT6333_PMIC_RGS_CHRIN_LV_DET_SHIFT 6
407 #define MT6333_PMIC_RGS_CHRIN_HV_DET_MASK 0x1
408 #define MT6333_PMIC_RGS_CHRIN_HV_DET_SHIFT 7
409 #define MT6333_PMIC_RGS_THERMAL_SD_MODE_MASK 0x1
410 #define MT6333_PMIC_RGS_THERMAL_SD_MODE_SHIFT 0
411 #define MT6333_PMIC_RGS_CHR_HV_MODE_MASK 0x1
412 #define MT6333_PMIC_RGS_CHR_HV_MODE_SHIFT 1
413 #define MT6333_PMIC_RGS_BAT_ONLY_MODE_MASK 0x1
414 #define MT6333_PMIC_RGS_BAT_ONLY_MODE_SHIFT 2
415 #define MT6333_PMIC_RGS_CHR_SUSPEND_MODE_MASK 0x1
416 #define MT6333_PMIC_RGS_CHR_SUSPEND_MODE_SHIFT 3
417 #define MT6333_PMIC_RGS_PRECC_MODE_MASK 0x1
418 #define MT6333_PMIC_RGS_PRECC_MODE_SHIFT 4
419 #define MT6333_PMIC_RGS_CV_MODE_MASK 0x1
420 #define MT6333_PMIC_RGS_CV_MODE_SHIFT 5
421 #define MT6333_PMIC_RGS_CC_MODE_MASK 0x1
422 #define MT6333_PMIC_RGS_CC_MODE_SHIFT 6
423 #define MT6333_PMIC_RGS_OT_REG_MASK 0x1
424 #define MT6333_PMIC_RGS_OT_REG_SHIFT 0
425 #define MT6333_PMIC_RGS_OT_SD_MASK 0x1
426 #define MT6333_PMIC_RGS_OT_SD_SHIFT 1
427 #define MT6333_PMIC_RGS_PWM_BAT_CONFIG_MASK 0x1
428 #define MT6333_PMIC_RGS_PWM_BAT_CONFIG_SHIFT 2
429 #define MT6333_PMIC_RGS_PWM_CURRENT_CONFIG_MASK 0x1
430 #define MT6333_PMIC_RGS_PWM_CURRENT_CONFIG_SHIFT 3
431 #define MT6333_PMIC_RGS_PWM_VOLTAGE_CONFIG_MASK 0x1
432 #define MT6333_PMIC_RGS_PWM_VOLTAGE_CONFIG_SHIFT 4
433 #define MT6333_PMIC_RGS_BUCK_OVERLOAD_MASK 0x1
434 #define MT6333_PMIC_RGS_BUCK_OVERLOAD_SHIFT 0
435 #define MT6333_PMIC_RGS_BAT_DPPM_MODE_MASK 0x1
436 #define MT6333_PMIC_RGS_BAT_DPPM_MODE_SHIFT 1
437 #define MT6333_PMIC_RGS_ADAPTIVE_CV_MODE_MASK 0x1
438 #define MT6333_PMIC_RGS_ADAPTIVE_CV_MODE_SHIFT 2
439 #define MT6333_PMIC_RGS_VIN_DPM_MODE_MASK 0x1
440 #define MT6333_PMIC_RGS_VIN_DPM_MODE_SHIFT 3
441 #define MT6333_PMIC_RGS_THERMAL_REG_MODE_MASK 0x1
442 #define MT6333_PMIC_RGS_THERMAL_REG_MODE_SHIFT 4
443 #define MT6333_PMIC_RGS_ICH_SETTING_MASK 0xF
444 #define MT6333_PMIC_RGS_ICH_SETTING_SHIFT 0
445 #define MT6333_PMIC_RGS_CS_SEL_MASK 0xF
446 #define MT6333_PMIC_RGS_CS_SEL_SHIFT 4
447 #define MT6333_PMIC_RGS_SYSCV_FINE_SEL_MASK 0x7
448 #define MT6333_PMIC_RGS_SYSCV_FINE_SEL_SHIFT 0
449 #define MT6333_PMIC_RGS_OC_SD_SEL_MASK 0x1
450 #define MT6333_PMIC_RGS_OC_SD_SEL_SHIFT 4
451 #define MT6333_PMIC_RGS_PWM_OC_SEL_MASK 0x3
452 #define MT6333_PMIC_RGS_PWM_OC_SEL_SHIFT 6
453 #define MT6333_PMIC_RGS_CHRWDT_TOUT_MASK 0x1
454 #define MT6333_PMIC_RGS_CHRWDT_TOUT_SHIFT 0
455 #define MT6333_PMIC_RGS_VSYS_OV_VTH_MASK 0x7
456 #define MT6333_PMIC_RGS_VSYS_OV_VTH_SHIFT 1
457 #define MT6333_PMIC_RGS_SYSCV_COARSE_SEL_MASK 0xF
458 #define MT6333_PMIC_RGS_SYSCV_COARSE_SEL_SHIFT 4
459 #define MT6333_PMIC_RGS_USB_DL_KEY_MASK 0x1
460 #define MT6333_PMIC_RGS_USB_DL_KEY_SHIFT 0
461 #define MT6333_PMIC_RGS_FORCE_PP_ON_MASK 0x1
462 #define MT6333_PMIC_RGS_FORCE_PP_ON_SHIFT 1
463 #define MT6333_PMIC_RGS_INI_SYS_ON_MASK 0x1
464 #define MT6333_PMIC_RGS_INI_SYS_ON_SHIFT 2
465 #define MT6333_PMIC_RGS_ICH_OC_FLAG_CHR_CORE_MASK 0x1
466 #define MT6333_PMIC_RGS_ICH_OC_FLAG_CHR_CORE_SHIFT 0
467 #define MT6333_PMIC_RGS_PWM_OC_CHR_CORE_MASK 0x1
468 #define MT6333_PMIC_RGS_PWM_OC_CHR_CORE_SHIFT 1
469 #define MT6333_PMIC_RGS_POWER_ON_READY_MASK 0x1
470 #define MT6333_PMIC_RGS_POWER_ON_READY_SHIFT 0
471 #define MT6333_PMIC_RGS_AUTO_PWRON_MASK 0x1
472 #define MT6333_PMIC_RGS_AUTO_PWRON_SHIFT 1
473 #define MT6333_PMIC_RGS_AUTO_PWRON_DONE_MASK 0x1
474 #define MT6333_PMIC_RGS_AUTO_PWRON_DONE_SHIFT 2
475 #define MT6333_PMIC_RGS_CHR_MODE_MASK 0x1
476 #define MT6333_PMIC_RGS_CHR_MODE_SHIFT 3
477 #define MT6333_PMIC_RGS_OTG_MODE_MASK 0x1
478 #define MT6333_PMIC_RGS_OTG_MODE_SHIFT 4
479 #define MT6333_PMIC_RGS_POSEQ_DONE_MASK 0x1
480 #define MT6333_PMIC_RGS_POSEQ_DONE_SHIFT 5
481 #define MT6333_PMIC_RGS_OTG_PRECC_MASK 0x1
482 #define MT6333_PMIC_RGS_OTG_PRECC_SHIFT 6
483 #define MT6333_PMIC_RGS_CHRIN_SHORT_MASK 0x1
484 #define MT6333_PMIC_RGS_CHRIN_SHORT_SHIFT 0
485 #define MT6333_PMIC_RGS_DRVCDT_SHORT_MASK 0x1
486 #define MT6333_PMIC_RGS_DRVCDT_SHORT_SHIFT 1
487 #define MT6333_PMIC_RGS_OTG_M3_OC_MASK 0x1
488 #define MT6333_PMIC_RGS_OTG_M3_OC_SHIFT 2
489 #define MT6333_PMIC_RGS_OTG_THERMAL_MASK 0x1
490 #define MT6333_PMIC_RGS_OTG_THERMAL_SHIFT 3
491 #define MT6333_PMIC_RGS_CHR_IN_FLASH_MASK 0x1
492 #define MT6333_PMIC_RGS_CHR_IN_FLASH_SHIFT 4
493 #define MT6333_PMIC_RGS_VLED_SHORT_MASK 0x1
494 #define MT6333_PMIC_RGS_VLED_SHORT_SHIFT 5
495 #define MT6333_PMIC_RGS_VLED_OPEN_MASK 0x1
496 #define MT6333_PMIC_RGS_VLED_OPEN_SHIFT 6
497 #define MT6333_PMIC_RGS_FLASH_EN_TIMEOUT_MASK 0x1
498 #define MT6333_PMIC_RGS_FLASH_EN_TIMEOUT_SHIFT 7
499 #define MT6333_PMIC_RGS_CHR_OC_MASK 0x1
500 #define MT6333_PMIC_RGS_CHR_OC_SHIFT 0
501 #define MT6333_PMIC_RGS_PWM_EN_MASK 0x1
502 #define MT6333_PMIC_RGS_PWM_EN_SHIFT 2
503 #define MT6333_PMIC_RGS_OTG_EN_MASK 0x1
504 #define MT6333_PMIC_RGS_OTG_EN_SHIFT 3
505 #define MT6333_PMIC_RGS_OTG_EN_STB_MASK 0x1
506 #define MT6333_PMIC_RGS_OTG_EN_STB_SHIFT 4
507 #define MT6333_PMIC_RGS_OTG_DRV_EN_MASK 0x1
508 #define MT6333_PMIC_RGS_OTG_DRV_EN_SHIFT 5
509 #define MT6333_PMIC_RGS_FLASH_EN_MASK 0x1
510 #define MT6333_PMIC_RGS_FLASH_EN_SHIFT 6
511 #define MT6333_PMIC_RGS_M3_BOOST_EN_MASK 0x1
512 #define MT6333_PMIC_RGS_M3_BOOST_EN_SHIFT 0
513 #define MT6333_PMIC_RGS_M3_R_EN_MASK 0x1
514 #define MT6333_PMIC_RGS_M3_R_EN_SHIFT 1
515 #define MT6333_PMIC_RGS_M3_S_EN_MASK 0x1
516 #define MT6333_PMIC_RGS_M3_S_EN_SHIFT 2
517 #define MT6333_PMIC_RGS_M3_EN_MASK 0x1
518 #define MT6333_PMIC_RGS_M3_EN_SHIFT 3
519 #define MT6333_PMIC_RGS_CPCSTSYS_EN_MASK 0x1
520 #define MT6333_PMIC_RGS_CPCSTSYS_EN_SHIFT 4
521 #define MT6333_PMIC_RGS_SW_GATE_CTRL_MASK 0x1
522 #define MT6333_PMIC_RGS_SW_GATE_CTRL_SHIFT 5
523 #define MT6333_PMIC_QI_OTG_CHR_GT_LV_MASK 0x1
524 #define MT6333_PMIC_QI_OTG_CHR_GT_LV_SHIFT 6
525 #define MT6333_PMIC_RGS_THERMAL_RG_TH_MASK 0xF
526 #define MT6333_PMIC_RGS_THERMAL_RG_TH_SHIFT 0
527 #define MT6333_PMIC_RGS_OTG_OC_TH_MASK 0x3
528 #define MT6333_PMIC_RGS_OTG_OC_TH_SHIFT 5
529 #define MT6333_PMIC_RG_CHR_SUSPEND_MASK 0x1
530 #define MT6333_PMIC_RG_CHR_SUSPEND_SHIFT 0
531 #define MT6333_PMIC_RG_SYS_ON_MASK 0x1
532 #define MT6333_PMIC_RG_SYS_ON_SHIFT 1
533 #define MT6333_PMIC_RG_SYS_UNSTABLE_MASK 0x1
534 #define MT6333_PMIC_RG_SYS_UNSTABLE_SHIFT 2
535 #define MT6333_PMIC_RG_SKIP_EFUSE_OUT_MASK 0x1
536 #define MT6333_PMIC_RG_SKIP_EFUSE_OUT_SHIFT 0
537 #define MT6333_PMIC_RG_VSYS_SEL_MASK 0x3
538 #define MT6333_PMIC_RG_VSYS_SEL_SHIFT 2
539 #define MT6333_PMIC_RG_CV_SEL_MASK 0xF
540 #define MT6333_PMIC_RG_CV_SEL_SHIFT 4
541 #define MT6333_PMIC_RG_ICH_SEL_MASK 0xF
542 #define MT6333_PMIC_RG_ICH_SEL_SHIFT 0
543 #define MT6333_PMIC_RG_ICH_PRE_SEL_MASK 0x3
544 #define MT6333_PMIC_RG_ICH_PRE_SEL_SHIFT 6
545 #define MT6333_PMIC_RG_OC_SEL_MASK 0x3
546 #define MT6333_PMIC_RG_OC_SEL_SHIFT 2
547 #define MT6333_PMIC_RG_CHRIN_LV_VTH_MASK 0x3
548 #define MT6333_PMIC_RG_CHRIN_LV_VTH_SHIFT 4
549 #define MT6333_PMIC_RG_CHRIN_HV_VTH_MASK 0x3
550 #define MT6333_PMIC_RG_CHRIN_HV_VTH_SHIFT 6
551 #define MT6333_PMIC_RG_USBDL_EXT_MASK 0x1
552 #define MT6333_PMIC_RG_USBDL_EXT_SHIFT 0
553 #define MT6333_PMIC_RG_USBDL_MODE_B_MASK 0x1
554 #define MT6333_PMIC_RG_USBDL_MODE_B_SHIFT 1
555 #define MT6333_PMIC_RG_USBDL_OC_SEL_MASK 0xF
556 #define MT6333_PMIC_RG_USBDL_OC_SEL_SHIFT 4
557 #define MT6333_PMIC_RG_BUCK_OVERLOAD_PROT_EN_MASK 0x1
558 #define MT6333_PMIC_RG_BUCK_OVERLOAD_PROT_EN_SHIFT 0
559 #define MT6333_PMIC_RG_CH_COMPLETE_AUTO_OFF_MASK 0x1
560 #define MT6333_PMIC_RG_CH_COMPLETE_AUTO_OFF_SHIFT 1
561 #define MT6333_PMIC_RG_TERM_TIMER_MASK 0x3
562 #define MT6333_PMIC_RG_TERM_TIMER_SHIFT 2
563 #define MT6333_PMIC_RG_CHR_OC_AUTO_OFF_MASK 0x1
564 #define MT6333_PMIC_RG_CHR_OC_AUTO_OFF_SHIFT 0
565 #define MT6333_PMIC_RG_CHR_OC_RESET_MASK 0x1
566 #define MT6333_PMIC_RG_CHR_OC_RESET_SHIFT 2
567 #define MT6333_PMIC_RG_OTG_M3_OC_AUTO_OFF_MASK 0x1
568 #define MT6333_PMIC_RG_OTG_M3_OC_AUTO_OFF_SHIFT 4
569 #define MT6333_PMIC_RG_OTG_EN_MASK 0x1
570 #define MT6333_PMIC_RG_OTG_EN_SHIFT 0
571 #define MT6333_PMIC_RG_FLASH_EN_MASK 0x1
572 #define MT6333_PMIC_RG_FLASH_EN_SHIFT 0
573 #define MT6333_PMIC_RG_FLASH_PWM_EN_MASK 0x1
574 #define MT6333_PMIC_RG_FLASH_PWM_EN_SHIFT 0
575 #define MT6333_PMIC_RG_FLASH_PWM_EN_STB_MASK 0x1
576 #define MT6333_PMIC_RG_FLASH_PWM_EN_STB_SHIFT 2
577 #define MT6333_PMIC_RG_TORCH_MODE_MASK 0x1
578 #define MT6333_PMIC_RG_TORCH_MODE_SHIFT 4
579 #define MT6333_PMIC_RG_TORCH_CHRIN_CHK_MASK 0x1
580 #define MT6333_PMIC_RG_TORCH_CHRIN_CHK_SHIFT 6
581 #define MT6333_PMIC_RG_FLASH_DIM_DUTY_MASK 0x1F
582 #define MT6333_PMIC_RG_FLASH_DIM_DUTY_SHIFT 0
583 #define MT6333_PMIC_RG_CHK_CHRIN_TIME_EXT_MASK 0x3
584 #define MT6333_PMIC_RG_CHK_CHRIN_TIME_EXT_SHIFT 6
585 #define MT6333_PMIC_RG_FLASH_DIM_FSEL_MASK 0xFF
586 #define MT6333_PMIC_RG_FLASH_DIM_FSEL_SHIFT 0
587 #define MT6333_PMIC_RG_FLASH_ISET_MASK 0xF
588 #define MT6333_PMIC_RG_FLASH_ISET_SHIFT 0
589 #define MT6333_PMIC_RG_FLASH_ISET_STEP_MASK 0x3
590 #define MT6333_PMIC_RG_FLASH_ISET_STEP_SHIFT 5
591 #define MT6333_PMIC_RG_THERMAL_RG_TH_MASK 0xF
592 #define MT6333_PMIC_RG_THERMAL_RG_TH_SHIFT 0
593 #define MT6333_PMIC_RG_THERMAL_TEMP_SEL_MASK 0x1
594 #define MT6333_PMIC_RG_THERMAL_TEMP_SEL_SHIFT 0
595 #define MT6333_PMIC_RG_THERMAL_CHECKER_SEL_MASK 0x7
596 #define MT6333_PMIC_RG_THERMAL_CHECKER_SEL_SHIFT 2
597 #define MT6333_PMIC_RG_FLASH_EN_TIMEOUT_SEL_MASK 0x3
598 #define MT6333_PMIC_RG_FLASH_EN_TIMEOUT_SEL_SHIFT 6
599 #define MT6333_PMIC_RG_OTG_OC_TH_MASK 0x3
600 #define MT6333_PMIC_RG_OTG_OC_TH_SHIFT 0
601 #define MT6333_PMIC_RG_RESERVE_V0_MASK 0x3F
602 #define MT6333_PMIC_RG_RESERVE_V0_SHIFT 2
603 #define MT6333_PMIC_RG_CV_SEL_USBDL_MASK 0x3
604 #define MT6333_PMIC_RG_CV_SEL_USBDL_SHIFT 0
605 #define MT6333_PMIC_RG_OV_SEL_USBDL_MASK 0x3
606 #define MT6333_PMIC_RG_OV_SEL_USBDL_SHIFT 3
607 #define MT6333_PMIC_RG_SW_GATE_CTRL_MASK 0x1
608 #define MT6333_PMIC_RG_SW_GATE_CTRL_SHIFT 0
609 #define MT6333_PMIC_RG_RESERVE_V1_MASK 0x3F
610 #define MT6333_PMIC_RG_RESERVE_V1_SHIFT 2
611 #define MT6333_PMIC_RG_RESERVE_V2_MASK 0xFF
612 #define MT6333_PMIC_RG_RESERVE_V2_SHIFT 0
613 #define MT6333_PMIC_I2C_CONFIG_MASK 0x1
614 #define MT6333_PMIC_I2C_CONFIG_SHIFT 0
615 #define MT6333_PMIC_I2C_DEG_EN_MASK 0x1
616 #define MT6333_PMIC_I2C_DEG_EN_SHIFT 1
617 #define MT6333_PMIC_SDA_MODE_MASK 0x3
618 #define MT6333_PMIC_SDA_MODE_SHIFT 0
619 #define MT6333_PMIC_SDA_OE_MASK 0x1
620 #define MT6333_PMIC_SDA_OE_SHIFT 2
621 #define MT6333_PMIC_SDA_OUT_MASK 0x1
622 #define MT6333_PMIC_SDA_OUT_SHIFT 3
623 #define MT6333_PMIC_SCL_MODE_MASK 0x3
624 #define MT6333_PMIC_SCL_MODE_SHIFT 4
625 #define MT6333_PMIC_SCL_OE_MASK 0x1
626 #define MT6333_PMIC_SCL_OE_SHIFT 6
627 #define MT6333_PMIC_SCL_OUT_MASK 0x1
628 #define MT6333_PMIC_SCL_OUT_SHIFT 7
629 #define MT6333_PMIC_INT_MODE_MASK 0x3
630 #define MT6333_PMIC_INT_MODE_SHIFT 0
631 #define MT6333_PMIC_INT_OE_MASK 0x1
632 #define MT6333_PMIC_INT_OE_SHIFT 2
633 #define MT6333_PMIC_INT_OUT_MASK 0x1
634 #define MT6333_PMIC_INT_OUT_SHIFT 3
635 #define MT6333_PMIC_RG_CHR_250K_CK_EN_MASK 0x1
636 #define MT6333_PMIC_RG_CHR_250K_CK_EN_SHIFT 0
637 #define MT6333_PMIC_RG_CHR_1M_CK_EN_MASK 0x1
638 #define MT6333_PMIC_RG_CHR_1M_CK_EN_SHIFT 1
639 #define MT6333_PMIC_RG_CHR_PWM_CK_EN_MASK 0x1
640 #define MT6333_PMIC_RG_CHR_PWM_CK_EN_SHIFT 2
641 #define MT6333_PMIC_RG_BUCK_1M_CK_EN_MASK 0x1
642 #define MT6333_PMIC_RG_BUCK_1M_CK_EN_SHIFT 4
643 #define MT6333_PMIC_RG_BUCK_2M_CK_EN_MASK 0x1
644 #define MT6333_PMIC_RG_BUCK_2M_CK_EN_SHIFT 5
645 #define MT6333_PMIC_RG_BUCK_3M_CK_EN_MASK 0x1
646 #define MT6333_PMIC_RG_BUCK_3M_CK_EN_SHIFT 6
647 #define MT6333_PMIC_RG_BUCK_6M_CK_EN_MASK 0x1
648 #define MT6333_PMIC_RG_BUCK_6M_CK_EN_SHIFT 7
649 #define MT6333_PMIC_CLK_CON0_SET_MASK 0x1
650 #define MT6333_PMIC_CLK_CON0_SET_SHIFT 7
651 #define MT6333_PMIC_CLK_CON0_CLR_MASK 0x1
652 #define MT6333_PMIC_CLK_CON0_CLR_SHIFT 7
653 #define MT6333_PMIC_RG_BUCK_OSC_EN_MASK 0x1
654 #define MT6333_PMIC_RG_BUCK_OSC_EN_SHIFT 0
655 #define MT6333_PMIC_QI_OSC_EN_MASK 0x1
656 #define MT6333_PMIC_QI_OSC_EN_SHIFT 7
657 #define MT6333_PMIC_RG_BUCK_CALI_32K_CK_EN_MASK 0x1
658 #define MT6333_PMIC_RG_BUCK_CALI_32K_CK_EN_SHIFT 0
659 #define MT6333_PMIC_RG_BUCK_CALI_PWM_CK_EN_MASK 0x1
660 #define MT6333_PMIC_RG_BUCK_CALI_PWM_CK_EN_SHIFT 1
661 #define MT6333_PMIC_RG_BUCK_CALI_6M_CK_EN_MASK 0x1
662 #define MT6333_PMIC_RG_BUCK_CALI_6M_CK_EN_SHIFT 2
663 #define MT6333_PMIC_RG_TEST_EFUSE_MASK 0x1
664 #define MT6333_PMIC_RG_TEST_EFUSE_SHIFT 3
665 #define MT6333_PMIC_RG_TEST_NI_CK_MASK 0x1
666 #define MT6333_PMIC_RG_TEST_NI_CK_SHIFT 4
667 #define MT6333_PMIC_RG_TEST_SMPS_CK_MASK 0x1
668 #define MT6333_PMIC_RG_TEST_SMPS_CK_SHIFT 5
669 #define MT6333_PMIC_RG_TEST_PWM_CK_MASK 0x1
670 #define MT6333_PMIC_RG_TEST_PWM_CK_SHIFT 6
671 #define MT6333_PMIC_RG_INT_EN_CHR_COMPLETE_MASK 0x1
672 #define MT6333_PMIC_RG_INT_EN_CHR_COMPLETE_SHIFT 0
673 #define MT6333_PMIC_RG_INT_EN_THERMAL_SD_MASK 0x1
674 #define MT6333_PMIC_RG_INT_EN_THERMAL_SD_SHIFT 1
675 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_IN_MASK 0x1
676 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_IN_SHIFT 2
677 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_OUT_MASK 0x1
678 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_OUT_SHIFT 3
679 #define MT6333_PMIC_RG_INT_EN_OTG_OC_MASK 0x1
680 #define MT6333_PMIC_RG_INT_EN_OTG_OC_SHIFT 4
681 #define MT6333_PMIC_RG_INT_EN_OTG_THERMAL_MASK 0x1
682 #define MT6333_PMIC_RG_INT_EN_OTG_THERMAL_SHIFT 5
683 #define MT6333_PMIC_RG_INT_EN_OTG_CHRIN_SHORT_MASK 0x1
684 #define MT6333_PMIC_RG_INT_EN_OTG_CHRIN_SHORT_SHIFT 6
685 #define MT6333_PMIC_RG_INT_EN_OTG_DRVCDT_SHORT_MASK 0x1
686 #define MT6333_PMIC_RG_INT_EN_OTG_DRVCDT_SHORT_SHIFT 7
687 #define MT6333_PMIC_RG_INT_EN_CHR_COMPLETE_SET_MASK 0x1
688 #define MT6333_PMIC_RG_INT_EN_CHR_COMPLETE_SET_SHIFT 0
689 #define MT6333_PMIC_RG_INT_EN_THERMAL_SD_SET_MASK 0x1
690 #define MT6333_PMIC_RG_INT_EN_THERMAL_SD_SET_SHIFT 1
691 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_IN_SET_MASK 0x1
692 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_IN_SET_SHIFT 2
693 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_OUT_SET_MASK 0x1
694 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_OUT_SET_SHIFT 3
695 #define MT6333_PMIC_RG_INT_EN_OTG_OC_SET_MASK 0x1
696 #define MT6333_PMIC_RG_INT_EN_OTG_OC_SET_SHIFT 4
697 #define MT6333_PMIC_RG_INT_EN_OTG_THERMAL_SET_MASK 0x1
698 #define MT6333_PMIC_RG_INT_EN_OTG_THERMAL_SET_SHIFT 5
699 #define MT6333_PMIC_RG_INT_EN_OTG_CHRIN_SHORT_SET_MASK 0x1
700 #define MT6333_PMIC_RG_INT_EN_OTG_CHRIN_SHORT_SET_SHIFT 6
701 #define MT6333_PMIC_RG_INT_EN_OTG_DRVCDT_SHORT_SET_MASK 0x1
702 #define MT6333_PMIC_RG_INT_EN_OTG_DRVCDT_SHORT_SET_SHIFT 7
703 #define MT6333_PMIC_RG_INT_EN_CHR_COMPLETE_CLR_MASK 0x1
704 #define MT6333_PMIC_RG_INT_EN_CHR_COMPLETE_CLR_SHIFT 0
705 #define MT6333_PMIC_RG_INT_EN_THERMAL_SD_CLR_MASK 0x1
706 #define MT6333_PMIC_RG_INT_EN_THERMAL_SD_CLR_SHIFT 1
707 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_IN_CLR_MASK 0x1
708 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_IN_CLR_SHIFT 2
709 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_OUT_CLR_MASK 0x1
710 #define MT6333_PMIC_RG_INT_EN_THERMAL_REG_OUT_CLR_SHIFT 3
711 #define MT6333_PMIC_RG_INT_EN_OTG_OC_CLR_MASK 0x1
712 #define MT6333_PMIC_RG_INT_EN_OTG_OC_CLR_SHIFT 4
713 #define MT6333_PMIC_RG_INT_EN_OTG_THERMAL_CLR_MASK 0x1
714 #define MT6333_PMIC_RG_INT_EN_OTG_THERMAL_CLR_SHIFT 5
715 #define MT6333_PMIC_RG_INT_EN_OTG_CHRIN_SHORT_CLR_MASK 0x1
716 #define MT6333_PMIC_RG_INT_EN_OTG_CHRIN_SHORT_CLR_SHIFT 6
717 #define MT6333_PMIC_RG_INT_EN_OTG_DRVCDT_SHORT_CLR_MASK 0x1
718 #define MT6333_PMIC_RG_INT_EN_OTG_DRVCDT_SHORT_CLR_SHIFT 7
719 #define MT6333_PMIC_RG_INT_EN_CHRWDT_FLAG_MASK 0x1
720 #define MT6333_PMIC_RG_INT_EN_CHRWDT_FLAG_SHIFT 0
721 #define MT6333_PMIC_RG_INT_EN_BUCK_VCORE_OC_MASK 0x1
722 #define MT6333_PMIC_RG_INT_EN_BUCK_VCORE_OC_SHIFT 1
723 #define MT6333_PMIC_RG_INT_EN_BUCK_VMEM_OC_MASK 0x1
724 #define MT6333_PMIC_RG_INT_EN_BUCK_VMEM_OC_SHIFT 2
725 #define MT6333_PMIC_RG_INT_EN_BUCK_VRF18_OC_MASK 0x1
726 #define MT6333_PMIC_RG_INT_EN_BUCK_VRF18_OC_SHIFT 3
727 #define MT6333_PMIC_RG_INT_EN_BUCK_THERMAL_MASK 0x1
728 #define MT6333_PMIC_RG_INT_EN_BUCK_THERMAL_SHIFT 4
729 #define MT6333_PMIC_RG_INT_EN_FLASH_EN_TIMEOUT_MASK 0x1
730 #define MT6333_PMIC_RG_INT_EN_FLASH_EN_TIMEOUT_SHIFT 5
731 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_SHORT_MASK 0x1
732 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_SHORT_SHIFT 6
733 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_OPEN_MASK 0x1
734 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_OPEN_SHIFT 7
735 #define MT6333_PMIC_RG_INT_EN_CHRWDT_FLAG_SET_MASK 0x1
736 #define MT6333_PMIC_RG_INT_EN_CHRWDT_FLAG_SET_SHIFT 0
737 #define MT6333_PMIC_RG_INT_EN_BUCK_VCORE_OC_SET_MASK 0x1
738 #define MT6333_PMIC_RG_INT_EN_BUCK_VCORE_OC_SET_SHIFT 1
739 #define MT6333_PMIC_RG_INT_EN_BUCK_VMEM_OC_SET_MASK 0x1
740 #define MT6333_PMIC_RG_INT_EN_BUCK_VMEM_OC_SET_SHIFT 2
741 #define MT6333_PMIC_RG_INT_EN_BUCK_VRF18_OC_SET_MASK 0x1
742 #define MT6333_PMIC_RG_INT_EN_BUCK_VRF18_OC_SET_SHIFT 3
743 #define MT6333_PMIC_RG_INT_EN_BUCK_THERMAL_SET_MASK 0x1
744 #define MT6333_PMIC_RG_INT_EN_BUCK_THERMAL_SET_SHIFT 4
745 #define MT6333_PMIC_RG_INT_EN_FLASH_EN_TIMEOUT_SET_MASK 0x1
746 #define MT6333_PMIC_RG_INT_EN_FLASH_EN_TIMEOUT_SET_SHIFT 5
747 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_SHORT_SET_MASK 0x1
748 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_SHORT_SET_SHIFT 6
749 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_OPEN_SET_MASK 0x1
750 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_OPEN_SET_SHIFT 7
751 #define MT6333_PMIC_RG_INT_EN_CHRWDT_FLAG_CLR_MASK 0x1
752 #define MT6333_PMIC_RG_INT_EN_CHRWDT_FLAG_CLR_SHIFT 0
753 #define MT6333_PMIC_RG_INT_EN_BUCK_VCORE_OC_CLR_MASK 0x1
754 #define MT6333_PMIC_RG_INT_EN_BUCK_VCORE_OC_CLR_SHIFT 1
755 #define MT6333_PMIC_RG_INT_EN_BUCK_VMEM_OC_CLR_MASK 0x1
756 #define MT6333_PMIC_RG_INT_EN_BUCK_VMEM_OC_CLR_SHIFT 2
757 #define MT6333_PMIC_RG_INT_EN_BUCK_VRF18_OC_CLR_MASK 0x1
758 #define MT6333_PMIC_RG_INT_EN_BUCK_VRF18_OC_CLR_SHIFT 3
759 #define MT6333_PMIC_RG_INT_EN_BUCK_THERMAL_CLR_MASK 0x1
760 #define MT6333_PMIC_RG_INT_EN_BUCK_THERMAL_CLR_SHIFT 4
761 #define MT6333_PMIC_RG_INT_EN_FLASH_EN_TIMEOUT_CLR_MASK 0x1
762 #define MT6333_PMIC_RG_INT_EN_FLASH_EN_TIMEOUT_CLR_SHIFT 5
763 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_SHORT_CLR_MASK 0x1
764 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_SHORT_CLR_SHIFT 6
765 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_OPEN_CLR_MASK 0x1
766 #define MT6333_PMIC_RG_INT_EN_FLASH_VLED_OPEN_CLR_SHIFT 7
767 #define MT6333_PMIC_RG_INT_EN_CHR_OC_MASK 0x1
768 #define MT6333_PMIC_RG_INT_EN_CHR_OC_SHIFT 0
769 #define MT6333_PMIC_RG_INT_EN_CHR_PLUG_IN_FLASH_MASK 0x1
770 #define MT6333_PMIC_RG_INT_EN_CHR_PLUG_IN_FLASH_SHIFT 1
771 #define MT6333_PMIC_RG_INT_EN_CHR_OC_SET_MASK 0x1
772 #define MT6333_PMIC_RG_INT_EN_CHR_OC_SET_SHIFT 0
773 #define MT6333_PMIC_RG_INT_EN_CHR_PLUG_IN_FLASH_SET_MASK 0x1
774 #define MT6333_PMIC_RG_INT_EN_CHR_PLUG_IN_FLASH_SET_SHIFT 1
775 #define MT6333_PMIC_RG_INT_EN_CHR_OC_CLR_MASK 0x1
776 #define MT6333_PMIC_RG_INT_EN_CHR_OC_CLR_SHIFT 0
777 #define MT6333_PMIC_RG_INT_EN_CHR_PLUG_IN_FLASH_CLR_MASK 0x1
778 #define MT6333_PMIC_RG_INT_EN_CHR_PLUG_IN_FLASH_CLR_SHIFT 1
779 #define MT6333_PMIC_RG_CHRWDT_EN_MASK 0x1
780 #define MT6333_PMIC_RG_CHRWDT_EN_SHIFT 0
781 #define MT6333_PMIC_RG_CHRWDT_TD_MASK 0x7
782 #define MT6333_PMIC_RG_CHRWDT_TD_SHIFT 1
783 #define MT6333_PMIC_RG_CHRWDT_WR_MASK 0x1
784 #define MT6333_PMIC_RG_CHRWDT_WR_SHIFT 7
785 #define MT6333_PMIC_RG_CHRWDT_FLAG_MASK 0x1
786 #define MT6333_PMIC_RG_CHRWDT_FLAG_SHIFT 0
787 #define MT6333_PMIC_RG_INT_STATUS_CHR_COMPLETE_MASK 0x1
788 #define MT6333_PMIC_RG_INT_STATUS_CHR_COMPLETE_SHIFT 0
789 #define MT6333_PMIC_RG_INT_STATUS_THERMAL_SD_MASK 0x1
790 #define MT6333_PMIC_RG_INT_STATUS_THERMAL_SD_SHIFT 1
791 #define MT6333_PMIC_RG_INT_STATUS_THERMAL_REG_IN_MASK 0x1
792 #define MT6333_PMIC_RG_INT_STATUS_THERMAL_REG_IN_SHIFT 2
793 #define MT6333_PMIC_RG_INT_STATUS_THERMAL_REG_OUT_MASK 0x1
794 #define MT6333_PMIC_RG_INT_STATUS_THERMAL_REG_OUT_SHIFT 3
795 #define MT6333_PMIC_RG_INT_STATUS_OTG_OC_MASK 0x1
796 #define MT6333_PMIC_RG_INT_STATUS_OTG_OC_SHIFT 4
797 #define MT6333_PMIC_RG_INT_STATUS_OTG_THERMAL_MASK 0x1
798 #define MT6333_PMIC_RG_INT_STATUS_OTG_THERMAL_SHIFT 5
799 #define MT6333_PMIC_RG_INT_STATUS_OTG_CHRIN_SHORT_MASK 0x1
800 #define MT6333_PMIC_RG_INT_STATUS_OTG_CHRIN_SHORT_SHIFT 6
801 #define MT6333_PMIC_RG_INT_STATUS_OTG_DRVCDT_SHORT_MASK 0x1
802 #define MT6333_PMIC_RG_INT_STATUS_OTG_DRVCDT_SHORT_SHIFT 7
803 #define MT6333_PMIC_RG_INT_STATUS_CHRWDT_FLAG_MASK 0x1
804 #define MT6333_PMIC_RG_INT_STATUS_CHRWDT_FLAG_SHIFT 0
805 #define MT6333_PMIC_RG_INT_STATUS_BUCK_VCORE_OC_MASK 0x1
806 #define MT6333_PMIC_RG_INT_STATUS_BUCK_VCORE_OC_SHIFT 1
807 #define MT6333_PMIC_RG_INT_STATUS_BUCK_VMEM_OC_MASK 0x1
808 #define MT6333_PMIC_RG_INT_STATUS_BUCK_VMEM_OC_SHIFT 2
809 #define MT6333_PMIC_RG_INT_STATUS_BUCK_VRF18_OC_MASK 0x1
810 #define MT6333_PMIC_RG_INT_STATUS_BUCK_VRF18_OC_SHIFT 3
811 #define MT6333_PMIC_RG_INT_STATUS_BUCK_THERMAL_MASK 0x1
812 #define MT6333_PMIC_RG_INT_STATUS_BUCK_THERMAL_SHIFT 4
813 #define MT6333_PMIC_RG_INT_STATUS_FLASH_EN_TIMEOUT_MASK 0x1
814 #define MT6333_PMIC_RG_INT_STATUS_FLASH_EN_TIMEOUT_SHIFT 5
815 #define MT6333_PMIC_RG_INT_STATUS_FLASH_VLED_SHORT_MASK 0x1
816 #define MT6333_PMIC_RG_INT_STATUS_FLASH_VLED_SHORT_SHIFT 6
817 #define MT6333_PMIC_RG_INT_STATUS_FLASH_VLED_OPEN_MASK 0x1
818 #define MT6333_PMIC_RG_INT_STATUS_FLASH_VLED_OPEN_SHIFT 7
819 #define MT6333_PMIC_RG_INT_STATUS_CHR_OC_MASK 0x1
820 #define MT6333_PMIC_RG_INT_STATUS_CHR_OC_SHIFT 0
821 #define MT6333_PMIC_RG_INT_STATUS_CHR_PLUG_IN_FLASH_MASK 0x1
822 #define MT6333_PMIC_RG_INT_STATUS_CHR_PLUG_IN_FLASH_SHIFT 1
823 #define MT6333_PMIC_VCORE_DEG_EN_MASK 0x1
824 #define MT6333_PMIC_VCORE_DEG_EN_SHIFT 0
825 #define MT6333_PMIC_VCORE_OC_WND_MASK 0x3
826 #define MT6333_PMIC_VCORE_OC_WND_SHIFT 2
827 #define MT6333_PMIC_VCORE_OC_THD_MASK 0x3
828 #define MT6333_PMIC_VCORE_OC_THD_SHIFT 5
829 #define MT6333_PMIC_VMEM_DEG_EN_MASK 0x1
830 #define MT6333_PMIC_VMEM_DEG_EN_SHIFT 0
831 #define MT6333_PMIC_VMEM_OC_WND_MASK 0x3
832 #define MT6333_PMIC_VMEM_OC_WND_SHIFT 2
833 #define MT6333_PMIC_VMEM_OC_THD_MASK 0x3
834 #define MT6333_PMIC_VMEM_OC_THD_SHIFT 5
835 #define MT6333_PMIC_VRF18_DEG_EN_MASK 0x1
836 #define MT6333_PMIC_VRF18_DEG_EN_SHIFT 0
837 #define MT6333_PMIC_VRF18_OC_WND_MASK 0x3
838 #define MT6333_PMIC_VRF18_OC_WND_SHIFT 2
839 #define MT6333_PMIC_VRF18_OC_THD_MASK 0x3
840 #define MT6333_PMIC_VRF18_OC_THD_SHIFT 5
841 #define MT6333_PMIC_INT_POLARITY_MASK 0x1
842 #define MT6333_PMIC_INT_POLARITY_SHIFT 0
843 #define MT6333_PMIC_RG_SMPS_TESTMODE_B_MASK 0xFF
844 #define MT6333_PMIC_RG_SMPS_TESTMODE_B_SHIFT 0
845 #define MT6333_PMIC_RG_VCORE_TRIML_MASK 0x7
846 #define MT6333_PMIC_RG_VCORE_TRIML_SHIFT 0
847 #define MT6333_PMIC_RG_VCORE_TRIMH_MASK 0x7
848 #define MT6333_PMIC_RG_VCORE_TRIMH_SHIFT 5
849 #define MT6333_PMIC_RG_VCORE_CC_MASK 0x3
850 #define MT6333_PMIC_RG_VCORE_CC_SHIFT 3
851 #define MT6333_PMIC_RG_VCORE_RZSEL_MASK 0x3
852 #define MT6333_PMIC_RG_VCORE_RZSEL_SHIFT 6
853 #define MT6333_PMIC_RG_VCORE_SLP_MASK 0x3
854 #define MT6333_PMIC_RG_VCORE_SLP_SHIFT 2
855 #define MT6333_PMIC_RG_VCORE_CSL_MASK 0x3
856 #define MT6333_PMIC_RG_VCORE_CSL_SHIFT 4
857 #define MT6333_PMIC_RG_VCORE_CSR_MASK 0x3
858 #define MT6333_PMIC_RG_VCORE_CSR_SHIFT 6
859 #define MT6333_PMIC_RG_VCORE_AVP_OS_MASK 0x7
860 #define MT6333_PMIC_RG_VCORE_AVP_OS_SHIFT 0
861 #define MT6333_PMIC_RG_VCORE_AVP_EN_MASK 0x1
862 #define MT6333_PMIC_RG_VCORE_AVP_EN_SHIFT 3
863 #define MT6333_PMIC_RG_VCORE_NDIS_EN_MASK 0x1
864 #define MT6333_PMIC_RG_VCORE_NDIS_EN_SHIFT 4
865 #define MT6333_PMIC_RG_VCORE_MODESET_MASK 0x1
866 #define MT6333_PMIC_RG_VCORE_MODESET_SHIFT 5
867 #define MT6333_PMIC_RG_VCORE_ZX_OS_MASK 0x3
868 #define MT6333_PMIC_RG_VCORE_ZX_OS_SHIFT 6
869 #define MT6333_PMIC_RG_VCORE_CSM_MASK 0x7
870 #define MT6333_PMIC_RG_VCORE_CSM_SHIFT 5
871 #define MT6333_PMIC_RG_VCORE_ZXOS_TRIM_MASK 0x3F
872 #define MT6333_PMIC_RG_VCORE_ZXOS_TRIM_SHIFT 2
873 #define MT6333_PMIC_RG_VCORE_RSV_MASK 0xFF
874 #define MT6333_PMIC_RG_VCORE_RSV_SHIFT 0
875 #define MT6333_PMIC_QI_VCORE_DIG_MON_MASK 0xF
876 #define MT6333_PMIC_QI_VCORE_DIG_MON_SHIFT 0
877 #define MT6333_PMIC_QI_VCORE_OC_STATUS_MASK 0x1
878 #define MT6333_PMIC_QI_VCORE_OC_STATUS_SHIFT 7
879 #define MT6333_PMIC_VSLEEP_SRC1_MASK 0xF
880 #define MT6333_PMIC_VSLEEP_SRC1_SHIFT 4
881 #define MT6333_PMIC_VSLEEP_SRC0_7_0_MASK 0xFF
882 #define MT6333_PMIC_VSLEEP_SRC0_7_0_SHIFT 0
883 #define MT6333_PMIC_VSLEEP_SRC0_8_MASK 0x1
884 #define MT6333_PMIC_VSLEEP_SRC0_8_SHIFT 7
885 #define MT6333_PMIC_R2R_SRC0_8_MASK 0x1
886 #define MT6333_PMIC_R2R_SRC0_8_SHIFT 0
887 #define MT6333_PMIC_R2R_SRC1_MASK 0xF
888 #define MT6333_PMIC_R2R_SRC1_SHIFT 4
889 #define MT6333_PMIC_R2R_SRC0_7_0_MASK 0xFF
890 #define MT6333_PMIC_R2R_SRC0_7_0_SHIFT 0
891 #define MT6333_PMIC_SRCLKEN_DLY_SRC1_MASK 0xF
892 #define MT6333_PMIC_SRCLKEN_DLY_SRC1_SHIFT 4
893 #define MT6333_PMIC_RG_BUCK_RSV0_MASK 0xFF
894 #define MT6333_PMIC_RG_BUCK_RSV0_SHIFT 0
895 #define MT6333_PMIC_RG_SRCLKEN_DLY_SEL_MASK 0x1
896 #define MT6333_PMIC_RG_SRCLKEN_DLY_SEL_SHIFT 6
897 #define MT6333_PMIC_RG_R2R_EVENT_SEL_MASK 0x1
898 #define MT6333_PMIC_RG_R2R_EVENT_SEL_SHIFT 7
899 #define MT6333_PMIC_QI_VCORE_VSLEEP_MASK 0x3
900 #define MT6333_PMIC_QI_VCORE_VSLEEP_SHIFT 6
901 #define MT6333_PMIC_VCORE_EN_MASK 0x1
902 #define MT6333_PMIC_VCORE_EN_SHIFT 1
903 #define MT6333_PMIC_QI_VCORE_STB_MASK 0x1
904 #define MT6333_PMIC_QI_VCORE_STB_SHIFT 2
905 #define MT6333_PMIC_QI_VCORE_EN_MASK 0x1
906 #define MT6333_PMIC_QI_VCORE_EN_SHIFT 3
907 #define MT6333_PMIC_VCORE_EN_CTRL_MASK 0x1
908 #define MT6333_PMIC_VCORE_EN_CTRL_SHIFT 4
909 #define MT6333_PMIC_VCORE_VOSEL_CTRL_MASK 0x1
910 #define MT6333_PMIC_VCORE_VOSEL_CTRL_SHIFT 5
911 #define MT6333_PMIC_VCORE_DLC_CTRL_MASK 0x1
912 #define MT6333_PMIC_VCORE_DLC_CTRL_SHIFT 6
913 #define MT6333_PMIC_VCORE_BURST_CTRL_MASK 0x1
914 #define MT6333_PMIC_VCORE_BURST_CTRL_SHIFT 7
915 #define MT6333_PMIC_VCORE_SFCHG_REN_MASK 0x1
916 #define MT6333_PMIC_VCORE_SFCHG_REN_SHIFT 0
917 #define MT6333_PMIC_VCORE_SFCHG_RRATE_MASK 0x7F
918 #define MT6333_PMIC_VCORE_SFCHG_RRATE_SHIFT 1
919 #define MT6333_PMIC_VCORE_SFCHG_FEN_MASK 0x1
920 #define MT6333_PMIC_VCORE_SFCHG_FEN_SHIFT 0
921 #define MT6333_PMIC_VCORE_SFCHG_FRATE_MASK 0x7F
922 #define MT6333_PMIC_VCORE_SFCHG_FRATE_SHIFT 1
923 #define MT6333_PMIC_VCORE_VOSEL_MASK 0x7F
924 #define MT6333_PMIC_VCORE_VOSEL_SHIFT 0
925 #define MT6333_PMIC_VCORE_VOSEL_ON_MASK 0x7F
926 #define MT6333_PMIC_VCORE_VOSEL_ON_SHIFT 0
927 #define MT6333_PMIC_VCORE_VOSEL_SLEEP_MASK 0x7F
928 #define MT6333_PMIC_VCORE_VOSEL_SLEEP_SHIFT 0
929 #define MT6333_PMIC_NI_VCORE_VOSEL_MASK 0x7F
930 #define MT6333_PMIC_NI_VCORE_VOSEL_SHIFT 0
931 #define MT6333_PMIC_VCORE_BURST_MASK 0x3
932 #define MT6333_PMIC_VCORE_BURST_SHIFT 0
933 #define MT6333_PMIC_VCORE_BURST_ON_MASK 0x3
934 #define MT6333_PMIC_VCORE_BURST_ON_SHIFT 2
935 #define MT6333_PMIC_VCORE_BURST_SLEEP_MASK 0x3
936 #define MT6333_PMIC_VCORE_BURST_SLEEP_SHIFT 4
937 #define MT6333_PMIC_QI_VCORE_BURST_MASK 0x3
938 #define MT6333_PMIC_QI_VCORE_BURST_SHIFT 6
939 #define MT6333_PMIC_VCORE_DLC_MASK 0x3
940 #define MT6333_PMIC_VCORE_DLC_SHIFT 0
941 #define MT6333_PMIC_VCORE_DLC_ON_MASK 0x3
942 #define MT6333_PMIC_VCORE_DLC_ON_SHIFT 2
943 #define MT6333_PMIC_VCORE_DLC_SLEEP_MASK 0x3
944 #define MT6333_PMIC_VCORE_DLC_SLEEP_SHIFT 4
945 #define MT6333_PMIC_QI_VCORE_DLC_MASK 0x3
946 #define MT6333_PMIC_QI_VCORE_DLC_SHIFT 6
947 #define MT6333_PMIC_VCORE_DLC_N_MASK 0x3
948 #define MT6333_PMIC_VCORE_DLC_N_SHIFT 0
949 #define MT6333_PMIC_VCORE_DLC_N_ON_MASK 0x3
950 #define MT6333_PMIC_VCORE_DLC_N_ON_SHIFT 2
951 #define MT6333_PMIC_VCORE_DLC_N_SLEEP_MASK 0x3
952 #define MT6333_PMIC_VCORE_DLC_N_SLEEP_SHIFT 4
953 #define MT6333_PMIC_QI_VCORE_DLC_N_MASK 0x3
954 #define MT6333_PMIC_QI_VCORE_DLC_N_SHIFT 6
955 #define MT6333_PMIC_VCORE_VSLEEP_EN_MASK 0x1
956 #define MT6333_PMIC_VCORE_VSLEEP_EN_SHIFT 3
957 #define MT6333_PMIC_VCORE_R2R_PDN_MASK 0x1
958 #define MT6333_PMIC_VCORE_R2R_PDN_SHIFT 4
959 #define MT6333_PMIC_VCORE_VSLEEP_SEL_MASK 0x1
960 #define MT6333_PMIC_VCORE_VSLEEP_SEL_SHIFT 5
961 #define MT6333_PMIC_NI_VCORE_R2R_PDN_MASK 0x1
962 #define MT6333_PMIC_NI_VCORE_R2R_PDN_SHIFT 6
963 #define MT6333_PMIC_NI_VCORE_VSLEEP_SEL_MASK 0x1
964 #define MT6333_PMIC_NI_VCORE_VSLEEP_SEL_SHIFT 7
965 #define MT6333_PMIC_VCORE_TRANSTD_MASK 0x3
966 #define MT6333_PMIC_VCORE_TRANSTD_SHIFT 0
967 #define MT6333_PMIC_VCORE_VOSEL_TRANS_EN_MASK 0x3
968 #define MT6333_PMIC_VCORE_VOSEL_TRANS_EN_SHIFT 2
969 #define MT6333_PMIC_VCORE_VOSEL_TRANS_ONCE_MASK 0x1
970 #define MT6333_PMIC_VCORE_VOSEL_TRANS_ONCE_SHIFT 4
971 #define MT6333_PMIC_NI_VCORE_VOSEL_TRANS_MASK 0x1
972 #define MT6333_PMIC_NI_VCORE_VOSEL_TRANS_SHIFT 5
973 #define MT6333_PMIC_VCORE_SFCHG_FEN_SLEEP_MASK 0x1
974 #define MT6333_PMIC_VCORE_SFCHG_FEN_SLEEP_SHIFT 0
975 #define MT6333_PMIC_VCORE_SFCHG_REN_SLEEP_MASK 0x1
976 #define MT6333_PMIC_VCORE_SFCHG_REN_SLEEP_SHIFT 1
977 #define MT6333_PMIC_VCORE_VOSEL_ON_SPM_MASK 0x7F
978 #define MT6333_PMIC_VCORE_VOSEL_ON_SPM_SHIFT 0
979 #define MT6333_PMIC_RG_VCORE_EN_OC_SDN_SEL_MASK 0x1
980 #define MT6333_PMIC_RG_VCORE_EN_OC_SDN_SEL_SHIFT 0
981 #define MT6333_PMIC_RG_VMEM_EN_OC_SDN_SEL_MASK 0x1
982 #define MT6333_PMIC_RG_VMEM_EN_OC_SDN_SEL_SHIFT 1
983 #define MT6333_PMIC_RG_VCORE_EN_THR_SDN_SEL_MASK 0x1
984 #define MT6333_PMIC_RG_VCORE_EN_THR_SDN_SEL_SHIFT 2
985 #define MT6333_PMIC_RG_VMEM_RSV1_5_0_3_MASK 0x1
986 #define MT6333_PMIC_RG_VMEM_RSV1_5_0_3_SHIFT 3
987 #define MT6333_PMIC_RG_VMEM_RSV1_5_4_MASK 0x3
988 #define MT6333_PMIC_RG_VMEM_RSV1_5_4_SHIFT 4
989 #define MT6333_PMIC_RG_R2R_EVENT_SYNC_SEL_MASK 0x1
990 #define MT6333_PMIC_RG_R2R_EVENT_SYNC_SEL_SHIFT 6
991 #define MT6333_PMIC_RG_VMEM_EN_THR_SDN_SEL_MASK 0x1
992 #define MT6333_PMIC_RG_VMEM_EN_THR_SDN_SEL_SHIFT 7
993 #define MT6333_PMIC_RG_VMEM_TRIML_MASK 0x7
994 #define MT6333_PMIC_RG_VMEM_TRIML_SHIFT 0
995 #define MT6333_PMIC_RG_VMEM_TRIMH_MASK 0x7
996 #define MT6333_PMIC_RG_VMEM_TRIMH_SHIFT 5
997 #define MT6333_PMIC_RG_VMEM_CC_MASK 0x3
998 #define MT6333_PMIC_RG_VMEM_CC_SHIFT 3
999 #define MT6333_PMIC_RG_VMEM_RZSEL_MASK 0x3
1000 #define MT6333_PMIC_RG_VMEM_RZSEL_SHIFT 6
1001 #define MT6333_PMIC_RG_VMEM_SLP_MASK 0x3
1002 #define MT6333_PMIC_RG_VMEM_SLP_SHIFT 2
1003 #define MT6333_PMIC_RG_VMEM_CSL_MASK 0x3
1004 #define MT6333_PMIC_RG_VMEM_CSL_SHIFT 4
1005 #define MT6333_PMIC_RG_VMEM_CSR_MASK 0x3
1006 #define MT6333_PMIC_RG_VMEM_CSR_SHIFT 6
1007 #define MT6333_PMIC_RG_VMEM_AVP_OS_MASK 0x7
1008 #define MT6333_PMIC_RG_VMEM_AVP_OS_SHIFT 0
1009 #define MT6333_PMIC_RG_VMEM_AVP_EN_MASK 0x1
1010 #define MT6333_PMIC_RG_VMEM_AVP_EN_SHIFT 3
1011 #define MT6333_PMIC_RG_VMEM_NDIS_EN_MASK 0x1
1012 #define MT6333_PMIC_RG_VMEM_NDIS_EN_SHIFT 4
1013 #define MT6333_PMIC_RG_VMEM_MODESET_MASK 0x1
1014 #define MT6333_PMIC_RG_VMEM_MODESET_SHIFT 5
1015 #define MT6333_PMIC_RG_VMEM_ZX_OS_MASK 0x3
1016 #define MT6333_PMIC_RG_VMEM_ZX_OS_SHIFT 6
1017 #define MT6333_PMIC_RG_VMEM_CSM_MASK 0x7
1018 #define MT6333_PMIC_RG_VMEM_CSM_SHIFT 5
1019 #define MT6333_PMIC_RG_VMEM_ZXOS_TRIM_MASK 0x3F
1020 #define MT6333_PMIC_RG_VMEM_ZXOS_TRIM_SHIFT 2
1021 #define MT6333_PMIC_RG_VMEM_RSV_MASK 0xFF
1022 #define MT6333_PMIC_RG_VMEM_RSV_SHIFT 0
1023 #define MT6333_PMIC_QI_VMEM_DIG_MON_MASK 0xF
1024 #define MT6333_PMIC_QI_VMEM_DIG_MON_SHIFT 0
1025 #define MT6333_PMIC_QI_VMEM_OC_STATUS_MASK 0x1
1026 #define MT6333_PMIC_QI_VMEM_OC_STATUS_SHIFT 7
1027 #define MT6333_PMIC_QI_VMEM_VSLEEP_MASK 0x3
1028 #define MT6333_PMIC_QI_VMEM_VSLEEP_SHIFT 6
1029 #define MT6333_PMIC_VMEM_EN_MASK 0x1
1030 #define MT6333_PMIC_VMEM_EN_SHIFT 1
1031 #define MT6333_PMIC_QI_VMEM_STB_MASK 0x1
1032 #define MT6333_PMIC_QI_VMEM_STB_SHIFT 2
1033 #define MT6333_PMIC_QI_VMEM_EN_MASK 0x1
1034 #define MT6333_PMIC_QI_VMEM_EN_SHIFT 3
1035 #define MT6333_PMIC_VMEM_EN_CTRL_MASK 0x1
1036 #define MT6333_PMIC_VMEM_EN_CTRL_SHIFT 4
1037 #define MT6333_PMIC_VMEM_VOSEL_CTRL_MASK 0x1
1038 #define MT6333_PMIC_VMEM_VOSEL_CTRL_SHIFT 5
1039 #define MT6333_PMIC_VMEM_DLC_CTRL_MASK 0x1
1040 #define MT6333_PMIC_VMEM_DLC_CTRL_SHIFT 6
1041 #define MT6333_PMIC_VMEM_BURST_CTRL_MASK 0x1
1042 #define MT6333_PMIC_VMEM_BURST_CTRL_SHIFT 7
1043 #define MT6333_PMIC_VMEM_VOSEL_MASK 0x7F
1044 #define MT6333_PMIC_VMEM_VOSEL_SHIFT 0
1045 #define MT6333_PMIC_VMEM_VOSEL_ON_MASK 0x7F
1046 #define MT6333_PMIC_VMEM_VOSEL_ON_SHIFT 0
1047 #define MT6333_PMIC_VMEM_VOSEL_SLEEP_MASK 0x7F
1048 #define MT6333_PMIC_VMEM_VOSEL_SLEEP_SHIFT 0
1049 #define MT6333_PMIC_NI_VMEM_VOSEL_MASK 0x7F
1050 #define MT6333_PMIC_NI_VMEM_VOSEL_SHIFT 0
1051 #define MT6333_PMIC_QI_VMEM_BURST_MASK 0x3
1052 #define MT6333_PMIC_QI_VMEM_BURST_SHIFT 6
1053 #define MT6333_PMIC_VMEM_BURST_MASK 0x3
1054 #define MT6333_PMIC_VMEM_BURST_SHIFT 0
1055 #define MT6333_PMIC_VMEM_BURST_ON_MASK 0x3
1056 #define MT6333_PMIC_VMEM_BURST_ON_SHIFT 2
1057 #define MT6333_PMIC_VMEM_BURST_SLEEP_MASK 0x3
1058 #define MT6333_PMIC_VMEM_BURST_SLEEP_SHIFT 4
1059 #define MT6333_PMIC_VMEM_DLC_MASK 0x3
1060 #define MT6333_PMIC_VMEM_DLC_SHIFT 0
1061 #define MT6333_PMIC_VMEM_DLC_ON_MASK 0x3
1062 #define MT6333_PMIC_VMEM_DLC_ON_SHIFT 2
1063 #define MT6333_PMIC_VMEM_DLC_SLEEP_MASK 0x3
1064 #define MT6333_PMIC_VMEM_DLC_SLEEP_SHIFT 4
1065 #define MT6333_PMIC_QI_VMEM_DLC_MASK 0x3
1066 #define MT6333_PMIC_QI_VMEM_DLC_SHIFT 6
1067 #define MT6333_PMIC_QI_VMEM_DLC_N_MASK 0x3
1068 #define MT6333_PMIC_QI_VMEM_DLC_N_SHIFT 6
1069 #define MT6333_PMIC_VMEM_DLC_N_MASK 0x3
1070 #define MT6333_PMIC_VMEM_DLC_N_SHIFT 0
1071 #define MT6333_PMIC_VMEM_DLC_N_ON_MASK 0x3
1072 #define MT6333_PMIC_VMEM_DLC_N_ON_SHIFT 2
1073 #define MT6333_PMIC_VMEM_DLC_N_SLEEP_MASK 0x3
1074 #define MT6333_PMIC_VMEM_DLC_N_SLEEP_SHIFT 4
1075 #define MT6333_PMIC_VMEM_VSLEEP_EN_MASK 0x1
1076 #define MT6333_PMIC_VMEM_VSLEEP_EN_SHIFT 3
1077 #define MT6333_PMIC_VMEM_R2R_PDN_MASK 0x1
1078 #define MT6333_PMIC_VMEM_R2R_PDN_SHIFT 4
1079 #define MT6333_PMIC_VMEM_VSLEEP_SEL_MASK 0x1
1080 #define MT6333_PMIC_VMEM_VSLEEP_SEL_SHIFT 5
1081 #define MT6333_PMIC_NI_VMEM_R2R_PDN_MASK 0x1
1082 #define MT6333_PMIC_NI_VMEM_R2R_PDN_SHIFT 6
1083 #define MT6333_PMIC_NI_VMEM_VSLEEP_SEL_MASK 0x1
1084 #define MT6333_PMIC_NI_VMEM_VSLEEP_SEL_SHIFT 7
1085 #define MT6333_PMIC_VMEM_TRANSTD_MASK 0x3
1086 #define MT6333_PMIC_VMEM_TRANSTD_SHIFT 0
1087 #define MT6333_PMIC_VMEM_VOSEL_TRANS_EN_MASK 0x3
1088 #define MT6333_PMIC_VMEM_VOSEL_TRANS_EN_SHIFT 2
1089 #define MT6333_PMIC_VMEM_VOSEL_TRANS_ONCE_MASK 0x1
1090 #define MT6333_PMIC_VMEM_VOSEL_TRANS_ONCE_SHIFT 4
1091 #define MT6333_PMIC_NI_VMEM_VOSEL_TRANS_MASK 0x1
1092 #define MT6333_PMIC_NI_VMEM_VOSEL_TRANS_SHIFT 5
1093 #define MT6333_PMIC_RG_VRF18_VOCAL_MASK 0x7
1094 #define MT6333_PMIC_RG_VRF18_VOCAL_SHIFT 4
1095 #define MT6333_PMIC_RG_VRF18_GMSEL_MASK 0x1
1096 #define MT6333_PMIC_RG_VRF18_GMSEL_SHIFT 7
1097 #define MT6333_PMIC_RG_VRF18_BK_LDO_MASK 0x1
1098 #define MT6333_PMIC_RG_VRF18_BK_LDO_SHIFT 0
1099 #define MT6333_PMIC_RG_VRF18_SLEW_NMOS_MASK 0x3
1100 #define MT6333_PMIC_RG_VRF18_SLEW_NMOS_SHIFT 3
1101 #define MT6333_PMIC_RG_VRF18_SLEW_MASK 0x3
1102 #define MT6333_PMIC_RG_VRF18_SLEW_SHIFT 6
1103 #define MT6333_PMIC_RG_VRF18_CC_MASK 0x3
1104 #define MT6333_PMIC_RG_VRF18_CC_SHIFT 3
1105 #define MT6333_PMIC_RG_VRF18_RZSEL_MASK 0x7
1106 #define MT6333_PMIC_RG_VRF18_RZSEL_SHIFT 5
1107 #define MT6333_PMIC_RG_VRF18_SLP_MASK 0x3
1108 #define MT6333_PMIC_RG_VRF18_SLP_SHIFT 2
1109 #define MT6333_PMIC_RG_VRF18_CSL_MASK 0x3
1110 #define MT6333_PMIC_RG_VRF18_CSL_SHIFT 4
1111 #define MT6333_PMIC_RG_VRF18_CSR_MASK 0x3
1112 #define MT6333_PMIC_RG_VRF18_CSR_SHIFT 6
1113 #define MT6333_PMIC_RG_VRF18_NDIS_EN_MASK 0x1
1114 #define MT6333_PMIC_RG_VRF18_NDIS_EN_SHIFT 4
1115 #define MT6333_PMIC_RG_VRF18_ZX_OS_MASK 0x3
1116 #define MT6333_PMIC_RG_VRF18_ZX_OS_SHIFT 6
1117 #define MT6333_PMIC_RG_VRF18_BURSTL_MASK 0x7
1118 #define MT6333_PMIC_RG_VRF18_BURSTL_SHIFT 0
1119 #define MT6333_PMIC_RG_VRF18_BURSTH_MASK 0x7
1120 #define MT6333_PMIC_RG_VRF18_BURSTH_SHIFT 5
1121 #define MT6333_PMIC_RG_VRF18_RSV_MASK 0xFF
1122 #define MT6333_PMIC_RG_VRF18_RSV_SHIFT 0
1123 #define MT6333_PMIC_QI_VRF18_OC_STATUS_MASK 0x1
1124 #define MT6333_PMIC_QI_VRF18_OC_STATUS_SHIFT 7
1125 #define MT6333_PMIC_RG_BUCK_RSV1_MASK 0xFF
1126 #define MT6333_PMIC_RG_BUCK_RSV1_SHIFT 0
1127 #define MT6333_PMIC_VRF18_VOSEL_CTRL_MASK 0x1
1128 #define MT6333_PMIC_VRF18_VOSEL_CTRL_SHIFT 5
1129 #define MT6333_PMIC_VRF18_DLC_CTRL_MASK 0x1
1130 #define MT6333_PMIC_VRF18_DLC_CTRL_SHIFT 6
1131 #define MT6333_PMIC_VRF18_BURST_CTRL_MASK 0x1
1132 #define MT6333_PMIC_VRF18_BURST_CTRL_SHIFT 7
1133 #define MT6333_PMIC_VRF18_VOSEL_MASK 0x1F
1134 #define MT6333_PMIC_VRF18_VOSEL_SHIFT 3
1135 #define MT6333_PMIC_VRF18_VOSEL_ON_MASK 0x1F
1136 #define MT6333_PMIC_VRF18_VOSEL_ON_SHIFT 0
1137 #define MT6333_PMIC_VRF18_VOSEL_SLEEP_MASK 0x1F
1138 #define MT6333_PMIC_VRF18_VOSEL_SLEEP_SHIFT 3
1139 #define MT6333_PMIC_NI_VRF18_VOSEL_MASK 0x1F
1140 #define MT6333_PMIC_NI_VRF18_VOSEL_SHIFT 3
1141 #define MT6333_PMIC_RG_BUCK_MON_FLAG_SEL_MASK 0xFF
1142 #define MT6333_PMIC_RG_BUCK_MON_FLAG_SEL_SHIFT 0
1143 #define MT6333_PMIC_RG_BUCK_RSV2_5_0_MASK 0x3F
1144 #define MT6333_PMIC_RG_BUCK_RSV2_5_0_SHIFT 0
1145 #define MT6333_PMIC_RG_BUCK_BYPASS_VOSEL_LIMIT_MASK 0x1
1146 #define MT6333_PMIC_RG_BUCK_BYPASS_VOSEL_LIMIT_SHIFT 6
1147 #define MT6333_PMIC_RG_BUCK_MON_FLAG_EN_MASK 0x1
1148 #define MT6333_PMIC_RG_BUCK_MON_FLAG_EN_SHIFT 7
1149 #define MT6333_PMIC_VRF18_DLC_MASK 0x3
1150 #define MT6333_PMIC_VRF18_DLC_SHIFT 0
1151 #define MT6333_PMIC_VRF18_DLC_ON_MASK 0x3
1152 #define MT6333_PMIC_VRF18_DLC_ON_SHIFT 2
1153 #define MT6333_PMIC_VRF18_DLC_SLEEP_MASK 0x3
1154 #define MT6333_PMIC_VRF18_DLC_SLEEP_SHIFT 4
1155 #define MT6333_PMIC_QI_VRF18_DLC_MASK 0x3
1156 #define MT6333_PMIC_QI_VRF18_DLC_SHIFT 6
1157 #define MT6333_PMIC_QI_VRF18_DLC_N_MASK 0x3
1158 #define MT6333_PMIC_QI_VRF18_DLC_N_SHIFT 6
1159 #define MT6333_PMIC_VRF18_DLC_N_MASK 0x3
1160 #define MT6333_PMIC_VRF18_DLC_N_SHIFT 0
1161 #define MT6333_PMIC_VRF18_DLC_N_ON_MASK 0x3
1162 #define MT6333_PMIC_VRF18_DLC_N_ON_SHIFT 2
1163 #define MT6333_PMIC_VRF18_DLC_N_SLEEP_MASK 0x3
1164 #define MT6333_PMIC_VRF18_DLC_N_SLEEP_SHIFT 4
1165 #define MT6333_PMIC_RG_VRF18_MODESET_MASK 0x1
1166 #define MT6333_PMIC_RG_VRF18_MODESET_SHIFT 0
1167 #define MT6333_PMIC_VRF18_EN_MASK 0x1
1168 #define MT6333_PMIC_VRF18_EN_SHIFT 1
1169 #define MT6333_PMIC_RG_VRF18_STB_SEL_MASK 0x3
1170 #define MT6333_PMIC_RG_VRF18_STB_SEL_SHIFT 2
1171 #define MT6333_PMIC_QI_VRF18_STB_MASK 0x1
1172 #define MT6333_PMIC_QI_VRF18_STB_SHIFT 5
1173 #define MT6333_PMIC_QI_VRF18_EN_MASK 0x1
1174 #define MT6333_PMIC_QI_VRF18_EN_SHIFT 6
1175 #define MT6333_PMIC_VRF18_EN_CTRL_MASK 0x1
1176 #define MT6333_PMIC_VRF18_EN_CTRL_SHIFT 7
1177 #define MT6333_PMIC_RG_VRF18_MODESET_SPM_MASK 0x1
1178 #define MT6333_PMIC_RG_VRF18_MODESET_SPM_SHIFT 0
1179 #define MT6333_PMIC_VRF18_EN_SPM_MASK 0x1
1180 #define MT6333_PMIC_VRF18_EN_SPM_SHIFT 1
1181 #define MT6333_PMIC_RG_VCORE_VOSEL_SET_SPM_MASK 0x1
1182 #define MT6333_PMIC_RG_VCORE_VOSEL_SET_SPM_SHIFT 2
1183 #define MT6333_PMIC_K_RST_DONE_MASK 0x1
1184 #define MT6333_PMIC_K_RST_DONE_SHIFT 0
1185 #define MT6333_PMIC_K_MAP_SEL_MASK 0x1
1186 #define MT6333_PMIC_K_MAP_SEL_SHIFT 1
1187 #define MT6333_PMIC_K_ONCE_EN_MASK 0x1
1188 #define MT6333_PMIC_K_ONCE_EN_SHIFT 2
1189 #define MT6333_PMIC_K_ONCE_MASK 0x1
1190 #define MT6333_PMIC_K_ONCE_SHIFT 3
1191 #define MT6333_PMIC_K_START_MANUAL_MASK 0x1
1192 #define MT6333_PMIC_K_START_MANUAL_SHIFT 4
1193 #define MT6333_PMIC_K_SRC_SEL_MASK 0x1
1194 #define MT6333_PMIC_K_SRC_SEL_SHIFT 5
1195 #define MT6333_PMIC_K_AUTO_EN_MASK 0x1
1196 #define MT6333_PMIC_K_AUTO_EN_SHIFT 6
1197 #define MT6333_PMIC_K_INV_MASK 0x1
1198 #define MT6333_PMIC_K_INV_SHIFT 7
1199 #define MT6333_PMIC_K_CONTROL_SMPS_MASK 0x1F
1200 #define MT6333_PMIC_K_CONTROL_SMPS_SHIFT 3
1201 #define MT6333_PMIC_QI_SMPS_OSC_CAL_MASK 0x1F
1202 #define MT6333_PMIC_QI_SMPS_OSC_CAL_SHIFT 3
1203 #define MT6333_PMIC_K_RESULT_MASK 0x1
1204 #define MT6333_PMIC_K_RESULT_SHIFT 0
1205 #define MT6333_PMIC_K_DONE_MASK 0x1
1206 #define MT6333_PMIC_K_DONE_SHIFT 1
1207 #define MT6333_PMIC_K_CONTROL_MASK 0x1F
1208 #define MT6333_PMIC_K_CONTROL_SHIFT 3
1209 #define MT6333_PMIC_K_BUCK_CK_CNT_MASK 0xFF
1210 #define MT6333_PMIC_K_BUCK_CK_CNT_SHIFT 0
1211 #define MT6333_PMIC_K_CHR_CK_CNT_MASK 0xFF
1212 #define MT6333_PMIC_K_CHR_CK_CNT_SHIFT 0
1213 #define MT6333_PMIC_RG_STRUP_RSV1_2_0_MASK 0x7
1214 #define MT6333_PMIC_RG_STRUP_RSV1_2_0_SHIFT 0
1215 #define MT6333_PMIC_RG_STRUP_SLEEP_MODE_DEB_SEL_MASK 0x1
1216 #define MT6333_PMIC_RG_STRUP_SLEEP_MODE_DEB_SEL_SHIFT 3
1217 #define MT6333_PMIC_RG_STRUP_POSEQ_DONE_DEB_SEL_MASK 0x1
1218 #define MT6333_PMIC_RG_STRUP_POSEQ_DONE_DEB_SEL_SHIFT 4
1219 #define MT6333_PMIC_RG_STRUP_VMEM_EN_DEB_SEL_MASK 0x1
1220 #define MT6333_PMIC_RG_STRUP_VMEM_EN_DEB_SEL_SHIFT 5
1221 #define MT6333_PMIC_RG_STRUP_VCORE_EN_DEB_SEL_MASK 0x1
1222 #define MT6333_PMIC_RG_STRUP_VCORE_EN_DEB_SEL_SHIFT 6
1223 #define MT6333_PMIC_RG_STRUP_BUCK_EN_DEB_SEL_MASK 0x1
1224 #define MT6333_PMIC_RG_STRUP_BUCK_EN_DEB_SEL_SHIFT 7
1225 #define MT6333_PMIC_RG_STRUP_OSC_EN_MASK 0x1
1226 #define MT6333_PMIC_RG_STRUP_OSC_EN_SHIFT 0
1227 #define MT6333_PMIC_RG_STRUP_OSC_EN_SEL_MASK 0x1
1228 #define MT6333_PMIC_RG_STRUP_OSC_EN_SEL_SHIFT 1
1229 #define MT6333_PMIC_RG_STRUP_IVGEN_ENB_MASK 0x1
1230 #define MT6333_PMIC_RG_STRUP_IVGEN_ENB_SHIFT 2
1231 #define MT6333_PMIC_RG_STRUP_IVGEN_ENB_SEL_MASK 0x1
1232 #define MT6333_PMIC_RG_STRUP_IVGEN_ENB_SEL_SHIFT 3
1233 #define MT6333_PMIC_RG_STRUP_RSV2_7_4_MASK 0xF
1234 #define MT6333_PMIC_RG_STRUP_RSV2_7_4_SHIFT 4
1235 #define MT6333_PMIC_RG_STRUP_RSV3_7_0_MASK 0xFF
1236 #define MT6333_PMIC_RG_STRUP_RSV3_7_0_SHIFT 0
1237 #define MT6333_PMIC_RG_EFUSE_ADDR_MASK 0x1F
1238 #define MT6333_PMIC_RG_EFUSE_ADDR_SHIFT 0
1239 #define MT6333_PMIC_RG_EFUSE_PROG_MASK 0x1
1240 #define MT6333_PMIC_RG_EFUSE_PROG_SHIFT 0
1241 #define MT6333_PMIC_RG_EFUSE_EN_MASK 0x1
1242 #define MT6333_PMIC_RG_EFUSE_EN_SHIFT 0
1243 #define MT6333_PMIC_RG_EFUSE_PKEY_MASK 0xFF
1244 #define MT6333_PMIC_RG_EFUSE_PKEY_SHIFT 0
1245 #define MT6333_PMIC_RG_EFUSE_RD_TRIG_MASK 0x1
1246 #define MT6333_PMIC_RG_EFUSE_RD_TRIG_SHIFT 0
1247 #define MT6333_PMIC_RG_EFUSE_PROG_SRC_MASK 0x1
1248 #define MT6333_PMIC_RG_EFUSE_PROG_SRC_SHIFT 0
1249 #define MT6333_PMIC_RG_PROG_MACRO_SEL_MASK 0x1
1250 #define MT6333_PMIC_RG_PROG_MACRO_SEL_SHIFT 0
1251 #define MT6333_PMIC_RG_RD_RDY_BYPASS_MASK 0x1
1252 #define MT6333_PMIC_RG_RD_RDY_BYPASS_SHIFT 0
1253 #define MT6333_PMIC_RG_EFUSE_RD_ACK_MASK 0x1
1254 #define MT6333_PMIC_RG_EFUSE_RD_ACK_SHIFT 0
1255 #define MT6333_PMIC_RG_EFUSE_BUSY_MASK 0x1
1256 #define MT6333_PMIC_RG_EFUSE_BUSY_SHIFT 2
1257 #define MT6333_PMIC_RG_OTP_PA_MASK 0x3
1258 #define MT6333_PMIC_RG_OTP_PA_SHIFT 0
1259 #define MT6333_PMIC_RG_OTP_PDIN_MASK 0xFF
1260 #define MT6333_PMIC_RG_OTP_PDIN_SHIFT 0
1261 #define MT6333_PMIC_RG_OTP_PTM_MASK 0x3
1262 #define MT6333_PMIC_RG_OTP_PTM_SHIFT 0
1263 #define MT6333_PMIC_RG_FSOURCE_EN_MASK 0x1
1264 #define MT6333_PMIC_RG_FSOURCE_EN_SHIFT 0
1265 #define MT6333_PMIC_RG_EFUSE_DOUT_0_7_MASK 0xFF
1266 #define MT6333_PMIC_RG_EFUSE_DOUT_0_7_SHIFT 0
1267 #define MT6333_PMIC_RG_EFUSE_DOUT_8_15_MASK 0xFF
1268 #define MT6333_PMIC_RG_EFUSE_DOUT_8_15_SHIFT 0
1269 #define MT6333_PMIC_RG_EFUSE_DOUT_16_23_MASK 0xFF
1270 #define MT6333_PMIC_RG_EFUSE_DOUT_16_23_SHIFT 0
1271 #define MT6333_PMIC_RG_EFUSE_DOUT_24_31_MASK 0xFF
1272 #define MT6333_PMIC_RG_EFUSE_DOUT_24_31_SHIFT 0
1273 #define MT6333_PMIC_RG_EFUSE_DOUT_32_39_MASK 0xFF
1274 #define MT6333_PMIC_RG_EFUSE_DOUT_32_39_SHIFT 0
1275 #define MT6333_PMIC_RG_EFUSE_DOUT_40_47_MASK 0xFF
1276 #define MT6333_PMIC_RG_EFUSE_DOUT_40_47_SHIFT 0
1277 #define MT6333_PMIC_RG_EFUSE_DOUT_48_55_MASK 0xFF
1278 #define MT6333_PMIC_RG_EFUSE_DOUT_48_55_SHIFT 0
1279 #define MT6333_PMIC_RG_EFUSE_DOUT_56_63_MASK 0xFF
1280 #define MT6333_PMIC_RG_EFUSE_DOUT_56_63_SHIFT 0
1281 #define MT6333_PMIC_TESTI0_MASK 0xFF
1282 #define MT6333_PMIC_TESTI0_SHIFT 0
1283 #define MT6333_PMIC_TESTI1_MASK 0xFF
1284 #define MT6333_PMIC_TESTI1_SHIFT 0
1285 #define MT6333_PMIC_TESTI2_MASK 0xFF
1286 #define MT6333_PMIC_TESTI2_SHIFT 0
1287 #define MT6333_PMIC_TESTI3_MASK 0xFF
1288 #define MT6333_PMIC_TESTI3_SHIFT 0
1289 #define MT6333_PMIC_TESTI4_MASK 0xFF
1290 #define MT6333_PMIC_TESTI4_SHIFT 0
1291 #define MT6333_PMIC_TESTI5_MASK 0xFF
1292 #define MT6333_PMIC_TESTI5_SHIFT 0
1293 #define MT6333_PMIC_TESTI6_MASK 0xFF
1294 #define MT6333_PMIC_TESTI6_SHIFT 0
1295 #define MT6333_PMIC_TESTI7_MASK 0xFF
1296 #define MT6333_PMIC_TESTI7_SHIFT 0
1297 #define MT6333_PMIC_TESTI8_MASK 0xFF
1298 #define MT6333_PMIC_TESTI8_SHIFT 0
1299 #define MT6333_PMIC_TESTI0_SEL_MASK 0xFF
1300 #define MT6333_PMIC_TESTI0_SEL_SHIFT 0
1301 #define MT6333_PMIC_TESTI1_SEL_MASK 0xFF
1302 #define MT6333_PMIC_TESTI1_SEL_SHIFT 0
1303 #define MT6333_PMIC_TESTI2_SEL_MASK 0xFF
1304 #define MT6333_PMIC_TESTI2_SEL_SHIFT 0
1305 #define MT6333_PMIC_TESTI3_SEL_MASK 0xFF
1306 #define MT6333_PMIC_TESTI3_SEL_SHIFT 0
1307 #define MT6333_PMIC_TESTI4_SEL_MASK 0xFF
1308 #define MT6333_PMIC_TESTI4_SEL_SHIFT 0
1309 #define MT6333_PMIC_TESTI5_SEL_MASK 0xFF
1310 #define MT6333_PMIC_TESTI5_SEL_SHIFT 0
1311 #define MT6333_PMIC_TESTI6_SEL_MASK 0xFF
1312 #define MT6333_PMIC_TESTI6_SEL_SHIFT 0
1313 #define MT6333_PMIC_TESTI7_SEL_MASK 0xFF
1314 #define MT6333_PMIC_TESTI7_SEL_SHIFT 0
1315 #define MT6333_PMIC_TESTI8_SEL_MASK 0xFF
1316 #define MT6333_PMIC_TESTI8_SEL_SHIFT 0
1317 #define MT6333_PMIC_TESTO0_MASK 0xFF
1318 #define MT6333_PMIC_TESTO0_SHIFT 0
1319 #define MT6333_PMIC_TESTO1_MASK 0xFF
1320 #define MT6333_PMIC_TESTO1_SHIFT 0
1321 #define MT6333_PMIC_TESTO2_MASK 0xFF
1322 #define MT6333_PMIC_TESTO2_SHIFT 0
1323 #define MT6333_PMIC_TESTO3_MASK 0xFF
1324 #define MT6333_PMIC_TESTO3_SHIFT 0
1325 #define MT6333_PMIC_TESTO0_SEL_MASK 0xFF
1326 #define MT6333_PMIC_TESTO0_SEL_SHIFT 0
1327 #define MT6333_PMIC_TESTO1_SEL_MASK 0xFF
1328 #define MT6333_PMIC_TESTO1_SEL_SHIFT 0
1329 #define MT6333_PMIC_TESTO2_SEL_MASK 0xFF
1330 #define MT6333_PMIC_TESTO2_SEL_SHIFT 0
1331 #define MT6333_PMIC_TESTO3_SEL_MASK 0xFF
1332 #define MT6333_PMIC_TESTO3_SEL_SHIFT 0
1333 #define MT6333_PMIC_DEBUG_SEL_MASK 0xFF
1334 #define MT6333_PMIC_DEBUG_SEL_SHIFT 0
1335 #define MT6333_PMIC_DEBUG_MON_MASK 0xFF
1336 #define MT6333_PMIC_DEBUG_MON_SHIFT 0
1337 #define MT6333_PMIC_DEBUG_BIT_SEL_MASK 0x7
1338 #define MT6333_PMIC_DEBUG_BIT_SEL_SHIFT 0
1339 #define MT6333_PMIC_CID1_MASK 0xFF
1340 #define MT6333_PMIC_CID1_SHIFT 0
1342 /**********************************************************
1346 *********************************************************/
1347 extern kal_uint8
mt6333_get_cid0(void);
1348 extern void mt6333_set_rg_bgr_rsel(kal_uint8 val
);
1349 extern void mt6333_set_rg_bgr_unchop(kal_uint8 val
);
1350 extern void mt6333_set_rg_bgr_unchop_ph(kal_uint8 val
);
1351 extern void mt6333_set_rg_bgr_trim(kal_uint8 val
);
1352 extern void mt6333_set_rg_bgr_trim_en(kal_uint8 val
);
1353 extern void mt6333_set_rg_bgr_test_en(kal_uint8 val
);
1354 extern void mt6333_set_rg_bgr_test_rstb(kal_uint8 val
);
1355 extern void mt6333_set_rg_bgr_test_ckin(kal_uint8 val
);
1356 extern void mt6333_set_rg_chr_en(kal_uint8 val
);
1357 extern void mt6333_set_rg_vbout_en(kal_uint8 val
);
1358 extern void mt6333_set_rg_adcin_vbat_en(kal_uint8 val
);
1359 extern void mt6333_set_rg_adcin_chrin_en(kal_uint8 val
);
1360 extern void mt6333_set_rg_adcin_baton_en(kal_uint8 val
);
1361 extern void mt6333_set_rg_bat_on_open_vth(kal_uint8 val
);
1362 extern void mt6333_set_rg_bat_on_pull_high_en(kal_uint8 val
);
1363 extern void mt6333_set_rg_int_ph_enb(kal_uint8 val
);
1364 extern void mt6333_set_rg_scl_ph_enb(kal_uint8 val
);
1365 extern void mt6333_set_rg_sda_ph_enb(kal_uint8 val
);
1366 extern void mt6333_set_rg_vdrv_rdivsel(kal_uint8 val
);
1367 extern void mt6333_set_rg_swchr_rv1(kal_uint8 val
);
1368 extern void mt6333_set_rg_chr_otg_lv_th(kal_uint8 val
);
1369 extern void mt6333_set_rg_chr_otg_hv_th(kal_uint8 val
);
1370 extern void mt6333_set_rg_strup_ther_rg_th(kal_uint8 val
);
1371 extern void mt6333_set_rg_strup_rsv(kal_uint8 val
);
1372 extern void mt6333_set_rg_swchr_ana_test_mode(kal_uint8 val
);
1373 extern void mt6333_set_rg_swchr_ana_test_mode_sel(kal_uint8 val
);
1374 extern void mt6333_set_rg_csa_otg_sel(kal_uint8 val
);
1375 extern void mt6333_set_rg_otg_cs_slp_en(kal_uint8 val
);
1376 extern void mt6333_set_rg_slp_otg_sel(kal_uint8 val
);
1377 extern void mt6333_set_rg_iterm_sel(kal_uint8 val
);
1378 extern void mt6333_set_rg_ics_loop(kal_uint8 val
);
1379 extern void mt6333_set_rg_zxgm_tune(kal_uint8 val
);
1380 extern void mt6333_set_rg_chop_en(kal_uint8 val
);
1381 extern void mt6333_set_rg_force_non_oc(kal_uint8 val
);
1382 extern void mt6333_set_rg_force_non_ov(kal_uint8 val
);
1383 extern void mt6333_set_rg_gdri_minoff_en(kal_uint8 val
);
1384 extern void mt6333_set_rg_sys_vreftrim(kal_uint8 val
);
1385 extern void mt6333_set_rg_cs_vreftrim(kal_uint8 val
);
1386 extern void mt6333_set_rg_osc_trim(kal_uint8 val
);
1387 extern void mt6333_set_rg_vsys_ov_trim(kal_uint8 val
);
1388 extern void mt6333_set_rg_swchr_rv2(kal_uint8 val
);
1389 extern void mt6333_set_rg_input_cc_reg(kal_uint8 val
);
1390 extern void mt6333_set_rg_otg_chrin_vol(kal_uint8 val
);
1391 extern void mt6333_set_rg_force_otg_non_ov(kal_uint8 val
);
1392 extern void mt6333_set_rg_inout_csreg_sel(kal_uint8 val
);
1393 extern void mt6333_set_rg_chopfreq_sel(kal_uint8 val
);
1394 extern void mt6333_set_rg_chgpreg_sel(kal_uint8 val
);
1395 extern void mt6333_set_rg_flash_drv_en(kal_uint8 val
);
1396 extern void mt6333_set_rg_fpwm_otg(kal_uint8 val
);
1397 extern void mt6333_set_rg_otg_zx_testmode(kal_uint8 val
);
1398 extern void mt6333_set_rg_swchr_zx_testmode(kal_uint8 val
);
1399 extern void mt6333_set_rg_zx_trim(kal_uint8 val
);
1400 extern void mt6333_set_rg_zx_trim_otg(kal_uint8 val
);
1401 extern kal_uint8
mt6333_get_rgs_auto_recharge(void);
1402 extern kal_uint8
mt6333_get_rgs_charge_complete_hw(void);
1403 extern kal_uint8
mt6333_get_rgs_pwm_oc_det(void);
1404 extern kal_uint8
mt6333_get_rgs_vsys_ov_det(void);
1405 extern kal_uint8
mt6333_get_rgs_power_path(void);
1406 extern kal_uint8
mt6333_get_rgs_force_no_pp_config(void);
1407 extern kal_uint8
mt6333_get_rgs_chrg_status(void);
1408 extern kal_uint8
mt6333_get_rgs_bat_st_recc(void);
1409 extern kal_uint8
mt6333_get_rgs_sys_gt_cv(void);
1410 extern kal_uint8
mt6333_get_rgs_bat_gt_cc(void);
1411 extern kal_uint8
mt6333_get_rgs_bat_gt_30(void);
1412 extern kal_uint8
mt6333_get_rgs_bat_gt_22(void);
1413 extern kal_uint8
mt6333_get_rgs_buck_mode(void);
1414 extern kal_uint8
mt6333_get_rgs_buck_precc_mode(void);
1415 extern kal_uint8
mt6333_get_rgs_chrdet(void);
1416 extern kal_uint8
mt6333_get_rgs_chr_hv_det(void);
1417 extern kal_uint8
mt6333_get_rgs_chr_plug_in(void);
1418 extern kal_uint8
mt6333_get_rgs_baton_undet(void);
1419 extern kal_uint8
mt6333_get_rgs_chrin_lv_det(void);
1420 extern kal_uint8
mt6333_get_rgs_chrin_hv_det(void);
1421 extern kal_uint8
mt6333_get_rgs_thermal_sd_mode(void);
1422 extern kal_uint8
mt6333_get_rgs_chr_hv_mode(void);
1423 extern kal_uint8
mt6333_get_rgs_bat_only_mode(void);
1424 extern kal_uint8
mt6333_get_rgs_chr_suspend_mode(void);
1425 extern kal_uint8
mt6333_get_rgs_precc_mode(void);
1426 extern kal_uint8
mt6333_get_rgs_cv_mode(void);
1427 extern kal_uint8
mt6333_get_rgs_cc_mode(void);
1428 extern kal_uint8
mt6333_get_rgs_ot_reg(void);
1429 extern kal_uint8
mt6333_get_rgs_ot_sd(void);
1430 extern kal_uint8
mt6333_get_rgs_pwm_bat_config(void);
1431 extern kal_uint8
mt6333_get_rgs_pwm_current_config(void);
1432 extern kal_uint8
mt6333_get_rgs_pwm_voltage_config(void);
1433 extern kal_uint8
mt6333_get_rgs_buck_overload(void);
1434 extern kal_uint8
mt6333_get_rgs_bat_dppm_mode(void);
1435 extern kal_uint8
mt6333_get_rgs_adaptive_cv_mode(void);
1436 extern kal_uint8
mt6333_get_rgs_vin_dpm_mode(void);
1437 extern kal_uint8
mt6333_get_rgs_thermal_reg_mode(void);
1438 extern kal_uint8
mt6333_get_rgs_ich_setting(void);
1439 extern kal_uint8
mt6333_get_rgs_cs_sel(void);
1440 extern kal_uint8
mt6333_get_rgs_syscv_fine_sel(void);
1441 extern kal_uint8
mt6333_get_rgs_oc_sd_sel(void);
1442 extern kal_uint8
mt6333_get_rgs_pwm_oc_sel(void);
1443 extern kal_uint8
mt6333_get_rgs_chrwdt_tout(void);
1444 extern kal_uint8
mt6333_get_rgs_vsys_ov_vth(void);
1445 extern kal_uint8
mt6333_get_rgs_syscv_coarse_sel(void);
1446 extern kal_uint8
mt6333_get_rgs_usb_dl_key(void);
1447 extern kal_uint8
mt6333_get_rgs_force_pp_on(void);
1448 extern kal_uint8
mt6333_get_rgs_ini_sys_on(void);
1449 extern kal_uint8
mt6333_get_rgs_ich_oc_flag_chr_core(void);
1450 extern kal_uint8
mt6333_get_rgs_pwm_oc_chr_core(void);
1451 extern kal_uint8
mt6333_get_rgs_power_on_ready(void);
1452 extern kal_uint8
mt6333_get_rgs_auto_pwron(void);
1453 extern kal_uint8
mt6333_get_rgs_auto_pwron_done(void);
1454 extern kal_uint8
mt6333_get_rgs_chr_mode(void);
1455 extern kal_uint8
mt6333_get_rgs_otg_mode(void);
1456 extern kal_uint8
mt6333_get_rgs_poseq_done(void);
1457 extern kal_uint8
mt6333_get_rgs_otg_precc(void);
1458 extern kal_uint8
mt6333_get_rgs_chrin_short(void);
1459 extern kal_uint8
mt6333_get_rgs_drvcdt_short(void);
1460 extern kal_uint8
mt6333_get_rgs_otg_m3_oc(void);
1461 extern kal_uint8
mt6333_get_rgs_otg_thermal(void);
1462 extern kal_uint8
mt6333_get_rgs_chr_in_flash(void);
1463 extern kal_uint8
mt6333_get_rgs_vled_short(void);
1464 extern kal_uint8
mt6333_get_rgs_vled_open(void);
1465 extern kal_uint8
mt6333_get_rgs_flash_en_timeout(void);
1466 extern kal_uint8
mt6333_get_rgs_chr_oc(void);
1467 extern kal_uint8
mt6333_get_rgs_pwm_en(void);
1468 extern kal_uint8
mt6333_get_rgs_otg_en(void);
1469 extern kal_uint8
mt6333_get_rgs_otg_en_stb(void);
1470 extern kal_uint8
mt6333_get_rgs_otg_drv_en(void);
1471 extern kal_uint8
mt6333_get_rgs_flash_en(void);
1472 extern kal_uint8
mt6333_get_rgs_m3_boost_en(void);
1473 extern kal_uint8
mt6333_get_rgs_m3_r_en(void);
1474 extern kal_uint8
mt6333_get_rgs_m3_s_en(void);
1475 extern kal_uint8
mt6333_get_rgs_m3_en(void);
1476 extern kal_uint8
mt6333_get_rgs_cpcstsys_en(void);
1477 extern kal_uint8
mt6333_get_rgs_sw_gate_ctrl(void);
1478 extern kal_uint8
mt6333_get_qi_otg_chr_gt_lv(void);
1479 extern kal_uint8
mt6333_get_rgs_thermal_rg_th(void);
1480 extern kal_uint8
mt6333_get_rgs_otg_oc_th(void);
1481 extern void mt6333_set_rg_chr_suspend(kal_uint8 val
);
1482 extern void mt6333_set_rg_sys_on(kal_uint8 val
);
1483 extern void mt6333_set_rg_sys_unstable(kal_uint8 val
);
1484 extern void mt6333_set_rg_skip_efuse_out(kal_uint8 val
);
1485 extern void mt6333_set_rg_vsys_sel(kal_uint8 val
);
1486 extern void mt6333_set_rg_cv_sel(kal_uint8 val
);
1487 extern void mt6333_set_rg_ich_sel(kal_uint8 val
);
1488 extern void mt6333_set_rg_ich_pre_sel(kal_uint8 val
);
1489 extern void mt6333_set_rg_oc_sel(kal_uint8 val
);
1490 extern void mt6333_set_rg_chrin_lv_vth(kal_uint8 val
);
1491 extern void mt6333_set_rg_chrin_hv_vth(kal_uint8 val
);
1492 extern void mt6333_set_rg_usbdl_ext(kal_uint8 val
);
1493 extern void mt6333_set_rg_usbdl_mode_b(kal_uint8 val
);
1494 extern void mt6333_set_rg_usbdl_oc_sel(kal_uint8 val
);
1495 extern void mt6333_set_rg_buck_overload_prot_en(kal_uint8 val
);
1496 extern void mt6333_set_rg_ch_complete_auto_off(kal_uint8 val
);
1497 extern void mt6333_set_rg_term_timer(kal_uint8 val
);
1498 extern void mt6333_set_rg_chr_oc_auto_off(kal_uint8 val
);
1499 extern void mt6333_set_rg_chr_oc_reset(kal_uint8 val
);
1500 extern void mt6333_set_rg_otg_m3_oc_auto_off(kal_uint8 val
);
1501 extern void mt6333_set_rg_otg_en(kal_uint8 val
);
1502 extern void mt6333_set_rg_flash_en(kal_uint8 val
);
1503 extern void mt6333_set_rg_flash_pwm_en(kal_uint8 val
);
1504 extern void mt6333_set_rg_flash_pwm_en_stb(kal_uint8 val
);
1505 extern void mt6333_set_rg_torch_mode(kal_uint8 val
);
1506 extern void mt6333_set_rg_torch_chrin_chk(kal_uint8 val
);
1507 extern void mt6333_set_rg_flash_dim_duty(kal_uint8 val
);
1508 extern void mt6333_set_rg_chk_chrin_time_ext(kal_uint8 val
);
1509 extern void mt6333_set_rg_flash_dim_fsel(kal_uint8 val
);
1510 extern void mt6333_set_rg_flash_iset(kal_uint8 val
);
1511 extern void mt6333_set_rg_flash_iset_step(kal_uint8 val
);
1512 extern void mt6333_set_rg_thermal_rg_th(kal_uint8 val
);
1513 extern void mt6333_set_rg_thermal_temp_sel(kal_uint8 val
);
1514 extern void mt6333_set_rg_thermal_checker_sel(kal_uint8 val
);
1515 extern void mt6333_set_rg_flash_en_timeout_sel(kal_uint8 val
);
1516 extern void mt6333_set_rg_otg_oc_th(kal_uint8 val
);
1517 extern void mt6333_set_rg_reserve_v0(kal_uint8 val
);
1518 extern void mt6333_set_rg_cv_sel_usbdl(kal_uint8 val
);
1519 extern void mt6333_set_rg_ov_sel_usbdl(kal_uint8 val
);
1520 extern void mt6333_set_rg_sw_gate_ctrl(kal_uint8 val
);
1521 extern void mt6333_set_rg_reserve_v1(kal_uint8 val
);
1522 extern void mt6333_set_rg_reserve_v2(kal_uint8 val
);
1523 extern void mt6333_set_i2c_config(kal_uint8 val
);
1524 extern void mt6333_set_i2c_deg_en(kal_uint8 val
);
1525 extern void mt6333_set_sda_mode(kal_uint8 val
);
1526 extern void mt6333_set_sda_oe(kal_uint8 val
);
1527 extern void mt6333_set_sda_out(kal_uint8 val
);
1528 extern void mt6333_set_scl_mode(kal_uint8 val
);
1529 extern void mt6333_set_scl_oe(kal_uint8 val
);
1530 extern void mt6333_set_scl_out(kal_uint8 val
);
1531 extern void mt6333_set_int_mode(kal_uint8 val
);
1532 extern void mt6333_set_int_oe(kal_uint8 val
);
1533 extern void mt6333_set_int_out(kal_uint8 val
);
1534 extern void mt6333_set_rg_chr_250k_ck_en(kal_uint8 val
);
1535 extern void mt6333_set_rg_chr_1m_ck_en(kal_uint8 val
);
1536 extern void mt6333_set_rg_chr_pwm_ck_en(kal_uint8 val
);
1537 extern void mt6333_set_rg_buck_1m_ck_en(kal_uint8 val
);
1538 extern void mt6333_set_rg_buck_2m_ck_en(kal_uint8 val
);
1539 extern void mt6333_set_rg_buck_3m_ck_en(kal_uint8 val
);
1540 extern void mt6333_set_rg_buck_6m_ck_en(kal_uint8 val
);
1541 extern void mt6333_set_rg_buck_osc_en(kal_uint8 val
);
1542 extern kal_uint8
mt6333_get_qi_osc_en(void);
1543 extern void mt6333_set_rg_buck_cali_32k_ck_en(kal_uint8 val
);
1544 extern void mt6333_set_rg_buck_cali_pwm_ck_en(kal_uint8 val
);
1545 extern void mt6333_set_rg_buck_cali_6m_ck_en(kal_uint8 val
);
1546 extern void mt6333_set_rg_test_efuse(kal_uint8 val
);
1547 extern void mt6333_set_rg_test_ni_ck(kal_uint8 val
);
1548 extern void mt6333_set_rg_test_smps_ck(kal_uint8 val
);
1549 extern void mt6333_set_rg_test_pwm_ck(kal_uint8 val
);
1550 extern void mt6333_set_rg_int_en_chr_complete(kal_uint8 val
);
1551 extern void mt6333_set_rg_int_en_thermal_sd(kal_uint8 val
);
1552 extern void mt6333_set_rg_int_en_thermal_reg_in(kal_uint8 val
);
1553 extern void mt6333_set_rg_int_en_thermal_reg_out(kal_uint8 val
);
1554 extern void mt6333_set_rg_int_en_otg_oc(kal_uint8 val
);
1555 extern void mt6333_set_rg_int_en_otg_thermal(kal_uint8 val
);
1556 extern void mt6333_set_rg_int_en_otg_chrin_short(kal_uint8 val
);
1557 extern void mt6333_set_rg_int_en_otg_drvcdt_short(kal_uint8 val
);
1558 extern void mt6333_set_rg_int_en_chrwdt_flag(kal_uint8 val
);
1559 extern void mt6333_set_rg_int_en_buck_vcore_oc(kal_uint8 val
);
1560 extern void mt6333_set_rg_int_en_buck_vmem_oc(kal_uint8 val
);
1561 extern void mt6333_set_rg_int_en_buck_vrf18_oc(kal_uint8 val
);
1562 extern void mt6333_set_rg_int_en_buck_thermal(kal_uint8 val
);
1563 extern void mt6333_set_rg_int_en_flash_en_timeout(kal_uint8 val
);
1564 extern void mt6333_set_rg_int_en_flash_vled_short(kal_uint8 val
);
1565 extern void mt6333_set_rg_int_en_flash_vled_open(kal_uint8 val
);
1566 extern void mt6333_set_rg_int_en_chr_oc(kal_uint8 val
);
1567 extern void mt6333_set_rg_int_en_chr_plug_in_flash(kal_uint8 val
);
1568 extern void mt6333_set_rg_chrwdt_en(kal_uint8 val
);
1569 extern void mt6333_set_rg_chrwdt_td(kal_uint8 val
);
1570 extern void mt6333_set_rg_chrwdt_wr(kal_uint8 val
);
1571 extern kal_uint8
mt6333_get_rg_chrwdt_flag(void);
1572 extern kal_uint8
mt6333_get_rg_int_status_chr_complete(void);
1573 extern kal_uint8
mt6333_get_rg_int_status_thermal_sd(void);
1574 extern kal_uint8
mt6333_get_rg_int_status_thermal_reg_in(void);
1575 extern kal_uint8
mt6333_get_rg_int_status_thermal_reg_out(void);
1576 extern kal_uint8
mt6333_get_rg_int_status_otg_oc(void);
1577 extern kal_uint8
mt6333_get_rg_int_status_otg_thermal(void);
1578 extern kal_uint8
mt6333_get_rg_int_status_otg_chrin_short(void);
1579 extern kal_uint8
mt6333_get_rg_int_status_otg_drvcdt_short(void);
1580 extern kal_uint8
mt6333_get_rg_int_status_chrwdt_flag(void);
1581 extern kal_uint8
mt6333_get_rg_int_status_buck_vcore_oc(void);
1582 extern kal_uint8
mt6333_get_rg_int_status_buck_vmem_oc(void);
1583 extern kal_uint8
mt6333_get_rg_int_status_buck_vrf18_oc(void);
1584 extern kal_uint8
mt6333_get_rg_int_status_buck_thermal(void);
1585 extern kal_uint8
mt6333_get_rg_int_status_flash_en_timeout(void);
1586 extern kal_uint8
mt6333_get_rg_int_status_flash_vled_short(void);
1587 extern kal_uint8
mt6333_get_rg_int_status_flash_vled_open(void);
1588 extern kal_uint8
mt6333_get_rg_int_status_chr_oc(void);
1589 extern kal_uint8
mt6333_get_rg_int_status_chr_plug_in_flash(void);
1590 extern void mt6333_set_vcore_deg_en(kal_uint8 val
);
1591 extern void mt6333_set_vcore_oc_wnd(kal_uint8 val
);
1592 extern void mt6333_set_vcore_oc_thd(kal_uint8 val
);
1593 extern void mt6333_set_vmem_deg_en(kal_uint8 val
);
1594 extern void mt6333_set_vmem_oc_wnd(kal_uint8 val
);
1595 extern void mt6333_set_vmem_oc_thd(kal_uint8 val
);
1596 extern void mt6333_set_vrf18_deg_en(kal_uint8 val
);
1597 extern void mt6333_set_vrf18_oc_wnd(kal_uint8 val
);
1598 extern void mt6333_set_vrf18_oc_thd(kal_uint8 val
);
1599 extern void mt6333_set_int_polarity(kal_uint8 val
);
1600 extern void mt6333_set_rg_smps_testmode_b(kal_uint8 val
);
1601 extern void mt6333_set_rg_vcore_triml(kal_uint8 val
);
1602 extern void mt6333_set_rg_vcore_trimh(kal_uint8 val
);
1603 extern void mt6333_set_rg_vcore_cc(kal_uint8 val
);
1604 extern void mt6333_set_rg_vcore_rzsel(kal_uint8 val
);
1605 extern void mt6333_set_rg_vcore_slp(kal_uint8 val
);
1606 extern void mt6333_set_rg_vcore_csl(kal_uint8 val
);
1607 extern void mt6333_set_rg_vcore_csr(kal_uint8 val
);
1608 extern void mt6333_set_rg_vcore_avp_os(kal_uint8 val
);
1609 extern void mt6333_set_rg_vcore_avp_en(kal_uint8 val
);
1610 extern void mt6333_set_rg_vcore_ndis_en(kal_uint8 val
);
1611 extern void mt6333_set_rg_vcore_modeset(kal_uint8 val
);
1612 extern void mt6333_set_rg_vcore_zx_os(kal_uint8 val
);
1613 extern void mt6333_set_rg_vcore_csm(kal_uint8 val
);
1614 extern void mt6333_set_rg_vcore_zxos_trim(kal_uint8 val
);
1615 extern void mt6333_set_rg_vcore_rsv(kal_uint8 val
);
1616 extern kal_uint8
mt6333_get_qi_vcore_dig_mon(void);
1617 extern kal_uint8
mt6333_get_qi_vcore_oc_status(void);
1618 extern void mt6333_set_vsleep_src1(kal_uint8 val
);
1619 extern void mt6333_set_vsleep_src0_7_0(kal_uint8 val
);
1620 extern void mt6333_set_vsleep_src0_8(kal_uint8 val
);
1621 extern void mt6333_set_r2r_src0_8(kal_uint8 val
);
1622 extern void mt6333_set_r2r_src1(kal_uint8 val
);
1623 extern void mt6333_set_r2r_src0_7_0(kal_uint8 val
);
1624 extern void mt6333_set_srclken_dly_src1(kal_uint8 val
);
1625 extern void mt6333_set_rg_buck_rsv0(kal_uint8 val
);
1626 extern void mt6333_set_rg_srclken_dly_sel(kal_uint8 val
);
1627 extern void mt6333_set_rg_r2r_event_sel(kal_uint8 val
);
1628 extern void mt6333_set_qi_vcore_vsleep(kal_uint8 val
);
1629 extern void mt6333_set_vcore_en(kal_uint8 val
);
1630 extern kal_uint8
mt6333_get_qi_vcore_stb(void);
1631 extern kal_uint8
mt6333_get_qi_vcore_en(void);
1632 extern void mt6333_set_vcore_en_ctrl(kal_uint8 val
);
1633 extern void mt6333_set_vcore_vosel_ctrl(kal_uint8 val
);
1634 extern void mt6333_set_vcore_dlc_ctrl(kal_uint8 val
);
1635 extern void mt6333_set_vcore_burst_ctrl(kal_uint8 val
);
1636 extern void mt6333_set_vcore_sfchg_ren(kal_uint8 val
);
1637 extern void mt6333_set_vcore_sfchg_rrate(kal_uint8 val
);
1638 extern void mt6333_set_vcore_sfchg_fen(kal_uint8 val
);
1639 extern void mt6333_set_vcore_sfchg_frate(kal_uint8 val
);
1640 extern void mt6333_set_vcore_vosel(kal_uint8 val
);
1641 extern void mt6333_set_vcore_vosel_on(kal_uint8 val
);
1642 extern void mt6333_set_vcore_vosel_sleep(kal_uint8 val
);
1643 extern kal_uint8
mt6333_get_ni_vcore_vosel(void);
1644 extern void mt6333_set_vcore_burst(kal_uint8 val
);
1645 extern void mt6333_set_vcore_burst_on(kal_uint8 val
);
1646 extern void mt6333_set_vcore_burst_sleep(kal_uint8 val
);
1647 extern kal_uint8
mt6333_get_qi_vcore_burst(void);
1648 extern void mt6333_set_vcore_dlc(kal_uint8 val
);
1649 extern void mt6333_set_vcore_dlc_on(kal_uint8 val
);
1650 extern void mt6333_set_vcore_dlc_sleep(kal_uint8 val
);
1651 extern kal_uint8
mt6333_get_qi_vcore_dlc(void);
1652 extern void mt6333_set_vcore_dlc_n(kal_uint8 val
);
1653 extern void mt6333_set_vcore_dlc_n_on(kal_uint8 val
);
1654 extern void mt6333_set_vcore_dlc_n_sleep(kal_uint8 val
);
1655 extern kal_uint8
mt6333_get_qi_vcore_dlc_n(void);
1656 extern void mt6333_set_vcore_vsleep_en(kal_uint8 val
);
1657 extern void mt6333_set_vcore_r2r_pdn(kal_uint8 val
);
1658 extern void mt6333_set_vcore_vsleep_sel(kal_uint8 val
);
1659 extern kal_uint8
mt6333_get_ni_vcore_r2r_pdn(void);
1660 extern kal_uint8
mt6333_get_ni_vcore_vsleep_sel(void);
1661 extern void mt6333_set_vcore_transtd(kal_uint8 val
);
1662 extern void mt6333_set_vcore_vosel_trans_en(kal_uint8 val
);
1663 extern void mt6333_set_vcore_vosel_trans_once(kal_uint8 val
);
1664 extern kal_uint8
mt6333_get_ni_vcore_vosel_trans(void);
1665 extern void mt6333_set_vcore_sfchg_fen_sleep(kal_uint8 val
);
1666 extern void mt6333_set_vcore_sfchg_ren_sleep(kal_uint8 val
);
1667 extern void mt6333_set_vcore_vosel_on_spm(kal_uint8 val
);
1668 extern void mt6333_set_rg_vcore_en_oc_sdn_sel(kal_uint8 val
);
1669 extern void mt6333_set_rg_vmem_en_oc_sdn_sel(kal_uint8 val
);
1670 extern void mt6333_set_rg_vcore_en_thr_sdn_sel(kal_uint8 val
);
1671 extern void mt6333_set_rg_vmem_rsv1_5_0_3(kal_uint8 val
);
1672 extern void mt6333_set_rg_vmem_rsv1_5_4(kal_uint8 val
);
1673 extern void mt6333_set_rg_r2r_event_sync_sel(kal_uint8 val
);
1674 extern void mt6333_set_rg_vmem_en_thr_sdn_sel(kal_uint8 val
);
1675 extern void mt6333_set_rg_vmem_triml(kal_uint8 val
);
1676 extern void mt6333_set_rg_vmem_trimh(kal_uint8 val
);
1677 extern void mt6333_set_rg_vmem_cc(kal_uint8 val
);
1678 extern void mt6333_set_rg_vmem_rzsel(kal_uint8 val
);
1679 extern void mt6333_set_rg_vmem_slp(kal_uint8 val
);
1680 extern void mt6333_set_rg_vmem_csl(kal_uint8 val
);
1681 extern void mt6333_set_rg_vmem_csr(kal_uint8 val
);
1682 extern void mt6333_set_rg_vmem_avp_os(kal_uint8 val
);
1683 extern void mt6333_set_rg_vmem_avp_en(kal_uint8 val
);
1684 extern void mt6333_set_rg_vmem_ndis_en(kal_uint8 val
);
1685 extern void mt6333_set_rg_vmem_modeset(kal_uint8 val
);
1686 extern void mt6333_set_rg_vmem_zx_os(kal_uint8 val
);
1687 extern void mt6333_set_rg_vmem_csm(kal_uint8 val
);
1688 extern void mt6333_set_rg_vmem_zxos_trim(kal_uint8 val
);
1689 extern void mt6333_set_rg_vmem_rsv(kal_uint8 val
);
1690 extern kal_uint8
mt6333_get_qi_vmem_dig_mon(void);
1691 extern kal_uint8
mt6333_get_qi_vmem_oc_status(void);
1692 extern void mt6333_set_qi_vmem_vsleep(kal_uint8 val
);
1693 extern void mt6333_set_vmem_en(kal_uint8 val
);
1694 extern kal_uint8
mt6333_get_qi_vmem_stb(void);
1695 extern kal_uint8
mt6333_get_qi_vmem_en(void);
1696 extern void mt6333_set_vmem_en_ctrl(kal_uint8 val
);
1697 extern void mt6333_set_vmem_vosel_ctrl(kal_uint8 val
);
1698 extern void mt6333_set_vmem_dlc_ctrl(kal_uint8 val
);
1699 extern void mt6333_set_vmem_burst_ctrl(kal_uint8 val
);
1700 extern void mt6333_set_vmem_vosel(kal_uint8 val
);
1701 extern void mt6333_set_vmem_vosel_on(kal_uint8 val
);
1702 extern void mt6333_set_vmem_vosel_sleep(kal_uint8 val
);
1703 extern kal_uint8
mt6333_get_ni_vmem_vosel(void);
1704 extern kal_uint8
mt6333_get_qi_vmem_burst(void);
1705 extern void mt6333_set_vmem_burst(kal_uint8 val
);
1706 extern void mt6333_set_vmem_burst_on(kal_uint8 val
);
1707 extern void mt6333_set_vmem_burst_sleep(kal_uint8 val
);
1708 extern void mt6333_set_vmem_dlc(kal_uint8 val
);
1709 extern void mt6333_set_vmem_dlc_on(kal_uint8 val
);
1710 extern void mt6333_set_vmem_dlc_sleep(kal_uint8 val
);
1711 extern kal_uint8
mt6333_get_qi_vmem_dlc(void);
1712 extern kal_uint8
mt6333_get_qi_vmem_dlc_n(void);
1713 extern void mt6333_set_vmem_dlc_n(kal_uint8 val
);
1714 extern void mt6333_set_vmem_dlc_n_on(kal_uint8 val
);
1715 extern void mt6333_set_vmem_dlc_n_sleep(kal_uint8 val
);
1716 extern void mt6333_set_vmem_vsleep_en(kal_uint8 val
);
1717 extern void mt6333_set_vmem_r2r_pdn(kal_uint8 val
);
1718 extern void mt6333_set_vmem_vsleep_sel(kal_uint8 val
);
1719 extern kal_uint8
mt6333_get_ni_vmem_r2r_pdn(void);
1720 extern kal_uint8
mt6333_get_ni_vmem_vsleep_sel(void);
1721 extern void mt6333_set_vmem_transtd(kal_uint8 val
);
1722 extern void mt6333_set_vmem_vosel_trans_en(kal_uint8 val
);
1723 extern void mt6333_set_vmem_vosel_trans_once(kal_uint8 val
);
1724 extern kal_uint8
mt6333_get_ni_vmem_vosel_trans(void);
1725 extern void mt6333_set_rg_vrf18_vocal(kal_uint8 val
);
1726 extern void mt6333_set_rg_vrf18_gmsel(kal_uint8 val
);
1727 extern void mt6333_set_rg_vrf18_bk_ldo(kal_uint8 val
);
1728 extern void mt6333_set_rg_vrf18_slew_nmos(kal_uint8 val
);
1729 extern void mt6333_set_rg_vrf18_slew(kal_uint8 val
);
1730 extern void mt6333_set_rg_vrf18_cc(kal_uint8 val
);
1731 extern void mt6333_set_rg_vrf18_rzsel(kal_uint8 val
);
1732 extern void mt6333_set_rg_vrf18_slp(kal_uint8 val
);
1733 extern void mt6333_set_rg_vrf18_csl(kal_uint8 val
);
1734 extern void mt6333_set_rg_vrf18_csr(kal_uint8 val
);
1735 extern void mt6333_set_rg_vrf18_ndis_en(kal_uint8 val
);
1736 extern void mt6333_set_rg_vrf18_zx_os(kal_uint8 val
);
1737 extern void mt6333_set_rg_vrf18_burstl(kal_uint8 val
);
1738 extern void mt6333_set_rg_vrf18_bursth(kal_uint8 val
);
1739 extern void mt6333_set_rg_vrf18_rsv(kal_uint8 val
);
1740 extern kal_uint8
mt6333_get_qi_vrf18_oc_status(void);
1741 extern void mt6333_set_rg_buck_rsv1(kal_uint8 val
);
1742 extern void mt6333_set_vrf18_vosel_ctrl(kal_uint8 val
);
1743 extern void mt6333_set_vrf18_dlc_ctrl(kal_uint8 val
);
1744 extern void mt6333_set_vrf18_burst_ctrl(kal_uint8 val
);
1745 extern void mt6333_set_vrf18_vosel(kal_uint8 val
);
1746 extern void mt6333_set_vrf18_vosel_on(kal_uint8 val
);
1747 extern void mt6333_set_vrf18_vosel_sleep(kal_uint8 val
);
1748 extern kal_uint8
mt6333_get_ni_vrf18_vosel(void);
1749 extern void mt6333_set_rg_buck_mon_flag_sel(kal_uint8 val
);
1750 extern void mt6333_set_rg_buck_rsv2_5_0(kal_uint8 val
);
1751 extern void mt6333_set_rg_buck_bypass_vosel_limit(kal_uint8 val
);
1752 extern void mt6333_set_rg_buck_mon_flag_en(kal_uint8 val
);
1753 extern void mt6333_set_vrf18_dlc(kal_uint8 val
);
1754 extern void mt6333_set_vrf18_dlc_on(kal_uint8 val
);
1755 extern void mt6333_set_vrf18_dlc_sleep(kal_uint8 val
);
1756 extern kal_uint8
mt6333_get_qi_vrf18_dlc(void);
1757 extern kal_uint8
mt6333_get_qi_vrf18_dlc_n(void);
1758 extern void mt6333_set_vrf18_dlc_n(kal_uint8 val
);
1759 extern void mt6333_set_vrf18_dlc_n_on(kal_uint8 val
);
1760 extern void mt6333_set_vrf18_dlc_n_sleep(kal_uint8 val
);
1761 extern void mt6333_set_rg_vrf18_modeset(kal_uint8 val
);
1762 extern void mt6333_set_vrf18_en(kal_uint8 val
);
1763 extern void mt6333_set_rg_vrf18_stb_sel(kal_uint8 val
);
1764 extern kal_uint8
mt6333_get_qi_vrf18_stb(void);
1765 extern kal_uint8
mt6333_get_qi_vrf18_en(void);
1766 extern void mt6333_set_vrf18_en_ctrl(kal_uint8 val
);
1767 extern void mt6333_set_rg_vrf18_modeset_spm(kal_uint8 val
);
1768 extern void mt6333_set_vrf18_en_spm(kal_uint8 val
);
1769 extern void mt6333_set_rg_vcore_vosel_set_spm(kal_uint8 val
);
1770 extern void mt6333_set_k_rst_done(kal_uint8 val
);
1771 extern void mt6333_set_k_map_sel(kal_uint8 val
);
1772 extern void mt6333_set_k_once_en(kal_uint8 val
);
1773 extern void mt6333_set_k_once(kal_uint8 val
);
1774 extern void mt6333_set_k_start_manual(kal_uint8 val
);
1775 extern void mt6333_set_k_src_sel(kal_uint8 val
);
1776 extern void mt6333_set_k_auto_en(kal_uint8 val
);
1777 extern void mt6333_set_k_inv(kal_uint8 val
);
1778 extern void mt6333_set_k_control_smps(kal_uint8 val
);
1779 extern kal_uint8
mt6333_get_qi_smps_osc_cal(void);
1780 extern kal_uint8
mt6333_get_k_result(void);
1781 extern kal_uint8
mt6333_get_k_done(void);
1782 extern kal_uint8
mt6333_get_k_control(void);
1783 extern void mt6333_set_k_buck_ck_cnt(kal_uint8 val
);
1784 extern void mt6333_set_k_chr_ck_cnt(kal_uint8 val
);
1785 extern void mt6333_set_rg_strup_rsv1_2_0(kal_uint8 val
);
1786 extern void mt6333_set_rg_strup_sleep_mode_deb_sel(kal_uint8 val
);
1787 extern void mt6333_set_rg_strup_poseq_done_deb_sel(kal_uint8 val
);
1788 extern void mt6333_set_rg_strup_vmem_en_deb_sel(kal_uint8 val
);
1789 extern void mt6333_set_rg_strup_vcore_en_deb_sel(kal_uint8 val
);
1790 extern void mt6333_set_rg_strup_buck_en_deb_sel(kal_uint8 val
);
1791 extern void mt6333_set_rg_strup_osc_en(kal_uint8 val
);
1792 extern void mt6333_set_rg_strup_osc_en_sel(kal_uint8 val
);
1793 extern void mt6333_set_rg_strup_ivgen_enb(kal_uint8 val
);
1794 extern void mt6333_set_rg_strup_ivgen_enb_sel(kal_uint8 val
);
1795 extern void mt6333_set_rg_strup_rsv2_7_4(kal_uint8 val
);
1796 extern void mt6333_set_rg_strup_rsv3_7_0(kal_uint8 val
);
1797 extern void mt6333_set_rg_efuse_addr(kal_uint8 val
);
1798 extern void mt6333_set_rg_efuse_prog(kal_uint8 val
);
1799 extern void mt6333_set_rg_efuse_en(kal_uint8 val
);
1800 extern void mt6333_set_rg_efuse_pkey(kal_uint8 val
);
1801 extern void mt6333_set_rg_efuse_rd_trig(kal_uint8 val
);
1802 extern void mt6333_set_rg_efuse_prog_src(kal_uint8 val
);
1803 extern void mt6333_set_rg_prog_macro_sel(kal_uint8 val
);
1804 extern void mt6333_set_rg_rd_rdy_bypass(kal_uint8 val
);
1805 extern kal_uint8
mt6333_get_rg_efuse_rd_ack(void);
1806 extern kal_uint8
mt6333_get_rg_efuse_busy(void);
1807 extern void mt6333_set_rg_otp_pa(kal_uint8 val
);
1808 extern void mt6333_set_rg_otp_pdin(kal_uint8 val
);
1809 extern void mt6333_set_rg_otp_ptm(kal_uint8 val
);
1810 extern void mt6333_set_rg_fsource_en(kal_uint8 val
);
1811 extern kal_uint8
mt6333_get_rg_efuse_dout_0_7(void);
1812 extern kal_uint8
mt6333_get_rg_efuse_dout_8_15(void);
1813 extern kal_uint8
mt6333_get_rg_efuse_dout_16_23(void);
1814 extern kal_uint8
mt6333_get_rg_efuse_dout_24_31(void);
1815 extern kal_uint8
mt6333_get_rg_efuse_dout_32_39(void);
1816 extern kal_uint8
mt6333_get_rg_efuse_dout_40_47(void);
1817 extern kal_uint8
mt6333_get_rg_efuse_dout_48_55(void);
1818 extern kal_uint8
mt6333_get_rg_efuse_dout_56_63(void);
1819 extern void mt6333_set_testi0(kal_uint8 val
);
1820 extern void mt6333_set_testi1(kal_uint8 val
);
1821 extern void mt6333_set_testi2(kal_uint8 val
);
1822 extern void mt6333_set_testi3(kal_uint8 val
);
1823 extern void mt6333_set_testi4(kal_uint8 val
);
1824 extern void mt6333_set_testi5(kal_uint8 val
);
1825 extern void mt6333_set_testi6(kal_uint8 val
);
1826 extern void mt6333_set_testi7(kal_uint8 val
);
1827 extern void mt6333_set_testi8(kal_uint8 val
);
1828 extern void mt6333_set_testi0_sel(kal_uint8 val
);
1829 extern void mt6333_set_testi1_sel(kal_uint8 val
);
1830 extern void mt6333_set_testi2_sel(kal_uint8 val
);
1831 extern void mt6333_set_testi3_sel(kal_uint8 val
);
1832 extern void mt6333_set_testi4_sel(kal_uint8 val
);
1833 extern void mt6333_set_testi5_sel(kal_uint8 val
);
1834 extern void mt6333_set_testi6_sel(kal_uint8 val
);
1835 extern void mt6333_set_testi7_sel(kal_uint8 val
);
1836 extern void mt6333_set_testi8_sel(kal_uint8 val
);
1837 extern void mt6333_set_testo0(kal_uint8 val
);
1838 extern void mt6333_set_testo1(kal_uint8 val
);
1839 extern void mt6333_set_testo2(kal_uint8 val
);
1840 extern void mt6333_set_testo3(kal_uint8 val
);
1841 extern void mt6333_set_testo0_sel(kal_uint8 val
);
1842 extern void mt6333_set_testo1_sel(kal_uint8 val
);
1843 extern void mt6333_set_testo2_sel(kal_uint8 val
);
1844 extern void mt6333_set_testo3_sel(kal_uint8 val
);
1845 extern void mt6333_set_debug_sel(kal_uint8 val
);
1846 extern kal_uint8
mt6333_get_debug_mon(void);
1847 extern void mt6333_set_debug_bit_sel(kal_uint8 val
);
1848 extern kal_uint8
mt6333_get_cid1(void);
1850 extern void mt6333_dump_register(void);
1851 extern kal_uint32
mt6333_read_interface (kal_uint8 RegNum
, kal_uint8
*val
, kal_uint8 MASK
, kal_uint8 SHIFT
);
1852 extern kal_uint32
mt6333_config_interface (kal_uint8 RegNum
, kal_uint8 val
, kal_uint8 MASK
, kal_uint8 SHIFT
);
1854 #endif // _MT6333_SW_H_
projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob