arch/arm/mach-mt8127/include/mach/isp.h

   1 #ifndef _MT_ISP_H
   2 #define _MT_ISP_H
   3
   4 #include <linux/ioctl.h>
   5
   6 /*******************************************************************************
   7 *
   8 ********************************************************************************/
   9 #define ISP_DEV_MAJOR_NUMBER    251
  10 #define ISP_MAGIC               'k'
  11 /*******************************************************************************
  12 *
  13 ********************************************************************************/
  14 #define ISP_INT_EXP_DONE        ((u32)0x1)
  15 #define ISP_INT_IDLE            ((u32)0x1 << 3)
  16 #define ISP_INT_ISP_DONE        ((u32)0x1 << 4)
  17 #define ISP_INT_VSYNC           ((u32)0x1 << 10)
  18 #define ISP_INT_STNR            ((u32)0x1 << 29)
  19 #define ISP_INT_CLEAR_ALL       ((u32)0x1 << 30)
  20 #define ISP_INT_CLEAR_WAIT      ((u32)0x1 << 31)
  21
  22 /*******************************************************************************
  23 *
  24 ********************************************************************************/
  25 typedef struct mt_isp_reg_s {
  26     unsigned long addr;   // register's addr
  27     unsigned long val;    // register's value
  28 } mt_isp_reg_t;
  29
  30 typedef struct mt_isp_reg_io_s {
  31     unsigned long data;   // pointer to mt_isp_reg_t
  32     unsigned long count;  // count
  33 } mt_isp_reg_io_t;
  34
  35 typedef struct mt_isp_wait_irq_s {
  36     unsigned long mode;     // Mode for wait irq
  37     unsigned long timeout;  // Timeout for wait irq, uint:ms
  38 } mt_isp_wait_irq_t;
  39 /*******************************************************************************
  40 *
  41 ********************************************************************************/
  42 //IOCTRL(inode * ,file * ,cmd ,arg )
  43 //S means "set through a ptr"
  44 //T means "tell by a arg value"
  45 //G means "get by a ptr"
  46 //Q means "get by return a value"
  47 //X means "switch G and S atomically"
  48 //H means "switch T and Q atomically"
  49 // ioctrl commands
  50 // Reset
  51 #define MT_ISP_IOC_T_RESET      _IO  (ISP_MAGIC, 1)
  52 // Read register from driver
  53 #define MT_ISP_IOC_G_READ_REG   _IOWR(ISP_MAGIC, 2, mt_isp_reg_io_t)
  54 // Write register to driver
  55 #define MT_ISP_IOC_S_WRITE_REG  _IOWR(ISP_MAGIC, 3, mt_isp_reg_io_t)
  56 // Hold reg write to hw, on/off
  57 #define MT_ISP_IOC_T_HOLD_REG   _IOW (ISP_MAGIC, 4, u32)
  58 // MT_ISP_IOC_T_RUN : Tell ISP to run/stop
  59 #define MT_ISP_IOC_T_RUN        _IOW (ISP_MAGIC, 5, u32)
  60 // Wait IRQ
  61 #define MT_ISP_IOC_T_WAIT_IRQ   _IOW (ISP_MAGIC, 6, u32) //seanlin 111223 fix conpilier error mt_isp_wait_irq_t)
  62 // Dump ISP registers , for debug usage
  63 #define MT_ISP_IOC_T_DUMP_REG   _IO  (ISP_MAGIC, 7)
  64 // Dump message level
  65 #define MT_ISP_IOC_T_DBG_FLAG   _IOW (ISP_MAGIC, 8, u32)
  66 // Reset SW Buffer
  67 #define MT_ISP_IOC_T_RESET_BUF  _IO  (ISP_MAGIC, 9)
  68 // enable cam gate clock
  69 #define MT_ISP_IOC_T_ENABLE_CAM_CLOCK  _IO  (ISP_MAGIC, 10)
  70 /*******************************************************************************
  71 *
  72 ********************************************************************************/
  73 void mt_isp_mclk_ctrl(int en);
  74 //
  75 #endif
  76