arch/arm/mach-mt8127/include/mach/dma.h

   1 #ifndef __ASM_ARCH_DMA_H
   2 #define __ASM_ARCH_DMA_H
   3
   4 #define MAX_DMA_ADDRESS     (0xFFFFFFFF)
   5 #define MAX_DMA_CHANNELS    (0)
   6
   7 #endif  /* !__ASM_ARCH_DMA_H */
   8
   9 #ifndef __MT_DMA_H__
  10 #define __MT_DMA_H__
  11
  12 /* define DMA channels */
  13 enum {
  14     G_DMA_1 = 0, G_DMA_2,
  15     P_DMA_AP_HIF, P_DMA_MD_HIF,
  16     P_DMA_SIM1, P_DMA_SIM2,
  17     P_DMA_IRDA,
  18     P_DMA_UART1_TX, P_DMA_UART1_RX,
  19     P_DMA_UART2_TX, P_DMA_UART2_RX,
  20     P_DMA_UART3_TX, P_DMA_UART3_RX,
  21 };
  22
  23 /* define DMA error code */
  24 enum {
  25     DMA_ERR_CH_BUSY = 1,
  26     DMA_ERR_INVALID_CH = 2,
  27     DMA_ERR_CH_FREE = 3,
  28     DMA_ERR_NO_FREE_CH = 4,
  29     DMA_ERR_INV_CONFIG = 5,
  30 };
  31
  32 /* define DMA ISR callback function's prototype */
  33 typedef void (*DMA_ISR_CALLBACK)(void *);
  34
  35 typedef enum
  36 {
  37     DMA_FALSE = 0,
  38     DMA_TRUE
  39 } DMA_BOOL;
  40
  41 typedef enum
  42 {
  43     DMA_OK = 0,
  44     DMA_FAIL
  45 } DMA_STATUS;
  46
  47 typedef enum
  48 {
  49     REMAINING_LENGTH = 0, /* not valid for virtual FIFO */
  50     VF_READPTR,           /* only valid for virtual FIFO */
  51     VF_WRITEPTR,          /* only valid for virtual FIFO */
  52     VF_FFCNT,             /* only valid for virtual FIFO */
  53     VF_ALERT,             /* only valid for virtual FIFO */
  54     VF_EMPTY,             /* only valid for virtual FIFO */
  55     VF_FULL,              /* only valid for virtual FIFO */
  56     VF_PORT
  57 } INFO_TYPE;
  58
  59 typedef enum
  60 {
  61     GDMA_1 = 0,
  62     GDMA_2,
  63     GDMA_ANY
  64 } DMA_CHAN;
  65
  66 typedef enum
  67 {
  68     ALL = 0,
  69     SRC,
  70     DST,
  71     SRC_AND_DST
  72 } DMA_CONF_FLAG;
  73
  74 /* define GDMA configurations */
  75 struct mt_gdma_conf
  76 {
  77     unsigned int count;
  78     int iten;
  79     unsigned int burst;
  80     int dfix;
  81     int sfix;
  82     unsigned int limiter;
  83     unsigned int src;
  84     unsigned int dst;
  85     int wpen;
  86     int wpsd;
  87     unsigned int wplen;
  88     unsigned int wpto;
  89     //unsigned int cohen;
  90     unsigned int sec;
  91     void (*isr_cb)(void *);
  92     void *data;
  93 };
  94
  95 /* burst */
  96 #define DMA_CON_BURST_SINGLE    (0x00000000)
  97 #define DMA_CON_BURST_2BEAT     (0x00010000)
  98 #define DMA_CON_BURST_3BEAT     (0x00020000)
  99 #define DMA_CON_BURST_4BEAT     (0x00030000)
 100 #define DMA_CON_BURST_5BEAT     (0x00040000)
 101 #define DMA_CON_BURST_6BEAT     (0x00050000)
 102 #define DMA_CON_BURST_7BEAT     (0x00060000)
 103 #define DMA_CON_BURST_8BEAT     (0x00070000)
 104
 105 /* size */
 106 /* keep for backward compatibility only */
 107 #define DMA_CON_SIZE_BYTE   (0x00000000)
 108 #define DMA_CON_SIZE_SHORT  (0x00000001)
 109 #define DMA_CON_SIZE_LONG   (0x00000002)
 110
 111 extern void mt_reset_gdma_conf(const unsigned int iChannel);
 112
 113 extern int mt_config_gdma(int channel, struct mt_gdma_conf *config, DMA_CONF_FLAG flag);
 114 extern int mt_free_gdma(int channel);
 115 extern int mt_req_gdma(DMA_CHAN chan);
 116 extern int mt_start_gdma(int channel);
 117 extern int mt_polling_gdma(int channel, unsigned long timeout);
 118 extern int mt_stop_gdma(int channel);
 119 extern int mt_dump_gdma(int channel);
 120 extern int mt_warm_reset_gdma(int channel);
 121 extern int mt_hard_reset_gdma(int channel);
 122 extern int mt_reset_gdma(int channel);
 123 extern void mt_dma_running_status(void);
 124 /* This channel is used for APDMA Dummy READ.
 125    in MT6592 this channel will be used by Frequency hopping all the time
 126    .Owner: Chieh-Jay Liu
 127  */
 128 #define DFS_APDMA_CHANNEL 0
 129 #endif  /* !__MT_DMA_H__ */