Merge tag 'v3.10.55' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / include / mach / camera_sysram_imp.h
1 #ifndef CAMERA_SYSRAM_IMP_H
2 #define CAMERA_SYSRAM_IMP_H
3 //-----------------------------------------------------------------------------
4 typedef unsigned long long MUINT64;
5 typedef long long MINT64;
6 typedef unsigned long MUINT32;
7 typedef long MINT32;
8 typedef unsigned char MUINT8;
9 typedef char MINT8;
10 typedef bool MBOOL;
11 #define MTRUE true
12 #define MFALSE false
13 //-----------------------------------------------------------------------------
14 #define LOG_TAG "SYSRAM"
15 #define LOG_MSG(fmt, arg...) xlog_printk(ANDROID_LOG_VERBOSE, LOG_TAG, "[%s]" fmt "\r\n", __FUNCTION__, ##arg)
16 #define LOG_WRN(fmt, arg...) xlog_printk(ANDROID_LOG_VERBOSE, LOG_TAG, "[%s]WRN(%5d):" fmt "\r\n", __FUNCTION__, __LINE__, ##arg)
17 #define LOG_ERR(fmt, arg...) xlog_printk(ANDROID_LOG_ERROR, LOG_TAG, "[%s]ERR(%5d):" fmt "\r\n", __FUNCTION__, __LINE__, ##arg)
18 #define LOG_DMP(fmt, arg...) xlog_printk(ANDROID_LOG_ERROR, LOG_TAG, "" fmt, ##arg)
19 //-----------------------------------------------------------------------------
20 #define SYSRAM_DEBUG_DEFAULT (0xFFFFFFFF)
21 #define SYSRAM_JIFFIES_MAX (0xFFFFFFFF)
22 #define SYSRAM_PROC_NAME "Default"
23 //-----------------------------------------------------------------------------
24 #define SYSRAM_BASE_PHY_ADDR ((SYSRAM_BASE&0x0FFFFFFF)|0x10000000)
25 #define SYSRAM_BASE_SIZE (81920) //32K+48K
26 #define SYSRAM_BASE_ADDR_BANK_0 (SYSRAM_BASE_PHY_ADDR)
27 #define SYSRAM_BASE_SIZE_BANK_0 (SYSRAM_BASE_SIZE)
28 //
29 #define SYSRAM_USER_SIZE_VIDO (SYSRAM_BASE_SIZE)//(78408)//(74496) // Always allocate max SYSRAM size because there is no other user. //78408: Max size used when format is RGB565.
30 #define SYSRAM_USER_SIZE_GDMA (46080)
31 #define SYSRAM_USER_SIZE_SW_FD (0) //TBD
32 //
33 #define SYSRAM_MEM_NODE_AMOUNT_PER_POOL (SYSRAM_USER_AMOUNT*2 + 2)
34 //-----------------------------------------------------------------------------
35 typedef struct
36 {
37 pid_t pid; // thread id
38 pid_t tgid; // process id
39 char ProcName[TASK_COMM_LEN]; // executable name
40 MUINT64 Time64;
41 MUINT32 TimeS;
42 MUINT32 TimeUS;
43 }SYSRAM_USER_STRUCT;
44 //
45 typedef struct
46 {
47 spinlock_t SpinLock;
48 MUINT32 TotalUserCount;
49 MUINT32 AllocatedTbl;
50 MUINT32 AllocatedSize[SYSRAM_USER_AMOUNT];
51 SYSRAM_USER_STRUCT UserInfo[SYSRAM_USER_AMOUNT];
52 wait_queue_head_t WaitQueueHead;
53 MBOOL EnableClk;
54 MUINT32 DebugFlag;
55 dev_t DevNo;
56 struct cdev* pCharDrv;
57 struct class* pClass;
58 }SYSRAM_STRUCT;
59 //
60 typedef struct
61 {
62 pid_t Pid;
63 pid_t Tgid;
64 char ProcName[TASK_COMM_LEN];
65 MUINT32 Table;
66 MUINT64 Time64;
67 MUINT32 TimeS;
68 MUINT32 TimeUS;
69 }SYSRAM_PROC_STRUCT;
70
71 //
72 typedef enum
73 {
74 SYSRAM_MEM_BANK_0,
75 SYSRAM_MEM_BANK_AMOUNT,
76 SYSRAM_MEM_BANK_BAD
77 }SYSRAM_MEM_BANK_ENUM;
78 //
79 typedef struct SYSRAM_MEM_NODE
80 {
81 SYSRAM_USER_ENUM User;
82 MUINT32 Offset;
83 MUINT32 Length;
84 MUINT32 Index;
85 struct SYSRAM_MEM_NODE* pNext;
86 struct SYSRAM_MEM_NODE* pPrev;
87 }SYSRAM_MEM_NODE_STRUCT;
88 //
89 typedef struct
90 {
91 SYSRAM_MEM_NODE_STRUCT* const pMemNode;
92 MUINT32 const UserAmount;
93 MUINT32 const Addr;
94 MUINT32 const Size;
95 MUINT32 IndexTbl;
96 MUINT32 UserCount;
97 }SYSRAM_MEM_POOL_STRUCT;
98 //------------------------------------------------------------------------------
99 static SYSRAM_MEM_NODE_STRUCT SysramMemNodeBank0Tbl[SYSRAM_MEM_NODE_AMOUNT_PER_POOL];
100 static SYSRAM_MEM_POOL_STRUCT SysramMemPoolInfo[SYSRAM_MEM_BANK_AMOUNT] =
101 {
102 [SYSRAM_MEM_BANK_0] =
103 {
104 .pMemNode = &SysramMemNodeBank0Tbl[0],
105 .UserAmount = SYSRAM_MEM_NODE_AMOUNT_PER_POOL,
106 .Addr = SYSRAM_BASE_ADDR_BANK_0,
107 .Size = SYSRAM_BASE_SIZE_BANK_0,
108 .IndexTbl = (~0x1),
109 .UserCount = 0,
110 }
111 };
112 //
113 static inline SYSRAM_MEM_POOL_STRUCT* SYSRAM_GetMemPoolInfo(SYSRAM_MEM_BANK_ENUM const MemBankNo)
114 {
115 if(SYSRAM_MEM_BANK_AMOUNT > MemBankNo)
116 {
117 return &SysramMemPoolInfo[MemBankNo];
118 }
119 return NULL;
120 }
121 //
122 enum
123 {
124 SysramMemBank0UserMask =
125 (1<<SYSRAM_USER_VIDO)
126 |(1<<SYSRAM_USER_GDMA)
127 |(1<<SYSRAM_USER_SW_FD)
128 ,
129 SysramLogUserMask =
130 (1<<SYSRAM_USER_VIDO)
131 |(1<<SYSRAM_USER_GDMA)
132 |(1<<SYSRAM_USER_SW_FD)
133 };
134 //
135 static SYSRAM_MEM_BANK_ENUM SYSRAM_GetMemBankNo(SYSRAM_USER_ENUM const User)
136 {
137 MUINT32 const UserMask = (1<<User);
138 //
139 if(UserMask & SysramMemBank0UserMask)
140 {
141 return SYSRAM_MEM_BANK_0;
142 }
143 //
144 return SYSRAM_MEM_BANK_BAD;
145 }
146 //
147 static char const*const SysramUserName[SYSRAM_USER_AMOUNT] =
148 {
149 [SYSRAM_USER_VIDO] = "VIDO",
150 [SYSRAM_USER_GDMA] = "GDMA",
151 [SYSRAM_USER_SW_FD] = "SW FD"
152 };
153 //
154 static MUINT32 const SysramUserSize[SYSRAM_USER_AMOUNT] =
155 {
156 [SYSRAM_USER_VIDO] = (3 + SYSRAM_USER_SIZE_VIDO) / 4 * 4,
157 [SYSRAM_USER_GDMA] = (3 + SYSRAM_USER_SIZE_GDMA) / 4 * 4,
158 [SYSRAM_USER_SW_FD] = (3 + SYSRAM_USER_SIZE_SW_FD) / 4 * 4
159 };
160 //------------------------------------------------------------------------------
161 #endif
162