arch/arm/mach-mt8127/emi_bwl.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/semaphore.h>
   5 #include <linux/device.h>
   6 #include <linux/platform_device.h>
   7 #include <linux/xlog.h>
   8
   9 #include "mach/mt_reg_base.h"
  10 #include "mach/emi_bwl.h"
  11 #include "mach/sync_write.h"
  12
  13 DEFINE_SEMAPHORE(emi_bwl_sem);
  14
  15 static struct platform_driver mem_bw_ctrl = {
  16     .driver     = {
  17         .name = "mem_bw_ctrl",
  18         .owner = THIS_MODULE,
  19     },
  20 };
  21
  22 static struct platform_driver ddr_type = {
  23     .driver     = {
  24         .name = "ddr_type",
  25         .owner = THIS_MODULE,
  26     },
  27 };
  28
  29 #if 0
  30
  31 static struct platform_driver dramc_high = {
  32     .driver     = {
  33         .name = "dramc_high",
  34         .owner = THIS_MODULE,
  35     },
  36 };
  37
  38 static struct platform_driver mem_bw_finetune_md = {
  39     .driver     = {
  40         .name = "mem_bw_finetune_md",
  41         .owner = THIS_MODULE,
  42     },
  43 };
  44
  45 static struct platform_driver mem_bw_finetune_mm = {
  46     .driver     = {
  47         .name = "mem_bw_finetune_mm",
  48         .owner = THIS_MODULE,
  49     },
  50 };
  51 #endif
  52
  53 /* define EMI bandwiwth limiter control table */
  54 static struct emi_bwl_ctrl ctrl_tbl[NR_CON_SCE];
  55
  56 /* current concurrency scenario */
  57 static int cur_con_sce = 0x0FFFFFFF;
  58
  59 /* define concurrency scenario strings */
  60 static const char *con_sce_str[] =
  61 {
  62 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) #con_sce,
  63 #include "mach/con_sce_lpddr2.h"
  64 #undef X_CON_SCE
  65 };
  66
  67 /* define EMI bandwidth allocation tables */
  68 /****************** For LPDDR2 ******************/
  69 static const unsigned int emi_arba_lpddr2_val[] =
  70 {
  71 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arba,
  72 #include "mach/con_sce_lpddr2.h"
  73 #undef X_CON_SCE
  74 };
  75
  76 static const unsigned int emi_arbb_lpddr2_val[] =
  77 {
  78 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbb,
  79 #include "mach/con_sce_lpddr2.h"
  80 #undef X_CON_SCE
  81 };
  82 static const unsigned int emi_arbc_lpddr2_val[] =
  83 {
  84 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbc,
  85 #include "mach/con_sce_lpddr2.h"
  86 #undef X_CON_SCE
  87 };
  88 static const unsigned int emi_arbd_lpddr2_val[] =
  89 {
  90 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbd,
  91 #include "mach/con_sce_lpddr2.h"
  92 #undef X_CON_SCE
  93 };
  94 static const unsigned int emi_arbe_lpddr2_val[] =
  95 {
  96 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbe,
  97 #include "mach/con_sce_lpddr2.h"
  98 #undef X_CON_SCE
  99 };
 100
 101 /****************** For DDR3-16bit ******************/
 102
 103 static const unsigned int emi_arba_ddr3_16_val[] =
 104 {
 105 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arba,
 106 #include "mach/con_sce_ddr3_16.h"
 107 #undef X_CON_SCE
 108 };
 109
 110 static const unsigned int emi_arbb_ddr3_16_val[] =
 111 {
 112 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbb,
 113 #include "mach/con_sce_ddr3_16.h"
 114 #undef X_CON_SCE
 115 };
 116 static const unsigned int emi_arbc_ddr3_16_val[] =
 117 {
 118 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbc,
 119 #include "mach/con_sce_ddr3_16.h"
 120 #undef X_CON_SCE
 121 };
 122 static const unsigned int emi_arbd_ddr3_16_val[] =
 123 {
 124 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbd,
 125 #include "mach/con_sce_ddr3_16.h"
 126 #undef X_CON_SCE
 127 };
 128 static const unsigned int emi_arbe_ddr3_16_val[] =
 129 {
 130 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbe,
 131 #include "mach/con_sce_ddr3_16.h"
 132 #undef X_CON_SCE
 133 };
 134
 135 /****************** For LPDDR3 ******************/
 136
 137 static const unsigned int emi_arba_lpddr3_val[] =
 138 {
 139 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arba,
 140 #include "mach/con_sce_lpddr3.h"
 141 #undef X_CON_SCE
 142 };
 143
 144 static const unsigned int emi_arbb_lpddr3_val[] =
 145 {
 146 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbb,
 147 #include "mach/con_sce_lpddr3.h"
 148 #undef X_CON_SCE
 149 };
 150 static const unsigned int emi_arbc_lpddr3_val[] =
 151 {
 152 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbc,
 153 #include "mach/con_sce_lpddr3.h"
 154 #undef X_CON_SCE
 155 };
 156 static const unsigned int emi_arbd_lpddr3_val[] =
 157 {
 158 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbd,
 159 #include "mach/con_sce_lpddr3.h"
 160 #undef X_CON_SCE
 161 };
 162 static const unsigned int emi_arbe_lpddr3_val[] =
 163 {
 164 #define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe) arbe,
 165 #include "mach/con_sce_lpddr3.h"
 166 #undef X_CON_SCE
 167 };
 168
 169 int get_ddr_type(void)
 170 {
 171   unsigned int value;
 172
 173   value = DRAMC_READ(DRAMC_LPDDR2);
 174   if((value>>28) & 0x1) //check LPDDR2_EN
 175   {
 176     return LPDDR2;
 177   }
 178
 179   value = DRAMC_READ(DRAMC_PADCTL4);
 180   if((value>>7) & 0x1) //check DDR3_EN
 181   {
 182     if (DRAMC_READ(DRAMC_CONF1) & 0x1)
 183     {
 184       return DDR3_32;
 185     }
 186     else
 187     {
 188       return DDR3_16;
 189     }
 190   }
 191
 192   value = DRAMC_READ(DRAMC_ACTIM1);
 193   if((value>>28) & 0x1) //check LPDDR3_EN
 194   {
 195     return LPDDR3;
 196   }
 197
 198   return mDDR;
 199 }
 200
 201 /*
 202  * mtk_mem_bw_ctrl: set EMI bandwidth limiter for memory bandwidth control
 203  * @sce: concurrency scenario ID
 204  * @op: either ENABLE_CON_SCE or DISABLE_CON_SCE
 205  * Return 0 for success; return negative values for failure.
 206  */
 207 int mtk_mem_bw_ctrl(int sce, int op)
 208 {
 209   int i, highest;
 210
 211   if (sce >= NR_CON_SCE) {
 212     return -1;
 213   }
 214
 215   if (op != ENABLE_CON_SCE && op != DISABLE_CON_SCE) {
 216     return -1;
 217   }
 218   if (in_interrupt()) {
 219    return -1;
 220   }
 221
 222   down(&emi_bwl_sem);
 223
 224   if (op == ENABLE_CON_SCE) {
 225     ctrl_tbl[sce].ref_cnt++;
 226   }
 227   else if (op == DISABLE_CON_SCE) {
 228     if (ctrl_tbl[sce].ref_cnt != 0) {
 229       ctrl_tbl[sce].ref_cnt--;
 230     }
 231   }
 232
 233   /* find the scenario with the highest priority */
 234   highest = -1;
 235   for (i = 0; i < NR_CON_SCE; i++) {
 236       if (ctrl_tbl[i].ref_cnt != 0) {
 237           highest = i;
 238           break;
 239       }
 240   }
 241   if (highest == -1) {
 242       highest = CON_SCE_NORMAL;
 243   }
 244
 245   /* set new EMI bandwidth limiter value */
 246   if (highest != cur_con_sce) {
 247
 248 #if 1
 249     if(get_ddr_type() == LPDDR2)
 250     {
 251       mt65xx_reg_sync_writel(emi_arba_lpddr2_val[highest], EMI_ARBA);
 252       mt65xx_reg_sync_writel(emi_arbb_lpddr2_val[highest], EMI_ARBB);
 253       mt65xx_reg_sync_writel(emi_arbc_lpddr2_val[highest], EMI_ARBC);
 254       mt65xx_reg_sync_writel(emi_arbd_lpddr2_val[highest], EMI_ARBD);
 255       mt65xx_reg_sync_writel(emi_arbe_lpddr2_val[highest], EMI_ARBE);
 256     }
 257     else if(get_ddr_type() == DDR3_16)
 258     {
 259       mt65xx_reg_sync_writel(emi_arba_ddr3_16_val[highest], EMI_ARBA);
 260       mt65xx_reg_sync_writel(emi_arbb_ddr3_16_val[highest], EMI_ARBB);
 261       mt65xx_reg_sync_writel(emi_arbc_ddr3_16_val[highest], EMI_ARBC);
 262       mt65xx_reg_sync_writel(emi_arbd_ddr3_16_val[highest], EMI_ARBD);
 263       mt65xx_reg_sync_writel(emi_arbe_ddr3_16_val[highest], EMI_ARBE);
 264     }
 265     else if(get_ddr_type() == LPDDR3)
 266     {
 267       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBA);
 268       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBB);
 269       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBC);
 270       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBD);
 271       mt65xx_reg_sync_writel(emi_arba_lpddr3_val[highest], EMI_ARBE);
 272     }
 273 #endif
 274       cur_con_sce = highest;
 275   }
 276
 277   up(&emi_bwl_sem);
 278
 279   return 0;
 280 }
 281
 282 /*
 283  * ddr_type_show: sysfs ddr_type file show function.
 284  * @driver:
 285  * @buf: the string of ddr type
 286  * Return the number of read bytes.
 287  */
 288 static ssize_t ddr_type_show(struct device_driver *driver, char *buf)
 289 {
 290     if(get_ddr_type() == LPDDR2)
 291     {
 292       sprintf(buf, "LPDDR2\n");
 293     }
 294     else if(get_ddr_type() == DDR3_16)
 295     {
 296       sprintf(buf, "DDR3_16\n");
 297     }
 298     else if(get_ddr_type() == DDR3_32)
 299     {
 300       sprintf(buf, "DDR3_32\n");
 301     }
 302     else if(get_ddr_type() == LPDDR3)
 303     {
 304       sprintf(buf, "LPDDR3\n");
 305     }
 306     else
 307     {
 308       sprintf(buf, "mDDR\n");
 309     }
 310
 311     return strlen(buf);
 312 }
 313
 314 /*
 315  * ddr_type_store: sysfs ddr_type file store function.
 316  * @driver:
 317  * @buf:
 318  * @count:
 319  * Return the number of write bytes.
 320  */
 321 static ssize_t ddr_type_store(struct device_driver *driver, const char *buf, size_t count)
 322 {
 323   /*do nothing*/
 324   return count;
 325 }
 326
 327 DRIVER_ATTR(ddr_type, 0644, ddr_type_show, ddr_type_store);
 328
 329 /*
 330  * con_sce_show: sysfs con_sce file show function.
 331  * @driver:
 332  * @buf:
 333  * Return the number of read bytes.
 334  */
 335 static ssize_t con_sce_show(struct device_driver *driver, char *buf)
 336 {
 337     if (cur_con_sce >= NR_CON_SCE) {
 338         sprintf(buf, "none\n");
 339     } else {
 340         sprintf(buf, "%s\n", con_sce_str[cur_con_sce]);
 341     }
 342
 343     return strlen(buf);
 344 }
 345
 346 /*
 347  * con_sce_store: sysfs con_sce file store function.
 348  * @driver:
 349  * @buf:
 350  * @count:
 351  * Return the number of write bytes.
 352  */
 353 static ssize_t con_sce_store(struct device_driver *driver, const char *buf, size_t count)
 354 {
 355   int i;
 356
 357   for (i = 0; i < NR_CON_SCE; i++) {
 358     if (!strncmp(buf, con_sce_str[i], strlen(con_sce_str[i]))) {
 359       if (!strncmp(buf + strlen(con_sce_str[i]) + 1, EN_CON_SCE_STR, strlen(EN_CON_SCE_STR))) {
 360         mtk_mem_bw_ctrl(i, ENABLE_CON_SCE);
 361         printk("concurrency scenario %s ON\n", con_sce_str[i]);
 362         break;
 363       }
 364       else if (!strncmp(buf + strlen(con_sce_str[i]) + 1, DIS_CON_SCE_STR, strlen(DIS_CON_SCE_STR))) {
 365         mtk_mem_bw_ctrl(i, DISABLE_CON_SCE);
 366         printk("concurrency scenario %s OFF\n", con_sce_str[i]);
 367         break;
 368       }
 369     }
 370   }
 371
 372   return count;
 373 }
 374
 375 DRIVER_ATTR(concurrency_scenario, 0644, con_sce_show, con_sce_store);
 376
 377
 378 /*
 379  * finetune_md_show: sysfs con_sce file show function.
 380  * @driver:
 381  * @buf:
 382  * Return the number of read bytes.
 383  */
 384 static ssize_t finetune_md_show(struct device_driver *driver, char *buf)
 385 {
 386   unsigned int dram_type;
 387
 388   dram_type = get_ddr_type();
 389
 390   if(dram_type == LPDDR2) /*LPDDR2. FIXME*/
 391   {
 392     switch(cur_con_sce)
 393     {
 394       case CON_SCE_VR:
 395         sprintf(buf, "true");
 396         break;
 397       default:
 398         sprintf(buf, "false");
 399         break;
 400     }
 401   }
 402   else if(dram_type == DDR3_16) /*DDR3-16bit. FIXME*/
 403   {
 404     /*TBD*/
 405   }
 406   else if(dram_type == DDR3_32) /*DDR3-32bit. FIXME*/
 407   {
 408     /*TBD*/
 409   }
 410   else if(dram_type == mDDR) /*mDDR. FIXME*/
 411   {
 412     /*TBD*/
 413   }
 414   else
 415   {
 416     /*unkown dram type*/
 417     sprintf(buf, "ERROR: unkown dram type!");
 418   }
 419
 420   return strlen(buf);
 421 }
 422
 423 /*
 424  * finetune_md_store: sysfs con_sce file store function.
 425  * @driver:
 426  * @buf:
 427  * @count:
 428  * Return the number of write bytes.
 429  */
 430 static ssize_t finetune_md_store(struct device_driver *driver, const char *buf, size_t count)
 431 {
 432   /*Do nothing*/
 433   return count;
 434 }
 435
 436 DRIVER_ATTR(finetune_md, 0644, finetune_md_show, finetune_md_store);
 437
 438
 439 /*
 440  * finetune_mm_show: sysfs con_sce file show function.
 441  * @driver:
 442  * @buf:
 443  * Return the number of read bytes.
 444  */
 445 static ssize_t finetune_mm_show(struct device_driver *driver, char *buf)
 446 {
 447   unsigned int dram_type;
 448
 449   dram_type = get_ddr_type();
 450
 451   if(dram_type == LPDDR2) /*LPDDR2. FIXME*/
 452   {
 453     switch(cur_con_sce)
 454     {
 455       default:
 456         sprintf(buf, "false");
 457         break;
 458     }
 459   }
 460   else if(dram_type == DDR3_16) /*DDR3-16bit. FIXME*/
 461   {
 462     /*TBD*/
 463   }
 464   else if(dram_type == DDR3_32) /*DDR3-32bit. FIXME*/
 465   {
 466     /*TBD*/
 467   }
 468   else if(dram_type == mDDR) /*mDDR. FIXME*/
 469   {
 470     /*TBD*/
 471   }
 472   else
 473   {
 474     /*unkown dram type*/
 475     sprintf(buf, "ERROR: unkown dram type!");
 476   }
 477
 478   return strlen(buf);
 479 }
 480
 481 /*
 482  * finetune_md_store: sysfs con_sce file store function.
 483  * @driver:
 484  * @buf:
 485  * @count:
 486  * Return the number of write bytes.
 487  */
 488 static ssize_t finetune_mm_store(struct device_driver *driver, const char *buf, size_t count)
 489 {
 490   /*Do nothing*/
 491   return count;
 492 }
 493
 494 DRIVER_ATTR(finetune_mm, 0644, finetune_mm_show, finetune_mm_store);
 495
 496 #if 0
 497 /*
 498  * dramc_high_show: show the status of DRAMC_HI_EN
 499  * @driver:
 500  * @buf:
 501  * Return the number of read bytes.
 502  */
 503 static ssize_t dramc_high_show(struct device_driver *driver, char *buf)
 504 {
 505  unsigned int dramc_hi;
 506
 507  dramc_hi = (readl(EMI_TESTB) >> 12) & 0x1;
 508  if(dramc_hi == 1)
 509   return sprintf(buf, "DRAMC_HI is ON\n");
 510  else
 511   return sprintf(buf, "DRAMC_HI is OFF\n");
 512 }
 513
 514 /*
 515  dramc_hign_store: enable/disable DRAMC untra high. WARNING: ONLY CAN BE ENABLED AT MD_STANDALONE!!!
 516  * @driver:
 517  * @buf: need to be "0" or "1"
 518  * @count:
 519  * Return the number of write bytes.
 520 */
 521 static ssize_t dramc_high_store(struct device_driver *driver, const char *buf, size_t count)
 522 {
 523   unsigned int value;
 524   unsigned int emi_testb;
 525
 526   if (sscanf(buf, "%u", &value) != 1)
 527     return -EINVAL;
 528
 529   emi_testb = readl(EMI_TESTB);
 530
 531   if(value == 1)
 532   {
 533     emi_testb |= 0x1000; /* Enable DRAM_HI */
 534     mt65xx_reg_sync_writel(emi_testb, EMI_TESTB);
 535   }
 536   else if(value == 0)
 537   {
 538     emi_testb &= ~0x1000; /* Disable DRAM_HI */
 539     mt65xx_reg_sync_writel(emi_testb, EMI_TESTB);
 540   }
 541   else
 542     return -EINVAL;
 543
 544   return count;
 545 }
 546
 547 DRIVER_ATTR(dramc_high, 0644, dramc_high_show, dramc_high_store);
 548 #endif
 549 /*
 550  * emi_bwl_mod_init: module init function.
 551  */
 552 static int __init emi_bwl_mod_init(void)
 553 {
 554   int ret;
 555
 556 #if 0 //Marcos: TBD
 557   if(get_ddr_type() == LPDDR2) //LPDDR2
 558   {
 559     /* apply co-sim result for LPDDR2. */
 560     mt65xx_reg_sync_writel(0x14212836, EMI_CONB);
 561     mt65xx_reg_sync_writel(0x0f131314, EMI_CONC);
 562     mt65xx_reg_sync_writel(0x14212836, EMI_COND);
 563     mt65xx_reg_sync_writel(0x0f131314, EMI_CONE);
 564     mt65xx_reg_sync_writel(0x0f131428, EMI_CONG);
 565     mt65xx_reg_sync_writel(0x0f131428, EMI_CONH);
 566     /* testing for MD2 timing fail */
 567     mt65xx_reg_sync_writel(0x0c8f0ccd, EMI_SLCT);
 568     //mt65xx_reg_sync_writel(0x088b08cd, EMI_SLCT);
 569     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK);
 570     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK_2ND);
 571     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ);
 572     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ_2ND);
 573     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI);
 574     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI_2ND);
 575     mt65xx_reg_sync_writel(0x00070714, EMI_TESTB);
 576     //mt65xx_reg_sync_writel(0x00070754, EMI_TESTB);
 577     //mt65xx_reg_sync_writel(0x10000000, EMI_TESTD);
 578   }
 579
 580   else if(get_ddr_type() == DDR3_16) //DDR3-16bit
 581   {
 582     //write overhead value
 583     mt65xx_reg_sync_writel(0x0B0B0E17, EMI_CONB);       //read  overhead for 4~1
 584     mt65xx_reg_sync_writel(0x0B0B0B0B, EMI_CONC);       //read  overhead for 8~5
 585     mt65xx_reg_sync_writel(0x1012161E, EMI_COND);       //write overhead for 4~1
 586     mt65xx_reg_sync_writel(0x0B0B0D0E, EMI_CONE);   //write overhead for 8~5
 587   }
 588   else if(get_ddr_type() == DDR3_32)
 589   {
 590     /* apply co-sim result for LPDDR2. */
 591     mt65xx_reg_sync_writel(0x14212836, EMI_CONB);
 592     mt65xx_reg_sync_writel(0x0f131314, EMI_CONC);
 593     mt65xx_reg_sync_writel(0x14212836, EMI_COND);
 594     mt65xx_reg_sync_writel(0x0f131314, EMI_CONE);
 595     mt65xx_reg_sync_writel(0x0f131428, EMI_CONG);
 596     mt65xx_reg_sync_writel(0x0f131428, EMI_CONH);
 597     /* testing for MD2 timing fail */
 598     mt65xx_reg_sync_writel(0x088b08cd, EMI_SLCT);
 599     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK);
 600     mt65xx_reg_sync_writel(0x00720038, EMI_ARBK_2ND);
 601     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ);
 602     mt65xx_reg_sync_writel(0x84462f2f, EMI_ARBJ_2ND);
 603     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI);
 604     mt65xx_reg_sync_writel(0x10202488, EMI_ARBI_2ND);
 605     mt65xx_reg_sync_writel(0x00070714, EMI_TESTB);
 606     //mt65xx_reg_sync_writel(0x00070754, EMI_TESTB);
 607     //mt65xx_reg_sync_writel(0x10000000, EMI_TESTD);
 608   }
 609   else if(get_ddr_type() == LPDDR3)
 610   {
 611     //TBD
 612   }  */
 613   else //mDDR
 614   {
 615     mt65xx_reg_sync_writel(0x2B2C2C2E, EMI_CONB);       //read  overhead for 4~1
 616     mt65xx_reg_sync_writel(0x2627292B, EMI_CONC);       //read  overhead for 8~5
 617     mt65xx_reg_sync_writel(0x2B2C2C2E, EMI_COND);       //write overhead for 4~1
 618     mt65xx_reg_sync_writel(0x2627292B, EMI_CONE);       //write overhead for 8~5
 619   }
 620 #endif
 621
 622   //write Filter Priority Encode
 623   //writel(0x01812488, EMI_ARBI); //TBD. need to set EMI_ARBI_2ND???
 624
 625   ret = mtk_mem_bw_ctrl(CON_SCE_NORMAL, ENABLE_CON_SCE);
 626   if (ret) {
 627     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to set EMI bandwidth limiter\n");
 628   }
 629
 630   /* Register BW ctrl interface */
 631   ret = platform_driver_register(&mem_bw_ctrl);
 632   if (ret) {
 633     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register EMI_BW_LIMITER driver\n");
 634   }
 635
 636   ret = driver_create_file(&mem_bw_ctrl.driver, &driver_attr_concurrency_scenario);
 637   if (ret) {
 638     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create EMI_BW_LIMITER sysfs file\n");
 639   }
 640
 641   /* Register DRAM type information interface */
 642   ret = platform_driver_register(&ddr_type);
 643   if (ret) {
 644     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register DRAM_TYPE driver\n");
 645   }
 646
 647   ret = driver_create_file(&ddr_type.driver, &driver_attr_ddr_type);
 648   if (ret) {
 649     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create DRAM_TYPE sysfs file\n");
 650   }
 651 #if 0
 652   /* Register DRAMC ultra high interface */
 653   ret = platform_driver_register(&dramc_high);
 654   ret = driver_create_file(&dramc_high.driver, &driver_attr_dramc_high);
 655   if (ret) {
 656     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create DRAMC_HIGH sysfs file\n");
 657   }
 658 #endif
 659 #if 0
 660   /* Register MD feature fine-tune interface */
 661   ret = platform_driver_register(&mem_bw_finetune_md);
 662   if (ret) {
 663     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register EMI_BW_FINETUNE_MD driver\n");
 664   }
 665
 666   ret = driver_create_file(&mem_bw_finetune_md.driver, &driver_attr_finetune_md);
 667   if (ret) {
 668     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create EMI_BW_FINETUNE_MD sysfs file\n");
 669   }
 670
 671   /* Register MM feature fine-tune interface */
 672   ret = platform_driver_register(&mem_bw_finetune_mm);
 673   if (ret) {
 674     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to register EMI_BW_FINETUNE_MM driver\n");
 675   }
 676
 677   ret = driver_create_file(&mem_bw_finetune_mm.driver, &driver_attr_finetune_mm);
 678   if (ret) {
 679     xlog_printk(ANDROID_LOG_ERROR, "EMI/BWL", "fail to create EMI_BW_FINETUNE_MM sysfs file\n");
 680   }
 681 #endif
 682
 683   return 0;
 684 }
 685
 686 /*
 687  * emi_bwl_mod_exit: module exit function.
 688  */
 689 static void __exit emi_bwl_mod_exit(void)
 690 {
 691 }
 692
 693 EXPORT_SYMBOL(get_ddr_type);
 694
 695 module_init(emi_bwl_mod_init);
 696 module_exit(emi_bwl_mod_exit);
 697