arch/arm/mach-mt8127/dram_overclock.c

   1 #include <linux/kernel.h>
   2 #include <linux/device.h>
   3 #include <linux/module.h>
   4 #include <linux/platform_device.h>
   5 #include <linux/kallsyms.h>
   6 #include <linux/cpu.h>
   7 #include <linux/smp.h>
   8 #include <asm/cacheflush.h>
   9 #include <asm/outercache.h>
  10 #include <asm/system.h>
  11 #include <asm/delay.h>
  12 #include <mach/mt_reg_base.h>
  13 #include <mach/mt_clkmgr.h>
  14 #include <mach/mt_freqhopping.h>
  15 #include <mach/emi_bwl.h>
  16 #include <mach/mt_typedefs.h>
  17 #include <mach/memory.h>
  18
  19 #define DRAMC_WRITE_REG(val,offset)     do{ \
  20                                       (*(volatile unsigned int *)(DRAMC0_BASE + (offset))) = (unsigned int)(val); \
  21                                       (*(volatile unsigned int *)(DDRPHY_BASE + (offset))) = (unsigned int)(val); \
  22                                       (*(volatile unsigned int *)(DRAMC_NAO_BASE + (offset))) = (unsigned int)(val); \
  23                                       }while(0)
  24
  25 static int dram_clk;
  26 static DEFINE_SPINLOCK(lock);
  27
  28 __attribute__ ((__section__ (".sram.func"))) int sram_set_dram(int clk)
  29 {
  30     /* set ac timing */
  31     if(clk == 293) {
  32         DRAMC_WRITE_REG( 0x778844D5     , 0x0  );
  33         DRAMC_WRITE_REG( 0xC0064301     , 0x7C );
  34         DRAMC_WRITE_REG( 0x9F0C8CA0     , 0x44 );
  35         DRAMC_WRITE_REG( 0x03406348     , 0x8  );
  36         DRAMC_WRITE_REG( 0x11662742     , 0x1DC);
  37         DRAMC_WRITE_REG( 0x01001010     , 0x1E8);
  38         DRAMC_WRITE_REG( 0x17000000     , 0xFC );
  39         udelay(10);
  40     }
  41     return 0;
  42 }
  43 static void enable_gpu(void)
  44 {
  45     enable_clock(MT_CG_MFG_HYD, "MFG");
  46     enable_clock(MT_CG_MFG_G3D, "MFG");
  47     enable_clock(MT_CG_MFG_MEM, "MFG");
  48     enable_clock(MT_CG_MFG_AXI, "MFG");
  49 }
  50 static void disable_gpu(void)
  51 {
  52     disable_clock(MT_CG_MFG_AXI, "MFG");
  53     disable_clock(MT_CG_MFG_MEM, "MFG");
  54     disable_clock(MT_CG_MFG_G3D, "MFG");
  55     disable_clock(MT_CG_MFG_HYD, "MFG");
  56 }
  57 static ssize_t dram_overclock_show(struct device_driver *driver, char *buf)
  58 {
  59     return snprintf(buf, PAGE_SIZE, "%d,%d\n",get_ddr_type(), mt_fh_get_dramc());
  60 }
  61 static ssize_t dram_overclock_store(struct device_driver *driver, const char *buf, size_t count)
  62 {
  63     int clk, ret = 0;
  64
  65     clk = simple_strtol(buf, 0, 10);
  66     dram_clk = mt_fh_get_dramc();
  67     if(clk == dram_clk) {
  68         printk(KERN_ERR "dram_clk:%d, is equal to user inpu clk:%d\n", dram_clk, clk);
  69         return count;
  70     }
  71     spin_lock(&lock);
  72     ret = sram_set_dram(clk);
  73     if(ret < 0)
  74         printk(KERN_ERR "dram overclock in sram failed:%d, clk:%d\n", ret, clk);
  75     spin_unlock(&lock);
  76     ret = mt_fh_dram_overclock(clk);
  77     if(ret < 0)
  78         printk(KERN_ERR "dram overclock failed:%d, clk:%d\n", ret, clk);
  79     printk(KERN_INFO "In %s pass, dram_clk:%d, clk:%d\n", __func__, dram_clk, clk);
  80     return count;
  81 }
  82 extern unsigned int RESERVED_MEM_SIZE_FOR_TEST_3D;
  83 extern unsigned int FB_SIZE_EXTERN;
  84 extern unsigned int get_max_DRAM_size (void);
  85 static ssize_t ftm_dram_3d_show(struct device_driver *driver, char *buf)
  86 {
  87     unsigned int pa_3d_base = PHYS_OFFSET + get_max_DRAM_size() - RESERVED_MEM_SIZE_FOR_TEST_3D - FB_SIZE_EXTERN;
  88     return snprintf(buf, PAGE_SIZE, "%u\n", pa_3d_base);
  89 }
  90 static ssize_t ftm_dram_3d_store(struct device_driver *driver, const char *buf, size_t count)
  91 {
  92     return count;
  93 }
  94 static ssize_t ftm_dram_mtcmos_show(struct device_driver *driver, char *buf)
  95 {
  96     return 0;
  97 }
  98 static ssize_t ftm_dram_mtcmos_store(struct device_driver *driver, const char *buf, size_t count)
  99 {
 100     int enable;
 101     enable = simple_strtol(buf, 0, 10);
 102     if(enable == 1) {
 103         enable_gpu();
 104         printk(KERN_INFO "enable in %s, enable:%d\n", __func__, enable);
 105     } else if(enable == 0) {
 106         disable_gpu();
 107         printk(KERN_INFO "enable in %s, disable:%d\n", __func__, enable);
 108     } else
 109         printk(KERN_ERR "dram overclock failed:%s, enable:%d\n", __func__, enable);
 110     return count;
 111 }
 112
 113 DRIVER_ATTR(emi_clk_test, 0664, dram_overclock_show, dram_overclock_store);
 114 DRIVER_ATTR(emi_clk_3d_test, 0664, ftm_dram_3d_show, ftm_dram_3d_store);
 115 DRIVER_ATTR(emi_clk_mtcmos_test, 0664, ftm_dram_mtcmos_show, ftm_dram_mtcmos_store);
 116
 117 static struct device_driver dram_overclock_drv =
 118 {
 119     .name = "emi_clk_test",
 120     .bus = &platform_bus_type,
 121     .owner = THIS_MODULE,
 122 };
 123
 124 extern char __ssram_text, _sram_start, __esram_text;
 125 int __init dram_overclock_init(void)
 126 {
 127     int ret;
 128     unsigned char * dst = &__ssram_text;
 129     unsigned char * src =  &_sram_start;
 130
 131     ret = driver_register(&dram_overclock_drv);
 132     if (ret) {
 133         printk(KERN_ERR "fail to create the dram_overclock driver\n");
 134         return ret;
 135     }
 136     ret = driver_create_file(&dram_overclock_drv, &driver_attr_emi_clk_test);
 137     if (ret) {
 138         printk(KERN_ERR "fail to create the dram_overclock sysfs files\n");
 139         return ret;
 140     }
 141     ret = driver_create_file(&dram_overclock_drv, &driver_attr_emi_clk_3d_test);
 142     if (ret) {
 143         printk(KERN_ERR "fail to create the ftm_dram_3d_drv sysfs files\n");
 144         return ret;
 145     }
 146     ret = driver_create_file(&dram_overclock_drv, &driver_attr_emi_clk_mtcmos_test);
 147     if (ret) {
 148         printk(KERN_ERR "fail to create the ftm_dram_mtcmos_drv sysfs files\n");
 149         return ret;
 150     }
 151
 152     for (dst = &__ssram_text ; dst < (unsigned char *)&__esram_text ; dst++,src++) {
 153         *dst = *src;
 154     }
 155
 156     return 0;
 157 }
 158
 159 arch_initcall(dram_overclock_init);