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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mach-mt8127 / camera_isp.c
1 /******************************************************************************
2 * camera_isp.c - Linux ISP Device Driver
3 *
4 * Copyright 2008-2009 MediaTek Co.,Ltd.
5 *
6 * DESCRIPTION:
7 * This file provid the other drivers ISP relative functions
8 *
9 ******************************************************************************/
10
11 #include <linux/types.h>
12 #include <linux/device.h>
13 #include <linux/cdev.h>
14 #include <linux/platform_device.h>
15 #include <linux/interrupt.h>
16 //#include <asm/io.h>
17 //#include <asm/tcm.h>
18 #include <linux/proc_fs.h> //proc file use
19 #include <linux/slab.h> //kmalloc/kfree in kernel 3.10
20 #include <linux/spinlock.h>
21 //#include <linux/io.h>
22 #include <linux/delay.h>
23 #include <linux/uaccess.h>
24 #include <asm/atomic.h>
25 #include <linux/sched.h>
26 #include <linux/mm.h>
27 #include <linux/xlog.h> // For xlog_printk().
28 #include <linux/aee.h>
29
30 #include <mach/hardware.h>
31 //#include <mach/mt6589_pll.h>
32 #include <mach/camera_isp.h>
33 #include <mach/mt_reg_base.h>
34 #include <mach/mt_clkmgr.h> // For clock mgr APIS. enable_clock()/disable_clock().
35 #include <mach/sync_write.h> // For mt65xx_reg_sync_writel().
36 #include <mach/mt_spm_idle.h> // For spm_enable_sodi()/spm_disable_sodi().
37 //for sysfs
38 #include <linux/kobject.h>
39 #include <linux/sysfs.h>
40 #include <linux/init.h>
41
42 #include <smi_common.h>
43 #include <ddp_cmdq.h>
44
45 #include <mach/m4u.h>
46
47 /*******************************************************************************
48 * common type define
49 ********************************************************************************/
50 typedef unsigned char MUINT8;
51 typedef unsigned short MUINT16;
52 typedef unsigned int MUINT32;
53 typedef unsigned long long MUINT64;
54
55 typedef signed char MINT8;
56 typedef signed short MINT16;
57 typedef signed int MINT32;
58 typedef signed long long MINT64;
59
60 typedef float MFLOAT;
61
62 typedef void MVOID;
63 typedef int MBOOL;
64
65 #ifndef MTRUE
66 #define MTRUE 1
67 #endif
68
69 #ifndef MFALSE
70 #define MFALSE 0
71 #endif
72
73 /*******************************************************************************
74 * LOG marco
75 ********************************************************************************/
76 //#define LOG_MSG(fmt, arg...) printk(KERN_ERR "[ISP][%s]" fmt,__FUNCTION__, ##arg)
77 //#define LOG_DBG(fmt, arg...) printk(KERN_ERR "[ISP][%s]" fmt,__FUNCTION__, ##arg)
78 //#define LOG_WRN(fmt, arg...) printk(KERN_ERR "[ISP][%s]Warning" fmt,__FUNCTION__, ##arg)
79 //#define LOG_ERR(fmt, arg...) printk(KERN_ERR "[ISP][%s]Err(%5d):" fmt, __FUNCTION__,__LINE__, ##arg)
80
81 #define LOG_VRB(format, args...) xlog_printk(ANDROID_LOG_VERBOSE, "ISP", "[%s] " format, __FUNCTION__, ##args)
82 #define LOG_DBG(format, args...) xlog_printk(ANDROID_LOG_DEBUG , "ISP", "[%s] " format, __FUNCTION__, ##args)
83 #define LOG_INF(format, args...) xlog_printk(ANDROID_LOG_INFO , "ISP", "[%s] " format, __FUNCTION__, ##args)
84 #define LOG_WRN(format, args...) xlog_printk(ANDROID_LOG_WARN , "ISP", "[%s] WARNING: " format, __FUNCTION__, ##args)
85 #define LOG_ERR(format, args...) xlog_printk(ANDROID_LOG_ERROR , "ISP", "[%s, line%04d] ERROR: " format, __FUNCTION__, __LINE__, ##args)
86 #define LOG_AST(format, args...) xlog_printk(ANDROID_LOG_ASSERT , "ISP", "[%s, line%04d] ASSERT: " format, __FUNCTION__, __LINE__, ##args)
87 #define LOG_GPIO_REG(format, args...) xlog_printk(ANDROID_LOG_ERROR , "CAM", "[%s ]: " format, __FUNCTION__, ##args)
88
89 /*******************************************************************************
90 * defined marco
91 ********************************************************************************/
92
93 #define ISP_WR32(addr, data) iowrite32(data, addr) // For other projects.
94 //#define ISP_WR32(addr, data) mt65xx_reg_sync_writel(data, addr) // For 89 Only.NEED_TUNING_BY_PROJECT
95 #define ISP_RD32(addr) ioread32(addr)
96 #define ISP_SET_BIT(reg, bit) ((*(volatile MUINT32*)(reg)) |= (MUINT32)(1 << (bit)))
97 #define ISP_CLR_BIT(reg, bit) ((*(volatile MUINT32*)(reg)) &= ~((MUINT32)(1 << (bit))))
98
99 #define OVERRUN_AEE_WARNING
100
101 /*******************************************************************************
102 * defined value
103 ********************************************************************************/
104 ///////////////////////////////////////////////////////////////////
105 //for restricting range in mmap function
106 //isp driver
107 #define ISP_RTBUF_REG_RANGE 0x10000
108 #define IMGSYS_BASE_ADDR 0x15000000
109 #define ISP_REG_RANGE (0x10000) //0x6100,the same with the value in isp_reg.h and page-aligned
110 //seninf driver
111 #define SENINF_BASE_ADDR 0x15008000 //the same with the value in seninf_drv.cpp(chip-dependent)
112 #define SENINF_REG_RANGE (0x1000) //0x800,the same with the value in seninf_reg.h and page-aligned
113 //#define IMGSYS_CG_CLR0_ADDR 0x15000000 //the same with the value in seninf_drv.cpp(chip-dependent)
114 //#define MMSYS_RANGE (0x1000) //0x100,the same with the value in seninf_drv.cpp and page-aligned
115 #define PLL_BASE_ADDR 0x10000000 //the same with the value in seninf_drv.cpp(chip-dependent)
116 #define PLL_RANGE (0x1000) //0x200,the same with the value in seninf_drv.cpp and page-aligned
117 #define MIPIRX_CONFIG_ADDR 0x1500C000 //the same with the value in seninf_drv.cpp(chip-dependent)
118 #define MIPIRX_CONFIG_RANGE (0x1000)//0x100,the same with the value in seninf_drv.cpp and page-aligned
119 #define MIPIRX_ANALOG_ADDR 0x10010000 //the same with the value in seninf_drv.cpp(chip-dependent)
120 #define MIPIRX_ANALOG_RANGE (0x1000)
121 #define GPIO_BASE_ADDR 0x10005000 //the same with the value in seninf_drv.cpp(chip-dependent)
122 #define GPIO_RANGE (0x1000)
123 #define EFUSE_BASE_ADDR 0x10206000
124 #define EFUSE_RANGE (0x1000) //0x400,the same with the value in seninf_drv.cpp and page-aligned
125 //security concern
126 #define ISP_RANGE (0x10000)
127 ///////////////////////////////////////////////////////////////////
128
129
130 #define ISP_DEV_NAME "camera-isp"
131 #define ISP_IRQ_POLLING (0)
132
133 #define ISP_DBG_INT (0x00000001)
134 #define ISP_DBG_HOLD_REG (0x00000002)
135 #define ISP_DBG_READ_REG (0x00000004)
136 #define ISP_DBG_WRITE_REG (0x00000008)
137 #define ISP_DBG_CLK (0x00000010)
138 #define ISP_DBG_TASKLET (0x00000020)
139 #define ISP_DBG_SCHEDULE_WORK (0x00000040)
140 #define ISP_DBG_BUF_WRITE (0x00000080)
141 #define ISP_DBG_BUF_CTRL (0x00000100)
142 #define ISP_DBG_REF_CNT_CTRL (0x00000200)
143
144 #define ISP_ADDR (CAMINF_BASE + 0x4000)
145 #define ISP_ADDR_CAMINF CAMINF_BASE
146 #define ISP_REG_ADDR_EN1 (ISP_ADDR + 0x4)
147 #define ISP_REG_ADDR_INT_STATUS (ISP_ADDR + 0x24)
148 #define ISP_REG_ADDR_DMA_INT (ISP_ADDR + 0x28)
149 #define ISP_REG_ADDR_INTB_STATUS (ISP_ADDR + 0x30)
150 #define ISP_REG_ADDR_DMAB_INT (ISP_ADDR + 0x34)
151 #define ISP_REG_ADDR_INTC_STATUS (ISP_ADDR + 0x3C)
152 #define ISP_REG_ADDR_DMAC_INT (ISP_ADDR + 0x40)
153 #define ISP_REG_ADDR_INT_STATUSX (ISP_ADDR + 0x44)
154 #define ISP_REG_ADDR_DMA_INTX (ISP_ADDR + 0x48)
155 #define ISP_REG_ADDR_SW_CTL (ISP_ADDR + 0x5C)
156 #define ISP_REG_ADDR_CQ0C_BASE_ARRR (ISP_ADDR + 0xBC)
157 #define ISP_REG_ADDR_IMGO_FBC (ISP_ADDR + 0xF4)
158 #define ISP_REG_ADDR_IMG2O_FBC (ISP_ADDR + 0xF8)
159 #define ISP_REG_ADDR_IMGO_BASE_ADDR (ISP_ADDR + 0x300)
160 #define ISP_REG_ADDR_IMG2O_BASE_ADDR (ISP_ADDR + 0x320)
161 #define ISP_REG_ADDR_TG_VF_CON (ISP_ADDR + 0x414)
162 #define ISP_REG_ADDR_CTL_DBG_SET (ISP_ADDR + 0x160)
163 #define ISP_REG_ADDR_CTL_DBG_PORT (ISP_ADDR + 0x164)
164 #define ISP_REG_ADDR_CTL_EN2 (ISP_ADDR + 0x008)
165 #define ISP_REG_ADDR_CTL_CROP_X (ISP_ADDR + 0x110)
166
167 #define ISP_REG_ADDR_CTL_DBG_SET_CQ_STS (0x6000)
168
169 #define ISP_REG_ADDR_CTL_DBG_SET_IMGI_STS (0x9003)
170 #define ISP_REG_ADDR_CTL_DBG_SET_IMGI_SYNC (0x9004)
171 #define ISP_REG_ADDR_CTL_DBG_SET_IMGI_NO_SYNC (0x9005)
172
173 #define ISP_REG_ADDR_CTL_DBG_SET_CFA_STS (0x9006)
174 #define ISP_REG_ADDR_CTL_DBG_SET_CFA_SYNC (0x9007)
175 #define ISP_REG_ADDR_CTL_DBG_SET_CFA_NO_SYNC (0x9008)
176
177 #define ISP_REG_ADDR_CTL_DBG_SET_YUV_STS (0x9009)
178 #define ISP_REG_ADDR_CTL_DBG_SET_YUV_SYNC (0x900a)
179 #define ISP_REG_ADDR_CTL_DBG_SET_YUV_NO_SYNC (0x900b)
180
181 #define ISP_REG_ADDR_CTL_DBG_SET_OUT_STS (0x900c)
182 #define ISP_REG_ADDR_CTL_DBG_SET_OUT_SYNC (0x900d)
183 #define ISP_REG_ADDR_CTL_DBG_SET_OUT_NO_SYNC (0x900e)
184
185 #define ISP_REG_ADDR_CTL_EN2_UV_CRSA_EN_BIT (1<<23)
186 #define ISP_REG_ADDR_CTL_CROP_X_MDP_CROP_EN_BIT (1<<15)
187
188 //#define ISP_REG_ADDR_TG2_VF_CON (ISP_ADDR + 0x4B4)
189
190
191 #define ISP_TPIPE_ADDR (0x15004000)
192
193 //====== CAM_CTL_SW_CTL ======
194
195 #define ISP_REG_SW_CTL_SW_RST_TRIG (0x00000001)
196 #define ISP_REG_SW_CTL_SW_RST_STATUS (0x00000002)
197 #define ISP_REG_SW_CTL_HW_RST (0x00000004)
198
199 //====== CAM_CTL_INT_STATUS ======
200
201 //IRQ Mask
202 #define ISP_REG_MASK_INT_STATUS (ISP_IRQ_INT_STATUS_VS1_ST |\
203 ISP_IRQ_INT_STATUS_TG1_ST1 |\
204 ISP_IRQ_INT_STATUS_TG1_ST2 |\
205 ISP_IRQ_INT_STATUS_EXPDON1_ST |\
206 ISP_IRQ_INT_STATUS_PASS1_TG1_DON_ST |\
207 ISP_IRQ_INT_STATUS_SOF1_INT_ST |\
208 ISP_IRQ_INT_STATUS_PASS2_DON_ST |\
209 ISP_IRQ_INT_STATUS_TPIPE_DON_ST |\
210 ISP_IRQ_INT_STATUS_AF_DON_ST |\
211 ISP_IRQ_INT_STATUS_FLK_DON_ST |\
212 ISP_IRQ_INT_STATUS_CQ_DON_ST)
213 //IRQ Error Mask
214 #define ISP_REG_MASK_INT_STATUS_ERR (ISP_IRQ_INT_STATUS_TG1_ERR_ST |\
215 ISP_IRQ_INT_STATUS_CQ_ERR_ST |\
216 ISP_IRQ_INT_STATUS_IMGO_ERR_ST |\
217 ISP_IRQ_INT_STATUS_AAO_ERR_ST |\
218 ISP_IRQ_INT_STATUS_IMG2O_ERR_ST |\
219 ISP_IRQ_INT_STATUS_ESFKO_ERR_ST |\
220 ISP_IRQ_INT_STATUS_FLK_ERR_ST |\
221 ISP_IRQ_INT_STATUS_LSC_ERR_ST |\
222 ISP_IRQ_INT_STATUS_LSC2_ERR_ST |\
223 ISP_IRQ_INT_STATUS_BPC_ERR_ST |\
224 ISP_IRQ_INT_STATUS_DMA_ERR_ST)
225 //====== CAM_CTL_DMA_INT ======
226
227 //IRQ Mask
228 #define ISP_REG_MASK_DMA_INT ( ISP_IRQ_DMA_INT_IMGO_DONE_ST |\
229 ISP_IRQ_DMA_INT_IMG2O_DONE_ST |\
230 ISP_IRQ_DMA_INT_AAO_DONE_ST |\
231 ISP_IRQ_DMA_INT_ESFKO_DONE_ST)
232 //IRQ Error Mask
233 #define ISP_REG_MASK_DMA_INT_ERR (ISP_IRQ_DMA_INT_CQ0_ERR_ST |\
234 ISP_IRQ_DMA_INT_TG1_GBERR_ST )
235
236 //====== CAM_CTL_INTB_STATUS ======
237
238 //IRQ Mask
239 #define ISP_REG_MASK_INTB_STATUS (ISP_IRQ_INTB_STATUS_PASS2_DON_ST |\
240 ISP_IRQ_INTB_STATUS_TPIPE_DON_ST |\
241 ISP_IRQ_INTB_STATUS_CQ_DON_ST)
242 //IRQ Error Mask
243 #define ISP_REG_MASK_INTB_STATUS_ERR (ISP_IRQ_INTB_STATUS_CQ_ERR_ST |\
244 ISP_IRQ_INTB_STATUS_IMGO_ERR_ST |\
245 ISP_IRQ_INTB_STATUS_LCSO_ERR_ST |\
246 ISP_IRQ_INTB_STATUS_IMG2O_ERR_ST |\
247 ISP_IRQ_INTB_STATUS_LSC_ERR_ST |\
248 ISP_IRQ_INTB_STATUS_LCE_ERR_ST |\
249 ISP_IRQ_INTB_STATUS_DMA_ERR_ST)
250 //CAM_CTL_DMAB_INT
251 //IRQ Mask
252 #define ISP_REG_MASK_DMAB_INT (ISP_IRQ_DMAB_INT_IMGO_DONE_ST |\
253 ISP_IRQ_DMAB_INT_IMG2O_DONE_ST |\
254 ISP_IRQ_DMAB_INT_AAO_DONE_ST |\
255 ISP_IRQ_DMAB_INT_LCSO_DONE_ST |\
256 ISP_IRQ_DMAB_INT_ESFKO_DONE_ST |\
257 ISP_IRQ_DMAB_INT_DISPO_DONE_ST |\
258 ISP_IRQ_DMAB_INT_VIDO_DONE_ST )
259 //IRQ Error Mask
260 #define ISP_REG_MASK_DMAB_INT_ERR //( ISP_IRQ_DMAB_INT_NR3O_ERR_ST)
261
262 //====== CAM_CTL_INTC_STATUS ======
263
264 //IRQ Mask
265 #define ISP_REG_MASK_INTC_STATUS (ISP_IRQ_INTC_STATUS_PASS2_DON_ST |\
266 ISP_IRQ_INTC_STATUS_TPIPE_DON_ST |\
267 ISP_IRQ_INTC_STATUS_CQ_DON_ST)
268 //IRQ Error Mask
269 #define ISP_REG_MASK_INTC_STATUS_ERR (ISP_IRQ_INTC_STATUS_CQ_ERR_ST |\
270 ISP_IRQ_INTC_STATUS_IMGO_ERR_ST |\
271 ISP_IRQ_INTC_STATUS_LCSO_ERR_ST |\
272 ISP_IRQ_INTC_STATUS_IMG2O_ERR_ST |\
273 ISP_IRQ_INTC_STATUS_LSC_ERR_ST |\
274 ISP_IRQ_INTC_STATUS_BPC_ERR_ST |\
275 ISP_IRQ_INTC_STATUS_LCE_ERR_ST |\
276 ISP_IRQ_INTC_STATUS_DMA_ERR_ST)
277 //====== CAM_CTL_DMAC_INT ======
278
279 //IRQ Mask
280 #define ISP_REG_MASK_DMAC_INT ( ISP_IRQ_DMAC_INT_IMGO_DONE_ST |\
281 ISP_IRQ_DMAC_INT_IMG2O_DONE_ST |\
282 ISP_IRQ_DMAC_INT_AAO_DONE_ST |\
283 ISP_IRQ_DMAC_INT_LCSO_DONE_ST |\
284 ISP_IRQ_DMAC_INT_ESFKO_DONE_ST |\
285 ISP_IRQ_DMAC_INT_DISPO_DONE_ST |\
286 ISP_IRQ_DMAC_INT_VIDO_DONE_ST )
287 //IRQ Error Mask
288 #define ISP_REG_MASK_DMAC_INT_ERR //( ISP_IRQ_DMAC_INT_NR3O_ERR_ST)
289
290 //====== CAM_CTL_INT_STATUSX ======
291
292 //IRQ Mask
293 #define ISP_REG_MASK_INTX_STATUS (ISP_IRQ_INTX_STATUS_VS1_ST |\
294 ISP_IRQ_INTX_STATUS_TG1_ST1 |\
295 ISP_IRQ_INTX_STATUS_TG1_ST2 |\
296 ISP_IRQ_INTX_STATUS_EXPDON1_ST |\
297 ISP_IRQ_INTX_STATUS_VS2_ST |\
298 ISP_IRQ_INTX_STATUS_TG2_ST1 |\
299 ISP_IRQ_INTX_STATUS_TG2_ST2 |\
300 ISP_IRQ_INTX_STATUS_EXPDON2_ST |\
301 ISP_IRQ_INTX_STATUS_PASS1_TG1_DON_ST |\
302 ISP_IRQ_INTX_STATUS_PASS1_TG2_DON_ST |\
303 ISP_IRQ_INTX_STATUS_PASS2_DON_ST |\
304 ISP_IRQ_INTX_STATUS_TPIPE_DON_ST |\
305 ISP_IRQ_INTX_STATUS_AF_DON_ST |\
306 ISP_IRQ_INTX_STATUS_FLK_DON_ST |\
307 ISP_IRQ_INTX_STATUS_FMT_DON_ST |\
308 ISP_IRQ_INTX_STATUS_CQ_DON_ST)
309 //IRQ Error Mask
310 #define ISP_REG_MASK_INTX_STATUS_ERR (ISP_IRQ_INTX_STATUS_TG1_ERR_ST |\
311 ISP_IRQ_INTX_STATUS_TG2_ERR_ST |\
312 ISP_IRQ_INTX_STATUS_CQ_ERR_ST |\
313 ISP_IRQ_INTX_STATUS_IMGO_ERR_ST |\
314 ISP_IRQ_INTX_STATUS_AAO_ERR_ST |\
315 ISP_IRQ_INTX_STATUS_LCSO_ERR_ST |\
316 ISP_IRQ_INTX_STATUS_LCSO_ERR_ST |\
317 ISP_IRQ_INTX_STATUS_ESFKO_ERR_ST |\
318 ISP_IRQ_INTX_STATUS_FLK_ERR_ST |\
319 ISP_IRQ_INTX_STATUS_LSC_ERR_ST |\
320 ISP_IRQ_INTX_STATUS_LCE_ERR_ST |\
321 ISP_IRQ_INTX_STATUS_DMA_ERR_ST)
322 // ISP_IRQ_INTX_STATUS_BPC_ERR_ST //Vent@20121025: Remove ISP_IRQ_INTX_STATUS_BPC_ERR_ST. From TH Wu's explanation, this bit is not used as an error state anymore.
323
324
325 //====== CAM_CTL_DMA_INTX ======
326
327 //IRQ Mask
328 #define ISP_REG_MASK_DMAX_INT (ISP_IRQ_DMAX_INT_IMGO_DONE_ST |\
329 ISP_IRQ_DMAX_INT_IMG2O_DONE_ST |\
330 ISP_IRQ_DMAX_INT_AAO_DONE_ST |\
331 ISP_IRQ_DMAX_INT_LCSO_DONE_ST |\
332 ISP_IRQ_DMAX_INT_ESFKO_DONE_ST |\
333 ISP_IRQ_DMAX_INT_DISPO_DONE_ST |\
334 ISP_IRQ_DMAX_INT_VIDO_DONE_ST |\
335 ISP_IRQ_DMAX_INT_VRZO_DONE_ST |\
336 ISP_IRQ_DMAX_INT_NR3O_DONE_ST |\
337 ISP_IRQ_DMAX_INT_BUF_OVL_ST)
338 //IRQ Error Mask
339 #define ISP_REG_MASK_DMAX_INT_ERR (ISP_IRQ_DMAX_INT_NR3O_ERR_ST |\
340 ISP_IRQ_DMAX_INT_CQ_ERR_ST |\
341 ISP_IRQ_DMAX_INT_TG1_GBERR_ST |\
342 ISP_IRQ_DMAX_INT_TG2_GBERR_ST)
343
344 /*******************************************************************************
345 * struct & enum
346 ********************************************************************************/
347
348 #define ISP_BUF_SIZE (4096)
349 #define ISP_BUF_SIZE_WRITE 1024
350 #define ISP_BUF_WRITE_AMOUNT 6
351
352 typedef enum
353 {
354 ISP_BUF_STATUS_EMPTY,
355 ISP_BUF_STATUS_HOLD,
356 ISP_BUF_STATUS_READY
357 }ISP_BUF_STATUS_ENUM;
358
359 typedef struct
360 {
361 pid_t Pid;
362 pid_t Tid;
363 }ISP_USER_INFO_STRUCT;
364
365 typedef struct
366 {
367 volatile ISP_BUF_STATUS_ENUM Status;
368 volatile MUINT32 Size;
369 MUINT8* pData;
370 }ISP_BUF_STRUCT;
371
372 typedef struct
373 {
374 ISP_BUF_STRUCT Read;
375 ISP_BUF_STRUCT Write[ISP_BUF_WRITE_AMOUNT];
376 }ISP_BUF_INFO_STRUCT;
377
378 typedef struct
379 {
380 atomic_t HoldEnable;
381 atomic_t WriteEnable;
382 ISP_HOLD_TIME_ENUM Time;
383 }ISP_HOLD_INFO_STRUCT;
384
385 typedef struct
386 {
387 MUINT32 Status[ISP_IRQ_TYPE_AMOUNT];
388 MUINT32 Mask[ISP_IRQ_TYPE_AMOUNT];
389 MUINT32 ErrMask[ISP_IRQ_TYPE_AMOUNT];
390 }ISP_IRQ_INFO_STRUCT;
391
392 typedef struct
393 {
394 MUINT32 Vd;
395 MUINT32 Expdone;
396 MUINT32 WorkQueueVd;
397 MUINT32 WorkQueueExpdone;
398 MUINT32 WorkQueueSeninf;
399 MUINT32 TaskletVd;
400 MUINT32 TaskletExpdone;
401 MUINT32 TaskletSeninf;
402 }ISP_TIME_LOG_STRUCT;
403
404 typedef struct
405 {
406 spinlock_t SpinLockIspRef;
407 spinlock_t SpinLockIsp;
408 spinlock_t SpinLockIrq;
409 spinlock_t SpinLockHold;
410 spinlock_t SpinLockRTBC;
411 wait_queue_head_t WaitQueueHead;
412 struct work_struct ScheduleWorkVD;
413 struct work_struct ScheduleWorkEXPDONE;
414 struct work_struct ScheduleWorkSENINF;
415 MUINT32 UserCount;
416 MUINT32 DebugMask;
417 MINT32 IrqNum;
418 ISP_IRQ_INFO_STRUCT IrqInfo;
419 ISP_HOLD_INFO_STRUCT HoldInfo;
420 ISP_BUF_INFO_STRUCT BufInfo;
421 ISP_TIME_LOG_STRUCT TimeLog;
422 ISP_CALLBACK_STRUCT Callback[ISP_CALLBACK_AMOUNT];
423 }ISP_INFO_STRUCT;
424
425 /*******************************************************************************
426 * internal global data
427 ********************************************************************************/
428
429 // pointer to the kmalloc'd area, rounded up to a page boundary
430 static MINT32 *g_pTbl_RTBuf = NULL;
431
432 // original pointer for kmalloc'd area as returned by kmalloc
433 static MVOID *g_pBuf_kmalloc = NULL;
434
435 static ISP_RT_BUF_STRUCT *g_pstRTBuf = NULL;
436
437 static ISP_INFO_STRUCT g_IspInfo;
438
439 static atomic_t g_imem_ref_cnt[ISP_REF_CNT_ID_MAX];
440
441 MUINT32 g_EnableClkCnt = 0;
442 volatile MUINT32 g_TempAddr = 0;
443
444 //static ISP_DEQUE_BUF_INFO_STRUCT g_deque_buf = {0,{}}; // Marked to remove build warning.WARNING
445
446 unsigned long g_Flash_SpinLock;
447
448 #ifndef _rtbc_use_cq0c_
449 static MUINT32 g_rtbcAAA = 0;
450 static MUINT32 g_EnqBuf = 0;
451 static MUINT32 g_DeqBuf = 0;
452 static MINT32 g_rtbc_enq_dma = _rt_dma_max_;
453 static MINT32 g_rtbc_deq_dma = _rt_dma_max_;
454 #endif
455
456 static ISP_RT_BUF_INFO_STRUCT g_rt_buf_info;
457 static ISP_RT_BUF_INFO_STRUCT g_ex_rt_buf_info;
458 static ISP_DEQUE_BUF_INFO_STRUCT g_deque_buf;
459
460 static MUINT32 g_prv_tstamp_s = 0;
461 static MUINT32 g_prv_tstamp_us = 0;
462
463 static MUINT32 g_sof_count = 0;
464 static MUINT32 g_start_time = 0;
465 static MUINT32 g_avg_frame_time = 0;
466
467 //allan
468 static MINT32 g_sof_pass1done = 0;
469
470 static dev_t g_IspDevNo;
471 static struct cdev *g_pIspCharDrv = NULL;
472 static struct class *g_pIspClass = NULL;
473
474 static MINT32 g_bPass1_On_In_Resume_TG1 = 0;
475
476 #define DEFAULT_PA 0x3773
477
478 static volatile MUINT32 g_oldImgoAddr = DEFAULT_PA;
479 static volatile MUINT32 g_newImgoAddr = DEFAULT_PA;
480 static volatile MUINT32 g_oldImg2oAddr = DEFAULT_PA;
481 static volatile MUINT32 g_newImg2oAddr = DEFAULT_PA;
482
483 typedef struct
484 {
485 MUINT32 regVal_1;
486 MUINT32 regVal_2;
487 }SENINF_DEBUG;
488
489 static SENINF_DEBUG g_seninfDebug[30];
490
491 /*******************************************************************************
492 *
493 ********************************************************************************/
494
495 //test flag
496 #define ISP_KERNEL_MOTIFY_SINGAL_TEST
497 #ifdef ISP_KERNEL_MOTIFY_SINGAL_TEST
498 /*** Linux signal test ***/
499 #include <linux/module.h>
500 #include <linux/kernel.h>
501 #include <linux/init.h>
502 #include <asm/siginfo.h> //siginfo
503 #include <linux/rcupdate.h> //rcu_read_lock
504 #include <linux/sched.h> //find_task_by_pid_type
505 #include <linux/debugfs.h>
506 #include <linux/uaccess.h>
507
508 //js_test
509 #define __tcmfunc
510
511
512 #define SIG_TEST 44 // we choose 44 as our signal number (real-time signals are in the range of 33 to 64)
513
514 struct siginfo info;
515 struct task_struct *t;
516
517
518 int getTaskInfo( pid_t pid )
519 {
520 /* send the signal */
521 memset(&info, 0, sizeof(struct siginfo));
522 info.si_signo = SIG_TEST;
523 info.si_code = SI_QUEUE; // this is bit of a trickery: SI_QUEUE is normally used by sigqueue from user space,
524 // and kernel space should use SI_KERNEL. But if SI_KERNEL is used the real_time data
525 // is not delivered to the user space signal handler function.
526 info.si_int = 1234; // real time signals may have 32 bits of data.
527
528 rcu_read_lock();
529
530 t = find_task_by_vpid(pid);
531 //t = find_task_by_pid_type(PIDTYPE_PID, g_pid); //find the task_struct associated with this pid
532 if(t == NULL){
533 LOG_DBG("no such pid");
534 rcu_read_unlock();
535 return -ENODEV;
536 }
537 rcu_read_unlock();
538
539 return 0;
540 }
541
542 int sendSignal( void )
543 {
544 int ret = 0;
545 ret = send_sig_info(SIG_TEST, &info, t); //send the signal
546 if (ret < 0) {
547 LOG_DBG("error sending signal");
548 return ret;
549 }
550
551 return ret;
552 }
553
554 /*** Linux signal test ***/
555
556 #endif // ISP_KERNEL_MOTIFY_SINGAL_TEST
557
558 /*******************************************************************************
559 * transfer ms to jiffies
560 ********************************************************************************/
561 static __inline MUINT32 ISP_MsToJiffies(MUINT32 Ms)
562 {
563 return ((Ms * HZ + 512) >> 10);
564 }
565
566 /*******************************************************************************
567 * transfer jiffies to ms
568 ********************************************************************************/
569 static __inline MUINT32 ISP_JiffiesToMs(MUINT32 Jiffies)
570 {
571 return ((Jiffies*1000)/HZ);
572 }
573
574 /*******************************************************************************
575 *
576 ********************************************************************************/
577 static __inline MUINT32 ISP_GetIRQState(MUINT32 type, MUINT32 stus)
578 {
579 MUINT32 ret;
580 unsigned long flags;
581
582 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
583 ret = (g_IspInfo.IrqInfo.Status[type] & stus);
584 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
585
586 return ret;
587 }
588
589 /*******************************************************************************
590 * get kernel time
591 ********************************************************************************/
592 static void ISP_GetTime(MUINT32 *pSec, MUINT32 *pUSec)
593 {
594 ktime_t Time;
595 MUINT64 TimeSec;
596
597 Time = ktime_get(); //ns
598 TimeSec = Time.tv64;
599 do_div( TimeSec, 1000 );
600 *pUSec = do_div( TimeSec, 1000000);
601 *pSec = (MUINT64)TimeSec;
602 }
603
604 /*******************************************************************************
605 *
606 ********************************************************************************/
607 static MINT32 ISP_DumpReg(MVOID)
608 {
609 MINT32 Ret = 0;
610 MINT32 i;
611
612 LOG_DBG("+");
613
614 //spin_lock_irqsave(&(g_IspInfo.SpinLock), flags);
615
616 //tile tool parse range
617 //Joseph Hung (xa)#define ISP_ADDR_START 0x15004000
618 // #define ISP_ADDR_END 0x15006000
619 //
620
621 #if 0 //kk test 0:new tile format
622 for(i = 0x0; i <= 0x20; i += 4)
623 {
624 //LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32(ISP_ADDR + i));
625 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32(ISP_ADDR + i));
626 }
627 //ignore read clear registers
628 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x24, 0);
629 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x28, 0);
630 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x2C, ISP_RD32(ISP_ADDR + 0x2C));
631 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x30, 0);
632 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x34, 0);
633 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x38, ISP_RD32(ISP_ADDR + 0x38));
634 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x3C, 0);
635 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x40, 0);
636 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x44, 0);
637 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x48, 0);
638 for(i = 0x4C; i <= 0x5048; i += 4)
639 {
640 //LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32(ISP_ADDR + i));
641 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32(ISP_ADDR + i));
642 }
643 #else
644
645 // for tpipe main start
646 LOG_DBG("start MT");
647 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x000, ISP_RD32((void *)(ISP_ADDR + 0x000)));
648 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x004, ISP_RD32((void *)(ISP_ADDR + 0x004)));
649 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x008, ISP_RD32((void *)(ISP_ADDR + 0x008)));
650 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x00C, ISP_RD32((void *)(ISP_ADDR + 0x00C)));
651 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x010, ISP_RD32((void *)(ISP_ADDR + 0x010)));
652 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x018, ISP_RD32((void *)(ISP_ADDR + 0x018)));
653 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x01C, ISP_RD32((void *)(ISP_ADDR + 0x01C)));
654 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x020, ISP_RD32((void *)(ISP_ADDR + 0x020)));
655
656 #if 1 //it may touch ReadClear register
657 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x024, ISP_RD32((void *)(ISP_ADDR + 0x024)));
658 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x028, ISP_RD32((void *)(ISP_ADDR + 0x028)));
659 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x02C, ISP_RD32((void *)(ISP_ADDR + 0x02C)));
660 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x030, ISP_RD32((void *)(ISP_ADDR + 0x030)));
661 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x034, ISP_RD32((void *)(ISP_ADDR + 0x034)));
662 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x038, ISP_RD32((void *)(ISP_ADDR + 0x038)));
663 #else
664 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x024, 0);
665 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x028, 0);
666 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x02C, 0);
667 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x030, 0);
668 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x034, 0);
669 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x038, 0);
670 #endif
671
672 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x050, ISP_RD32((void *)(ISP_ADDR + 0x050)));
673 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x074, ISP_RD32((void *)(ISP_ADDR + 0x074)));
674 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x078, ISP_RD32((void *)(ISP_ADDR + 0x078)));
675 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x07C, ISP_RD32((void *)(ISP_ADDR + 0x07C)));
676 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x080, ISP_RD32((void *)(ISP_ADDR + 0x080)));
677 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x084, ISP_RD32((void *)(ISP_ADDR + 0x084)));
678 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x088, ISP_RD32((void *)(ISP_ADDR + 0x088)));
679 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x08C, ISP_RD32((void *)(ISP_ADDR + 0x08C)));
680 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x090, ISP_RD32((void *)(ISP_ADDR + 0x090)));
681 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x094, ISP_RD32((void *)(ISP_ADDR + 0x094)));
682 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x0A8, ISP_RD32((void *)(ISP_ADDR + 0x0A8)));
683 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x0AC, ISP_RD32((void *)(ISP_ADDR + 0x0AC)));
684 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x0B0, ISP_RD32((void *)(ISP_ADDR + 0x0B0)));
685 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x0B4, ISP_RD32((void *)(ISP_ADDR + 0x0B4)));
686 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x0E8, ISP_RD32((void *)(ISP_ADDR + 0x0E8)));
687 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x138, ISP_RD32((void *)(ISP_ADDR + 0x138)));
688 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x13C, ISP_RD32((void *)(ISP_ADDR + 0x13C)));
689 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x144, ISP_RD32((void *)(ISP_ADDR + 0x144)));
690 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x148, ISP_RD32((void *)(ISP_ADDR + 0x148)));
691 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x14C, ISP_RD32((void *)(ISP_ADDR + 0x14C)));
692 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x204, ISP_RD32((void *)(ISP_ADDR + 0x204)));
693 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x20C, ISP_RD32((void *)(ISP_ADDR + 0x20C)));
694 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x22C, ISP_RD32((void *)(ISP_ADDR + 0x22C)));
695 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x230, ISP_RD32((void *)(ISP_ADDR + 0x230)));
696 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x234, ISP_RD32((void *)(ISP_ADDR + 0x234)));
697 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x238, ISP_RD32((void *)(ISP_ADDR + 0x238)));
698 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x23C, ISP_RD32((void *)(ISP_ADDR + 0x23C)));
699 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x240, ISP_RD32((void *)(ISP_ADDR + 0x240)));
700 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x244, ISP_RD32((void *)(ISP_ADDR + 0x244)));
701 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x258, ISP_RD32((void *)(ISP_ADDR + 0x258)));
702 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x260, ISP_RD32((void *)(ISP_ADDR + 0x260)));
703 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x26C, ISP_RD32((void *)(ISP_ADDR + 0x26C)));
704 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x270, ISP_RD32((void *)(ISP_ADDR + 0x270)));
705 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x27C, ISP_RD32((void *)(ISP_ADDR + 0x27C)));
706 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x298, ISP_RD32((void *)(ISP_ADDR + 0x298)));
707 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x2B4, ISP_RD32((void *)(ISP_ADDR + 0x2B4)));
708 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x2D0, ISP_RD32((void *)(ISP_ADDR + 0x2D0)));
709 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x2D4, ISP_RD32((void *)(ISP_ADDR + 0x2D4)));
710 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x2F0, ISP_RD32((void *)(ISP_ADDR + 0x2F0)));
711 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x2F4, ISP_RD32((void *)(ISP_ADDR + 0x2F4)));
712 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x300, ISP_RD32((void *)(ISP_ADDR + 0x300)));
713 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x304, ISP_RD32((void *)(ISP_ADDR + 0x304)));
714 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x308, ISP_RD32((void *)(ISP_ADDR + 0x308)));
715 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x30C, ISP_RD32((void *)(ISP_ADDR + 0x30C)));
716 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x310, ISP_RD32((void *)(ISP_ADDR + 0x310)));
717 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x314, ISP_RD32((void *)(ISP_ADDR + 0x314)));
718 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x318, ISP_RD32((void *)(ISP_ADDR + 0x318)));
719 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x31C, ISP_RD32((void *)(ISP_ADDR + 0x31C)));
720 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x328, ISP_RD32((void *)(ISP_ADDR + 0x328)));
721 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x32C, ISP_RD32((void *)(ISP_ADDR + 0x32C)));
722 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x330, ISP_RD32((void *)(ISP_ADDR + 0x330)));
723 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x334, ISP_RD32((void *)(ISP_ADDR + 0x334)));
724 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x338, ISP_RD32((void *)(ISP_ADDR + 0x338)));
725 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x33C, ISP_RD32((void *)(ISP_ADDR + 0x33C)));
726 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x350, ISP_RD32((void *)(ISP_ADDR + 0x350)));
727 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x37C, ISP_RD32((void *)(ISP_ADDR + 0x37C)));
728 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x398, ISP_RD32((void *)(ISP_ADDR + 0x398)));
729 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x410, ISP_RD32((void *)(ISP_ADDR + 0x410)));
730 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x414, ISP_RD32((void *)(ISP_ADDR + 0x414)));
731 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x418, ISP_RD32((void *)(ISP_ADDR + 0x418)));
732 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x41C, ISP_RD32((void *)(ISP_ADDR + 0x41C)));
733 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x420, ISP_RD32((void *)(ISP_ADDR + 0x420)));
734 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x448, ISP_RD32((void *)(ISP_ADDR + 0x448)));
735 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4B0, ISP_RD32((void *)(ISP_ADDR + 0x4B0)));
736 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4B4, ISP_RD32((void *)(ISP_ADDR + 0x4B4)));
737 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4B8, ISP_RD32((void *)(ISP_ADDR + 0x4B8)));
738 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4BC, ISP_RD32((void *)(ISP_ADDR + 0x4BC)));
739 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4E8, ISP_RD32((void *)(ISP_ADDR + 0x4E8)));
740 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x534, ISP_RD32((void *)(ISP_ADDR + 0x534)));
741 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x538, ISP_RD32((void *)(ISP_ADDR + 0x538)));
742 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x53C, ISP_RD32((void *)(ISP_ADDR + 0x53C)));
743 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x580, ISP_RD32((void *)(ISP_ADDR + 0x580)));
744 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x584, ISP_RD32((void *)(ISP_ADDR + 0x584)));
745 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x800, ISP_RD32((void *)(ISP_ADDR + 0x800)));
746 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x880, ISP_RD32((void *)(ISP_ADDR + 0x880)));
747 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x884, ISP_RD32((void *)(ISP_ADDR + 0x884)));
748 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x888, ISP_RD32((void *)(ISP_ADDR + 0x888)));
749 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x8A0, ISP_RD32((void *)(ISP_ADDR + 0x8A0)));
750 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x920, ISP_RD32((void *)(ISP_ADDR + 0x920)));
751 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x924, ISP_RD32((void *)(ISP_ADDR + 0x924)));
752 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x928, ISP_RD32((void *)(ISP_ADDR + 0x928)));
753 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x92C, ISP_RD32((void *)(ISP_ADDR + 0x92C)));
754 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x930, ISP_RD32((void *)(ISP_ADDR + 0x930)));
755 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x934, ISP_RD32((void *)(ISP_ADDR + 0x934)));
756 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x938, ISP_RD32((void *)(ISP_ADDR + 0x938)));
757 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x93C, ISP_RD32((void *)(ISP_ADDR + 0x93C)));
758 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x960, ISP_RD32((void *)(ISP_ADDR + 0x960)));
759 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x9C4, ISP_RD32((void *)(ISP_ADDR + 0x9C4)));
760 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x9E4, ISP_RD32((void *)(ISP_ADDR + 0x9E4)));
761 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x9E8, ISP_RD32((void *)(ISP_ADDR + 0x9E8)));
762 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x9EC, ISP_RD32((void *)(ISP_ADDR + 0x9EC)));
763 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xA00, ISP_RD32((void *)(ISP_ADDR + 0xA00)));
764 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xA04, ISP_RD32((void *)(ISP_ADDR + 0xA04)));
765 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xA08, ISP_RD32((void *)(ISP_ADDR + 0xA08)));
766 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xA0C, ISP_RD32((void *)(ISP_ADDR + 0xA0C)));
767 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xA10, ISP_RD32((void *)(ISP_ADDR + 0xA10)));
768 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xA14, ISP_RD32((void *)(ISP_ADDR + 0xA14)));
769 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xA20, ISP_RD32((void *)(ISP_ADDR + 0xA20)));
770 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xAA0, ISP_RD32((void *)(ISP_ADDR + 0xAA0)));
771 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xACC, ISP_RD32((void *)(ISP_ADDR + 0xACC)));
772 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB00, ISP_RD32((void *)(ISP_ADDR + 0xB00)));
773 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB04, ISP_RD32((void *)(ISP_ADDR + 0xB04)));
774 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB08, ISP_RD32((void *)(ISP_ADDR + 0xB08)));
775 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB0C, ISP_RD32((void *)(ISP_ADDR + 0xB0C)));
776 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB10, ISP_RD32((void *)(ISP_ADDR + 0xB10)));
777 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB14, ISP_RD32((void *)(ISP_ADDR + 0xB14)));
778 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB18, ISP_RD32((void *)(ISP_ADDR + 0xB18)));
779 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB1C, ISP_RD32((void *)(ISP_ADDR + 0xB1C)));
780 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB20, ISP_RD32((void *)(ISP_ADDR + 0xB20)));
781 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB44, ISP_RD32((void *)(ISP_ADDR + 0xB44)));
782 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB48, ISP_RD32((void *)(ISP_ADDR + 0xB48)));
783 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB4C, ISP_RD32((void *)(ISP_ADDR + 0xB4C)));
784 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB50, ISP_RD32((void *)(ISP_ADDR + 0xB50)));
785 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB54, ISP_RD32((void *)(ISP_ADDR + 0xB54)));
786 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB58, ISP_RD32((void *)(ISP_ADDR + 0xB58)));
787 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB5C, ISP_RD32((void *)(ISP_ADDR + 0xB5C)));
788 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xB60, ISP_RD32((void *)(ISP_ADDR + 0xB60)));
789 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBA0, ISP_RD32((void *)(ISP_ADDR + 0xBA0)));
790 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBA4, ISP_RD32((void *)(ISP_ADDR + 0xBA4)));
791 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBA8, ISP_RD32((void *)(ISP_ADDR + 0xBA8)));
792 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBAC, ISP_RD32((void *)(ISP_ADDR + 0xBAC)));
793 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBB0, ISP_RD32((void *)(ISP_ADDR + 0xBB0)));
794 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBB4, ISP_RD32((void *)(ISP_ADDR + 0xBB4)));
795 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBB8, ISP_RD32((void *)(ISP_ADDR + 0xBB8)));
796 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBBC, ISP_RD32((void *)(ISP_ADDR + 0xBBC)));
797 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xBC0, ISP_RD32((void *)(ISP_ADDR + 0xBC0)));
798 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xC20, ISP_RD32((void *)(ISP_ADDR + 0xC20)));
799 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCC0, ISP_RD32((void *)(ISP_ADDR + 0xCC0)));
800 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCE4, ISP_RD32((void *)(ISP_ADDR + 0xCE4)));
801 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCE8, ISP_RD32((void *)(ISP_ADDR + 0xCE8)));
802 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCEC, ISP_RD32((void *)(ISP_ADDR + 0xCEC)));
803 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCF0, ISP_RD32((void *)(ISP_ADDR + 0xCF0)));
804 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCF4, ISP_RD32((void *)(ISP_ADDR + 0xCF4)));
805 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCF8, ISP_RD32((void *)(ISP_ADDR + 0xCF8)));
806 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xCFC, ISP_RD32((void *)(ISP_ADDR + 0xCFC)));
807 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD24, ISP_RD32((void *)(ISP_ADDR + 0xD24)));
808 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD28, ISP_RD32((void *)(ISP_ADDR + 0xD28)));
809 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD2C, ISP_RD32((void *)(ISP_ADDR + 0xD2c)));
810 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD40, ISP_RD32((void *)(ISP_ADDR + 0xD40)));
811 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD64, ISP_RD32((void *)(ISP_ADDR + 0xD64)));
812 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD68, ISP_RD32((void *)(ISP_ADDR + 0xD68)));
813 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD6C, ISP_RD32((void *)(ISP_ADDR + 0xD6c)));
814 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD70, ISP_RD32((void *)(ISP_ADDR + 0xD70)));
815 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD74, ISP_RD32((void *)(ISP_ADDR + 0xD74)));
816 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD78, ISP_RD32((void *)(ISP_ADDR + 0xD78)));
817 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xD7C, ISP_RD32((void *)(ISP_ADDR + 0xD7C)));
818 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xDA4, ISP_RD32((void *)(ISP_ADDR + 0xDA4)));
819 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xDA8, ISP_RD32((void *)(ISP_ADDR + 0xDA8)));
820 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0xDAC, ISP_RD32((void *)(ISP_ADDR + 0xDAC)));
821 ISP_WR32((void *)(ISP_ADDR + 0x4618), 0x0000FFFF);
822 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4010, ISP_RD32((void *)(ISP_ADDR + 0x4010)));
823 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4014, ISP_RD32((void *)(ISP_ADDR + 0x4014)));
824 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4018, ISP_RD32((void *)(ISP_ADDR + 0x4018)));
825 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x401C, ISP_RD32((void *)(ISP_ADDR + 0x401C)));
826 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4020, ISP_RD32((void *)(ISP_ADDR + 0x4020)));
827 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4024, ISP_RD32((void *)(ISP_ADDR + 0x4024)));
828 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4028, ISP_RD32((void *)(ISP_ADDR + 0x4028)));
829 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x402C, ISP_RD32((void *)(ISP_ADDR + 0x402C)));
830 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4100, ISP_RD32((void *)(ISP_ADDR + 0x4100)));
831 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4104, ISP_RD32((void *)(ISP_ADDR + 0x4104)));
832 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4108, ISP_RD32((void *)(ISP_ADDR + 0x4108)));
833 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x410C, ISP_RD32((void *)(ISP_ADDR + 0x410C)));
834 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4120, ISP_RD32((void *)(ISP_ADDR + 0x4120)));
835 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x412C, ISP_RD32((void *)(ISP_ADDR + 0x412C)));
836 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x420C, ISP_RD32((void *)(ISP_ADDR + 0x420C)));
837 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4234, ISP_RD32((void *)(ISP_ADDR + 0x4234)));
838 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4240, ISP_RD32((void *)(ISP_ADDR + 0x4240)));
839 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4300, ISP_RD32((void *)(ISP_ADDR + 0x4300)));
840 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4304, ISP_RD32((void *)(ISP_ADDR + 0x4304)));
841 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4600, ISP_RD32((void *)(ISP_ADDR + 0x4600)));
842 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4604, ISP_RD32((void *)(ISP_ADDR + 0x4604)));
843 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4608, ISP_RD32((void *)(ISP_ADDR + 0x4608)));
844 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x460C, ISP_RD32((void *)(ISP_ADDR + 0x460C)));
845 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4610, ISP_RD32((void *)(ISP_ADDR + 0x4610)));
846 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4614, ISP_RD32((void *)(ISP_ADDR + 0x4614)));
847 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4618, ISP_RD32((void *)(ISP_ADDR + 0x4618)));
848 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x10);
849 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
850 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
851 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x11);
852 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
853 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
854 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x12);
855 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
856 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
857 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x10);
858 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
859 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
860 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x11);
861 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
862 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
863 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x12);
864 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
865 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
866 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x10);
867 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
868 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
869 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x11);
870 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
871 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
872 ISP_WR32((void *)(ISP_ADDR + 0x461C), 0x12);
873 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x461C, ISP_RD32((void *)(ISP_ADDR + 0x461C)));
874 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4620, ISP_RD32((void *)(ISP_ADDR + 0x4620)));
875
876 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4618, ISP_RD32((void *)(ISP_ADDR + 0x4618)));
877 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4624, ISP_RD32((void *)(ISP_ADDR + 0x4624)));
878 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4628, ISP_RD32((void *)(ISP_ADDR + 0x4628)));
879 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x462C, ISP_RD32((void *)(ISP_ADDR + 0x462C)));
880 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x4630, ISP_RD32((void *)(ISP_ADDR + 0x4630)));
881
882 LOG_DBG("end MT");
883 // for tpipe main end
884
885 //INT STX
886 for( i = 0x44; i <= 0x48; i += 4)
887 {
888 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
889 }
890
891 //DMA
892 for( i = 0x248; i <= 0x24C; i += 4)//IMGI
893 {
894 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
895 }
896 for( i = 0x280; i <= 0x284; i += 4)//LSCI
897 {
898 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
899 }
900 for( i = 0x29C; i <= 0x2A0; i += 4)//FLKI
901 {
902 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
903 }
904 for( i = 0x2D8; i <= 0x2DC; i += 4)//VIPI
905 {
906 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
907 }
908 for( i = 0x2F8; i <= 0x2FC; i += 4)//VIP2I
909 {
910 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
911 }
912 for( i = 0x300; i <= 0x31C; i += 4)//IMGO
913 {
914 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
915 }
916 for( i = 0x334; i <= 0x338; i += 4)//IMG2O
917 {
918 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
919 }
920 for( i = 0x380; i <= 0x384; i += 4)//ESFKO
921 {
922 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
923 }
924 for( i = 0x39C; i <= 0x3A0; i += 4)//ESFKO
925 {
926 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
927 }
928
929 //DMA ERR ST
930 for( i = 0x3A4; i <= 0x3D8; i += 4)
931 {
932 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
933 }
934
935 //TG1
936 for( i = 0x410; i <= 0x44C; i += 4)
937 {
938 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
939 }
940
941 //CDP
942 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0xCC0, ISP_RD32((void *)(ISP_ADDR + 0xCC0)));
943 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0xD40, ISP_RD32((void *)(ISP_ADDR + 0xD40)));
944
945 //SENINF1_INT_STA
946 for( i = 0x4014; i <= 0x4018; i += 4)
947 {
948 LOG_DBG("0x%08X %08X ", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
949 }
950
951 LOG_DBG("0x%08X %08X ", ISP_ADDR_CAMINF, ISP_RD32((void *)ISP_ADDR_CAMINF));
952 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x150, ISP_RD32((void *)(ISP_ADDR + 0x150)));
953
954 #if 0
955 /*
956 1. Debug port information:
957
958 [30]:ultra-high is enable
959 */
960 ISP_WR32(ISP_ADDR + 0x160,0x94);
961 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
962 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
963
964 /*
965 IMGI :
966 0x15004160 ] 0x00000011
967 Read 0x15004164
968 Check bit 21 ->N dmadone_flag
969 Check bit [9:7] -> NFSM (idle =0)
970 */
971 ISP_WR32(ISP_ADDR + 0x160,0x00000011);
972 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
973 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
974 /*
975 IMGCI :
976 0x15004160 ] 0x00000021
977 Read 0x15004164
978 Check bit 21 ->N dmadone_flag
979 Check bit [9:7] -> NFSM (idle =0)
980 */
981 ISP_WR32(ISP_ADDR + 0x160,0x00000021);
982 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
983 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
984 /*
985 LSCI :
986 0x15004160 ] 0x00000031
987 Read 0x15004164
988 Check bit 21 ->N dmadone_flag
989 Check bit [9:7] -> NFSM (idle =0)
990 */
991 ISP_WR32(ISP_ADDR + 0x160,0x00000031);
992 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
993 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
994
995 /*
996 FLKI :
997 0x15004160 ] 0x00000051
998 Read 0x15004164
999 Check bit 21 ->N dmadone_flag
1000 Check bit [9:7] -> NFSM (idle =0)
1001 */
1002 ISP_WR32(ISP_ADDR + 0x160,0x00000051);
1003 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1004 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1005
1006 /*
1007 LCEI :
1008 0x15004160 ] 0x00000061
1009 Read 0x15004164
1010 Check bit 21 ->N dmadone_flag
1011 Check bit [9:7] -> NFSM (idle =0)
1012 */
1013 ISP_WR32(ISP_ADDR + 0x160,0x00000061);
1014 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1015 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1016 /*
1017 VIPI :
1018 0x15004160 ] 0x00000071
1019 Read 0x15004164
1020 Check bit 21 ->N dmadone_flag
1021 Check bit [9:7] -> NFSM (idle =0)
1022 */
1023 ISP_WR32(ISP_ADDR + 0x160,0x00000071);
1024 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1025 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1026 /*
1027 VIP2I :
1028 0x15004160 ] 0x00000081
1029 Read 0x15004164
1030 Check bit 21 ->N dmadone_flag
1031 Check bit [9:7] -> NFSM (idle =0)
1032 */
1033 ISP_WR32(ISP_ADDR + 0x160,0x00000081);
1034 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1035 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1036 /*
1037 IMGO
1038 0x15004160 ] 0x00000194
1039 Read 0x15004164
1040 Check bit [4:2] ->NFSM (idle =0)
1041 Check bit 23 -> Ndmasent_flag
1042 Check bit 22 -> N dmadone_flag
1043 */
1044 ISP_WR32(ISP_ADDR + 0x160,0x00000194);
1045 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1046 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1047 /*
1048 IMG2O
1049 0x15004160 ] 0x000001a4
1050 Read 0x15004164
1051 Check bit [4:2] ->NFSM (idle =0)
1052 Check bit 23 -> Ndmasent_flag
1053 Check bit 22 -> N dmadone_flag
1054 */
1055 ISP_WR32(ISP_ADDR + 0x160,0x000001a4);
1056 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1057 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1058
1059 /*
1060 LCSO
1061 0x15004160 ] 0x000001b4
1062 Read 0x15004164
1063 Check bit [4:2] ->NFSM (idle =0)
1064 Check bit 23 -> Ndmasent_flag
1065 Check bit 22 -> N dmadone_flag
1066 */
1067 ISP_WR32(ISP_ADDR + 0x160,0x000001b4);
1068 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1069 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1070
1071 /*
1072 ESFKO
1073 0x15004160 ] 0x000001c4
1074 Read 0x15004164
1075 Check bit [4:2] ->NFSM (idle =0)
1076 Check bit 23 -> Ndmasent_flag
1077 Check bit 22 -> N dmadone_flag
1078 */
1079 ISP_WR32(ISP_ADDR + 0x160,0x000001c4);
1080 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1081 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1082 /*
1083 AAO
1084 0x15004160 ] 0x000001d4
1085 Read 0x15004164
1086 Check bit [4:2] ->NFSM (idle =0)
1087 Check bit 23 -> Ndmasent_flag
1088 Check bit 22 -> N dmadone_flag
1089 */
1090 ISP_WR32(ISP_ADDR + 0x160,0x000001d4);
1091 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x160, ISP_RD32(ISP_ADDR + 0x160));
1092 LOG_DBG("0x%08X %08X ", ISP_ADDR + 0x164, ISP_RD32(ISP_ADDR + 0x164));
1093
1094 #endif
1095
1096 #endif
1097
1098 //spin_unlock_irqrestore(&(g_IspInfo.SpinLock), flags);
1099
1100 LOG_DBG("-");
1101 return Ret;
1102 }
1103
1104 /*********************************************************************
1105 1.
1106 0x4160 = 0x9000, look 0x4164 , it is imgo status
1107 0x4160 = 0x9001, look 0x4164 , it is imgo line / pix cnt with sync
1108 0x4160 = 0x9002, look 0x4164 , it is imgo line / pix cnt without sync
1109
1110 0x4160 = 0x9003, look 0x4164 , it is imgi status
1111 0x4160 = 0x9004, look 0x4164, it is imgi line / pix cnt with sync
1112 0x4160 = 0x9005, look 0x4164, it is imgi line / pix cnt without sync
1113
1114 0x4160 = 0x9006, look 0x4164, it is raw_cfa status
1115 0x4160 = 0x9007, look 0x4164, it is raw_cfa line / pix cnt with sync
1116 0x4160 = 0x9008, look 0x4164, it is raw_cfa line / pix cnt without sync
1117
1118 0x4160 = 0x9009, look 0x4164, it is rgb_yuv status
1119 0x4160 = 0x900a, look 0x4164, it is rgb_yuv a line / pix cnt with sync
1120 0x4160 = 0x900b, look 0x4164, it is rgb_yuv line / pix cnt without sync
1121
1122 0x4160 = 0x900c, look 0x4164, it is yuv_out status
1123 0x4160 = 0x900d, look 0x4164, it is yuv_out line / pix cnt with sync
1124 0x4160 = 0x900e, look 0x4164, it is yuv_out line / pix cnt without sync
1125
1126 Status :
1127 Bit 31:28 ? {sot_reg, eol_reg, eot_reg, sof} , reg means status record
1128 Bit 27:24 ?{eot, eol,eot, req}
1129 Bit 23 : rdy
1130
1131 Rdy should be 1 at idle or end of tile, if not 0, «Ü¥i¯à¬Omdp ¨S¦^rdy
1132 Req should be 0 at idle or end of tile
1133
1134 sot_reg, eol_reg, eot_reg should be 1 at idle or end of tile
1135 you can also line / pix cnt without sync , to check if
1136
1137 line count : bit 31:16
1138 pix count : bit 15:0
1139
1140
1141 2. 0x4044 / 0x4048 status
1142 It is µL¶· enable,
1143 It is clear by 0x4020[31] write or read clear,
1144 It has many information on it,
1145 You can look coda
1146
1147 3. read CQ status status
1148 0x4160 = 0x6000
1149 Dump 0x4164 full register
1150 Bit 3:0 : cq1 , 1 means idle
1151 Bit 7:4 : cq2 , 1 means idle
1152 Bit 11:8 : cq3 , 1 means idle
1153 Bit 13:12 : apb status , 1 means idle
1154
1155
1156 #define ISP_REG_ADDR_CTL_DBG_SET_IMGI_STS (0x9003)
1157 #define ISP_REG_ADDR_CTL_DBG_SET_IMGI_SYNC (0x9004)
1158 #define ISP_REG_ADDR_CTL_DBG_SET_IMGI_NO_SYNC (0x9005)
1159
1160 #define ISP_REG_ADDR_CTL_DBG_SET_CFA_STS (0x9006)
1161 #define ISP_REG_ADDR_CTL_DBG_SET_CFA_SYNC (0x9007)
1162 #define ISP_REG_ADDR_CTL_DBG_SET_CFA_NO_SYNC (0x9008)
1163
1164 #define ISP_REG_ADDR_CTL_DBG_SET_YUV_STS (0x9009)
1165 #define ISP_REG_ADDR_CTL_DBG_SET_YUV_SYNC (0x900a)
1166 #define ISP_REG_ADDR_CTL_DBG_SET_YUV_NO_SYNC (0x900b)
1167
1168 #define ISP_REG_ADDR_CTL_DBG_SET_OUT_STS (0x900c)
1169 #define ISP_REG_ADDR_CTL_DBG_SET_OUT_SYNC (0x900d)
1170 #define ISP_REG_ADDR_CTL_DBG_SET_OUT_NO_SYNC (0x900e)
1171 *********************************************************************/
1172 static int ISPDbgPortDump(int params)
1173 {
1174 MINT32 Ret = 0;
1175 LOG_DBG("ISP DBG PORT DUMP >>");
1176
1177 LOG_DBG("CQ STATUS:>");
1178 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1179 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1180 LOG_DBG("IMGI STATUS:>");
1181 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_IMGI_STS);
1182 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1183 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1184 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_IMGI_SYNC);
1185 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1186 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1187 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_IMGI_NO_SYNC);
1188 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1189 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1190 LOG_DBG(" <");
1191
1192 LOG_DBG("RAW_CFA STATUS:>");
1193 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_CFA_STS);
1194 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1195 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1196 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_CFA_SYNC);
1197 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1198 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1199 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_CFA_NO_SYNC);
1200 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1201 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1202 LOG_DBG(" <");
1203
1204 LOG_DBG("RGB_YUV STATUS:>");
1205 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_YUV_STS);
1206 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1207 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1208 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_YUV_SYNC);
1209 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1210 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1211 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_YUV_NO_SYNC);
1212 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1213 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1214 LOG_DBG(" <");
1215
1216 LOG_DBG("YUV_OUT STATUS:>");
1217 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_OUT_STS);
1218 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1219 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1220 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_OUT_SYNC);
1221 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1222 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));;
1223 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_OUT_NO_SYNC);
1224 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1225 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1226 LOG_DBG(" <");
1227
1228
1229 LOG_DBG("CQ STATUS RETURN:>");
1230 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_CQ_STS);
1231 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1232 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1233 LOG_DBG(" <");
1234
1235 LOG_DBG("INT_STATUSX:>");
1236 LOG_DBG("(0x%08x 0x%08x)",ISP_REG_ADDR_INT_STATUSX,
1237 ISP_RD32((void *)ISP_REG_ADDR_INT_STATUSX) );
1238 LOG_DBG(" <");
1239 LOG_DBG("DMA_INTX:>");
1240 LOG_DBG("(0x%08x 0x%08x)",ISP_REG_ADDR_DMA_INTX,
1241 ISP_RD32((void *)ISP_REG_ADDR_DMA_INTX) );
1242 LOG_DBG(" <");
1243
1244 LOG_DBG("TDR0:>");
1245 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x5000);
1246 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1247 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1248 LOG_DBG(" <");
1249
1250 LOG_DBG("TDR1:>");
1251 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x5100);
1252 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1253 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1254 LOG_DBG(" <");
1255
1256 LOG_DBG("MDPINF:>");
1257 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0xA000);
1258 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1259 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1260 LOG_DBG(" <");
1261
1262 LOG_DBG("CRSP:>");
1263 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x910F);
1264 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1265 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1266 LOG_DBG(" <");
1267
1268 LOG_DBG("PASS2_DB_EN (~0x00000020):>");
1269 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x018, ISP_RD32((void *)(ISP_ADDR + 0x018)));
1270 LOG_DBG(" <");
1271
1272 LOG_DBG("TDR_EN (0x80000000):>");
1273 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x054, ISP_RD32((void *)(ISP_ADDR + 0x054)));
1274 LOG_DBG(" <");
1275
1276
1277 LOG_DBG("TDR_BASE_ADDR :>");
1278 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x204, ISP_RD32((void *)(ISP_ADDR + 0x204)));
1279 LOG_DBG(" <");
1280
1281 LOG_DBG("IMGI :>");
1282 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x230, ISP_RD32((void *)(ISP_ADDR + 0x230)));
1283 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x234, ISP_RD32((void *)(ISP_ADDR + 0x234)));
1284 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x238, ISP_RD32((void *)(ISP_ADDR + 0x238)));
1285 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x23C, ISP_RD32((void *)(ISP_ADDR + 0x23C)));
1286 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x240, ISP_RD32((void *)(ISP_ADDR + 0x240)));
1287 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x248, ISP_RD32((void *)(ISP_ADDR + 0x248)));
1288 LOG_DBG("0x%08X %08X", ISP_TPIPE_ADDR + 0x24C, ISP_RD32((void *)(ISP_ADDR + 0x24C)));
1289 LOG_DBG(" <");
1290 LOG_DBG("<CDP_OUT STATUS:>");
1291 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x0000400d);
1292 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1293 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1294 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x0000400e);
1295 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1296 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1297 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x0000400f);
1298 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1299 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1300 LOG_DBG("ISP DBG PORT DUMP <<");
1301 return Ret;
1302 }
1303
1304
1305 static void SeninfOverrunDump(void)
1306 {
1307 static MINT32 debugFlag = 0;
1308 LOG_DBG("+");
1309 LOG_DBG("(0xF0203108 0x%08x)",ISP_RD32((void *)0xF0203108));
1310
1311 #if 0
1312
1313 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1100);
1314 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1315
1316 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1002);
1317 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1318
1319 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1102);
1320 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1321
1322 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1202);
1323 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1324
1325 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1302);
1326 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1327
1328 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1006);
1329 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1330
1331 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1106);
1332 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1333
1334 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x110A);
1335 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1336
1337 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x100B);
1338 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1339
1340 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x110B);
1341 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1342
1343 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x110C);
1344 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1345
1346 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1016);
1347 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1348
1349 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1017);
1350 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1351
1352 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1018);
1353 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1354
1355 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1019);
1356 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1357
1358 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x101A);
1359 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1360
1361 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x101B);
1362 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1363
1364 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x9000);
1365 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1366
1367 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x9001);
1368 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1369
1370 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x9002);
1371 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1372
1373 #else
1374
1375 if(debugFlag == 0)
1376 {
1377
1378 MUINT32 idx = 0;
1379
1380 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1100);
1381 g_seninfDebug[idx].regVal_1 = 0x1100;
1382 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1383 idx++;
1384
1385 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1002);
1386 g_seninfDebug[idx].regVal_1 = 0x1002;
1387 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1388 idx++;
1389
1390 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1102);
1391 g_seninfDebug[idx].regVal_1 = 0x1102;
1392 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1393 idx++;
1394
1395 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1202);
1396 g_seninfDebug[idx].regVal_1 = 0x1202;
1397 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1398 idx++;
1399
1400 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1302);
1401 g_seninfDebug[idx].regVal_1 = 0x1302;
1402 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1403 idx++;
1404
1405 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1006);
1406 g_seninfDebug[idx].regVal_1 = 0x1006;
1407 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1408 idx++;
1409
1410 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1106);
1411 g_seninfDebug[idx].regVal_1 = 0x1106;
1412 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1413 idx++;
1414
1415 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x110A);
1416 g_seninfDebug[idx].regVal_1 = 0x110A;
1417 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1418 idx++;
1419
1420 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x100B);
1421 g_seninfDebug[idx].regVal_1 = 0x100B;
1422 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1423 idx++;
1424
1425 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x110B);
1426 g_seninfDebug[idx].regVal_1 = 0x110B;
1427 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1428 idx++;
1429
1430 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x110C);
1431 g_seninfDebug[idx].regVal_1 = 0x110C;
1432 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1433 idx++;
1434
1435 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1016);
1436 g_seninfDebug[idx].regVal_1 = 0x1016;
1437 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1438 idx++;
1439
1440 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1017);
1441 g_seninfDebug[idx].regVal_1 = 0x1017;
1442 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1443 idx++;
1444
1445 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1018);
1446 g_seninfDebug[idx].regVal_1 = 0x1018;
1447 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1448 idx++;
1449
1450 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x1019);
1451 g_seninfDebug[idx].regVal_1 = 0x1019;
1452 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1453 idx++;
1454
1455 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x101A);
1456 g_seninfDebug[idx].regVal_1 = 0x101A;
1457 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1458 idx++;
1459
1460 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x101B);
1461 g_seninfDebug[idx].regVal_1 = 0x101B;
1462 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1463 idx++;
1464
1465 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x9000);
1466 g_seninfDebug[idx].regVal_1 = 0x9000;
1467 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1468 idx++;
1469
1470 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x9001);
1471 g_seninfDebug[idx].regVal_1 = 0x9001;
1472 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1473 idx++;
1474
1475 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, 0x9002);
1476 g_seninfDebug[idx].regVal_1 = 0x9002;
1477 g_seninfDebug[idx].regVal_2 = ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT);
1478 idx++;
1479
1480 debugFlag = 1;
1481 }
1482
1483 #endif
1484 LOG_DBG("-");
1485 }
1486
1487
1488 int ISPRegDump(int params)
1489 {
1490 MINT32 Ret = 0;
1491
1492 LOG_DBG("+");
1493
1494 //spin_lock_irqsave(&(g_IspInfo.SpinLock), flags);
1495
1496 //tile tool parse range
1497 //Joseph Hung (xa)#define ISP_ADDR_START 0x15004000
1498 // #define ISP_ADDR_END 0x15006000
1499 //
1500
1501 // for tpipe main start
1502 LOG_DBG("Camera_isp RegDump start");
1503 LOG_DBG("start MT");
1504 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x000, ISP_RD32((void *)(ISP_ADDR + 0x000)));
1505 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x004, ISP_RD32((void *)(ISP_ADDR + 0x004)));
1506 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x008, ISP_RD32((void *)(ISP_ADDR + 0x008)));
1507 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x00C, ISP_RD32((void *)(ISP_ADDR + 0x00C)));
1508 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x010, ISP_RD32((void *)(ISP_ADDR + 0x010)));
1509 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x018, ISP_RD32((void *)(ISP_ADDR + 0x018)));
1510 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x01C, ISP_RD32((void *)(ISP_ADDR + 0x01C)));
1511 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x050, ISP_RD32((void *)(ISP_ADDR + 0x050)));
1512 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x054, ISP_RD32((void *)(ISP_ADDR + 0x054)));
1513 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x078, ISP_RD32((void *)(ISP_ADDR + 0x078)));
1514 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x110, ISP_RD32((void *)(ISP_ADDR + 0x110)));
1515 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x114, ISP_RD32((void *)(ISP_ADDR + 0x114)));
1516 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x22C, ISP_RD32((void *)(ISP_ADDR + 0x22C)));
1517 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x240, ISP_RD32((void *)(ISP_ADDR + 0x240)));
1518 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x27C, ISP_RD32((void *)(ISP_ADDR + 0x27C)));
1519 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x2B4, ISP_RD32((void *)(ISP_ADDR + 0x2B4)));
1520 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x308, ISP_RD32((void *)(ISP_ADDR + 0x308)));
1521 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x30C, ISP_RD32((void *)(ISP_ADDR + 0x30C)));
1522 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x310, ISP_RD32((void *)(ISP_ADDR + 0x310)));
1523 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x31C, ISP_RD32((void *)(ISP_ADDR + 0x31C)));
1524 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x328, ISP_RD32((void *)(ISP_ADDR + 0x328)));
1525 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x32C, ISP_RD32((void *)(ISP_ADDR + 0x32C)));
1526 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x330, ISP_RD32((void *)(ISP_ADDR + 0x330)));
1527 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x33C, ISP_RD32((void *)(ISP_ADDR + 0x33C)));
1528 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x3A8, ISP_RD32((void *)(ISP_ADDR + 0x3A8)));
1529 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x534, ISP_RD32((void *)(ISP_ADDR + 0x534)));
1530 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x538, ISP_RD32((void *)(ISP_ADDR + 0x538)));
1531 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x53C, ISP_RD32((void *)(ISP_ADDR + 0x53C)));
1532 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x800, ISP_RD32((void *)(ISP_ADDR + 0x800)));
1533 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x8A0, ISP_RD32((void *)(ISP_ADDR + 0x8A0)));
1534 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x9C4, ISP_RD32((void *)(ISP_ADDR + 0x9C4)));
1535 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x9E4, ISP_RD32((void *)(ISP_ADDR + 0x9E4)));
1536 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x9E8, ISP_RD32((void *)(ISP_ADDR + 0x9E8)));
1537 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0x9EC, ISP_RD32((void *)(ISP_ADDR + 0x9EC)));
1538 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xA20, ISP_RD32((void *)(ISP_ADDR + 0xA20)));
1539 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xACC, ISP_RD32((void *)(ISP_ADDR + 0xACC)));
1540 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB00, ISP_RD32((void *)(ISP_ADDR + 0xB00)));
1541 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB04, ISP_RD32((void *)(ISP_ADDR + 0xB04)));
1542 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB08, ISP_RD32((void *)(ISP_ADDR + 0xB08)));
1543 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB0C, ISP_RD32((void *)(ISP_ADDR + 0xB0C)));
1544 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB10, ISP_RD32((void *)(ISP_ADDR + 0xB10)));
1545 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB14, ISP_RD32((void *)(ISP_ADDR + 0xB14)));
1546 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB18, ISP_RD32((void *)(ISP_ADDR + 0xB18)));
1547 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB1C, ISP_RD32((void *)(ISP_ADDR + 0xB1C)));
1548 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xB20, ISP_RD32((void *)(ISP_ADDR + 0xB20)));
1549 LOG_DBG("[ISP/MDP][TPIPE_DumpReg] 0x%08X = 0x%08X", ISP_TPIPE_ADDR + 0xF50, ISP_RD32((void *)(ISP_ADDR + 0xF50)));
1550 LOG_DBG("end MT");
1551
1552
1553 //spin_unlock_irqrestore(&(g_IspInfo.SpinLock), flags);
1554
1555 LOG_DBG("-");
1556 ISPDbgPortDump(params);
1557 return Ret;
1558 }
1559 static int ISPResetPass2(int params)
1560 {
1561 MINT32 i = 0;
1562 MINT32 Ret = 0;
1563 MINT32 m32RegEn2= 0;
1564 MINT32 m32RegCropX= 0;
1565 LOG_DBG("ISPResetPass2 >>");
1566
1567
1568 // LOG_DBG("CQ STATUS: bef");
1569 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1570 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1571
1572
1573 LOG_DBG("ISP_REG_ADDR_CTL_EN2>: 0x%08x ", ISP_RD32((void *)ISP_REG_ADDR_CTL_EN2));
1574 m32RegEn2= ISP_RD32((void *)ISP_REG_ADDR_CTL_EN2);
1575 ISP_WR32((void *)ISP_REG_ADDR_CTL_EN2, m32RegEn2&(~ISP_REG_ADDR_CTL_EN2_UV_CRSA_EN_BIT));
1576 // LOG_DBG("ISP_REG_ADDR_CTL_EN2>>: 0x%08x ", ISP_RD32((void *)ISP_REG_ADDR_CTL_EN2));
1577
1578 LOG_DBG("ISP_REG_ADDR_CTL_CROP_X>: 0x%08x ", ISP_RD32((void *)ISP_REG_ADDR_CTL_CROP_X));
1579 m32RegCropX= ISP_RD32((void *)ISP_REG_ADDR_CTL_CROP_X);
1580 ISP_WR32((void *)ISP_REG_ADDR_CTL_CROP_X, m32RegCropX&(~ISP_REG_ADDR_CTL_CROP_X_MDP_CROP_EN_BIT));
1581 // LOG_DBG("ISP_REG_ADDR_CTL_CROP_X>>: 0x%08x ", ISP_RD32((void *)ISP_REG_ADDR_CTL_CROP_X));
1582
1583 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_CQ_STS);
1584 for(i=0;i<5000;i++)
1585 {
1586 if((ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT)&0x11) == 0x11)
1587 {
1588 break;
1589 }
1590 }
1591 LOG_DBG("i - %d ", i);
1592 ISP_WR32((void *)ISP_REG_ADDR_CTL_EN2, m32RegEn2);
1593 // LOG_DBG("ISP_REG_ADDR_CTL_EN2>>>: 0x%08x ", ISP_RD32((void *)ISP_REG_ADDR_CTL_EN2));
1594
1595 ISP_WR32((void *)ISP_REG_ADDR_CTL_CROP_X, m32RegCropX);
1596 // LOG_DBG("ISP_REG_ADDR_CTL_CROP_X>>>: 0x%08x ", ISP_RD32((void *)ISP_REG_ADDR_CTL_CROP_X));
1597
1598 // LOG_DBG("CQ STATUS: aft");
1599 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1600 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1601
1602
1603 LOG_DBG("ISPResetPass2 <<");
1604 return Ret;
1605 }
1606
1607 int MDPReset_Process(int params)
1608 {
1609 LOG_DBG("\n\n\n MDP cmdqReset_cb Test %d\n\n\n", params);
1610 ISPResetPass2(params);
1611 return 0;
1612 }
1613 /*******************************************************************************
1614 *
1615 ********************************************************************************/
1616 static MVOID ISP_EnableClock(MBOOL En)
1617 {
1618 #if 0 // using LDVT. Temp solution for LDVT
1619
1620 LOG_INF("in LDVT,En(%d),g_EnableClkCnt(%d)", En, g_EnableClkCnt);
1621
1622 ISP_WR32(CAMINF_BASE, 0x00);
1623
1624 #else // Not using LDVT
1625
1626 LOG_INF("En(%d),g_EnableClkCnt(%d)", En, g_EnableClkCnt);
1627
1628 if(En) // enable clock.
1629 {
1630 enable_clock(MT_CG_DISP0_SMI_COMMON,"CAMERA"); //new for MT, confirm with Abrams
1631 enable_clock(MT_CG_IMAGE_CAM_SMI, "CAMERA");
1632 enable_clock(MT_CG_IMAGE_CAM_CAM, "CAMERA");
1633 enable_clock(MT_CG_IMAGE_SEN_TG, "CAMERA");
1634 enable_clock(MT_CG_IMAGE_SEN_CAM, "CAMERA");
1635 enable_clock(MT_CG_IMAGE_LARB2_SMI, "CAMERA");
1636 g_EnableClkCnt++;
1637 LOG_DBG("Camera clock enbled. g_EnableClkCnt(%d)", g_EnableClkCnt);
1638
1639 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1640 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1641 if(ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET)!=ISP_REG_ADDR_CTL_DBG_SET_CQ_STS)
1642 {
1643 // LOG_DBG("CQ STATUS RETURN:>");
1644 ISP_WR32((void *)ISP_REG_ADDR_CTL_DBG_SET, ISP_REG_ADDR_CTL_DBG_SET_CQ_STS);
1645 LOG_DBG("(0x%08x 0x%08x)",ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_SET),
1646 ISP_RD32((void *)ISP_REG_ADDR_CTL_DBG_PORT));
1647 // LOG_DBG(" <");
1648 }
1649 }
1650 else // disable clock.
1651 {
1652 disable_clock(MT_CG_IMAGE_CAM_SMI, "CAMERA");
1653 disable_clock(MT_CG_IMAGE_CAM_CAM, "CAMERA");
1654 disable_clock(MT_CG_IMAGE_SEN_TG, "CAMERA");
1655 disable_clock(MT_CG_IMAGE_SEN_CAM, "CAMERA");
1656 disable_clock(MT_CG_IMAGE_LARB2_SMI, "CAMERA");
1657 disable_clock(MT_CG_DISP0_SMI_COMMON,"CAMERA"); //new for MT, confirm with Abrams
1658 g_EnableClkCnt--;
1659 LOG_DBG("Camera clock disabled. g_EnableClkCnt(%d)", g_EnableClkCnt);
1660 }
1661 #endif
1662
1663 LOG_DBG("-");
1664 }
1665
1666 /*******************************************************************************
1667 *
1668 ********************************************************************************/
1669 static inline MVOID ISP_Reset(MVOID)
1670 {
1671 // ensure the view finder is disabe. 0: take_picture
1672 //ISP_CLR_BIT(ISP_REG_ADDR_EN1, 0);
1673
1674 MUINT32 i, Reg;
1675 unsigned long flags;
1676
1677 LOG_DBG("+");
1678
1679 //TODO: MUST remove later
1680 // imgsys clk on
1681 //ISP_WR32(ISP_ADDR_CAMINF, 0);
1682 //ISP_EnableClock(MTRUE);
1683 LOG_DBG("isp gate clk(0x%x)",ISP_RD32((void *)ISP_ADDR_CAMINF));
1684
1685 //imgsys IMG_SW_RST -> reset HW register
1686 /*
1687 1500000C IMG_SW_RST
1688 17 16 SENINF SENINF R/W 2'b00 "SENINF clock domain hw reset
1689 bit 0 : cam_tg hw domain hw reset,
1690 bit 1 : (TBD)
1691 0 : no hw reset
1692 1 : hw reset"
1693
1694 14 12 CAM_RST CAM_RST R/W 3'b000 " CAM W reset
1695 bit 0 : fsmi domain HW reset
1696 bit 1 : fmem domain HW reset
1697 bit 2 : faxi(cpu bus) dom HW reset
1698 0 : no hw reset
1699 1 : hw reset"
1700 */
1701 // Reg = ISP_RD32(ISP_ADDR_CAMINF+0x0C);
1702 // ISP_WR32(ISP_ADDR_CAMINF+0x0C, (Reg|0x0003F000));
1703 // mdelay(5);
1704 // ISP_WR32(ISP_ADDR_CAMINF+0x0C, (Reg&(~0x0003F000)) );
1705
1706 //js_test, remove later once IMGSYS is working. Now it's NOT working on FPGA.
1707 //remove temp solutionfor(i = 0; i <= 0x54; i += 4)
1708 //{
1709 //remove temp solution ISP_WR32((void *)(ISP_ADDR + i), 0x00 );
1710 //}
1711
1712 LOG_DBG("remove 0x0~0x54 = 0x0");//remove temp solution
1713
1714 //bandwidth limitor for TG
1715 Reg = ISP_RD32((void *)(EMI_BASE + 0x120));
1716 Reg |= 0x3F;
1717
1718 ISP_WR32((void *)(EMI_BASE + 0x120), Reg);
1719 ISP_WR32((void *)ISP_REG_ADDR_SW_CTL, ISP_REG_SW_CTL_SW_RST_TRIG);
1720 /*
1721 while(1)
1722 {
1723 Reg = ISP_RD32(ISP_REG_ADDR_SW_CTL);
1724 if(Reg & ISP_REG_SW_CTL_SW_RST_STATUS)
1725 {
1726 break;
1727 }
1728 }
1729 */
1730
1731 do
1732 {
1733 Reg = ISP_RD32((void *)ISP_REG_ADDR_SW_CTL);
1734 }
1735 while((!Reg) & ISP_REG_SW_CTL_SW_RST_STATUS);
1736
1737 ISP_WR32((void *)ISP_REG_ADDR_SW_CTL, ISP_REG_SW_CTL_SW_RST_TRIG|ISP_REG_SW_CTL_HW_RST); //0x5
1738 ISP_WR32((void *)ISP_REG_ADDR_SW_CTL, ISP_REG_SW_CTL_HW_RST); //0x4
1739 ISP_WR32((void *)ISP_REG_ADDR_SW_CTL, 0);
1740
1741 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
1742
1743 for(i = 0; i < ISP_IRQ_TYPE_AMOUNT; i++)
1744 {
1745 g_IspInfo.IrqInfo.Status[i] = 0;
1746 }
1747
1748 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
1749
1750 g_TempAddr = 0;
1751
1752 //js_test
1753 #if 0 //TODO:test code for SMI bandwidth control , remove later
1754 //larb_clock_on();
1755 //SMI_PowerOn();
1756 #define SMI_LARB_NUMBER 5
1757 for (i=0; i<SMI_LARB_NUMBER; i++) {
1758 larb_clock_on(i);
1759 }
1760 LOG_DBG("+LARB in reset,BWL(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X),220(0x%08X)/(0x%08X),0x14(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X)", \
1761 ISP_RD32(0xF0202000+0x204), \
1762 ISP_RD32(0xF0202000+0x20c), \
1763 ISP_RD32(0xF0202000+0x210), \
1764 ISP_RD32(0xF0202000+0x214), \
1765 ISP_RD32(0xF0202000+0x220), \
1766 ISP_RD32(0xF0202000+0x230), \
1767 ISP_RD32(SMI_LARB0+0x10), \
1768 ISP_RD32(SMI_LARB1+0x10), \
1769 ISP_RD32(SMI_LARB2+0x10), \
1770 ISP_RD32(SMI_LARB3+0x10), \
1771 ISP_RD32(SMI_LARB4+0x10));
1772
1773 //BW limit:
1774 //SMI_COMMON_APB_BASE+0x204=0xb92 //larb0 venc
1775 //SMI_COMMON_APB_BASE+0x20c=0xa4b //larb2 disp
1776 //SMI_COMMON_APB_BASE+0x210=0x96d //larb3 cdp
1777 //SMI_COMMON_APB_BASE+0x214=0x9a7 //larb4 isp
1778 ISP_WR32(0xF0202000+0x204,0xb92);
1779 ISP_WR32(0xF0202000+0x20c,0xa4b);
1780 ISP_WR32(0xF0202000+0x210,0x96d);
1781 ISP_WR32(0xF0202000+0x214,0xfff);//pass1
1782
1783
1784 //Allocate larb->2 smi common
1785 //LARB2&3 use m4u#0, else use m4u#1
1786 //SMI_COMMON_APB_BASE+0x220=0x1505
1787 ISP_WR32(0xF0202000+0x220,0x1505);
1788
1789 //SMI COMMON reduce command buffer
1790 //ISP_WR32(SMI_COMMON_APB_BASE+0x230,0x1560);
1791 ISP_WR32(0xF0202000+0x230,0x1560);
1792
1793 //SMI LARB reduce command buffer
1794 ISP_WR32(SMI_LARB0+0x14,0x400420);
1795 ISP_WR32(SMI_LARB1+0x14,0x400420);
1796 ISP_WR32(SMI_LARB2+0x14,0x400420);
1797 ISP_WR32(SMI_LARB3+0x14,0x400420);//pass2
1798 //ISP_WR32(SMI_LARB4+0x14,0x400420);//pass1
1799
1800 LOG_DBG("-LARB in reset,BWL(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X),220(0x%08X)/(0x%08X),0x14(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X)", \
1801 ISP_RD32(0xF0202000+0x204), \
1802 ISP_RD32(0xF0202000+0x20c), \
1803 ISP_RD32(0xF0202000+0x210), \
1804 ISP_RD32(0xF0202000+0x214), \
1805 ISP_RD32(0xF0202000+0x220), \
1806 ISP_RD32(0xF0202000+0x230), \
1807 ISP_RD32(SMI_LARB0+0x10), \
1808 ISP_RD32(SMI_LARB1+0x10), \
1809 ISP_RD32(SMI_LARB2+0x10), \
1810 ISP_RD32(SMI_LARB3+0x10), \
1811 ISP_RD32(SMI_LARB4+0x10));
1812
1813 for (i=0; i<SMI_LARB_NUMBER; i++) {
1814 larb_clock_off(i);
1815 }
1816 #endif
1817
1818 LOG_DBG("-");
1819 }
1820
1821 /*******************************************************************************
1822 *
1823 ********************************************************************************/
1824 static MINT32 ISP_ReadReg(ISP_REG_IO_STRUCT *pRegIo)
1825 {
1826 MUINT32 *pData = (MUINT32 *)pRegIo->Data;
1827 MUINT32 i;
1828 MINT32 Ret = 0;
1829
1830 ISP_REG_STRUCT reg;
1831
1832 //====== Read Register ======
1833
1834 for(i = 0; i < pRegIo->Count; i++)
1835 {
1836 if(0 != get_user(reg.Addr, pData))
1837 {
1838 LOG_ERR("get_user failed");
1839 Ret = -EFAULT;
1840 goto EXIT;
1841 }
1842 pData++;
1843 if((ISP_ADDR_CAMINF + reg.Addr >= ISP_ADDR) && (ISP_ADDR_CAMINF + reg.Addr < (ISP_ADDR_CAMINF+ISP_RANGE)))
1844 {
1845 reg.Val = ISP_RD32((void *)(ISP_ADDR_CAMINF + reg.Addr));
1846 }
1847 else
1848 {
1849 LOG_ERR("Wrong address(0x%x)",(unsigned int)(ISP_ADDR_CAMINF + reg.Addr));
1850 reg.Val = 0;
1851 }
1852 if(0 != put_user(reg.Val, pData))
1853 {
1854 LOG_ERR("put_user failed");
1855 Ret = -EFAULT;
1856 goto EXIT;
1857 }
1858 pData++;
1859 }
1860
1861 EXIT:
1862 return Ret;
1863 }
1864
1865 /*******************************************************************************
1866 *
1867 ********************************************************************************/
1868 static MINT32 ISP_WriteRegToHw(ISP_REG_STRUCT *pReg,MUINT32 Count)
1869 {
1870 MINT32 Ret = 0;
1871 MUINT32 i;
1872
1873 if(g_IspInfo.DebugMask & ISP_DBG_WRITE_REG)
1874 {
1875 LOG_DBG("+");
1876 }
1877
1878 spin_lock(&(g_IspInfo.SpinLockIsp));
1879 for(i = 0; i < Count; i++)
1880 {
1881 if(g_IspInfo.DebugMask & ISP_DBG_WRITE_REG)
1882 {
1883 LOG_DBG("Addr(0x%08X), Val(0x%08X)", (MUINT32)(ISP_ADDR_CAMINF + pReg[i].Addr), (MUINT32)(pReg[i].Val));
1884 }
1885 if(((ISP_ADDR_CAMINF + pReg[i].Addr) >= ISP_ADDR) && ((ISP_ADDR_CAMINF + pReg[i].Addr) < (ISP_ADDR_CAMINF+ISP_RANGE)))
1886 {
1887 ISP_WR32((void *)(ISP_ADDR_CAMINF + pReg[i].Addr), pReg[i].Val);
1888 }
1889 else
1890 {
1891 LOG_ERR("wrong address(0x%x)",(unsigned int)(ISP_ADDR_CAMINF + pReg[i].Addr));
1892 }
1893 }
1894 spin_unlock(&(g_IspInfo.SpinLockIsp));
1895
1896 return Ret;
1897 }
1898
1899 /*******************************************************************************
1900 *
1901 ********************************************************************************
1902 static void ISP_BufWrite_Init(void) //Vent@20121106: Marked to remove build warning: 'ISP_BufWrite_Init' defined but not used [-Wunused-function]
1903 {
1904 MUINT32 i;
1905 //
1906 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
1907 {
1908 LOG_DBG("- E.");
1909 }
1910 //
1911 for(i=0; i<ISP_BUF_WRITE_AMOUNT; i++)
1912 {
1913 g_IspInfo.BufInfo.Write[i].Status = ISP_BUF_STATUS_EMPTY;
1914 g_IspInfo.BufInfo.Write[i].Size = 0;
1915 g_IspInfo.BufInfo.Write[i].pData = NULL;
1916 }
1917 }
1918
1919 *******************************************************************************
1920 *
1921 ********************************************************************************/
1922 static MVOID ISP_BufWrite_Dump(MVOID)
1923 {
1924 MUINT32 i;
1925
1926 LOG_DBG("+");
1927
1928 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
1929 {
1930 LOG_DBG("i(%d),Status(%d),Size(%d)",i,g_IspInfo.BufInfo.Write[i].Status,g_IspInfo.BufInfo.Write[i].Size);
1931 g_IspInfo.BufInfo.Write[i].Status = ISP_BUF_STATUS_EMPTY;
1932 g_IspInfo.BufInfo.Write[i].Size = 0;
1933 g_IspInfo.BufInfo.Write[i].pData = NULL;
1934 }
1935 }
1936
1937 /*******************************************************************************
1938 *
1939 ********************************************************************************/
1940 static MVOID ISP_BufWrite_Free(MVOID)
1941 {
1942 MUINT32 i;
1943
1944 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
1945 {
1946 LOG_DBG("+");
1947 }
1948
1949 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
1950 {
1951 g_IspInfo.BufInfo.Write[i].Status = ISP_BUF_STATUS_EMPTY;
1952 g_IspInfo.BufInfo.Write[i].Size = 0;
1953
1954 if(g_IspInfo.BufInfo.Write[i].pData != NULL)
1955 {
1956 kfree(g_IspInfo.BufInfo.Write[i].pData);
1957 g_IspInfo.BufInfo.Write[i].pData = NULL;
1958 }
1959 }
1960 }
1961
1962 /*******************************************************************************
1963 *
1964 ********************************************************************************/
1965 static MBOOL ISP_BufWrite_Alloc(MVOID)
1966 {
1967 MUINT32 i;
1968
1969 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
1970 {
1971 LOG_DBG("+");
1972 }
1973
1974 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
1975 {
1976 g_IspInfo.BufInfo.Write[i].Status = ISP_BUF_STATUS_EMPTY;
1977 g_IspInfo.BufInfo.Write[i].Size = 0;
1978 g_IspInfo.BufInfo.Write[i].pData = (MUINT8*)kmalloc(ISP_BUF_SIZE_WRITE, GFP_ATOMIC);
1979 if(g_IspInfo.BufInfo.Write[i].pData == NULL)
1980 {
1981 LOG_DBG("ERROR: i = %d, pData is NULL",i);
1982 ISP_BufWrite_Free();
1983 return MFALSE;
1984 }
1985 }
1986
1987 return MTRUE;
1988 }
1989
1990 /*******************************************************************************
1991 *
1992 ********************************************************************************/
1993 static MVOID ISP_BufWrite_Reset(MVOID)
1994 {
1995 MUINT32 i;
1996
1997 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
1998 {
1999 LOG_DBG("+");
2000 }
2001
2002 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
2003 {
2004 g_IspInfo.BufInfo.Write[i].Status = ISP_BUF_STATUS_EMPTY;
2005 g_IspInfo.BufInfo.Write[i].Size = 0;
2006 }
2007 }
2008
2009 /*******************************************************************************
2010 *
2011 ********************************************************************************/
2012 static __inline MUINT32 ISP_BufWrite_GetAmount(MVOID)
2013 {
2014 MUINT32 i;
2015 MUINT32 Count = 0;
2016
2017 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
2018 {
2019 if(g_IspInfo.BufInfo.Write[i].Status == ISP_BUF_STATUS_READY)
2020 {
2021 Count++;
2022 }
2023 }
2024
2025 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2026 {
2027 LOG_DBG("Count(%d)",Count);
2028 }
2029
2030 return Count;
2031 }
2032
2033 /*******************************************************************************
2034 *
2035 ********************************************************************************/
2036 static MBOOL ISP_BufWrite_Add(MUINT32 Size,MUINT8 *pData)
2037 {
2038 MUINT32 i;
2039
2040 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2041 {
2042 LOG_DBG("+");
2043 }
2044
2045 // write to hold buffer
2046 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
2047 {
2048 if(g_IspInfo.BufInfo.Write[i].Status == ISP_BUF_STATUS_HOLD)
2049 {
2050 if((g_IspInfo.BufInfo.Write[i].Size + Size) > ISP_BUF_SIZE_WRITE)
2051 {
2052 LOG_ERR("i(%d), BufWriteSize(%d) + Size(%d) > %d",i,g_IspInfo.BufInfo.Write[i].Size,Size,ISP_BUF_SIZE_WRITE);
2053 return MFALSE;
2054 }
2055
2056 if(copy_from_user((MUINT8 *)(g_IspInfo.BufInfo.Write[i].pData+g_IspInfo.BufInfo.Write[i].Size), (MUINT8 *)pData, Size) != 0)
2057 {
2058 LOG_ERR("copy_from_user failed");
2059 return MFALSE;
2060 }
2061
2062 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2063 {
2064 LOG_DBG("i(%d), BufSize(%d), Size(%d)",i,g_IspInfo.BufInfo.Write[i].Size,Size);
2065 }
2066
2067 g_IspInfo.BufInfo.Write[i].Size += Size;
2068 return MTRUE;
2069 }
2070 }
2071
2072 // write to empty buffer
2073 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
2074 {
2075 if(g_IspInfo.BufInfo.Write[i].Status == ISP_BUF_STATUS_EMPTY)
2076 {
2077 if(Size > ISP_BUF_SIZE_WRITE)
2078 {
2079 LOG_ERR("i(%d), Size(%d) > %d",i,Size,ISP_BUF_SIZE_WRITE);
2080 return MFALSE;
2081 }
2082
2083 if(copy_from_user((MUINT8 *)(g_IspInfo.BufInfo.Write[i].pData), (MUINT8 *)pData, Size) != 0)
2084 {
2085 LOG_ERR("copy_from_user failed");
2086 return MFALSE;
2087 }
2088
2089 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2090 {
2091 LOG_DBG("i = %d, Size = %d",i,Size);
2092 }
2093
2094 g_IspInfo.BufInfo.Write[i].Size = Size;
2095 g_IspInfo.BufInfo.Write[i].Status = ISP_BUF_STATUS_HOLD;
2096
2097 return MTRUE;
2098 }
2099 }
2100
2101 LOG_ERR("All write buffer are full of data!");
2102 return MFALSE;
2103 }
2104 /*******************************************************************************
2105 *
2106 ********************************************************************************/
2107 static MVOID ISP_BufWrite_SetReady(MVOID)
2108 {
2109 MUINT32 i;
2110
2111 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2112 {
2113 LOG_DBG("+");
2114 }
2115
2116 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
2117 {
2118 if(g_IspInfo.BufInfo.Write[i].Status == ISP_BUF_STATUS_HOLD)
2119 {
2120 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2121 {
2122 LOG_DBG("i(%d), Size(%d)",i,g_IspInfo.BufInfo.Write[i].Size);
2123 }
2124 g_IspInfo.BufInfo.Write[i].Status = ISP_BUF_STATUS_READY;
2125 }
2126 }
2127 }
2128
2129 /*******************************************************************************
2130 *
2131 ********************************************************************************/
2132 static MBOOL ISP_BufWrite_Get(
2133 MUINT32 *pIndex,
2134 MUINT32 *pSize,
2135 MUINT8 **ppData)
2136 {
2137 MUINT32 i;
2138
2139 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2140 {
2141 LOG_DBG("+");
2142 }
2143
2144 for(i = 0; i < ISP_BUF_WRITE_AMOUNT; i++)
2145 {
2146 if(g_IspInfo.BufInfo.Write[i].Status == ISP_BUF_STATUS_READY)
2147 {
2148 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2149 {
2150 LOG_DBG("i(%d), Size(%d)",i,g_IspInfo.BufInfo.Write[i].Size);
2151 }
2152
2153 *pIndex = i;
2154 *pSize = g_IspInfo.BufInfo.Write[i].Size;
2155 *ppData = g_IspInfo.BufInfo.Write[i].pData;
2156
2157 return MTRUE;
2158 }
2159 }
2160
2161 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2162 {
2163 LOG_DBG("No buf is ready!");
2164 }
2165 return MFALSE;
2166 }
2167
2168 /*******************************************************************************
2169 *
2170 ********************************************************************************/
2171 static MBOOL ISP_BufWrite_Clear(MUINT32 Index)
2172 {
2173 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2174 {
2175 LOG_DBG("+");
2176 }
2177
2178 if(g_IspInfo.BufInfo.Write[Index].Status == ISP_BUF_STATUS_READY)
2179 {
2180 if(g_IspInfo.DebugMask & ISP_DBG_BUF_WRITE)
2181 {
2182 LOG_DBG("Index(%d), Size(%d)",Index,g_IspInfo.BufInfo.Write[Index].Size);
2183 }
2184 g_IspInfo.BufInfo.Write[Index].Size = 0;
2185 g_IspInfo.BufInfo.Write[Index].Status = ISP_BUF_STATUS_EMPTY;
2186
2187 return MTRUE;
2188 }
2189 else
2190 {
2191 LOG_DBG("WARNING: Index(%d) is not ready! Status(%d)",Index,g_IspInfo.BufInfo.Write[Index].Status);
2192 return MFALSE;
2193 }
2194 }
2195
2196 /*******************************************************************************
2197 *
2198 ********************************************************************************/
2199 static MVOID ISP_BufWrite_WriteToHw(MVOID)
2200 {
2201 MUINT8 *pBuf;
2202 MUINT32 Index, BufSize;
2203
2204 LOG_DBG("+");
2205
2206 spin_lock(&(g_IspInfo.SpinLockHold));
2207
2208 while(ISP_BufWrite_Get(&Index,&BufSize,&pBuf))
2209 {
2210 if(g_IspInfo.DebugMask & ISP_DBG_TASKLET)
2211 {
2212 LOG_DBG("Index(%d), BufSize(%d)", Index, BufSize);
2213 }
2214
2215 ISP_WriteRegToHw((ISP_REG_STRUCT*)pBuf, BufSize/sizeof(ISP_REG_STRUCT));
2216 ISP_BufWrite_Clear(Index);
2217 }
2218
2219 //LOG_DBG("No more buf.");
2220 atomic_set(&(g_IspInfo.HoldInfo.WriteEnable), 0);
2221 wake_up_interruptible(&(g_IspInfo.WaitQueueHead));
2222
2223 spin_unlock(&(g_IspInfo.SpinLockHold));
2224 }
2225
2226
2227 /*******************************************************************************
2228 *
2229 ********************************************************************************/
2230 MVOID ISP_ScheduleWork_VD(struct work_struct *data)
2231 {
2232 if(g_IspInfo.DebugMask & ISP_DBG_SCHEDULE_WORK)
2233 {
2234 LOG_DBG("+");
2235 }
2236
2237 g_IspInfo.TimeLog.WorkQueueVd = ISP_JiffiesToMs(jiffies);
2238
2239 if(g_IspInfo.Callback[ISP_CALLBACK_WORKQUEUE_VD].Func != NULL)
2240 {
2241 g_IspInfo.Callback[ISP_CALLBACK_WORKQUEUE_VD].Func();
2242 }
2243 }
2244
2245 /*******************************************************************************
2246 *
2247 ********************************************************************************/
2248 MVOID ISP_ScheduleWork_EXPDONE(struct work_struct *data)
2249 {
2250 if(g_IspInfo.DebugMask & ISP_DBG_SCHEDULE_WORK)
2251 {
2252 LOG_DBG("+");
2253 }
2254
2255 g_IspInfo.TimeLog.WorkQueueExpdone = ISP_JiffiesToMs(jiffies);
2256
2257 if(g_IspInfo.Callback[ISP_CALLBACK_WORKQUEUE_EXPDONE].Func != NULL)
2258 {
2259 g_IspInfo.Callback[ISP_CALLBACK_WORKQUEUE_EXPDONE].Func();
2260 }
2261 }
2262
2263 /*******************************************************************************
2264 *
2265 ********************************************************************************/
2266 MVOID ISP_ScheduleWork_SENINF(struct work_struct *data)
2267 {
2268 if(g_IspInfo.DebugMask & ISP_DBG_SCHEDULE_WORK)
2269 {
2270 LOG_DBG("+");
2271 }
2272
2273 g_IspInfo.TimeLog.WorkQueueSeninf = ISP_JiffiesToMs(jiffies);
2274
2275 if(g_IspInfo.Callback[ISP_CALLBACK_WORKQUEUE_SENINF].Func != NULL)
2276 {
2277 g_IspInfo.Callback[ISP_CALLBACK_WORKQUEUE_SENINF].Func();
2278 }
2279 }
2280
2281
2282 /*******************************************************************************
2283 *
2284 ********************************************************************************/
2285 MVOID ISP_Tasklet_VD(unsigned long Param)
2286 {
2287 if(g_IspInfo.DebugMask & ISP_DBG_TASKLET)
2288 {
2289 LOG_DBG("+");
2290 }
2291
2292 g_IspInfo.TimeLog.TaskletVd = ISP_JiffiesToMs(jiffies);
2293
2294 if(g_IspInfo.Callback[ISP_CALLBACK_TASKLET_VD].Func != NULL)
2295 {
2296 g_IspInfo.Callback[ISP_CALLBACK_TASKLET_VD].Func();
2297 }
2298 //
2299 if(g_IspInfo.HoldInfo.Time == ISP_HOLD_TIME_VD)
2300 {
2301 ISP_BufWrite_WriteToHw();
2302 }
2303 }
2304 DECLARE_TASKLET(IspTaskletVD, ISP_Tasklet_VD, 0);
2305
2306 /*******************************************************************************
2307 *
2308 ********************************************************************************/
2309 void ISP_Tasklet_EXPDONE(unsigned long Param)
2310 {
2311 if(g_IspInfo.DebugMask & ISP_DBG_TASKLET)
2312 {
2313 LOG_DBG("+");
2314 }
2315
2316 g_IspInfo.TimeLog.TaskletExpdone = ISP_JiffiesToMs(jiffies);
2317
2318 if(g_IspInfo.Callback[ISP_CALLBACK_TASKLET_EXPDONE].Func != NULL)
2319 {
2320 g_IspInfo.Callback[ISP_CALLBACK_TASKLET_EXPDONE].Func();
2321 }
2322
2323 if(g_IspInfo.HoldInfo.Time == ISP_HOLD_TIME_EXPDONE)
2324 {
2325 ISP_BufWrite_WriteToHw();
2326 }
2327 }
2328 DECLARE_TASKLET(IspTaskletEXPDONE, ISP_Tasklet_EXPDONE, 0);
2329
2330 /*******************************************************************************
2331 *
2332 ********************************************************************************/
2333 void ISP_Tasklet_SENINF(unsigned long Param)
2334 {
2335 MUINT32 i;
2336
2337 if(g_IspInfo.DebugMask & ISP_DBG_TASKLET)
2338 {
2339 LOG_DBG("+");
2340 }
2341
2342 g_IspInfo.TimeLog.TaskletSeninf= ISP_JiffiesToMs(jiffies);
2343
2344 //SeninfOverrunDump();
2345
2346 LOG_DBG("SENINF_OVERRUN\n");
2347 for(i = 0; i < 20; i++)
2348 {
2349 LOG_DBG("(0x%08x,0x%08x)\n",g_seninfDebug[i].regVal_1,g_seninfDebug[i].regVal_2);
2350 }
2351 }
2352 DECLARE_TASKLET(IspTaskletSENIF, ISP_Tasklet_SENINF, 0);
2353
2354
2355 /*******************************************************************************
2356 *
2357 ********************************************************************************/
2358 static MINT32 ISP_WriteReg(ISP_REG_IO_STRUCT *pRegIo)
2359 {
2360 MINT32 Ret = 0;
2361 MINT32 TimeVd = 0;
2362 MINT32 TimeExpdone = 0;
2363 MINT32 TimeTasklet = 0;
2364 MUINT8 *pData = NULL;
2365
2366 if(g_IspInfo.DebugMask & ISP_DBG_WRITE_REG)
2367 {
2368 LOG_DBG("Data(0x%08X), Count(%d)", (MUINT32)(pRegIo->Data), (MUINT32)(pRegIo->Count));
2369 }
2370
2371 if(atomic_read(&(g_IspInfo.HoldInfo.HoldEnable)))
2372 {
2373 if(ISP_BufWrite_Add((pRegIo->Count)*sizeof(ISP_REG_STRUCT), (MUINT8*)(pRegIo->Data)))
2374 {
2375 //LOG_DBG("Add write buffer OK");
2376 }
2377 else
2378 {
2379 LOG_ERR("Add write buffer fail");
2380
2381 TimeVd = ISP_JiffiesToMs(jiffies)-g_IspInfo.TimeLog.Vd;
2382 TimeExpdone = ISP_JiffiesToMs(jiffies)-g_IspInfo.TimeLog.Expdone;
2383 TimeTasklet = ISP_JiffiesToMs(jiffies)-g_IspInfo.TimeLog.TaskletExpdone;
2384
2385 LOG_ERR("HoldTime(%d),VD(%d ms),Expdone(%d ms),Tasklet(%d ms)",g_IspInfo.HoldInfo.Time,TimeVd,TimeExpdone,TimeTasklet);
2386 ISP_BufWrite_Dump();
2387 ISP_DumpReg();
2388
2389 Ret = -EFAULT;
2390 goto EXIT;
2391 }
2392 }
2393 else
2394 {
2395 pData = (MUINT8*)kmalloc((pRegIo->Count)*sizeof(ISP_REG_STRUCT), GFP_ATOMIC);
2396 if(pData == NULL)
2397 {
2398 LOG_DBG("ERROR: kmalloc failed, (process, pid, tgid)=(%s, %d, %d)", current->comm, current->pid, current->tgid);
2399 Ret = -ENOMEM;
2400 }
2401 if(copy_from_user(pData, (MUINT8*)(pRegIo->Data), pRegIo->Count*sizeof(ISP_REG_STRUCT)) != 0)
2402 {
2403 LOG_ERR("copy_from_user failed");
2404 Ret = -EFAULT;
2405 goto EXIT;
2406 }
2407
2408 Ret = ISP_WriteRegToHw((ISP_REG_STRUCT *)pData,pRegIo->Count);
2409 }
2410
2411 EXIT:
2412
2413 if(pData != NULL)
2414 {
2415 kfree(pData);
2416 pData = NULL;
2417 }
2418 return Ret;
2419 }
2420
2421 /*******************************************************************************
2422 *
2423 ********************************************************************************/
2424 static MINT32 ISP_SetHoldTime(ISP_HOLD_TIME_ENUM HoldTime)
2425 {
2426 LOG_DBG("HoldTime(%d)", HoldTime);
2427 g_IspInfo.HoldInfo.Time = HoldTime;
2428
2429 return 0;
2430 }
2431
2432 /*******************************************************************************
2433 *
2434 ********************************************************************************/
2435 static MINT32 ISP_ResetBuf(MVOID)
2436 {
2437 LOG_DBG("hold_reg(%d), BufAmount(%d)", atomic_read(&(g_IspInfo.HoldInfo.HoldEnable)), ISP_BufWrite_GetAmount());
2438
2439 ISP_BufWrite_Reset();
2440 atomic_set(&(g_IspInfo.HoldInfo.HoldEnable), 0);
2441 atomic_set(&(g_IspInfo.HoldInfo.WriteEnable), 0);
2442
2443 LOG_DBG("-");
2444 return 0;
2445 }
2446
2447 /*******************************************************************************
2448 *
2449 ********************************************************************************/
2450 static MINT32 ISP_EnableHoldReg(MBOOL En)
2451 {
2452 MINT32 Ret = 0;
2453 MUINT32 BufAmount = 0;
2454
2455 if(g_IspInfo.DebugMask & ISP_DBG_HOLD_REG)
2456 {
2457 LOG_DBG("En(%d), HoldEnable(%d)", En, atomic_read(&(g_IspInfo.HoldInfo.HoldEnable)));
2458 }
2459
2460 if(!spin_trylock_bh(&(g_IspInfo.SpinLockHold)))
2461 {
2462 // Should wait until tasklet done.
2463 MINT32 Timeout;
2464 MINT32 IsLock = 0;
2465
2466 if(g_IspInfo.DebugMask & ISP_DBG_TASKLET)
2467 {
2468 LOG_DBG("Start wait");
2469 }
2470
2471 Timeout = wait_event_interruptible_timeout(g_IspInfo.WaitQueueHead,
2472 (IsLock = spin_trylock_bh(&(g_IspInfo.SpinLockHold))),
2473 ISP_MsToJiffies(500));
2474
2475 if(g_IspInfo.DebugMask & ISP_DBG_TASKLET)
2476 {
2477 LOG_DBG("End wait ");
2478 }
2479
2480 if(IsLock == 0)
2481 {
2482 LOG_ERR("Should not happen, Timeout & IsLock is 0");
2483 Ret = -EFAULT;
2484 goto EXIT;
2485 }
2486 }
2487
2488 // Here we get the lock.
2489 if(En == MFALSE)
2490 {
2491 ISP_BufWrite_SetReady();
2492 BufAmount = ISP_BufWrite_GetAmount();
2493
2494 if(BufAmount)
2495 {
2496 atomic_set(&(g_IspInfo.HoldInfo.WriteEnable), 1);
2497 }
2498 }
2499
2500 if(g_IspInfo.DebugMask & ISP_DBG_HOLD_REG)
2501 {
2502 LOG_DBG("En(%d), HoldEnable(%d), BufAmount(%d)", En, atomic_read(&(g_IspInfo.HoldInfo.HoldEnable)),BufAmount);
2503 }
2504
2505 atomic_set(&(g_IspInfo.HoldInfo.HoldEnable), En);
2506
2507 spin_unlock_bh(&(g_IspInfo.SpinLockHold));
2508
2509 EXIT:
2510 return Ret;
2511 }
2512
2513 /*******************************************************************************
2514 *
2515 ********************************************************************************/
2516 static long ISP_REF_CNT_CTRL_FUNC(MUINT32 Param)
2517 {
2518 MINT32 Ret = 0;
2519 ISP_REF_CNT_CTRL_STRUCT ref_cnt_ctrl;
2520 MINT32 imem_ref_cnt = 0;
2521
2522 // add lock here
2523 //spin_lock_irq(&(g_IspInfo.SpinLock));
2524
2525 if(g_IspInfo.DebugMask & ISP_DBG_REF_CNT_CTRL)
2526 {
2527 LOG_DBG("+");
2528 }
2529
2530 if (NULL == (void*)Param)
2531 {
2532 LOG_ERR("NULL Param");
2533 // add unlock here
2534 //spin_unlock_irqrestore(&(g_IspInfo.SpinLock), flags);
2535
2536 return -EFAULT;
2537 }
2538
2539 if(copy_from_user(&ref_cnt_ctrl, (void*)Param, sizeof(ISP_REF_CNT_CTRL_STRUCT)) == 0)
2540 {
2541 if(g_IspInfo.DebugMask & ISP_DBG_REF_CNT_CTRL)
2542 {
2543 LOG_DBG("ctrl(%d),id(%d)",ref_cnt_ctrl.ctrl,ref_cnt_ctrl.id);
2544 }
2545
2546 if(ISP_REF_CNT_ID_MAX > ref_cnt_ctrl.id )
2547 {
2548 // lock here
2549 spin_lock(&(g_IspInfo.SpinLockIspRef));
2550
2551 switch(ref_cnt_ctrl.ctrl)
2552 {
2553 case ISP_REF_CNT_GET:
2554 break;
2555 case ISP_REF_CNT_INC:
2556 atomic_inc(&g_imem_ref_cnt[ref_cnt_ctrl.id]);
2557 //g_imem_ref_cnt++;
2558 break;
2559 case ISP_REF_CNT_DEC:
2560 case ISP_REF_CNT_DEC_AND_RESET_IF_LAST_ONE:
2561 atomic_dec(&g_imem_ref_cnt[ref_cnt_ctrl.id]);
2562 //g_imem_ref_cnt--;
2563 break;
2564 default:
2565 case ISP_REF_CNT_MAX: // Add this to remove build warning.
2566 // Do nothing.
2567 break;
2568 }
2569
2570 imem_ref_cnt = (MINT32)atomic_read(&g_imem_ref_cnt[ref_cnt_ctrl.id]);
2571 LOG_DBG("g_imem_ref_cnt[%d]: %d.", ref_cnt_ctrl.id, imem_ref_cnt);
2572
2573 if((imem_ref_cnt == 0) && (ref_cnt_ctrl.ctrl == ISP_REF_CNT_DEC_AND_RESET_IF_LAST_ONE) ) // No user left and ctrl is RESET_IF_LAST_ONE, do ISP reset.
2574 {
2575 ISP_Reset();
2576 LOG_DBG("ISP_REF_CNT_DEC_AND_RESET_IF_LAST_ONE. Do ISP_Reset");
2577 }
2578
2579 // unlock here
2580 spin_unlock(&(g_IspInfo.SpinLockIspRef));
2581
2582 if(g_IspInfo.DebugMask & ISP_DBG_REF_CNT_CTRL)
2583 {
2584 LOG_DBG("ref_cnt(%d)",imem_ref_cnt);
2585 }
2586
2587 if(copy_to_user((void*)ref_cnt_ctrl.data_ptr, &imem_ref_cnt, sizeof(MINT32)) != 0)
2588 {
2589 LOG_ERR("[GET]:copy_to_user failed");
2590 Ret = -EFAULT;
2591 }
2592 }
2593 else
2594 {
2595 LOG_ERR("id(%d) exceed",ref_cnt_ctrl.id);
2596 Ret = -EFAULT;
2597 }
2598 }
2599 else
2600 {
2601 LOG_ERR("copy_from_user failed");
2602 Ret = -EFAULT;
2603 }
2604
2605 if(g_IspInfo.DebugMask & ISP_DBG_REF_CNT_CTRL)
2606 {
2607 LOG_DBG("-");
2608 }
2609
2610 // add unlock here
2611 //spin_unlock_irqrestore(&(g_IspInfo.SpinLock), flags);
2612
2613 LOG_DBG("Ret(%d)", Ret);
2614 return Ret;
2615 }
2616
2617 /*******************************************************************************
2618 *
2619 ********************************************************************************/
2620 static MINT32 ISP_RTBC_ENQUE(MINT32 dma)
2621 {
2622 MINT32 Ret = 0;
2623 MINT32 rt_dma = dma;
2624 MUINT32 buffer_exist = 0;
2625 MUINT32 i = 0;
2626 MUINT32 index = 0;
2627
2628 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2629 {
2630 LOG_DBG("[rtbc][ENQUE]+");
2631 }
2632
2633 //check max
2634 if(ISP_RT_BUF_SIZE == g_pstRTBuf->ring_buf[rt_dma].total_count)
2635 {
2636 LOG_ERR("[rtbc][ENQUE]:real time buffer number FULL:rt_dma(%d)",rt_dma);
2637 Ret = -EFAULT;
2638 }
2639
2640 //spin_lock_irqsave(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
2641
2642 #if 0
2643 //check if buffer exist
2644 for(i = 0; i < ISP_RT_BUF_SIZE; i++)
2645 {
2646 if(g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr == g_rt_buf_info.base_pAddr)
2647 {
2648 buffer_exist = 1;
2649 break;
2650 }
2651
2652 if(g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr == 0)
2653 {
2654 break;
2655 }
2656 }
2657 #endif
2658
2659 if(buffer_exist)
2660 {
2661 if(ISP_RTBC_BUF_EMPTY != g_pstRTBuf->ring_buf[rt_dma].data[i].bFilled)
2662 {
2663 g_pstRTBuf->ring_buf[rt_dma].data[i].bFilled = ISP_RTBC_BUF_EMPTY;
2664 g_pstRTBuf->ring_buf[rt_dma].empty_count++;
2665 index = i;
2666 }
2667
2668 //if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2669 //{
2670 LOG_DBG("[rtbc][ENQUE]:buffer_exist(%d),i(%d),PA(0x%x),bFilled(%d),empty(%d)",buffer_exist,
2671 i,
2672 g_rt_buf_info.base_pAddr,
2673 g_pstRTBuf->ring_buf[rt_dma].data[i].bFilled,
2674 g_pstRTBuf->ring_buf[rt_dma].empty_count);
2675 //}
2676
2677 }
2678 else
2679 {
2680 //overwrite oldest element if buffer is full
2681 if(g_pstRTBuf->ring_buf[rt_dma].total_count == ISP_RT_BUF_SIZE)
2682 {
2683 LOG_ERR("[rtbc][ENQUE]:buffer full(%d)",g_pstRTBuf->ring_buf[rt_dma].total_count);
2684 }
2685 else
2686 {
2687 //first time add
2688 index = g_pstRTBuf->ring_buf[rt_dma].total_count % ISP_RT_BUF_SIZE;
2689
2690 g_pstRTBuf->ring_buf[rt_dma].data[index].memID = g_rt_buf_info.memID;
2691 g_pstRTBuf->ring_buf[rt_dma].data[index].size = g_rt_buf_info.size;
2692 g_pstRTBuf->ring_buf[rt_dma].data[index].base_vAddr = g_rt_buf_info.base_vAddr;
2693 g_pstRTBuf->ring_buf[rt_dma].data[index].base_pAddr = g_rt_buf_info.base_pAddr;
2694 g_pstRTBuf->ring_buf[rt_dma].data[index].bFilled = ISP_RTBC_BUF_EMPTY;
2695
2696 g_pstRTBuf->ring_buf[rt_dma].total_count++;
2697 g_pstRTBuf->ring_buf[rt_dma].empty_count++;
2698
2699 //if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2700 //{
2701 LOG_DBG("[rtbc][ENQUE]:dma(%d),index(%d),PA(0x%x),empty(%d),total(%d)",rt_dma,
2702 index,
2703 g_pstRTBuf->ring_buf[rt_dma].data[index].base_pAddr,
2704 g_pstRTBuf->ring_buf[rt_dma].empty_count,
2705 g_pstRTBuf->ring_buf[rt_dma].total_count);
2706 //}
2707 }
2708 }
2709
2710 //count ==1 means DMA stalled already or NOT start yet
2711 if(1 == g_pstRTBuf->ring_buf[rt_dma].empty_count)
2712 {
2713 if(_imgo_ == rt_dma)
2714 {
2715 //set base_addr at beginning before VF_EN
2716 ISP_WR32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR,g_pstRTBuf->ring_buf[rt_dma].data[index].base_pAddr);
2717 }
2718 else
2719 {
2720 //set base_addr at beginning before VF_EN
2721 ISP_WR32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR,g_pstRTBuf->ring_buf[rt_dma].data[index].base_pAddr);
2722 }
2723
2724 //if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2725 //{
2726 LOG_DBG("[rtbc][ENQUE]:dma(%d),base_pAddr(0x%x),imgo(0x%x),img2o(0x%x),empty_count(%d)",rt_dma,
2727 g_pstRTBuf->ring_buf[rt_dma].data[index].base_pAddr,
2728 ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR),
2729 ISP_RD32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR),
2730 g_pstRTBuf->ring_buf[rt_dma].empty_count);
2731 //}
2732
2733 #if defined(_rtbc_use_cq0c_)
2734 //Do nothing
2735 #else
2736 MUINT32 reg_val = 0;
2737
2738 //disable FBC control to go on download
2739 if(_imgo_ == rt_dma)
2740 {
2741 reg_val = ISP_RD32(ISP_REG_ADDR_IMGO_FBC);
2742 reg_val &= ~0x4000;
2743 ISP_WR32(ISP_REG_ADDR_IMGO_FBC,reg_val);
2744 }
2745 else
2746 {
2747 reg_val = ISP_RD32(ISP_REG_ADDR_IMG2O_FBC);
2748 reg_val &= ~0x4000;
2749 ISP_WR32(ISP_REG_ADDR_IMG2O_FBC,reg_val);
2750 }
2751
2752 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2753 {
2754 LOG_DBG("[rtbc][ENQUE]:dma(%d),disable fbc:IMGO(0x%x),IMG2O(0x%x)",rt_dma,ISP_RD32(ISP_REG_ADDR_IMGO_FBC),ISP_RD32(ISP_REG_ADDR_IMG2O_FBC));
2755 }
2756 #endif
2757
2758 g_pstRTBuf->ring_buf[rt_dma].pre_empty_count = g_pstRTBuf->ring_buf[rt_dma].empty_count;
2759 }
2760
2761 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
2762
2763 if(g_IspInfo.DebugMask & ISP_DBG_INT)
2764 {
2765 LOG_DBG("[rtbc][ENQUE]:dma:(%d),start(%d),index(%d),empty_count(%d),base_pAddr(0x%x)",rt_dma,
2766 g_pstRTBuf->ring_buf[rt_dma].start,
2767 index,
2768 g_pstRTBuf->ring_buf[rt_dma].empty_count,
2769 g_pstRTBuf->ring_buf[rt_dma].data[index].base_pAddr);
2770 }
2771
2772 return Ret;
2773 }
2774
2775 /*******************************************************************************
2776 *
2777 ********************************************************************************/
2778 static MINT32 ISP_RTBC_DEQUE(MINT32 dma)
2779 {
2780 MINT32 Ret = 0;
2781 MINT32 rt_dma = dma;
2782 MUINT32 i=0;
2783 MUINT32 index = 0;
2784
2785 //spin_lock_irqsave(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
2786
2787 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2788 {
2789 LOG_DBG("[rtbc][DEQUE]+");
2790 }
2791 g_deque_buf.count = 0;
2792
2793 //in SOF, "start" is next buffer index
2794 for(i = 0; i < g_pstRTBuf->ring_buf[rt_dma].total_count; i++ )
2795 {
2796 index = ( g_pstRTBuf->ring_buf[rt_dma].start + i ) % g_pstRTBuf->ring_buf[rt_dma].total_count;
2797
2798 if(ISP_RTBC_BUF_FILLED == g_pstRTBuf->ring_buf[rt_dma].data[index].bFilled )
2799 {
2800 g_pstRTBuf->ring_buf[rt_dma].data[index].bFilled = ISP_RTBC_BUF_LOCKED;
2801 g_deque_buf.count= 1;
2802 break;
2803 }
2804 }
2805
2806 if(0 == g_deque_buf.count)
2807 {
2808 //queue buffer status
2809 LOG_DBG("[rtbc][DEQUE]:dma(%d),start(%d),total(%d),empty(%d), g_deque_buf.count(%d)",rt_dma,
2810 g_pstRTBuf->ring_buf[rt_dma].start,
2811 g_pstRTBuf->ring_buf[rt_dma].total_count,
2812 g_pstRTBuf->ring_buf[rt_dma].empty_count,
2813 g_deque_buf.count);
2814
2815 for(i = 0; i <= g_pstRTBuf->ring_buf[rt_dma].total_count - 1; i++)
2816 {
2817 LOG_DBG("[rtbc][DEQUE]Buf List:i(%d),memID(%d),size(0x%x),VA(0x%x),PA(0x%x),bFilled(%d)",i,
2818 g_pstRTBuf->ring_buf[rt_dma].data[i].memID,
2819 g_pstRTBuf->ring_buf[rt_dma].data[i].size,
2820 g_pstRTBuf->ring_buf[rt_dma].data[i].base_vAddr,
2821 g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr,
2822 g_pstRTBuf->ring_buf[rt_dma].data[i].bFilled);
2823 }
2824 }
2825
2826 if(g_deque_buf.count)
2827 {
2828 //Fill buffer head
2829 //"start" is current working index
2830 if(g_IspInfo.DebugMask & ISP_DBG_INT)
2831 {
2832 LOG_DBG("[rtbc][DEQUE]:rt_dma(%d),index(%d),empty(%d),total(%d)",rt_dma,
2833 index,
2834 g_pstRTBuf->ring_buf[rt_dma].empty_count,
2835 g_pstRTBuf->ring_buf[rt_dma].total_count);
2836 }
2837
2838 for(i = 0; i < g_deque_buf.count; i++)
2839 {
2840 g_deque_buf.data[i].memID = g_pstRTBuf->ring_buf[rt_dma].data[index+i].memID;
2841 g_deque_buf.data[i].size = g_pstRTBuf->ring_buf[rt_dma].data[index+i].size;
2842 g_deque_buf.data[i].base_vAddr = g_pstRTBuf->ring_buf[rt_dma].data[index+i].base_vAddr;
2843 g_deque_buf.data[i].base_pAddr = g_pstRTBuf->ring_buf[rt_dma].data[index+i].base_pAddr;
2844 g_deque_buf.data[i].timeStampS = g_pstRTBuf->ring_buf[rt_dma].data[index+i].timeStampS;
2845 g_deque_buf.data[i].timeStampUs = g_pstRTBuf->ring_buf[rt_dma].data[index+i].timeStampUs;
2846
2847 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2848 {
2849 LOG_DBG("[rtbc][DEQUE]:index(%d),PA(0x%x),memID(%d),size(0x%x),VA(0x%x)",index + i,
2850 g_deque_buf.data[i].base_pAddr,
2851 g_deque_buf.data[i].memID,
2852 g_deque_buf.data[i].size,
2853 g_deque_buf.data[i].base_vAddr);
2854 }
2855
2856 }
2857
2858 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2859 {
2860 LOG_DBG("[rtbc][DEQUE]-");
2861 }
2862
2863 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
2864 }
2865 else
2866 {
2867 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
2868 LOG_ERR("[rtbc][DEQUE]:no filled buffer");
2869 Ret = -EFAULT;
2870 }
2871
2872 return Ret;
2873 }
2874
2875 /*******************************************************************************
2876 *
2877 ********************************************************************************/
2878 static long ISP_Buf_CTRL_FUNC(MUINT32 Param)
2879 {
2880 MINT32 Ret = 0;
2881 MINT32 rt_dma;
2882 MUINT32 reg_val = 0;
2883 MUINT32 reg_val2 = 0;
2884 MUINT32 i = 0;
2885 MUINT32 iBuf = 0;
2886 MUINT32 size = 0;
2887 MUINT32 bWaitBufRdy = 0;
2888 ISP_BUFFER_CTRL_STRUCT rt_buf_ctrl;
2889 //MUINT32 buffer_exist = 0;
2890
2891 #if defined(_rtbc_use_cq0c_) // fix compile warning
2892
2893 CQ_RTBC_FBC imgo_fbc;
2894 CQ_RTBC_FBC img2o_fbc;
2895 volatile MUINT32 curr_pa = 0;
2896 #else
2897
2898 MINT32 Timeout = 1000; //ms
2899
2900 #endif
2901
2902
2903 if(NULL == g_pstRTBuf)
2904 {
2905 LOG_ERR("[rtbc]NULL g_pstRTBuf");
2906 return -EFAULT;
2907 }
2908
2909 if(copy_from_user(&rt_buf_ctrl, (void*)Param, sizeof(ISP_BUFFER_CTRL_STRUCT)) == 0)
2910 {
2911 rt_dma = rt_buf_ctrl.buf_id;
2912
2913 if(g_IspInfo.DebugMask & ISP_DBG_INT)
2914 {
2915 LOG_DBG("[rtbc]ctrl(0x%x),buf_id(0x%x),data_ptr(0x%x),ex_data_ptr(0x%x)",rt_buf_ctrl.ctrl,
2916 rt_buf_ctrl.buf_id,
2917 rt_buf_ctrl.data_ptr,
2918 rt_buf_ctrl.ex_data_ptr);
2919 }
2920
2921 if(_imgo_ != rt_dma && _img2o_ != rt_dma)
2922 {
2923 LOG_ERR("[rtbc]invalid dma channel(%d)",rt_dma);
2924 return -EFAULT;
2925 }
2926
2927 #if defined(_rtbc_use_cq0c_)
2928
2929 if((ISP_RT_BUF_CTRL_ENQUE == rt_buf_ctrl.ctrl) || \
2930 (ISP_RT_BUF_CTRL_EXCHANGE_ENQUE == rt_buf_ctrl.ctrl) || \
2931 (ISP_RT_BUF_CTRL_DEQUE == rt_buf_ctrl.ctrl) || \
2932 (ISP_RT_BUF_CTRL_IS_RDY == rt_buf_ctrl.ctrl))
2933 {
2934 imgo_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC);
2935 img2o_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC);
2936
2937 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2938 {
2939 LOG_DBG("[rtbc]:ctrl(%d),o(0x%x),2o(0x%x)",rt_buf_ctrl.ctrl,ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC),ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC));
2940 }
2941 }
2942 #endif
2943
2944 switch(rt_buf_ctrl.ctrl)
2945 {
2946 case ISP_RT_BUF_CTRL_ENQUE :
2947 case ISP_RT_BUF_CTRL_EXCHANGE_ENQUE :
2948 if(copy_from_user(&g_rt_buf_info, (void*)rt_buf_ctrl.data_ptr, sizeof(ISP_RT_BUF_INFO_STRUCT)) == 0)
2949 {
2950 reg_val = ISP_RD32((void *)ISP_REG_ADDR_TG_VF_CON);
2951 //reg_val2 = ISP_RD32(ISP_REG_ADDR_TG2_VF_CON);
2952
2953 //VF start already
2954 if((reg_val & 0x01) || (reg_val2 & 0x01))
2955 {
2956 #if defined(_rtbc_use_cq0c_)
2957
2958 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
2959 {
2960 LOG_DBG("[rtbc][ENQUE]:ex_data_ptr(0x%x)",rt_buf_ctrl.ex_data_ptr);
2961 }
2962
2963 if(0 != rt_buf_ctrl.ex_data_ptr)
2964 {
2965 if(copy_from_user(&g_ex_rt_buf_info, (void*)rt_buf_ctrl.ex_data_ptr, sizeof(ISP_RT_BUF_INFO_STRUCT)) == 0)
2966 {
2967 for(i = 0; i < ISP_RT_BUF_SIZE; i++)
2968 {
2969 if(g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr == g_rt_buf_info.base_pAddr)
2970 {
2971 g_oldImgoAddr = g_rt_buf_info.base_pAddr;
2972 LOG_DBG("[rtbc]dma(%d),old(%d),PA(0x%x),VA(0x%x)",rt_dma,
2973 i,
2974 g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr,
2975 g_pstRTBuf->ring_buf[rt_dma].data[i].base_vAddr);
2976
2977 g_newImgoAddr = g_ex_rt_buf_info.base_pAddr;
2978 g_pstRTBuf->ring_buf[rt_dma].data[i].memID = g_ex_rt_buf_info.memID;
2979 g_pstRTBuf->ring_buf[rt_dma].data[i].size = g_ex_rt_buf_info.size;
2980 g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr = g_ex_rt_buf_info.base_pAddr;
2981 g_pstRTBuf->ring_buf[rt_dma].data[i].base_vAddr = g_ex_rt_buf_info.base_vAddr;
2982
2983 LOG_DBG("[rtbc]dma(%d),new(%d),PA(0x%x),VA(0x%x)",rt_dma,
2984 i,
2985 g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr,
2986 g_pstRTBuf->ring_buf[rt_dma].data[i].base_vAddr);
2987
2988 //set imgo exchange buffer address to HW
2989 if(rt_dma == _imgo_)
2990 {
2991 curr_pa = ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR);
2992 LOG_DBG("[rtbc][EXG]o,curr_pa(0x%x),old(0x%x)",curr_pa,g_rt_buf_info.base_pAddr);
2993 LOG_DBG("[rtbc][EXG]o,NUM(0x%x),CNT(0x%x)",imgo_fbc.Bits.FB_NUM,imgo_fbc.Bits.FBC_CNT);
2994
2995 if((curr_pa == g_rt_buf_info.base_pAddr) &&
2996 (imgo_fbc.Bits.FB_NUM != 0) &&
2997 ((imgo_fbc.Bits.FB_NUM == imgo_fbc.Bits.FBC_CNT) || (imgo_fbc.Bits.FBC_CNT == (imgo_fbc.Bits.FB_NUM-1))))
2998 {
2999 ISP_WR32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR,g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr);
3000 }
3001 else // timing issue
3002 {
3003 g_oldImgoAddr = g_rt_buf_info.base_pAddr;
3004 g_newImgoAddr = g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr;
3005 LOG_DBG("[rtbc][EXG]o,g_old(0x%x),g_new(0x%x)",g_oldImgoAddr,g_newImgoAddr);
3006 }
3007 }
3008 else if(rt_dma == _img2o_)
3009 {
3010 curr_pa = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR);
3011 LOG_DBG("[rtbc][EXG]2o,curr_pa(0x%x),old(0x%x)",curr_pa,g_rt_buf_info.base_pAddr);
3012 LOG_DBG("[rtbc][EXG]2o,NUM(0x%x),CNT(0x%x)",img2o_fbc.Bits.FB_NUM,img2o_fbc.Bits.FBC_CNT);
3013
3014 if((curr_pa == g_rt_buf_info.base_pAddr) &&
3015 (img2o_fbc.Bits.FB_NUM != 0) &&
3016 ((img2o_fbc.Bits.FB_NUM == img2o_fbc.Bits.FBC_CNT) || (img2o_fbc.Bits.FBC_CNT == (img2o_fbc.Bits.FB_NUM-1))))
3017 {
3018 ISP_WR32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR,g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr);
3019 }
3020 else // timing issue
3021 {
3022 g_oldImg2oAddr = g_rt_buf_info.base_pAddr;
3023 g_newImg2oAddr = g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr;
3024 LOG_DBG("[rtbc][EXG]2o,g_old(0x%x),g_new(0x%x)",g_oldImg2oAddr,g_newImg2oAddr);
3025 }
3026 }
3027
3028 break;
3029 }
3030 }
3031 }
3032 }
3033
3034 //set RCN_INC = 1;
3035 //RCNT++
3036 //FBC_CNT--
3037 if(_imgo_ == rt_dma)
3038 {
3039 imgo_fbc.Bits.RCNT_INC = 1;
3040 ISP_WR32((void *)ISP_REG_ADDR_IMGO_FBC,imgo_fbc.Reg_val);
3041 }
3042 else if(_img2o_ == rt_dma)
3043 {
3044 img2o_fbc.Bits.RCNT_INC = 1;
3045 ISP_WR32((void *)ISP_REG_ADDR_IMG2O_FBC,img2o_fbc.Reg_val);
3046 }
3047
3048 //if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3049 //{
3050 LOG_DBG("[rtbc][ENQ]:dma(%d),P(0x%x),O(0x%x),2O(0x%x),fps(%d)us",rt_dma,
3051 g_rt_buf_info.base_pAddr,
3052 ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR),
3053 ISP_RD32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR),
3054 g_avg_frame_time);
3055 //}
3056 #else
3057
3058
3059 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3060 {
3061 LOG_DBG("[rtbc][ENQUE]+:wait enque done.(0x%x)(0x%x)",reg_val,reg_val2);
3062 }
3063
3064 //wait till enq done in SOF
3065 g_rtbc_enq_dma = rt_dma;
3066 g_EnqBuf = 1;
3067
3068 Timeout = wait_event_interruptible_timeout(g_IspInfo.WaitQueueHead,
3069 (0 == g_EnqBuf),
3070 ISP_MsToJiffies(Timeout));
3071
3072 if(Timeout == 0)
3073 {
3074 LOG_ERR("[rtbc][ENQUE]:timeout(%d)",g_EnqBuf);
3075 Ret = -EFAULT;
3076 }
3077
3078 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3079 {
3080 LOG_DBG("[rtbc][ENQUE]-:enque done");
3081 }
3082 #endif
3083 }
3084 else
3085 {
3086 ISP_RTBC_ENQUE(rt_dma);
3087 }
3088 }
3089 else
3090 {
3091 LOG_ERR("[rtbc][ENQUE]:copy_from_user fail");
3092 return -EFAULT;
3093 }
3094 break;
3095 case ISP_RT_BUF_CTRL_DEQUE :
3096 reg_val = ISP_RD32((void *)ISP_REG_ADDR_TG_VF_CON);
3097 //reg_val2 = ISP_RD32(ISP_REG_ADDR_TG2_VF_CON);
3098
3099 //VF start already
3100 if((reg_val & 0x01) || (reg_val2 & 0x01))
3101 {
3102
3103 #if defined(_rtbc_use_cq0c_)
3104
3105 g_deque_buf.count = 1;
3106
3107 iBuf = ( (_imgo_==rt_dma)?imgo_fbc.Bits.RCNT:img2o_fbc.Bits.RCNT ) - 1; //RCNT = [1,2,3,...]
3108
3109 for(i = 0; i < g_deque_buf.count; i++)
3110 {
3111 g_deque_buf.data[i].memID = g_pstRTBuf->ring_buf[rt_dma].data[iBuf+i].memID;
3112 g_deque_buf.data[i].size = g_pstRTBuf->ring_buf[rt_dma].data[iBuf+i].size;
3113 g_deque_buf.data[i].base_vAddr = g_pstRTBuf->ring_buf[rt_dma].data[iBuf+i].base_vAddr;
3114 g_deque_buf.data[i].base_pAddr = g_pstRTBuf->ring_buf[rt_dma].data[iBuf+i].base_pAddr;
3115 g_deque_buf.data[i].timeStampS = g_pstRTBuf->ring_buf[rt_dma].data[iBuf+i].timeStampS;
3116 g_deque_buf.data[i].timeStampUs = g_pstRTBuf->ring_buf[rt_dma].data[iBuf+i].timeStampUs;
3117
3118 //if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3119 //{
3120 LOG_DBG("[rtbc][DEQ]:T\"%d.%06d\",co(0x%08x),c2o(0x%08x),i(%d),iBuf+i(%d),V(0x%x),P(0x%x),O(0x%x),2O(0x%x)", \
3121 g_deque_buf.data[i].timeStampS,
3122 g_deque_buf.data[i].timeStampUs,
3123 imgo_fbc,
3124 img2o_fbc,
3125 i,
3126 iBuf+i,
3127 g_deque_buf.data[i].base_vAddr,
3128 g_deque_buf.data[i].base_pAddr,
3129 ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR),
3130 ISP_RD32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR));
3131 //}
3132
3133 //tstamp = g_deque_buf.data[i].timeStampS*1000000+g_deque_buf.data[i].timeStampUs;
3134 //if ( (0 != prv_tstamp) && (prv_tstamp >= tstamp) )
3135 //{
3136 if(0 != g_prv_tstamp_s )
3137 {
3138 if((g_prv_tstamp_s > g_deque_buf.data[i].timeStampS) ||
3139 ((g_prv_tstamp_s == g_deque_buf.data[i].timeStampS) && (g_prv_tstamp_us >= g_deque_buf.data[i].timeStampUs)))
3140 {
3141 LOG_ERR("[rtbc]TS rollback,prv\"%d.%06d\",cur\"%d.%06d\"",g_prv_tstamp_s,
3142 g_prv_tstamp_us,
3143 g_deque_buf.data[i].timeStampS,
3144 g_deque_buf.data[i].timeStampUs);
3145 }
3146 }
3147
3148 g_prv_tstamp_s = g_deque_buf.data[i].timeStampS;
3149 g_prv_tstamp_us = g_deque_buf.data[i].timeStampUs;
3150 //}
3151 }
3152
3153 #if 0
3154 LOG_DBG("+LARB in DEQUE,BWL(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X),220(0x%08X)/(0x%08X),0x14(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X)/(0x%08X)", \
3155 ISP_RD32(0xF0202000+0x204), \
3156 ISP_RD32(0xF0202000+0x20c), \
3157 ISP_RD32(0xF0202000+0x210), \
3158 ISP_RD32(0xF0202000+0x214), \
3159 ISP_RD32(0xF0202000+0x220), \
3160 ISP_RD32(0xF0202000+0x230), \
3161 ISP_RD32(SMI_LARB0+0x10), \
3162 ISP_RD32(SMI_LARB1+0x10), \
3163 ISP_RD32(SMI_LARB2+0x10), \
3164 ISP_RD32(SMI_LARB3+0x10), \
3165 ISP_RD32(SMI_LARB4+0x10));
3166 #endif
3167
3168 #else
3169
3170 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3171 {
3172 LOG_DBG("[rtbc][DEQUE]+:wait deque done.(0x%x)(0x%x)",reg_val,reg_val2);
3173 }
3174
3175 //wait till deq done in SOF
3176 g_rtbc_deq_dma = rt_dma;
3177 g_DeqBuf = 1;
3178
3179 Timeout = wait_event_interruptible_timeout(g_IspInfo.WaitQueueHead,
3180 (0 == g_DeqBuf),
3181 ISP_MsToJiffies(Timeout));
3182
3183 if(Timeout == 0)
3184 {
3185 LOG_ERR("[rtbc][DEQUE]:timeout(%d)",g_DeqBuf);
3186 LOG_ERR("ISP_IRQ_TYPE_INT:IrqStatus(0x%08X)",g_IspInfo.IrqInfo.Status[ISP_IRQ_TYPE_INT]);
3187 ISP_DumpReg();
3188 Ret = -EFAULT;
3189 }
3190
3191 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3192 {
3193 LOG_DBG("[rtbc][DEQUE]-:deque done");
3194 }
3195 #endif
3196 }
3197 else
3198 {
3199 ISP_RTBC_DEQUE(rt_dma);
3200 }
3201
3202 if(g_deque_buf.count )
3203 {
3204 if(copy_to_user((void*)rt_buf_ctrl.data_ptr, &g_deque_buf, sizeof(ISP_DEQUE_BUF_INFO_STRUCT)) != 0)
3205 {
3206 LOG_ERR("[rtbc][DEQUE]:copy_to_user failed");
3207 Ret = -EFAULT;
3208 }
3209 }
3210 else
3211 {
3212 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
3213 LOG_ERR("[rtbc][DEQUE]:no filled buffer");
3214 Ret = -EFAULT;
3215 }
3216 break;
3217 case ISP_RT_BUF_CTRL_IS_RDY:
3218 //spin_lock_irqsave(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
3219
3220 bWaitBufRdy = 1;
3221
3222 #if defined(_rtbc_use_cq0c_)
3223 bWaitBufRdy = ((_imgo_ == rt_dma) ? (imgo_fbc.Bits.FBC_CNT) : (img2o_fbc.Bits.FBC_CNT)) ? 0 : 1;
3224 #else
3225 for(i = 0; i <= g_pstRTBuf->ring_buf[rt_dma].total_count; i++)
3226 {
3227 if(ISP_RTBC_BUF_FILLED == g_pstRTBuf->ring_buf[rt_dma].data[i].bFilled)
3228 {
3229 bWaitBufRdy = 0;
3230 break;
3231 }
3232 }
3233 #endif
3234
3235 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3236 {
3237 LOG_DBG("[rtbc][IS_RDY]:bWaitBufRdy(%d)",bWaitBufRdy);
3238 }
3239
3240
3241 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
3242
3243 if(copy_to_user((void*)rt_buf_ctrl.data_ptr, &bWaitBufRdy, sizeof(MUINT32)) != 0)
3244 {
3245 LOG_ERR("[rtbc][IS_RDY]:copy_to_user failed");
3246 Ret = -EFAULT;
3247 }
3248
3249 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC), flags);
3250 break;
3251 case ISP_RT_BUF_CTRL_GET_SIZE:
3252 size = g_pstRTBuf->ring_buf[rt_dma].total_count;
3253
3254 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3255 {
3256 LOG_DBG("[rtbc][GET_SIZE]:rt_dma(%d)/size(%d)",rt_dma,size);
3257 }
3258
3259 if(copy_to_user((void*)rt_buf_ctrl.data_ptr, &size, sizeof(MUINT32)) != 0)
3260 {
3261 LOG_ERR("[rtbc][GET_SIZE]:copy_to_user failed");
3262 Ret = -EFAULT;
3263 }
3264 break;
3265 case ISP_RT_BUF_CTRL_CLEAR:
3266
3267 //if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3268 //{
3269 LOG_DBG("[rtbc][CLEAR]:rt_dma(%d)",rt_dma);
3270 //}
3271
3272 #if 0
3273 g_pstRTBuf->ring_buf[rt_dma].total_count= 0;
3274 g_pstRTBuf->ring_buf[rt_dma].start = 0;
3275 g_pstRTBuf->ring_buf[rt_dma].empty_count= 0;
3276 g_pstRTBuf->ring_buf[rt_dma].active = 0;
3277
3278 for (i=0;i<ISP_RT_BUF_SIZE;i++) {
3279 if ( g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr == g_rt_buf_info.base_pAddr ) {
3280 buffer_exist = 1;
3281 break;
3282 }
3283 //
3284 if ( g_pstRTBuf->ring_buf[rt_dma].data[i].base_pAddr == 0 ) {
3285 break;
3286 }
3287 }
3288 #else
3289 memset((char*)g_pstRTBuf,0x00,sizeof(ISP_RT_BUF_STRUCT));
3290 g_prv_tstamp_s = 0;
3291 g_prv_tstamp_us = 0;
3292
3293 g_sof_count = 0;
3294 g_start_time = 0;
3295 g_avg_frame_time = 0;
3296
3297 g_TempAddr = 0;
3298
3299 g_oldImgoAddr = DEFAULT_PA;
3300 g_newImgoAddr = DEFAULT_PA;
3301 g_oldImg2oAddr = DEFAULT_PA;
3302 g_newImg2oAddr = DEFAULT_PA;
3303
3304 #endif
3305 break;
3306 case ISP_RT_BUF_CTRL_MAX: // Add this to remove build warning
3307 break; // Do nothing
3308 }
3309 }
3310 else
3311 {
3312 LOG_ERR("[rtbc]copy_from_user failed");
3313 Ret = -EFAULT;
3314 }
3315
3316 return Ret;
3317 }
3318
3319 /*******************************************************************************
3320 *
3321 ********************************************************************************/
3322 static MINT32 ISP_SOF_Buf_Get(unsigned long long sec,unsigned long usec)
3323 {
3324 #if defined(_rtbc_use_cq0c_)
3325
3326 CQ_RTBC_FBC imgo_fbc;
3327 CQ_RTBC_FBC img2o_fbc;
3328 MUINT32 curr_imgo = 0; //(imgo_fbc.Bits.WCNT+imgo_fbc.Bits.FB_NUM-1)%imgo_fbc.Bits.FB_NUM; //[0,1,2,...]
3329 MUINT32 curr_img2o = 0; //(img2o_fbc.Bits.WCNT+img2o_fbc.Bits.FB_NUM-1)%img2o_fbc.Bits.FB_NUM; //[0,1,2,...]
3330 volatile MUINT32 curr_pa = 0;
3331 MUINT32 i = 0;
3332
3333 //====== Read FBC Register Value ======
3334
3335 imgo_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC);
3336 img2o_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC);
3337
3338 //====== Check Drop Frame Or Not ======
3339
3340 if(imgo_fbc.Bits.FB_NUM != imgo_fbc.Bits.FBC_CNT) //No drop
3341 {
3342 g_pstRTBuf->dropCnt = 0;
3343 }
3344 else //dropped
3345 {
3346 g_pstRTBuf->dropCnt = 1;
3347 }
3348
3349 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3350 {
3351 LOG_DBG("[rtbc]dropCnt(%d)",g_pstRTBuf->dropCnt);
3352 }
3353
3354 //No drop
3355 if(0 == g_pstRTBuf->dropCnt)
3356 {
3357 //verify write buffer
3358 curr_pa = ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR);
3359 if(g_TempAddr == curr_pa)
3360 {
3361 LOG_DBG("[WARNING]g_TempAddr:Last(0x%08X) == Cur(0x%08X)",g_TempAddr,curr_pa);
3362 //ISP_DumpReg();
3363 }
3364
3365 g_TempAddr = curr_pa;
3366
3367 //last update buffer index
3368 curr_imgo = imgo_fbc.Bits.WCNT - 1; //[0,1,2,...]
3369 //curr_img2o = img2o_fbc.Bits.WCNT - 1; //[0,1,2,...]
3370 curr_img2o = curr_imgo;
3371
3372 #if 1
3373
3374 //verify write buffer,once pass1_done lost, WCNT is untrustful.
3375 if(ISP_RT_CQ0C_BUF_SIZE < g_pstRTBuf->ring_buf[_imgo_].total_count)
3376 {
3377 LOG_ERR("[rtbc]buf cnt(%d)",g_pstRTBuf->ring_buf[_imgo_].total_count);
3378 g_pstRTBuf->ring_buf[_imgo_].total_count = ISP_RT_CQ0C_BUF_SIZE;
3379 }
3380
3381 if(curr_pa != g_pstRTBuf->ring_buf[_imgo_].data[curr_imgo].base_pAddr)
3382 {
3383 for(i = 0; i < g_pstRTBuf->ring_buf[_imgo_].total_count; i++)
3384 {
3385 if(curr_pa == g_pstRTBuf->ring_buf[_imgo_].data[i].base_pAddr)
3386 {
3387 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3388 {
3389 LOG_DBG("[rtbc]curr:old/new(%d/%d)",curr_imgo,i);
3390 }
3391
3392 curr_imgo = i;
3393 curr_img2o = i;
3394 break;
3395 }
3396 }
3397 }
3398 #endif
3399
3400 g_pstRTBuf->ring_buf[_imgo_].data[curr_imgo].timeStampS = sec;
3401 g_pstRTBuf->ring_buf[_imgo_].data[curr_imgo].timeStampUs = usec;
3402 g_pstRTBuf->ring_buf[_img2o_].data[curr_img2o].timeStampS = sec;
3403 g_pstRTBuf->ring_buf[_img2o_].data[curr_img2o].timeStampUs = usec;
3404
3405 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3406 {
3407 LOG_DBG("[rtbc]TStamp(%d.%06d),curr(%d),pa(0x%x/0x%x),o2o(0x%x/0x%x),fbc_o(0x%08x),fbc_2o(0x%08x),cq0c(0x%x)", \
3408 g_pstRTBuf->ring_buf[_imgo_].data[curr_imgo].timeStampS, \
3409 g_pstRTBuf->ring_buf[_imgo_].data[curr_imgo].timeStampUs, \
3410 curr_imgo, \
3411 g_pstRTBuf->ring_buf[_imgo_].data[curr_imgo].base_pAddr, \
3412 g_pstRTBuf->ring_buf[_img2o_].data[curr_imgo].base_pAddr, \
3413 ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR), \
3414 ISP_RD32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR), \
3415 imgo_fbc.Reg_val, \
3416 img2o_fbc.Reg_val, \
3417 ISP_RD32((void *)ISP_ADDR+0xBC) );
3418 }
3419 }
3420
3421 //frame time profile
3422 if(0 == g_sof_count)
3423 {
3424 g_start_time = sec*1000000+ usec; //us
3425 }
3426
3427 //calc once per senond
3428 if(1000000 < ((sec*1000000+ usec)- g_start_time))
3429 {
3430 if(0 != g_sof_count)
3431 {
3432 g_avg_frame_time = (sec*1000000+ usec)- g_start_time;
3433 g_avg_frame_time = (MUINT32)(g_avg_frame_time / g_sof_count) ;
3434 }
3435 g_sof_count = 0;
3436 }
3437 else
3438 {
3439 g_sof_count++;
3440 }
3441
3442 #else
3443
3444 MINT32 i, i_dma;
3445 MUINT32 pAddr = 0;
3446 MUINT32 dma_base_addr = 0;
3447 MUINT32 next = 0;
3448
3449 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3450 {
3451 LOG_DBG("[rtbc]E:fbc(0x%x/0x%x)/g_rtbcAAA(%d)",ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC),ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC),g_rtbcAAA++);
3452 }
3453
3454 //spin_lock_irqsave(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
3455
3456 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3457 {
3458 LOG_DBG("+:[rtbc]g_rtbcAAA(%d)",g_rtbcAAA++);
3459 }
3460
3461 for(i = 0; i <= 1; i++)
3462 {
3463 i_dma = (0 == i) ? _imgo_ : _img2o_;
3464 dma_base_addr = (_imgo_ == i_dma) ? ISP_REG_ADDR_IMGO_BASE_ADDR : ISP_REG_ADDR_IMG2O_BASE_ADDR;
3465
3466 //queue buffer status
3467 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3468 {
3469 LOG_DBG("[rtbc][SOF]:dma(%d),start(%d),total(%d),empty(%d) ", \
3470 i_dma,
3471 g_pstRTBuf->ring_buf[i_dma].start,
3472 g_pstRTBuf->ring_buf[i_dma].total_count,
3473 g_pstRTBuf->ring_buf[i_dma].empty_count);
3474
3475 for ( i=0;i<=g_pstRTBuf->ring_buf[i_dma].total_count-1;i++ )
3476 {
3477 LOG_DBG("[rtbc][SOF]Buf List:%d/%d/0x%x/0x%x/0x%x/%d/ ", \
3478 i, \
3479 g_pstRTBuf->ring_buf[i_dma].data[i].memID, \
3480 g_pstRTBuf->ring_buf[i_dma].data[i].size, \
3481 g_pstRTBuf->ring_buf[i_dma].data[i].base_vAddr, \
3482 g_pstRTBuf->ring_buf[i_dma].data[i].base_pAddr, \
3483 g_pstRTBuf->ring_buf[i_dma].data[i].bFilled);
3484 }
3485 }
3486
3487 //ring buffer get next buffer
3488 if( 0 == g_pstRTBuf->ring_buf[i_dma].empty_count)
3489 {
3490 //once if buffer put into queue between SOF and ISP_DONE.
3491 g_pstRTBuf->ring_buf[i_dma].active = MFALSE;
3492
3493 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3494 {
3495 LOG_DBG("[rtbc][SOF]:dma(%d)real time buffer number empty,start(%d) ",i_dma,g_pstRTBuf->ring_buf[i_dma].start);
3496 }
3497 }
3498 else
3499 {
3500 if(2 <= g_pstRTBuf->ring_buf[i_dma].empty_count)
3501 {
3502 //next buffer
3503 next = (g_pstRTBuf->ring_buf[i_dma].start+1)%g_pstRTBuf->ring_buf[i_dma].total_count;
3504 pAddr = g_pstRTBuf->ring_buf[i_dma].data[next].base_pAddr;
3505
3506 ISP_WR32(dma_base_addr, pAddr);
3507
3508 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3509 {
3510 LOG_DBG("[rtbc][SOF]:dma(%d),start(%d),empty(%d),next(%d),next_PA(0x%x) ", \
3511 i_dma,
3512 g_pstRTBuf->ring_buf[i_dma].start,
3513 g_pstRTBuf->ring_buf[i_dma].empty_count,
3514 next,
3515 pAddr);
3516 }
3517 }
3518 else
3519 {
3520 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3521 {
3522 LOG_DBG("[rtbc][SOF]:dma(%d)real time buffer number is running out ",i_dma);
3523 }
3524 }
3525
3526 //once if buffer put into queue between SOF and ISP_DONE.
3527 g_pstRTBuf->ring_buf[i_dma].active = MTRUE;
3528 }
3529 }
3530
3531 if(g_EnqBuf)
3532 {
3533 ISP_RTBC_ENQUE(g_rtbc_enq_dma);
3534 g_EnqBuf = 0;
3535 wake_up_interruptible(&g_IspInfo.WaitQueueHead);
3536 }
3537
3538 if (g_DeqBuf) {
3539 ISP_RTBC_DEQUE(g_rtbc_deq_dma);
3540 g_DeqBuf = 0;
3541 wake_up_interruptible(&g_IspInfo.WaitQueueHead);
3542 }
3543
3544 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL) {
3545 LOG_DBG("-:[rtbc]");
3546 }
3547
3548 g_pstRTBuf->state = ISP_RTBC_STATE_SOF;
3549
3550 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
3551 #endif
3552
3553 return 0;
3554 }
3555
3556 /*******************************************************************************
3557 *
3558 ********************************************************************************/
3559 #ifndef _rtbc_use_cq0c_
3560 static MINT32 ISP_DONE_Buf_Time(unsigned long long sec,unsigned long usec)
3561 {
3562 MINT32 i, i_dma;
3563 MUINT32 curr;
3564 MUINT32 reg_fbc;
3565 MUINT32 reg_val = 0;
3566
3567 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3568 {
3569 LOG_DBG("[rtbc]E:fbc(0x%x/0x%x)",ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC),ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC));
3570 }
3571
3572 #if 0
3573 if ( spin_trylock_bh(&(g_IspInfo.SpinLockRTBC)) ) {
3574 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL) {
3575 LOG_DBG("[rtbc]:unlock state");
3576 }
3577 }
3578 else {
3579 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL) {
3580 LOG_DBG("[rtbc]:locked state");
3581 }
3582 }
3583 #endif
3584
3585 //spin_lock_irqsave(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
3586
3587 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3588 {
3589 LOG_DBG("+:[rtbc]g_rtbcAAA(%d)",g_rtbcAAA++);
3590 }
3591
3592 for(i = 0; i <= 1; i++)
3593 {
3594 i_dma = (0 == i) ? _imgo_ : _img2o_;
3595 reg_fbc = (_imgo_ == i_dma) ? ISP_REG_ADDR_IMGO_FBC : ISP_REG_ADDR_IMG2O_FBC;
3596
3597 if(0 == g_pstRTBuf->ring_buf[i_dma].empty_count)
3598 {
3599 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3600 {
3601 LOG_DBG("[rtbc][DONE]:dma(%d)real time buffer number empty,start(%d)",i_dma,g_pstRTBuf->ring_buf[i_dma].start);
3602 }
3603
3604 continue;
3605 }
3606
3607 //once if buffer put into queue between SOF and ISP_DONE.
3608 if(MFALSE == g_pstRTBuf->ring_buf[i_dma].active)
3609 {
3610 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3611 {
3612 LOG_DBG("[rtbc][DONE] ERROR: missing SOF");
3613 }
3614
3615 continue;
3616 }
3617
3618 while(1)
3619 {
3620 MUINT32 loopCount = 0;
3621 curr = g_pstRTBuf->ring_buf[i_dma].start;
3622
3623 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3624 {
3625 LOG_DBG("i_dma(%d),curr(%d),bFilled(%d)",i_dma,
3626 curr,
3627 g_pstRTBuf->ring_buf[i_dma].data[curr].bFilled);
3628 }
3629
3630 if(g_pstRTBuf->ring_buf[i_dma].data[curr].bFilled == ISP_RTBC_BUF_EMPTY)
3631 {
3632 g_pstRTBuf->ring_buf[i_dma].data[curr].bFilled = ISP_RTBC_BUF_FILLED;
3633
3634 //start + 1
3635 g_pstRTBuf->ring_buf[i_dma].start = (curr + 1) % g_pstRTBuf->ring_buf[i_dma].total_count;
3636 g_pstRTBuf->ring_buf[i_dma].empty_count--;
3637 break;
3638 }
3639 else
3640 {
3641 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3642 {
3643 LOG_DBG("i_dma(%d),curr(%d),bFilled(%d) != ISP_RTBC_BUF_EMPTY",i_dma,
3644 curr,
3645 g_pstRTBuf->ring_buf[i_dma].data[curr].bFilled);
3646 }
3647
3648 //start + 1
3649 g_pstRTBuf->ring_buf[i_dma].start = (curr + 1) % g_pstRTBuf->ring_buf[i_dma].total_count;
3650 }
3651
3652 loopCount++;
3653 if(loopCount > g_pstRTBuf->ring_buf[i_dma].total_count)
3654 {
3655 LOG_ERR("Can't find empty dma(%d) buf in total_count(%d)",i_dma,g_pstRTBuf->ring_buf[i_dma].total_count);
3656 break;
3657 }
3658 }
3659
3660 //enable fbc to stall DMA
3661 if(0 == g_pstRTBuf->ring_buf[i_dma].empty_count)
3662 {
3663 if(_imgo_ == i_dma)
3664 {
3665 reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC);
3666 reg_val |= 0x4000;
3667 //ISP_WR32(ISP_REG_ADDR_IMGO_FBC,reg_val);
3668 }
3669 else
3670 {
3671 reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC);
3672 reg_val |= 0x4000;
3673 //ISP_WR32(ISP_REG_ADDR_IMG2O_FBC,reg_val);
3674 }
3675
3676 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3677 {
3678 LOG_DBG("[rtbc][DONE]:dma(%d),en fbc(0x%x) stalled DMA out",i_dma,ISP_RD32((void *)reg_fbc));
3679 }
3680 }
3681
3682 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3683 {
3684 LOG_DBG("[rtbc][DONE]:dma(%d),start(%d),empty(%d)",i_dma,
3685 g_pstRTBuf->ring_buf[i_dma].start,
3686 g_pstRTBuf->ring_buf[i_dma].empty_count);
3687 }
3688
3689 g_pstRTBuf->ring_buf[i_dma].data[curr].timeStampS = sec;
3690 g_pstRTBuf->ring_buf[i_dma].data[curr].timeStampUs = usec;
3691
3692 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3693 {
3694 LOG_DBG("[rtbc][DONE]:dma(%d),curr(%d),sec(%lld),usec(%ld) ", i_dma, curr, sec, usec);
3695 }
3696 }
3697
3698 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
3699 {
3700 LOG_DBG("-:[rtbc]");
3701 }
3702
3703 g_pstRTBuf->state = ISP_RTBC_STATE_DONE;
3704
3705 //spin_unlock_irqrestore(&(g_IspInfo.SpinLockRTBC),g_Flash_SpinLock);
3706
3707 return 0;
3708 }
3709
3710 #endif
3711
3712 /*******************************************************************************
3713 *
3714 ********************************************************************************/
3715 static MINT32 ISP_WaitIrq(ISP_WAIT_IRQ_STRUCT WaitIrq)
3716 {
3717 MINT32 Ret = 0, Timeout = WaitIrq.Timeout;
3718 MUINT32 i;
3719 unsigned long flags;
3720 MUINT32 startTimeS = 0, startTimeUS = 0;
3721 MUINT32 endTimeS = 0, endTimeUS = 0;
3722
3723 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3724 {
3725 LOG_DBG("Clear(%d),Type(%d),Status(0x%08X),Timeout(%d)",WaitIrq.Clear,
3726 WaitIrq.Type,
3727 WaitIrq.Status,
3728 WaitIrq.Timeout);
3729 }
3730
3731 if(WaitIrq.Clear == ISP_IRQ_CLEAR_WAIT)
3732 {
3733 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
3734 if(g_IspInfo.IrqInfo.Status[WaitIrq.Type] & WaitIrq.Status)
3735 {
3736 LOG_DBG("WARNING: Clear(%d), Type(%d): IrqStatus(0x%08X) has been cleared",WaitIrq.Clear,WaitIrq.Type,g_IspInfo.IrqInfo.Status[WaitIrq.Type] & WaitIrq.Status);
3737 g_IspInfo.IrqInfo.Status[WaitIrq.Type] &= (~WaitIrq.Status);
3738 }
3739 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
3740 }
3741 else if(WaitIrq.Clear == ISP_IRQ_CLEAR_ALL)
3742 {
3743 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
3744 LOG_DBG("WARNING: Clear(%d), Type(%d): IrqStatus(0x%08X) has been cleared",WaitIrq.Clear,WaitIrq.Type,g_IspInfo.IrqInfo.Status[WaitIrq.Type]);
3745 g_IspInfo.IrqInfo.Status[WaitIrq.Type] = 0;
3746 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
3747 }
3748
3749 #if ISP_IRQ_POLLING
3750
3751 ISP_IRQ_TYPE_ENUM IrqStatus[ISP_IRQ_TYPE_AMOUNT];
3752
3753 while(1)
3754 {
3755 IrqStatus[ISP_IRQ_TYPE_INT] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INT] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INT]));
3756 IrqStatus[ISP_IRQ_TYPE_DMA] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMA] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMA]));
3757 IrqStatus[ISP_IRQ_TYPE_INTB] = (ISP_RD32((void *)ISP_REG_ADDR_INTB_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTB]));
3758 IrqStatus[ISP_IRQ_TYPE_DMAB] = (ISP_RD32((void *)ISP_REG_ADDR_DMAB_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAB]));
3759 IrqStatus[ISP_IRQ_TYPE_INTC] = (ISP_RD32((void *)ISP_REG_ADDR_INTC_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTC]));
3760 IrqStatus[ISP_IRQ_TYPE_DMAC] = (ISP_RD32((void *)ISP_REG_ADDR_DMAC_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAC]));
3761 IrqStatus[ISP_IRQ_TYPE_INTX] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUSX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTX]));
3762 IrqStatus[ISP_IRQ_TYPE_DMAX] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INTX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAX]));
3763
3764 for(i = 0; i < ISP_IRQ_TYPE_AMOUNT; i++)
3765 {
3766 if(g_IspInfo.IrqInfo.ErrMask[i] & IrqStatus[i])
3767 {
3768 //LOG_ERR("Error IRQ, Type(%d), Status(0x%08X)",i,g_IspInfo.IrqInfo.ErrMask[i] & IrqStatus[i]);
3769 //TODO: Add error handler...
3770 }
3771
3772 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3773 {
3774 LOG_DBG("Type(%d), IrqStatus(0x%08X | 0x%08X)",i,g_IspInfo.IrqInfo.Status[i], IrqStatus[i]);
3775 //LOG_DBG("Mask(0x%08X), ErrMask(0x%08X)",g_IspInfo.IrqInfo.Mask[i], g_IspInfo.IrqInfo.ErrMask[i]);
3776 }
3777 g_IspInfo.IrqInfo.Status[i] |= (IrqStatus[i] & g_IspInfo.IrqInfo.Mask[i]);
3778 }
3779
3780 if((g_IspInfo.IrqInfo.Status[WaitIrq.Type] & WaitIrq.Status) == WaitIrq.Status || Timeout == 0)
3781 {
3782 break;
3783 }
3784
3785 mdelay(1);
3786 Timeout -= 1;
3787 }
3788
3789 #else
3790
3791 ISP_GetTime(&startTimeS, &startTimeUS);
3792
3793 Timeout = wait_event_interruptible_timeout(g_IspInfo.WaitQueueHead,
3794 ISP_GetIRQState(WaitIrq.Type, WaitIrq.Status),
3795 ISP_MsToJiffies(WaitIrq.Timeout));
3796 #endif
3797
3798 if(Timeout == 0)
3799 {
3800 ISP_GetTime(&endTimeS, &endTimeUS);
3801
3802 LOG_ERR("start(%u.%06u),end(%u.%06u)",startTimeS,startTimeUS,endTimeS,endTimeUS);
3803 LOG_ERR("Clear(%d),Type(%d),IrqStatus(0x%08X),WaitStatus(0x%08X),Timeout(%d)",WaitIrq.Clear,
3804 WaitIrq.Type,
3805 g_IspInfo.IrqInfo.Status[WaitIrq.Type],
3806 WaitIrq.Status,
3807 WaitIrq.Timeout);
3808
3809 if(WaitIrq.Type == ISP_IRQ_TYPE_INT && WaitIrq.Status == ISP_IRQ_INT_STATUS_AF_DON_ST)
3810 {
3811 //Do nothing.
3812 }
3813 else
3814 {
3815 ISP_DumpReg();
3816 }
3817
3818 Ret = -EFAULT;
3819 goto EXIT;
3820 }
3821
3822 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
3823
3824 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3825 {
3826 for(i = 0; i < ISP_IRQ_TYPE_AMOUNT; i++)
3827 {
3828 LOG_DBG("Type(%d), IrqStatus(0x%08X)",i,g_IspInfo.IrqInfo.Status[i]);
3829 }
3830 }
3831
3832 g_IspInfo.IrqInfo.Status[WaitIrq.Type] &= (~WaitIrq.Status);
3833
3834 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
3835
3836 //check CQ status, when pass2, pass2b, pass2c done
3837 if( WaitIrq.Status == ISP_IRQ_INT_STATUS_PASS2_DON_ST ||
3838 WaitIrq.Status == ISP_IRQ_INTB_STATUS_PASS2_DON_ST ||
3839 WaitIrq.Status == ISP_IRQ_INTC_STATUS_PASS2_DON_ST )
3840 {
3841 MUINT32 CQ_status;
3842 if(ISP_RD32((void *)(CAMINF_BASE + 0x4160))!=ISP_REG_ADDR_CTL_DBG_SET_CQ_STS)
3843 {
3844 LOG_WRN("0x4160 != 0x6000 !!!(0x%8x)",ISP_RD32((void *)(CAMINF_BASE + 0x4160)));
3845 ISP_WR32((void *)(CAMINF_BASE + 0x4160), 0x6000) ;
3846 }
3847
3848 CQ_status = ISP_RD32((void *)(CAMINF_BASE + 0x4164));
3849
3850 switch(WaitIrq.Type)
3851 {
3852 case ISP_IRQ_TYPE_INT:
3853 if((CQ_status & 0x0000000F) != 0x001)
3854 {
3855 LOG_ERR("CQ1 not idle dbg(0x%08x 0x%08x)",ISP_RD32((void *)(CAMINF_BASE + 0x4160)), CQ_status );
3856 }
3857 break;
3858 case ISP_IRQ_TYPE_INTB:
3859 if((CQ_status & 0x000000F0) != 0x010)
3860 {
3861 LOG_ERR("CQ2 not idle dbg(0x%08x 0x%08x)",ISP_RD32((void *)(CAMINF_BASE + 0x4160)), CQ_status );
3862 }
3863 break;
3864 case ISP_IRQ_TYPE_INTC:
3865 if((CQ_status & 0x00000F00) != 0x100)
3866 {
3867 LOG_ERR("CQ3 not idle dbg(0x%08x 0x%08x)",ISP_RD32((void *)(CAMINF_BASE + 0x4160)), CQ_status );
3868 }
3869 break;
3870 default:
3871 break;
3872 }
3873 }
3874
3875 EXIT:
3876 return Ret;
3877 }
3878
3879 #define _debug_dma_err_
3880 #if defined(_debug_dma_err_)
3881
3882 #define bit(x) (0x1<<(x))
3883
3884 MUINT32 DMA_ERR[3*12] = {
3885 bit(1) , 0xF50043A8, 0x00000011, //IMGI
3886 bit(2) , 0xF50043AC, 0x00000021, //IMGCI
3887 bit(4) , 0xF50043B0, 0x00000031, //LSCI
3888 bit(5) , 0xF50043B4, 0x00000051, //FLKI
3889 bit(6) , 0xF50043B8, 0x00000061, //LCEI
3890 bit(7) , 0xF50043BC, 0x00000071, //VIPI
3891 bit(8) , 0xF50043C0, 0x00000081, //VIP2I
3892 bit(9) , 0xF50043C4, 0x00000194, //IMGO
3893 bit(10), 0xF50043C8, 0x000001a4, //IMG2O
3894 bit(11), 0xF50043CC, 0x000001b4, //LCSO
3895 bit(12), 0xF50043D0, 0x000001c4, //ESFKO
3896 bit(13), 0xF50043D4, 0x000001d4, //AAO
3897 };
3898
3899 static void DMAErrHandler(void)
3900 {
3901 MUINT32 i = 0;
3902 MUINT32 err_ctrl = ISP_RD32(0xF50043A4);
3903 MUINT32 *pErr = DMA_ERR;
3904
3905 LOG_DBG("err_ctrl(0x%08x)", err_ctrl);
3906
3907 for(i = 0; i < 12; i++)
3908 {
3909 MUINT32 addr = 0;
3910 #if 1
3911 if(err_ctrl & (*pErr))
3912 {
3913 ISP_WR32(0xF5004160, pErr[2]);
3914 addr = pErr[1];
3915 LOG_DBG("(0x%08x,0x%08x),dbg(0x%08x, 0x%08x)",addr, ISP_RD32(addr),ISP_RD32(0xF5004160), ISP_RD32(0xF5004164));
3916 }
3917 #else
3918 addr = pErr[1];
3919 MUINT32 status = ISP_RD32( addr );
3920
3921 if( status & 0x0000FFFF )
3922 {
3923 ISP_WR32(0xF5004160, pErr[2]);
3924 addr = pErr[1];
3925
3926 LOG_DBG("(0x%08x, 0x%08x), dbg(0x%08x, 0x%08x)",
3927 addr, status,
3928 ISP_RD32(0xF5004160), ISP_RD32(0xF5004164));
3929 }
3930 #endif
3931 pErr = pErr + 3;
3932 }
3933 }
3934 #endif
3935
3936 /*******************************************************************************
3937 *
3938 ********************************************************************************/
3939 static __tcmfunc irqreturn_t ISP_Irq(MINT32 Irq, MVOID *DeviceId)
3940 {
3941 //LOG_DBG("- E.");
3942 MUINT32 i;
3943 MUINT32 IrqStatus[ISP_IRQ_TYPE_AMOUNT];
3944 MUINT32 IrqStatus_fbc_int;
3945 volatile MUINT32 tg_pa = 0;
3946 volatile MUINT32 sof_pa = 0;
3947 MUINT32 senifIntStA = 0, regVal = 0;
3948 CQ_RTBC_FBC imgo_fbc;
3949 CQ_RTBC_FBC img2o_fbc;
3950
3951 // Read irq status
3952 IrqStatus[ISP_IRQ_TYPE_INT] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INT] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INT]));
3953 IrqStatus[ISP_IRQ_TYPE_DMA] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMA] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMA]));
3954 IrqStatus[ISP_IRQ_TYPE_INTB] = (ISP_RD32((void *)ISP_REG_ADDR_INTB_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTB]));
3955 IrqStatus[ISP_IRQ_TYPE_DMAB] = (ISP_RD32((void *)ISP_REG_ADDR_DMAB_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAB]));
3956 IrqStatus[ISP_IRQ_TYPE_INTC] = (ISP_RD32((void *)ISP_REG_ADDR_INTC_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTC]));
3957 IrqStatus[ISP_IRQ_TYPE_DMAC] = (ISP_RD32((void *)ISP_REG_ADDR_DMAC_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAC]));
3958
3959 //below may need to read elsewhere
3960 IrqStatus[ISP_IRQ_TYPE_INTX] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUSX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTX]));
3961 IrqStatus[ISP_IRQ_TYPE_DMAX] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INTX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAX]));
3962 IrqStatus_fbc_int = ISP_RD32((void *)(ISP_ADDR + 0xFC));
3963
3964 spin_lock(&(g_IspInfo.SpinLockIrq));
3965
3966 for(i = 0; i < ISP_IRQ_TYPE_AMOUNT; i++)
3967 {
3968 if(g_IspInfo.IrqInfo.ErrMask[i] & IrqStatus[i])
3969 {
3970 // ISP_IRQ_INTX_STATUS_IMGO_ERR_ST: on-the-fly imgo error, not really overrun
3971 if(i != ISP_IRQ_TYPE_INTX || ( g_IspInfo.IrqInfo.ErrMask[i] & IrqStatus[i] & (~ISP_IRQ_INTX_STATUS_IMGO_ERR_ST)))
3972 {
3973 if(i != ISP_IRQ_TYPE_INTX ) //to reduce isp log
3974 {
3975 LOG_DBG("Error IRQ, Type(%d), Status(0x%08X)",i,g_IspInfo.IrqInfo.ErrMask[i] & IrqStatus[i]);
3976 }
3977 //TODO: Add error handler...
3978 }
3979 }
3980
3981 if(g_IspInfo.DebugMask & ISP_DBG_INT)
3982 {
3983 LOG_DBG("Type(%d), IrqStatus(0x%08X | 0x%08X)",i,g_IspInfo.IrqInfo.Status[i], IrqStatus[i]);
3984 }
3985 g_IspInfo.IrqInfo.Status[i] |= (IrqStatus[i] & g_IspInfo.IrqInfo.Mask[i]);
3986 }
3987
3988
3989 #if defined(OVERRUN_AEE_WARNING)
3990
3991 if(IrqStatus[ISP_IRQ_TYPE_INT] & ISP_IRQ_INT_STATUS_TG1_ERR_ST)
3992 {
3993 senifIntStA = ISP_RD32((void *)(ISP_ADDR + 0x4018));
3994 if(senifIntStA & 0x01)
3995 {
3996 regVal= ISP_RD32((void *)(ISP_ADDR + 0x414));
3997 if(regVal & 0x01)
3998 {
3999 LOG_DBG("sensor overrun,4024(0x%08x),8018(0x%08x)",IrqStatus[ISP_IRQ_TYPE_INT],senifIntStA);
4000
4001 LOG_DBG("8014(0x%08x),8018(0x%08x)",ISP_RD32((void *)(ISP_ADDR + 0x4014)),ISP_RD32((void *)(ISP_ADDR + 0x4018)));
4002 LOG_DBG("4004(0x%08x),4008(0x%08x)",ISP_RD32((void *)(ISP_ADDR + 0x4)),ISP_RD32((void *)(ISP_ADDR + 0x8)));
4003 LOG_DBG("400C(0x%08x),4414(0x%08x)",ISP_RD32((void *)(ISP_ADDR + 0xC)),ISP_RD32((void *)(ISP_ADDR + 0x414)));
4004 LOG_DBG("4020(0x%08x),4024(0x%08x)",ISP_RD32((void *)(ISP_ADDR + 0x20)),ISP_RD32((void *)(ISP_ADDR + 0x24))); // 0x4024 is read clear
4005
4006 DMAErrHandler();
4007 SeninfOverrunDump();
4008
4009 schedule_work(&g_IspInfo.ScheduleWorkSENINF);
4010 tasklet_schedule(&IspTaskletSENIF);
4011
4012 aee_kernel_warning_api(__FILE__, __LINE__, DB_OPT_DEFAULT, "CAMERA", "SENIF FIFO overrun/underrun");
4013 }
4014 }
4015 }
4016 #endif
4017
4018 //[MT]ToDo: Need to Check
4019 /*if ( IrqStatus[ISP_IRQ_TYPE_INTX]&ISP_IRQ_INTX_STATUS_DMA_ERR_ST ) {
4020
4021 #if defined(_debug_dma_err_)
4022 LOG_ERR("[rtbc]StatusX(0x%08X), DMA_ERR",IrqStatus[ISP_IRQ_TYPE_INTX]); //IMGO may overrun before setting smi regs
4023
4024 //allan
4025 DMAErrHandler();
4026
4027 LOG_DBG("ERR (8018 0x%08x)(8024 0x%08x)(802C 0x%08x)(4440 0x%08x) (810C 0x%08x)",
4028 ISP_RD32(0xF5008018),
4029 ISP_RD32(0xF5008024),
4030 ISP_RD32(0xF500802C),
4031 ISP_RD32(0xF5004440),
4032 ISP_RD32(0xF500810C));
4033 #endif
4034
4035 }*/
4036 //
4037 //if ( IrqStatus[ISP_IRQ_TYPE_INT]&ISP_IRQ_INT_STATUS_TG1_ERR_ST ||
4038 // IrqStatus[ISP_IRQ_TYPE_INT]&ISP_IRQ_INT_STATUS_TG2_ERR_ST ) {
4039 // LOG_ERR("[rtbc]Status(0x%08X), TG_ERR",IrqStatus[ISP_IRQ_TYPE_INT]);
4040 //}
4041 //
4042 //if (IrqStatus_fbc_int) {
4043 // LOG_ERR("[rtbc]dropframe st(0x%08X),co(0x%08X),c2o(0x%08X)",IrqStatus_fbc_int,ISP_RD32(ISP_REG_ADDR_IMGO_FBC),ISP_RD32(ISP_REG_ADDR_IMG2O_FBC));
4044 //}
4045
4046 spin_unlock(&(g_IspInfo.SpinLockIrq));
4047
4048 //service pass1_done first once if SOF/PASS1_DONE are coming together.
4049 //get time stamp
4050 //push hw filled buffer to sw list
4051 if(IrqStatus[ISP_IRQ_TYPE_INT] & ISP_IRQ_INT_STATUS_PASS1_TG1_DON_ST)
4052 {
4053 #if defined(_rtbc_use_cq0c_)
4054
4055 if(g_IspInfo.DebugMask & ISP_DBG_BUF_CTRL)
4056 {
4057 LOG_DBG("[rtbc]:PASS1_TG1_DON");
4058 }
4059
4060 //set imgo exchange buffer address to HW
4061 imgo_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC);
4062 tg_pa = ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR);
4063
4064 if( g_newImgoAddr != DEFAULT_PA &&
4065 (tg_pa == g_oldImgoAddr) &&
4066 (imgo_fbc.Bits.FB_NUM != 0) &&
4067 ((imgo_fbc.Bits.FB_NUM == imgo_fbc.Bits.FBC_CNT) || (imgo_fbc.Bits.FBC_CNT == (imgo_fbc.Bits.FB_NUM-1))))
4068 {
4069 LOG_DBG("[rtbc][TG1_DON]o,tg_pa(0x%x),old(0x%x)",tg_pa,g_oldImgoAddr);
4070 LOG_DBG("[rtbc][TG1_DON]o,NUM(0x%x),CNT(0x%x)",imgo_fbc.Bits.FB_NUM,imgo_fbc.Bits.FBC_CNT);
4071 LOG_DBG("[rtbc][TG1_DON]o,new(0x%x)",g_newImgoAddr);
4072 ISP_WR32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR,g_newImgoAddr);
4073 g_oldImgoAddr = DEFAULT_PA;
4074 g_newImgoAddr = DEFAULT_PA;
4075 }
4076
4077 img2o_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC);
4078 tg_pa = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR);
4079
4080 if(g_newImg2oAddr != DEFAULT_PA &&
4081 (tg_pa == g_oldImg2oAddr) &&
4082 (img2o_fbc.Bits.FB_NUM != 0) &&
4083 ((img2o_fbc.Bits.FB_NUM == img2o_fbc.Bits.FBC_CNT) || (img2o_fbc.Bits.FBC_CNT == (img2o_fbc.Bits.FB_NUM-1))))
4084 {
4085 LOG_DBG("[rtbc][TG1_DON]2o,tg_pa(0x%x),old(0x%x)",tg_pa,g_oldImg2oAddr);
4086 LOG_DBG("[rtbc][TG1_DON]2o,NUM(0x%x),CNT(0x%x)",img2o_fbc.Bits.FB_NUM,img2o_fbc.Bits.FBC_CNT);
4087 LOG_DBG("[rtbc][TG1_DON]2o,new(0x%x)",g_newImg2oAddr);
4088 ISP_WR32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR,g_newImg2oAddr);
4089 g_oldImg2oAddr = DEFAULT_PA;
4090 g_newImg2oAddr = DEFAULT_PA;
4091 }
4092 #else
4093 //LOG_DBG("[k_js_test]Pass1_done(0x%x)",IrqStatus[ISP_IRQ_TYPE_INT]);
4094 unsigned long long sec;
4095 unsigned long usec;
4096
4097 sec = cpu_clock(0); //ns
4098 do_div( sec, 1000 ); //usec
4099 usec = do_div( sec, 1000000); //sec and usec
4100
4101 ISP_DONE_Buf_Time(sec,usec);
4102 /*Check Timesamp reverse*/
4103 //what's this?
4104 #endif
4105
4106 g_sof_pass1done = 0;
4107 }
4108
4109 //switch pass1 WDMA buffer
4110 //fill time stamp for cq0c
4111 if(IrqStatus[ISP_IRQ_TYPE_INT] & ISP_IRQ_INT_STATUS_SOF1_INT_ST)
4112 {
4113 unsigned long long sec;
4114 unsigned long usec;
4115 ktime_t time;
4116 #if 1
4117 time = ktime_get(); //ns
4118 sec = time.tv64;
4119 #else
4120 sec = cpu_clock(0); //ns
4121 #endif
4122
4123 //set imgo exchange buffer address to HW
4124 imgo_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMGO_FBC);
4125 sof_pa = ISP_RD32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR);
4126
4127 if((sof_pa != 0) && (sof_pa == g_oldImgoAddr) && g_newImgoAddr != DEFAULT_PA &&
4128 (imgo_fbc.Bits.FB_NUM != 0) &&
4129 ((imgo_fbc.Bits.FB_NUM == imgo_fbc.Bits.FBC_CNT) || (imgo_fbc.Bits.FBC_CNT == (imgo_fbc.Bits.FB_NUM-1))))
4130 {
4131 LOG_DBG("[rtbc][SOF]o,sof_pa(0x%x),old(0x%x)",sof_pa,g_oldImgoAddr);
4132 LOG_DBG("[rtbc][SOF]o,NUM(0x%x),CNT(0x%x)",imgo_fbc.Bits.FB_NUM,imgo_fbc.Bits.FBC_CNT);
4133 LOG_DBG("[rtbc][SOF]o,new(0x%x)",g_newImgoAddr);
4134
4135 ISP_WR32((void *)ISP_REG_ADDR_IMGO_BASE_ADDR,g_newImgoAddr);
4136 g_oldImgoAddr = DEFAULT_PA;
4137 g_newImgoAddr = DEFAULT_PA;
4138 }
4139
4140 img2o_fbc.Reg_val = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_FBC);
4141 sof_pa = ISP_RD32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR);
4142
4143 if((sof_pa != 0) && (sof_pa == g_oldImg2oAddr) && g_newImg2oAddr != DEFAULT_PA &&
4144 (img2o_fbc.Bits.FB_NUM != 0) &&
4145 ((img2o_fbc.Bits.FB_NUM == img2o_fbc.Bits.FBC_CNT) || (img2o_fbc.Bits.FBC_CNT == (img2o_fbc.Bits.FB_NUM-1))))
4146 {
4147 LOG_DBG("[rtbc][SOF]2o,sof_pa(0x%x),old(0x%x)",sof_pa,g_oldImg2oAddr);
4148 LOG_DBG("[rtbc][SOF]2o,NUM(0x%x),CNT(0x%x)",img2o_fbc.Bits.FB_NUM,img2o_fbc.Bits.FBC_CNT);
4149 LOG_DBG("[rtbc][SOF]2o,new(0x%x)",sof_pa,g_newImg2oAddr);
4150
4151 ISP_WR32((void *)ISP_REG_ADDR_IMG2O_BASE_ADDR,g_newImg2oAddr);
4152 g_oldImg2oAddr = DEFAULT_PA;
4153 g_newImg2oAddr = DEFAULT_PA;
4154 }
4155
4156 do_div( sec, 1000 ); //usec
4157 usec = do_div( sec, 1000000); //sec and usec
4158
4159 ISP_SOF_Buf_Get(sec,usec);
4160
4161 if( g_sof_pass1done == 1 )
4162 {
4163 LOG_DBG("Lost pass1 done");
4164 }
4165 g_sof_pass1done = 1;
4166 }
4167
4168 wake_up_interruptible(&g_IspInfo.WaitQueueHead);
4169
4170 //Work queue. It is interruptible, so there can be "Sleep" in work queue function.
4171 if(IrqStatus[ISP_IRQ_TYPE_INT] & (ISP_IRQ_INT_STATUS_VS1_ST))//|ISP_IRQ_INT_STATUS_VS2_ST))
4172 {
4173 g_IspInfo.TimeLog.Vd = ISP_JiffiesToMs(jiffies);
4174 schedule_work(&g_IspInfo.ScheduleWorkVD);
4175 tasklet_schedule(&IspTaskletVD);
4176 }
4177
4178 //Tasklet. It is uninterrupted, so there can NOT be "Sleep" in tasklet function.
4179 if(IrqStatus[ISP_IRQ_TYPE_INT] & (ISP_IRQ_INT_STATUS_EXPDON1_ST))//|ISP_IRQ_INT_STATUS_EXPDON2_ST))
4180 {
4181 g_IspInfo.TimeLog.Expdone = ISP_JiffiesToMs(jiffies);
4182 schedule_work(&g_IspInfo.ScheduleWorkEXPDONE);
4183 tasklet_schedule(&IspTaskletEXPDONE);
4184 }
4185
4186 //LOG_DBG("- X.");
4187
4188 return IRQ_HANDLED;
4189 }
4190
4191 /*******************************************************************************
4192 *
4193 ********************************************************************************/
4194 static long ISP_ioctl(struct file *pFile,MUINT32 Cmd,unsigned long Param)
4195 {
4196 MINT32 Ret = 0;
4197 MBOOL HoldEnable = MFALSE;
4198 unsigned long flags;
4199 MUINT32 DebugFlag = 0,pid = 0;
4200 ISP_REG_IO_STRUCT RegIo;
4201 ISP_HOLD_TIME_ENUM HoldTime;
4202 ISP_WAIT_IRQ_STRUCT WaitIrq;
4203 ISP_READ_IRQ_STRUCT ReadIrq;
4204 ISP_CLEAR_IRQ_STRUCT ClearIrq;
4205 ISP_USER_INFO_STRUCT* pUserInfo;
4206
4207 if(pFile->private_data == NULL)
4208 {
4209 LOG_WRN("private_data is NULL,(process, pid, tgid)=(%s, %d, %d)",current->comm,current->pid,current->tgid);
4210 return -EFAULT;
4211 }
4212
4213 pUserInfo = (ISP_USER_INFO_STRUCT*)(pFile->private_data);
4214
4215 switch(Cmd)
4216 {
4217 case ISP_RESET:
4218 {
4219 spin_lock(&(g_IspInfo.SpinLockIsp));
4220 ISP_Reset();
4221 spin_unlock(&(g_IspInfo.SpinLockIsp));
4222 break;
4223 }
4224 case ISP_RESET_BUF:
4225 {
4226 spin_lock_bh(&(g_IspInfo.SpinLockHold));
4227 ISP_ResetBuf();
4228 spin_unlock_bh(&(g_IspInfo.SpinLockHold));
4229 break;
4230 }
4231 case ISP_READ_REGISTER:
4232 {
4233 if(copy_from_user(&RegIo, (void*)Param, sizeof(ISP_REG_IO_STRUCT)) == 0)
4234 {
4235 Ret = ISP_ReadReg(&RegIo);
4236 }
4237 else
4238 {
4239 LOG_ERR("copy_from_user failed");
4240 Ret = -EFAULT;
4241 }
4242 break;
4243 }
4244 case ISP_WRITE_REGISTER:
4245 {
4246 if(copy_from_user(&RegIo, (void*)Param, sizeof(ISP_REG_IO_STRUCT)) == 0)
4247 {
4248 Ret = ISP_WriteReg(&RegIo);
4249 }
4250 else
4251 {
4252 LOG_ERR("copy_from_user failed");
4253 Ret = -EFAULT;
4254 }
4255 break;
4256 }
4257 case ISP_HOLD_REG_TIME:
4258 {
4259 if(copy_from_user(&HoldTime, (void*)Param, sizeof(ISP_HOLD_TIME_ENUM)) == 0)
4260 {
4261 spin_lock(&(g_IspInfo.SpinLockIsp));
4262 Ret = ISP_SetHoldTime(HoldTime);
4263 spin_unlock(&(g_IspInfo.SpinLockIsp));
4264 }
4265 else
4266 {
4267 LOG_ERR("copy_from_user failed");
4268 Ret = -EFAULT;
4269 }
4270 break;
4271 }
4272 case ISP_HOLD_REG:
4273 {
4274 if(copy_from_user(&HoldEnable, (void*)Param, sizeof(MBOOL)) == 0)
4275 {
4276 Ret = ISP_EnableHoldReg(HoldEnable);
4277 }
4278 else
4279 {
4280 LOG_ERR("copy_from_user failed");
4281 Ret = -EFAULT;
4282 }
4283 break;
4284 }
4285 case ISP_WAIT_IRQ:
4286 {
4287 if(copy_from_user(&WaitIrq, (void*)Param, sizeof(ISP_WAIT_IRQ_STRUCT)) == 0)
4288 {
4289 if((WaitIrq.Type >= ISP_IRQ_TYPE_AMOUNT) ||(WaitIrq.Type<0))
4290 {
4291 Ret = -EFAULT;
4292 LOG_ERR("invalid type(%d)",WaitIrq.Type);
4293 goto EXIT;
4294 }
4295 Ret = ISP_WaitIrq(WaitIrq);
4296 }
4297 else
4298 {
4299 LOG_ERR("copy_from_user failed");
4300 Ret = -EFAULT;
4301 }
4302 break;
4303 }
4304 case ISP_READ_IRQ:
4305 {
4306 if(copy_from_user(&ReadIrq, (void*)Param, sizeof(ISP_READ_IRQ_STRUCT)) == 0)
4307 {
4308 LOG_DBG("ISP_READ_IRQ Type(%d)",ReadIrq.Type);
4309
4310 if((ReadIrq.Type >= ISP_IRQ_TYPE_AMOUNT) ||(ReadIrq.Type<0))
4311 {
4312 Ret = -EFAULT;
4313 LOG_ERR("invalid type(%d)",ReadIrq.Type);
4314 goto EXIT;
4315 }
4316
4317 #if ISP_IRQ_POLLING
4318
4319 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
4320
4321 ISP_IRQ_TYPE_ENUM IrqStatus[ISP_IRQ_TYPE_AMOUNT];
4322
4323 IrqStatus[ISP_IRQ_TYPE_INT] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INT] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INT]));
4324 IrqStatus[ISP_IRQ_TYPE_DMA] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMA] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMA]));
4325 IrqStatus[ISP_IRQ_TYPE_INTB] = (ISP_RD32((void *)ISP_REG_ADDR_INTB_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTB]));
4326 IrqStatus[ISP_IRQ_TYPE_DMAB] = (ISP_RD32((void *)ISP_REG_ADDR_DMAB_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAB]));
4327 IrqStatus[ISP_IRQ_TYPE_INTC] = (ISP_RD32((void *)ISP_REG_ADDR_INTC_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTC]));
4328 IrqStatus[ISP_IRQ_TYPE_DMAC] = (ISP_RD32((void *)ISP_REG_ADDR_DMAC_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAC]));
4329 IrqStatus[ISP_IRQ_TYPE_INTX] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUSX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTX]));
4330 IrqStatus[ISP_IRQ_TYPE_DMAX] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INTX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAX]));
4331
4332 for(i = 0; i < ISP_IRQ_TYPE_AMOUNT; i++)
4333 {
4334 g_IspInfo.IrqInfo.Status[i] |= (IrqStatus[i] & g_IspInfo.IrqInfo.Mask[i]);
4335 }
4336
4337 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
4338
4339 #endif
4340
4341 ReadIrq.Status = g_IspInfo.IrqInfo.Status[ReadIrq.Type];
4342
4343 if(copy_to_user((void*)Param, &ReadIrq, sizeof(ISP_READ_IRQ_STRUCT)) != 0)
4344 {
4345 LOG_ERR("copy_to_user failed");
4346 Ret = -EFAULT;
4347 }
4348 }
4349 else
4350 {
4351 LOG_ERR("copy_from_user failed");
4352 Ret = -EFAULT;
4353 }
4354 break;
4355 }
4356 case ISP_CLEAR_IRQ:
4357 {
4358 if(copy_from_user(&ClearIrq, (void*)Param, sizeof(ISP_CLEAR_IRQ_STRUCT)) == 0)
4359 {
4360 LOG_DBG("ISP_CLEAR_IRQ Type(%d)",ClearIrq.Type);
4361
4362 if((ClearIrq.Type >= ISP_IRQ_TYPE_AMOUNT) ||(ClearIrq.Type<0))
4363 {
4364 Ret = -EFAULT;
4365 LOG_ERR("invalid type(%d)",ClearIrq.Type);
4366 goto EXIT;
4367 }
4368
4369 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
4370
4371 #if ISP_IRQ_POLLING
4372
4373 ISP_IRQ_TYPE_ENUM IrqStatus[ISP_IRQ_TYPE_AMOUNT];
4374
4375 IrqStatus[ISP_IRQ_TYPE_INT] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INT] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INT]));
4376 IrqStatus[ISP_IRQ_TYPE_DMA] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMA] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMA]));
4377 IrqStatus[ISP_IRQ_TYPE_INTB] = (ISP_RD32((void *)ISP_REG_ADDR_INTB_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTB]));
4378 IrqStatus[ISP_IRQ_TYPE_DMAB] = (ISP_RD32((void *)ISP_REG_ADDR_DMAB_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAB] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAB]));
4379 IrqStatus[ISP_IRQ_TYPE_INTC] = (ISP_RD32((void *)ISP_REG_ADDR_INTC_STATUS) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTC]));
4380 IrqStatus[ISP_IRQ_TYPE_DMAC] = (ISP_RD32((void *)ISP_REG_ADDR_DMAC_INT) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAC] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAC]));
4381 IrqStatus[ISP_IRQ_TYPE_INTX] = (ISP_RD32((void *)ISP_REG_ADDR_INT_STATUSX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTX]));
4382 IrqStatus[ISP_IRQ_TYPE_DMAX] = (ISP_RD32((void *)ISP_REG_ADDR_DMA_INTX) & (g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAX] | g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAX]));
4383
4384 for(i = 0; i < ISP_IRQ_TYPE_AMOUNT; i++)
4385 {
4386 g_IspInfo.IrqInfo.Status[i] |= (IrqStatus[i] & g_IspInfo.IrqInfo.Mask[i]);
4387 }
4388
4389 #endif
4390
4391 LOG_DBG("ISP_CLEAR_IRQ:Type(%d),Status(0x%08X),IrqStatus(0x%08X)",ClearIrq.Type,ClearIrq.Status,g_IspInfo.IrqInfo.Status[ClearIrq.Type]);
4392
4393 g_IspInfo.IrqInfo.Status[ClearIrq.Type] &= (~ClearIrq.Status);
4394
4395 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
4396 }
4397 else
4398 {
4399 LOG_ERR("copy_from_user failed");
4400 Ret = -EFAULT;
4401 }
4402 break;
4403 }
4404 case ISP_DUMP_REG:
4405 {
4406 Ret = ISP_DumpReg();
4407 break;
4408 }
4409 case ISP_DEBUG_FLAG:
4410 {
4411 if(copy_from_user(&DebugFlag, (void*)Param, sizeof(MUINT32)) == 0)
4412 {
4413 spin_lock_irqsave(&(g_IspInfo.SpinLockIrq), flags);
4414 g_IspInfo.DebugMask = DebugFlag;
4415 spin_unlock_irqrestore(&(g_IspInfo.SpinLockIrq), flags);
4416 }
4417 else
4418 {
4419 LOG_ERR("copy_from_user failed");
4420 Ret = -EFAULT;
4421 }
4422 break;
4423 }
4424 case ISP_SENSOR_FREQ_CTRL:
4425 {
4426 MUINT32 senFreq = 0;
4427 if(copy_from_user(&senFreq, (void*)Param, sizeof(MUINT32)) == 0)
4428 {
4429 LOG_DBG("senFreq=%u",senFreq);
4430 clkmux_sel(MT_MUX_CAMTG, senFreq, "CAMERA_SENSOR");
4431 }
4432 else
4433 {
4434 LOG_ERR("senFreq copy_from_user failed");
4435 Ret = -EFAULT;
4436 }
4437 break;
4438 }
4439 #ifdef ISP_KERNEL_MOTIFY_SINGAL_TEST
4440
4441 case ISP_SET_USER_PID:
4442 {
4443 if(copy_from_user(&pid, (void*)Param, sizeof(MUINT32)) == 0)
4444 {
4445 spin_lock(&(g_IspInfo.SpinLockIsp));
4446 getTaskInfo( (pid_t) pid );
4447
4448 sendSignal();
4449
4450 LOG_DBG("[ISP_KERNEL_MOTIFY_SINGAL_TEST]:0x08%x ",pid);
4451 spin_unlock(&(g_IspInfo.SpinLockIsp));
4452 }
4453 else
4454 {
4455 LOG_ERR("copy_from_user failed");
4456 Ret = -EFAULT;
4457 }
4458
4459 break;
4460 }
4461 #endif
4462 case ISP_BUFFER_CTRL:
4463 Ret = ISP_Buf_CTRL_FUNC(Param);
4464 break;
4465 case ISP_REF_CNT_CTRL:
4466 Ret = ISP_REF_CNT_CTRL_FUNC(Param);
4467 break;
4468 default:
4469 {
4470 LOG_ERR("Unknown Cmd(%d)",Cmd);
4471 Ret = -EPERM;
4472 break;
4473 }
4474 }
4475 EXIT:
4476 if(Ret != 0)
4477 {
4478 LOG_ERR("Fail, Cmd(%d), Pid(%d), (process, pid, tgid)=(%s, %d, %d)",Cmd, pUserInfo->Pid, current->comm, current->pid, current->tgid);
4479 }
4480
4481 return Ret;
4482 }
4483
4484 /*******************************************************************************
4485 *
4486 ********************************************************************************/
4487 static MINT32 ISP_open(struct inode *pInode, struct file *pFile)
4488 {
4489 MINT32 Ret = 0;
4490 MUINT32 i;
4491 ISP_USER_INFO_STRUCT* pUserInfo;
4492
4493 LOG_DBG("+,UserCount(%d)", g_IspInfo.UserCount);
4494
4495 spin_lock(&(g_IspInfo.SpinLockIspRef));
4496
4497 //LOG_DBG("UserCount(%d)",g_IspInfo.UserCount);
4498
4499 pFile->private_data = NULL;
4500 pFile->private_data = kmalloc(sizeof(ISP_USER_INFO_STRUCT) , GFP_ATOMIC);
4501 if(pFile->private_data == NULL)
4502 {
4503 LOG_DBG("ERROR: kmalloc failed, (process, pid, tgid)=(%s, %d, %d)",current->comm,current->pid,current->tgid);
4504 Ret = -ENOMEM;
4505 }
4506 else
4507 {
4508 pUserInfo = (ISP_USER_INFO_STRUCT*)pFile->private_data;
4509 pUserInfo->Pid = current->pid;
4510 pUserInfo->Tid = current->tgid;
4511 }
4512
4513 if(g_IspInfo.UserCount > 0)
4514 {
4515 g_IspInfo.UserCount++;
4516 LOG_DBG("Curr UserCount(%d), (process, pid, tgid)=(%s, %d, %d), users exist",g_IspInfo.UserCount,current->comm,current->pid,current->tgid);
4517 goto EXIT;
4518 }
4519
4520 g_IspInfo.BufInfo.Read.pData = (MUINT8 *) kmalloc(ISP_BUF_SIZE, GFP_ATOMIC);
4521 g_IspInfo.BufInfo.Read.Size = ISP_BUF_SIZE;
4522 g_IspInfo.BufInfo.Read.Status = ISP_BUF_STATUS_EMPTY;
4523 if(g_IspInfo.BufInfo.Read.pData == NULL)
4524 {
4525 LOG_DBG("ERROR: BufRead kmalloc failed");
4526 Ret = -ENOMEM;
4527 goto EXIT;
4528 }
4529
4530 if(!ISP_BufWrite_Alloc())
4531 {
4532 LOG_DBG("ERROR: BufWrite kmalloc failed");
4533 Ret = -ENOMEM;
4534 goto EXIT;
4535 }
4536
4537 atomic_set(&(g_IspInfo.HoldInfo.HoldEnable), 0);
4538 atomic_set(&(g_IspInfo.HoldInfo.WriteEnable), 0);
4539 for(i = 0; i < ISP_REF_CNT_ID_MAX; i++)
4540 {
4541 atomic_set(&g_imem_ref_cnt[i],0);
4542 }
4543
4544 // Enable clock
4545 ISP_EnableClock(MTRUE);
4546
4547 for(i = 0; i < ISP_IRQ_TYPE_AMOUNT; i++)
4548 {
4549 g_IspInfo.IrqInfo.Status[i] = 0;
4550 }
4551
4552 for(i = 0; i < ISP_CALLBACK_AMOUNT; i++)
4553 {
4554 g_IspInfo.Callback[i].Func = NULL;
4555 }
4556
4557 g_IspInfo.UserCount++;
4558
4559 LOG_DBG("Curr UserCount(%d), (process, pid, tgid)=(%s, %d, %d), first user",g_IspInfo.UserCount,current->comm,current->pid,current->tgid);
4560
4561 //js_test
4562 //g_IspInfo.DebugMask = ISP_DBG_BUF_CTRL;
4563
4564 EXIT:
4565
4566 if(Ret < 0)
4567 {
4568 if(g_IspInfo.BufInfo.Read.pData != NULL)
4569 {
4570 kfree(g_IspInfo.BufInfo.Read.pData);
4571 g_IspInfo.BufInfo.Read.pData = NULL;
4572 }
4573
4574 ISP_BufWrite_Free();
4575 }
4576
4577 spin_unlock(&(g_IspInfo.SpinLockIspRef));
4578
4579 //LOG_DBG("Before spm_disable_sodi().");
4580 // Disable sodi (Multi-Core Deep Idle).
4581 //spm_disable_sodi();
4582
4583 LOG_DBG("-,Ret(%d),UserCount(%d)", Ret, g_IspInfo.UserCount);
4584
4585 return Ret;
4586 }
4587
4588 /*******************************************************************************
4589 *
4590 ********************************************************************************/
4591 static MINT32 ISP_release(struct inode *pInode, struct file *pFile)
4592 {
4593 ISP_USER_INFO_STRUCT* pUserInfo;
4594
4595 LOG_DBG("+,UserCount(%d)", g_IspInfo.UserCount);
4596
4597 spin_lock(&(g_IspInfo.SpinLockIspRef));
4598
4599 //LOG_DBG("UserCount(%d)",g_IspInfo.UserCount);
4600
4601 if(pFile->private_data != NULL)
4602 {
4603 pUserInfo = (ISP_USER_INFO_STRUCT*)pFile->private_data;
4604 kfree(pFile->private_data);
4605 pFile->private_data = NULL;
4606 }
4607
4608 g_IspInfo.UserCount--;
4609 if(g_IspInfo.UserCount > 0)
4610 {
4611 LOG_DBG("Curr UserCount(%d), (process, pid, tgid)=(%s, %d, %d), users exist",g_IspInfo.UserCount,current->comm, current->pid, current->tgid);
4612 goto EXIT;
4613 }
4614
4615 LOG_DBG("Curr UserCount(%d), (process, pid, tgid)=(%s, %d, %d), last user",g_IspInfo.UserCount,current->comm, current->pid, current->tgid);
4616
4617 // Disable clock.
4618 ISP_EnableClock(MFALSE);
4619
4620 if(g_IspInfo.BufInfo.Read.pData != NULL)
4621 {
4622 kfree(g_IspInfo.BufInfo.Read.pData);
4623 g_IspInfo.BufInfo.Read.pData = NULL;
4624 g_IspInfo.BufInfo.Read.Size = 0;
4625 g_IspInfo.BufInfo.Read.Status = ISP_BUF_STATUS_EMPTY;
4626 }
4627
4628 ISP_BufWrite_Free();
4629
4630 EXIT:
4631
4632 spin_unlock(&(g_IspInfo.SpinLockIspRef));
4633
4634 //LOG_DBG("Before spm_enable_sodi().");
4635 // Enable sodi (Multi-Core Deep Idle).
4636 //spm_enable_sodi();
4637
4638 LOG_DBG("-,UserCount(%d)", g_IspInfo.UserCount);
4639 return 0;
4640 }
4641
4642 /*******************************************************************************
4643 * helper function, mmap's the kmalloc'd area which is physically contiguous
4644 ********************************************************************************/
4645 static MINT32 mmap_kmem(struct file *filp, struct vm_area_struct *vma)
4646 {
4647 MINT32 ret;
4648 long length = 0;
4649 length=(long)(vma->vm_end - vma->vm_start);
4650
4651 // check length - do not allow larger mappings than the number of pages allocated
4652 if(length > RT_BUF_TBL_NPAGES * PAGE_SIZE)
4653 {
4654 return -EIO;
4655 }
4656
4657 // map the whole physically contiguous area in one piece
4658 LOG_INF("Vma->vm_pgoff(0x%x),Vma->vm_start(0x%x),Vma->vm_end(0x%x),length(0x%x)",\
4659 vma->vm_pgoff,vma->vm_start,vma->vm_end,length);
4660 if(length>ISP_RTBUF_REG_RANGE)
4661 {
4662 LOG_ERR("mmap range error! : length(0x%x),ISP_RTBUF_REG_RANGE(0x%x)!",length,ISP_RTBUF_REG_RANGE);
4663 return -EAGAIN;
4664 }
4665 if((ret = remap_pfn_range(vma,
4666 vma->vm_start,
4667 virt_to_phys((void *)g_pTbl_RTBuf) >> PAGE_SHIFT,
4668 length,
4669 vma->vm_page_prot)) < 0)
4670 {
4671 return ret;
4672 }
4673
4674 return 0;
4675 }
4676
4677 /*******************************************************************************
4678 *
4679 ********************************************************************************/
4680 static MINT32 ISP_mmap(struct file *pFile, struct vm_area_struct *pVma)
4681 {
4682 //LOG_DBG("+");
4683 long length = 0;
4684 MUINT32 pfn=0x0;
4685 length= (long)(pVma->vm_end - pVma->vm_start);
4686 // at offset RT_BUF_TBL_NPAGES we map the kmalloc'd area
4687 if(pVma->vm_pgoff == RT_BUF_TBL_NPAGES)
4688 {
4689 return mmap_kmem(pFile, pVma);
4690 }
4691 else
4692 {
4693 pVma->vm_page_prot = pgprot_noncached(pVma->vm_page_prot);
4694 LOG_INF("pVma->vm_pgoff(0x%x),phy(0x%x),pVmapVma->vm_start(0x%x),pVma->vm_end(0x%x),length(0x%x)",\
4695 pVma->vm_pgoff,pVma->vm_pgoff<<PAGE_SHIFT,pVma->vm_start,pVma->vm_end,length);
4696 pfn=pVma->vm_pgoff<<PAGE_SHIFT;//page from number, physical address of kernel memory
4697 switch(pfn)
4698 {
4699 case IMGSYS_BASE_ADDR: //imgsys
4700 if(length>ISP_REG_RANGE)
4701 {
4702 LOG_ERR("mmap range error : length(0x%x),ISP_REG_RANGE(0x%x)!",length,ISP_REG_RANGE);
4703 return -EAGAIN;
4704 }
4705 break;
4706 case SENINF_BASE_ADDR:
4707 if(length>SENINF_REG_RANGE)
4708 {
4709 LOG_ERR("mmap range error : length(0x%x),SENINF_REG_RANGE(0x%x)!",length,SENINF_REG_RANGE);
4710 return -EAGAIN;
4711 }
4712 break;
4713 case PLL_BASE_ADDR:
4714 if(length>PLL_RANGE)
4715 {
4716 LOG_ERR("mmap range error : length(0x%x),PLL_RANGE(0x%x)!",length,PLL_RANGE);
4717 return -EAGAIN;
4718 }
4719 break;
4720 case MIPIRX_CONFIG_ADDR:
4721 if(length>MIPIRX_CONFIG_RANGE)
4722 {
4723 LOG_ERR("mmap range error : length(0x%x),MIPIRX_CONFIG_RANGE(0x%x)!",length,MIPIRX_CONFIG_RANGE);
4724 return -EAGAIN;
4725 }
4726 break;
4727 case MIPIRX_ANALOG_ADDR:
4728 if(length>MIPIRX_ANALOG_RANGE)
4729 {
4730 LOG_ERR("mmap range error : length(0x%x),MIPIRX_ANALOG_RANGE(0x%x)!",length,MIPIRX_ANALOG_RANGE);
4731 return -EAGAIN;
4732 }
4733 break;
4734 case GPIO_BASE_ADDR:
4735 if(length>GPIO_RANGE)
4736 {
4737 LOG_ERR("mmap range error : length(0x%x),GPIO_RANGE(0x%x)!",length,GPIO_RANGE);
4738 return -EAGAIN;
4739 }
4740 break;
4741 case EFUSE_BASE_ADDR:
4742 if(length>EFUSE_RANGE)
4743 {
4744 LOG_ERR("mmap range error : length(0x%x),EFUSE_RANGE(0x%x)!",length,EFUSE_RANGE);
4745 return -EAGAIN;
4746 }
4747 break;
4748 default:
4749 LOG_ERR("Illegal starting HW addr for mmap!");
4750 return -EAGAIN;
4751 break;
4752 }
4753 if(remap_pfn_range(pVma, pVma->vm_start, pVma->vm_pgoff,pVma->vm_end - pVma->vm_start, pVma->vm_page_prot))
4754 {
4755 return -EAGAIN;
4756 }
4757 }
4758
4759 return 0;
4760 }
4761
4762 /*******************************************************************************
4763 *
4764 ********************************************************************************/
4765 static const struct file_operations g_IspFileOper =
4766 {
4767 .owner = THIS_MODULE,
4768 .open = ISP_open,
4769 .release = ISP_release,
4770 //.flush = mt_isp_flush,
4771 .mmap = ISP_mmap,
4772 .unlocked_ioctl = ISP_ioctl
4773 };
4774
4775 /*******************************************************************************
4776 *
4777 ********************************************************************************/
4778 inline static MVOID ISP_UnregCharDev(MVOID)
4779 {
4780 LOG_DBG("+");
4781
4782 //Release char driver
4783 if(g_pIspCharDrv != NULL)
4784 {
4785 cdev_del(g_pIspCharDrv);
4786 g_pIspCharDrv = NULL;
4787 }
4788
4789 unregister_chrdev_region(g_IspDevNo, 1);
4790 }
4791
4792 /*******************************************************************************
4793 *
4794 ********************************************************************************/
4795 inline static MINT32 ISP_RegCharDev(MVOID)
4796 {
4797 MINT32 Ret = 0;
4798
4799 LOG_DBG("+");
4800
4801 if((Ret = alloc_chrdev_region(&g_IspDevNo, 0, 1, ISP_DEV_NAME)) < 0)
4802 {
4803 LOG_ERR("alloc_chrdev_region failed, %d", Ret);
4804 return Ret;
4805 }
4806
4807 //Allocate driver
4808 g_pIspCharDrv = cdev_alloc();
4809 if(g_pIspCharDrv == NULL)
4810 {
4811 LOG_ERR("cdev_alloc failed");
4812 Ret = -ENOMEM;
4813 goto EXIT;
4814 }
4815
4816 //Attatch file operation.
4817 cdev_init(g_pIspCharDrv, &g_IspFileOper);
4818
4819 g_pIspCharDrv->owner = THIS_MODULE;
4820
4821 //Add to system
4822 if((Ret = cdev_add(g_pIspCharDrv, g_IspDevNo, 1)) < 0)
4823 {
4824 LOG_ERR("Attatch file operation failed, %d", Ret);
4825 goto EXIT;
4826 }
4827
4828 EXIT:
4829
4830 if(Ret < 0)
4831 {
4832 ISP_UnregCharDev();
4833 }
4834
4835 LOG_DBG("-");
4836 return Ret;
4837 }
4838
4839 /*******************************************************************************
4840 *
4841 ********************************************************************************/
4842 static MINT32 ISP_probe(struct platform_device *pDev)
4843 {
4844 MINT32 Ret = 0;
4845 struct resource *pRes = NULL;
4846 MINT32 i;
4847
4848 LOG_DBG("+");
4849
4850 // Check platform_device parameters
4851 if(pDev == NULL)
4852 {
4853 dev_err(&pDev->dev, "pDev is NULL");
4854 return -ENXIO;
4855 }
4856
4857 // Register char driver
4858 if((Ret = ISP_RegCharDev()))
4859 {
4860 dev_err(&pDev->dev, "register char failed");
4861 return Ret;
4862 }
4863
4864 // Mapping CAM_REGISTERS
4865 for(i = 0; i < 1; i++) // NEED_TUNING_BY_CHIP. 1: Only one IORESOURCE_MEM type resource in kernel\mt_devs.c\mt_resource_isp[].
4866 {
4867 LOG_DBG("Mapping CAM_REGISTERS. i: %d.", i);
4868
4869 pRes = platform_get_resource(pDev, IORESOURCE_MEM, i);
4870 if(pRes == NULL)
4871 {
4872 dev_err(&pDev->dev, "platform_get_resource failed");
4873 Ret = -ENOMEM;
4874 goto EXIT;
4875 }
4876
4877 pRes = request_mem_region(pRes->start, pRes->end - pRes->start + 1, pDev->name);
4878 if(pRes == NULL)
4879 {
4880 dev_err(&pDev->dev, "request_mem_region failed");
4881 Ret = -ENOMEM;
4882 goto EXIT;
4883 }
4884 }
4885
4886 // Create class register
4887 g_pIspClass = class_create(THIS_MODULE, "ispdrv");
4888 if(IS_ERR(g_pIspClass))
4889 {
4890 Ret = PTR_ERR(g_pIspClass);
4891 LOG_ERR("Unable to create class, err = %d", Ret);
4892 return Ret;
4893 }
4894
4895 // FIXME: error handling
4896 device_create(g_pIspClass, NULL, g_IspDevNo, NULL, ISP_DEV_NAME);
4897
4898 init_waitqueue_head(&g_IspInfo.WaitQueueHead);
4899
4900 INIT_WORK(&g_IspInfo.ScheduleWorkVD, ISP_ScheduleWork_VD);
4901 INIT_WORK(&g_IspInfo.ScheduleWorkEXPDONE, ISP_ScheduleWork_EXPDONE);
4902 INIT_WORK(&g_IspInfo.ScheduleWorkSENINF, ISP_ScheduleWork_SENINF);
4903
4904 spin_lock_init(&(g_IspInfo.SpinLockIspRef));
4905 spin_lock_init(&(g_IspInfo.SpinLockIsp));
4906 spin_lock_init(&(g_IspInfo.SpinLockIrq));
4907 spin_lock_init(&(g_IspInfo.SpinLockHold));
4908 spin_lock_init(&(g_IspInfo.SpinLockRTBC));
4909
4910 g_IspInfo.UserCount = 0;
4911 g_IspInfo.HoldInfo.Time = ISP_HOLD_TIME_EXPDONE;
4912
4913 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INT] = ISP_REG_MASK_INT_STATUS;
4914 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMA] = ISP_REG_MASK_DMA_INT;
4915 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTB] = ISP_REG_MASK_INTB_STATUS;
4916 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAB] = ISP_REG_MASK_DMAB_INT;
4917 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTC] = ISP_REG_MASK_INTC_STATUS;
4918 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAC] = ISP_REG_MASK_DMAC_INT;
4919 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_INTX] = ISP_REG_MASK_INTX_STATUS;
4920 g_IspInfo.IrqInfo.Mask[ISP_IRQ_TYPE_DMAX] = ISP_REG_MASK_DMAX_INT;
4921
4922 g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INT] = ISP_REG_MASK_INT_STATUS_ERR;
4923 g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMA] = ISP_REG_MASK_DMA_INT_ERR;
4924 g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTB] = ISP_REG_MASK_INTB_STATUS_ERR;
4925 //g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAB] = ISP_REG_MASK_DMAB_INT_ERR;
4926 g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTC] = ISP_REG_MASK_INTC_STATUS_ERR;
4927 //g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAC] = ISP_REG_MASK_DMAC_INT_ERR;
4928 g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_INTX] = ISP_REG_MASK_INTX_STATUS_ERR;
4929 g_IspInfo.IrqInfo.ErrMask[ISP_IRQ_TYPE_DMAX] = ISP_REG_MASK_DMAX_INT_ERR;
4930
4931 // Request CAM_ISP IRQ
4932 #if 1 // FIXME
4933 if (request_irq(CAMERA_ISP_IRQ0_ID, (irq_handler_t)ISP_Irq, IRQF_TRIGGER_LOW , "isp", NULL))
4934 // if (request_irq(CAMERA_ISP_IRQ0_ID, (irq_handler_t)ISP_Irq, IRQF_TRIGGER_HIGH, "isp", NULL))
4935 {
4936 LOG_ERR("MT_CAM_IRQ_LINE IRQ LINE NOT AVAILABLE!!");
4937 goto EXIT;
4938 }
4939 //mt_irq_unmask(CAMERA_ISP_IRQ0_ID);
4940 #endif
4941
4942 cmdqRegisterCallback(cbISP, ISPRegDump ,MDPReset_Process);
4943
4944 EXIT:
4945
4946 if(Ret < 0)
4947 {
4948 ISP_UnregCharDev();
4949 }
4950
4951 LOG_DBG("-");
4952 return Ret;
4953 }
4954
4955 /*******************************************************************************
4956 * Called when the device is being detached from the driver
4957 ********************************************************************************/
4958 static MINT32 ISP_remove(struct platform_device *pDev)
4959 {
4960 struct resource *pRes;
4961 MINT32 i;
4962 MINT32 IrqNum;
4963
4964 LOG_DBG("+");
4965
4966 // unregister char driver.
4967 ISP_UnregCharDev();
4968
4969 // unmaping ISP CAM_REGISTER registers
4970 for(i = 0; i < 2; i++)
4971 {
4972 pRes = platform_get_resource(pDev, IORESOURCE_MEM, 0);
4973 release_mem_region(pRes->start, (pRes->end - pRes->start + 1));
4974 }
4975
4976 // Release IRQ
4977 disable_irq(g_IspInfo.IrqNum);
4978 IrqNum = platform_get_irq(pDev, 0);
4979 free_irq(IrqNum , NULL);
4980
4981 device_destroy(g_pIspClass, g_IspDevNo);
4982
4983 class_destroy(g_pIspClass);
4984 g_pIspClass = NULL;
4985
4986 return 0;
4987 }
4988
4989 /*******************************************************************************
4990 *
4991 ********************************************************************************/
4992 static MINT32 ISP_suspend(struct platform_device *pDev,pm_message_t Mesg)
4993 {
4994 // TG_VF_CON[0] (0x15004414[0]): VFDATA_EN. TG1 Take Picture Request.
4995 MUINT32 regTG1Val = ISP_RD32((void *)(ISP_ADDR + 0x414));
4996
4997 LOG_DBG("g_bPass1_On_In_Resume_TG1(%d),regTG1Val(0x%08x)", g_bPass1_On_In_Resume_TG1, regTG1Val);
4998
4999 g_bPass1_On_In_Resume_TG1 = 0;
5000 if(regTG1Val & 0x01 ) // For TG1 Main sensor.
5001 {
5002 g_bPass1_On_In_Resume_TG1 = 1;
5003 ISP_WR32((void *)(ISP_ADDR + 0x414), (regTG1Val&(~0x01)) );
5004 }
5005
5006 return 0;
5007 }
5008
5009 /*******************************************************************************
5010 *
5011 ********************************************************************************/
5012 static MINT32 ISP_resume(struct platform_device *pDev)
5013 {
5014 // TG_VF_CON[0] (0x15004414[0]): VFDATA_EN. TG1 Take Picture Request.
5015 MUINT32 regTG1Val = ISP_RD32((void *)(ISP_ADDR + 0x414));
5016
5017 LOG_DBG("g_bPass1_On_In_Resume_TG1(%d),regTG1Val(0x%x)", g_bPass1_On_In_Resume_TG1, regTG1Val);
5018
5019 if(g_bPass1_On_In_Resume_TG1)
5020 {
5021 g_bPass1_On_In_Resume_TG1 = 0;
5022 ISP_WR32((void *)(ISP_ADDR + 0x414), (regTG1Val|0x01) ); // For TG1 Main sensor.
5023 }
5024
5025 return 0;
5026 }
5027
5028 /*******************************************************************************
5029 *
5030 ********************************************************************************/
5031 #ifdef CONFIG_PM
5032 MINT32 ISP_pm_suspend(struct device *device)
5033 {
5034 struct platform_device *pdev = to_platform_device(device);
5035 BUG_ON(pdev == NULL);
5036
5037 pr_debug("calling %s()\n", __func__);
5038
5039 return ISP_suspend(pdev, PMSG_SUSPEND);
5040 }
5041
5042 MINT32 ISP_pm_resume(struct device *device)
5043 {
5044 struct platform_device *pdev = to_platform_device(device);
5045 BUG_ON(pdev == NULL);
5046
5047 pr_debug("calling %s()\n", __func__);
5048
5049 return ISP_resume(pdev);
5050 }
5051
5052 extern MVOID mt_irq_set_sens(MUINT32 irq, MUINT32 sens);
5053 extern MVOID mt_irq_set_polarity(MUINT32 irq, MUINT32 polarity);
5054 MINT32 ISP_pm_restore_noirq(struct device *device)
5055 {
5056 pr_debug("calling %s()\n", __func__);
5057
5058 mt_irq_set_sens(CAMERA_ISP_IRQ0_ID, MT_LEVEL_SENSITIVE);
5059 mt_irq_set_polarity(CAMERA_ISP_IRQ0_ID, MT_POLARITY_LOW);
5060
5061 return 0;
5062
5063 }
5064
5065 #else
5066
5067 #define ISP_pm_suspend NULL
5068 #define ISP_pm_resume NULL
5069 #define ISP_pm_restore_noirq NULL
5070
5071 #endif /*CONFIG_PM*/
5072
5073 struct dev_pm_ops ISP_pm_ops = {
5074 .suspend = ISP_pm_suspend,
5075 .resume = ISP_pm_resume,
5076 .freeze = ISP_pm_suspend,
5077 .thaw = ISP_pm_resume,
5078 .poweroff = ISP_pm_suspend,
5079 .restore = ISP_pm_resume,
5080 .restore_noirq = ISP_pm_restore_noirq,
5081 };
5082
5083 /*******************************************************************************
5084 *
5085 ********************************************************************************/
5086 static struct platform_driver IspDriver =
5087 {
5088 .probe = ISP_probe,
5089 .remove = ISP_remove,
5090 .suspend = ISP_suspend,
5091 .resume = ISP_resume,
5092 .driver = {
5093 .name = ISP_DEV_NAME,
5094 .owner = THIS_MODULE,
5095 #ifdef CONFIG_PM
5096 .pm = &ISP_pm_ops,
5097 #endif
5098 }
5099 };
5100
5101 /*******************************************************************************
5102 *
5103 ********************************************************************************/
5104 static MINT32 ISP_DumpRegToProc(
5105 char *pPage,
5106 char **ppStart,
5107 off_t off,
5108 MINT32 Count,
5109 MINT32 *pEof,
5110 MVOID *pData)
5111 {
5112 char *p = pPage;
5113 MINT32 Length = 0;
5114 MUINT32 i = 0;
5115 MINT32 ret = 0;
5116
5117 LOG_DBG("pPage(0x%08x),off(%d),Count(%d)", (MUINT32)pPage, (MUINT32)off, Count);
5118
5119 p += sprintf(p, " MT ISP Register\n");
5120 p += sprintf(p, "====== top ====\n");
5121
5122 for(i = 0x0; i <= 0x1AC; i += 4)
5123 {
5124 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5125 }
5126
5127 p += sprintf(p,"====== dma ====\n");
5128 for(i = 0x200; i <= 0x3D8; i += 4)
5129 {
5130 p += sprintf(p,"+0x%08x 0x%08x\n\r", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5131 }
5132
5133 p += sprintf(p,"====== tg ====\n");
5134 for(i = 0x400; i <= 0x4EC; i += 4)
5135 {
5136 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5137 }
5138
5139 p += sprintf(p,"====== cdp (including EIS) ====\n");
5140 for(i = 0xB00; i <= 0xDE0; i += 4)
5141 {
5142 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5143 }
5144
5145 p += sprintf(p,"====== seninf ====\n");
5146 for(i = 0x4000; i <= 0x40C0; i += 4)
5147 {
5148 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5149 }
5150
5151 for(i = 0x4100; i <= 0x41BC; i += 4)
5152 {
5153 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5154 }
5155
5156 for(i = 0x4300; i <= 0x4310; i += 4)
5157 {
5158 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5159 }
5160
5161 for(i = 0x43A0; i <= 0x43B0; i += 4)
5162 {
5163 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5164 }
5165
5166 for(i = 0x4400; i <= 0x4424; i += 4)
5167 {
5168 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5169 }
5170
5171 for(i = 0x4500; i <= 0x4520; i += 4)
5172 {
5173 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5174 }
5175
5176 p += sprintf(p,"====== 3DNR ====\n");
5177 for(i = 0x4F00; i <= 0x4F38; i += 4)
5178 {
5179 p += sprintf(p,"+0x%08x 0x%08x\n", ISP_ADDR + i, ISP_RD32((void *)(ISP_ADDR + i)));
5180 }
5181
5182 *ppStart = pPage + off;
5183
5184 Length = p - pPage;
5185 if(Length > off)
5186 {
5187 Length -= off;
5188 }
5189 else
5190 {
5191 Length = 0;
5192 }
5193
5194 ret = Length < Count ? Length : Count;
5195
5196 LOG_DBG("ret(%d)", ret);
5197 return ret;
5198 }
5199
5200 /*******************************************************************************
5201 *
5202 ********************************************************************************/
5203 static MINT32 ISP_RegDebug(
5204 struct file *pFile,
5205 const char *pBuffer,
5206 unsigned long Count,
5207 MVOID *pData)
5208 {
5209 char RegBuf[64];
5210 MUINT32 CopyBufSize = (Count < (sizeof(RegBuf) - 1)) ? (Count) : (sizeof(RegBuf) - 1);
5211 MUINT32 Addr = 0;
5212 MUINT32 Data = 0;
5213
5214 LOG_DBG("pFile(0x%08x),pBuffer(0x%08x),Count(%d)", (MUINT32)pFile, (MUINT32)pBuffer, (MINT32)Count);
5215
5216 if(copy_from_user(RegBuf, pBuffer, CopyBufSize))
5217 {
5218 LOG_ERR("copy_from_user() fail.");
5219 return -EFAULT;
5220 }
5221
5222 if(sscanf(RegBuf, "%x %x", &Addr, &Data) == 2)
5223 {
5224 ISP_WR32((void *)(ISP_ADDR_CAMINF + Addr), Data);
5225 LOG_ERR("Write => Addr: 0x%08X, Write Data: 0x%08X. Read Data: 0x%08X.", ISP_ADDR_CAMINF + Addr, Data, ioread32((void *)(ISP_ADDR_CAMINF + Addr)));
5226 }
5227 else if (sscanf(RegBuf, "%x", &Addr) == 1)
5228 {
5229 LOG_ERR("Read => Addr: 0x%08X, Read Data: 0x%08X.", ISP_ADDR_CAMINF + Addr, ioread32((void *)(ISP_ADDR_CAMINF + Addr)));
5230 }
5231
5232 LOG_DBG("Count(%d)", (MINT32)Count);
5233 return Count;
5234 }
5235
5236 static MUINT32 proc_regOfst = 0;
5237 static MINT32 CAMIO_DumpRegToProc(
5238 char *pPage,
5239 char **ppStart,
5240 off_t off,
5241 MINT32 Count,
5242 MINT32 *pEof,
5243 MVOID *pData)
5244 {
5245 char *p = pPage;
5246 MINT32 Length = 0;
5247 MINT32 ret = 0;
5248
5249 LOG_DBG("pPage(0x%08x),off(%d),Count(%d)", (MUINT32)pPage, (MINT32)off, Count);
5250
5251 p += sprintf(p,"reg_0x%08X = 0x%X \n", ISP_ADDR_CAMINF + proc_regOfst , ioread32((void *)(ISP_ADDR_CAMINF + proc_regOfst)));
5252
5253 *ppStart = pPage + off;
5254
5255 Length = p - pPage;
5256 if(Length > off)
5257 {
5258 Length -= off;
5259 }
5260 else
5261 {
5262 Length = 0;
5263 }
5264 //
5265
5266 ret = Length < Count ? Length : Count;
5267
5268 LOG_DBG("ret(%d)", ret);
5269 return ret;
5270 }
5271
5272 /*******************************************************************************
5273 *
5274 ********************************************************************************/
5275 static MINT32 CAMIO_RegDebug(
5276 struct file *pFile,
5277 const char *pBuffer,
5278 unsigned long Count,
5279 MVOID *pData)
5280 {
5281 char RegBuf[64];
5282 MUINT32 CopyBufSize = (Count < (sizeof(RegBuf) - 1)) ? (Count) : (sizeof(RegBuf) - 1);
5283 MUINT32 Addr = 0;
5284 MUINT32 Data = 0;
5285
5286 LOG_DBG("pFile(0x%08x),pBuffer(0x%08x),Count(%d)", (MUINT32)pFile, (MUINT32)pBuffer, (MINT32)Count);
5287
5288 if(copy_from_user(RegBuf, pBuffer, CopyBufSize))
5289 {
5290 LOG_ERR("copy_from_user() fail.");
5291 return -EFAULT;
5292 }
5293
5294 if(sscanf(RegBuf, "%x %x", &Addr, &Data) == 2)
5295 {
5296 proc_regOfst = Addr;
5297 ISP_WR32((void *)(GPIO_BASE + Addr), Data);
5298 LOG_ERR("Write => Addr: 0x%08X, Write Data: 0x%08X. Read Data: 0x%08X.", GPIO_BASE + Addr, Data, ioread32((void *)(GPIO_BASE + Addr)));
5299 }
5300 else if (sscanf(RegBuf, "%x", &Addr) == 1)
5301 {
5302 proc_regOfst = Addr;
5303 LOG_ERR("Read => Addr: 0x%08X, Read Data: 0x%08X.", GPIO_BASE + Addr, ioread32((void *)(GPIO_BASE + Addr)));
5304 }
5305
5306 LOG_DBG("Count(%d)", (MINT32)Count);
5307 return Count;
5308 }
5309
5310 /*******************************************************************************
5311 *
5312 ********************************************************************************/
5313 static const struct file_operations fcameraisp_proc_fops = {
5314 .read = ISP_DumpRegToProc,
5315 .write = ISP_RegDebug,
5316 };
5317 static const struct file_operations fcameraio_proc_fops = {
5318 .read = CAMIO_DumpRegToProc,
5319 .write = CAMIO_RegDebug,
5320 };
5321
5322 /*******************************************************************************
5323 *
5324 ********************************************************************************/
5325 #define GPIO_BASE_ADDR 0xF0005000
5326
5327 static MINT32 CAM_CLK_DumpRegToProc(
5328 char* pPage,
5329 char** ppStart,
5330 off_t off,
5331 MINT32 Count,
5332 MINT32* pEof,
5333 void* pData)
5334 {
5335 return 0;
5336 }
5337
5338 int setPCLKDrivingCurrent(unsigned long ioDrivingCurrent)
5339 {
5340 int ret = 0;
5341 #if 0
5342 MUINT32 Addr = 0;
5343 MUINT32 Data = 0;
5344 MUINT32 DataTmp = 0;
5345 Addr = 0x5a0;
5346 DataTmp = ISP_RD32(GPIO_BASE_ADDR + Addr);
5347 Data = DataTmp&0xFFFF0FFF;
5348 ISP_WR32(GPIO_BASE_ADDR + Addr,Data);
5349
5350 DataTmp = ISP_RD32(GPIO_BASE_ADDR + Addr);
5351 Data = DataTmp|ioDrivingCurrent;
5352 ISP_WR32(GPIO_BASE_ADDR + Addr, Data);
5353
5354 LOG_GPIO_REG("Write => Addr: 0x%08X, Write Data: 0x%08X. Read Data: 0x%08X.", GPIO_BASE_ADDR + Addr, Data, ioread32(GPIO_BASE_ADDR + Addr));
5355 #endif
5356 return ret;
5357 }
5358
5359 int setMCLKDrivingCurrent(unsigned long ioDrivingCurrent)
5360 {
5361 int ret = 0;
5362
5363 MUINT32 Addr = 0;
5364 MUINT32 Data = 0;
5365 MUINT32 DataTmp = 0;
5366 Addr = 0xB60;
5367 DataTmp = ISP_RD32(GPIO_BASE_ADDR + Addr);
5368 Data = DataTmp&0xFFFF0FFF;
5369 ISP_WR32(GPIO_BASE_ADDR + Addr,Data );
5370
5371 DataTmp = ISP_RD32(GPIO_BASE_ADDR + Addr);
5372 Data = DataTmp|ioDrivingCurrent;
5373 ISP_WR32(GPIO_BASE_ADDR + Addr, Data);
5374
5375 LOG_GPIO_REG("Write => Addr: 0x%08X, Write Data: 0x%08X. Read Data: 0x%08X.", GPIO_BASE_ADDR + Addr, Data, ioread32(GPIO_BASE_ADDR + Addr));
5376
5377 return ret;
5378 }
5379
5380
5381 static MINT32 CAM_CLK_RegDebug(
5382 struct file* pFile,
5383 const char* pBuffer,
5384 unsigned long Count,
5385 void* pData)
5386 {
5387 char RegBuf[64];
5388 MUINT32 CopyBufSize = (Count < (sizeof(RegBuf) - 1)) ? (Count) : (sizeof(RegBuf) - 1);
5389 MUINT32 Addr = 0;
5390 MUINT32 Data = 0;
5391 MUINT32 DataTmp = 0;
5392 MINT32 ioDrivingCurrent = 0;
5393
5394 LOG_GPIO_REG("- E. pFile: 0x%08x. pBuffer: 0x%08x. Count: %d.", (unsigned int)pFile, (unsigned int)pBuffer, (int)Count);
5395 //
5396 if(copy_from_user(RegBuf, pBuffer, CopyBufSize))
5397 {
5398 LOG_GPIO_REG("copy_from_user() fail.");
5399 return -EFAULT;
5400 }
5401
5402
5403 if (sscanf(RegBuf, "MCLK=%x", &Data) == 1)
5404 {
5405 switch(Data)
5406 {
5407 case 2://4 //2mA
5408 ioDrivingCurrent = 0x0000;
5409 break;
5410 case 4:// 4mA
5411 ioDrivingCurrent = 0x2000;
5412 break;
5413 case 6://6mA
5414 ioDrivingCurrent = 0x4000;
5415 break;
5416 case 8://8mA
5417 ioDrivingCurrent = 0x6000;
5418 break;
5419 default:
5420 LOG_GPIO_REG("The driving current value is wrong\n");
5421 return -EFAULT;
5422 }
5423
5424 setMCLKDrivingCurrent(ioDrivingCurrent);
5425 }
5426 #if 0
5427 else if(sscanf(RegBuf, "PCLK=%x", &Data) == 1)
5428 {
5429 switch(Data)
5430 {
5431 case 2://4 //2mA
5432 ioDrivingCurrent = 0x0000;
5433 break;
5434 case 4:// 4mA
5435 ioDrivingCurrent = 0x2000;
5436 break;
5437 case 6://6mA
5438 ioDrivingCurrent = 0x4000;
5439 break;
5440 case 8://8mA
5441 ioDrivingCurrent = 0x6000;
5442 break;
5443 default:
5444 LOG_GPIO_REG("The driving current value is wrong\n");
5445 return -EFAULT;
5446 }
5447 setPCLKDrivingCurrent(ioDrivingCurrent);
5448 }
5449 #endif
5450 //
5451 LOG_GPIO_REG("- X. Count: %d.", (int)Count);
5452 return Count;
5453 }
5454
5455
5456
5457
5458 /*******************************************************************************
5459 *
5460 ********************************************************************************/
5461 static MINT32 __init ISP_Init(MVOID)
5462 {
5463 MINT32 i;
5464 MINT32 Ret = 0;
5465 struct proc_dir_entry* pEntry;
5466
5467 LOG_DBG("+");
5468
5469 if((Ret = platform_driver_register(&IspDriver)) < 0)
5470 {
5471 LOG_ERR("platform_driver_register fail");
5472 return Ret;
5473 }
5474 #if 1 //linux-3.10 procfs API changed
5475 proc_create("driver/isp_reg",0,NULL,&fcameraisp_proc_fops);
5476 proc_create("driver/camio_reg",0,NULL,&fcameraio_proc_fops);
5477 #else
5478 pEntry = create_proc_entry("driver/isp_reg", 0, NULL);
5479 if(pEntry)
5480 {
5481 pEntry->read_proc = ISP_DumpRegToProc;
5482 pEntry->write_proc = ISP_RegDebug;
5483 }
5484 else
5485 {
5486 LOG_ERR("add /proc/driver/isp_reg entry fail");
5487 }
5488
5489 pEntry = create_proc_entry("driver/camio_reg", 0, NULL);
5490 if(pEntry)
5491 {
5492 pEntry->read_proc = CAMIO_DumpRegToProc;
5493 pEntry->write_proc = CAMIO_RegDebug;
5494 }
5495 else
5496 {
5497 LOG_ERR("add /proc/driver/camio_reg entry fail");
5498 }
5499 #endif
5500 // allocate a memory area with kmalloc. Will be rounded up to a page boundary
5501 //RT_BUF_TBL_NPAGES*4096(1page) = 64k Bytes
5502 if((g_pBuf_kmalloc = kmalloc((RT_BUF_TBL_NPAGES + 2) * PAGE_SIZE, GFP_KERNEL)) == NULL)
5503 {
5504 return -ENOMEM;
5505
5506 }
5507
5508 memset(g_pBuf_kmalloc,0x00,RT_BUF_TBL_NPAGES * PAGE_SIZE);
5509
5510 // round it up to the page bondary
5511 g_pTbl_RTBuf = (MINT32 *)((((unsigned long)g_pBuf_kmalloc) + PAGE_SIZE - 1) & PAGE_MASK);
5512 g_pstRTBuf = (ISP_RT_BUF_STRUCT*)g_pTbl_RTBuf;
5513 g_pstRTBuf->state = ISP_RTBC_STATE_INIT;
5514
5515 // mark the pages reserved
5516 for (i = 0; i < RT_BUF_TBL_NPAGES * PAGE_SIZE; i += PAGE_SIZE)
5517 {
5518 SetPageReserved(virt_to_page(((unsigned long)g_pTbl_RTBuf) + i));
5519 }
5520
5521 LOG_DBG("Ret(%d)", Ret);
5522 return Ret;
5523 }
5524
5525 /*******************************************************************************
5526 *
5527 ********************************************************************************/
5528 static MVOID __exit ISP_Exit(MVOID)
5529 {
5530 MINT32 i;
5531 LOG_DBG("+");
5532
5533 platform_driver_unregister(&IspDriver);
5534
5535 // unreserve the pages
5536 for (i = 0; i < RT_BUF_TBL_NPAGES * PAGE_SIZE; i += PAGE_SIZE)
5537 {
5538 SetPageReserved(virt_to_page(((unsigned long)g_pTbl_RTBuf) + i));
5539 }
5540
5541 // free the memory areas
5542 kfree(g_pBuf_kmalloc);
5543 }
5544
5545 /*******************************************************************************
5546 *
5547 ********************************************************************************/
5548 bool ISP_RegCallback(ISP_CALLBACK_STRUCT *pCallback)
5549 {
5550 if(pCallback == NULL)
5551 {
5552 LOG_ERR("pCallback is null");
5553 return false;
5554 }
5555
5556 if(pCallback->Func == NULL)
5557 {
5558 LOG_ERR("Func is null");
5559 return false;
5560 }
5561
5562 LOG_DBG("Type(%d)",pCallback->Type);
5563 g_IspInfo.Callback[pCallback->Type].Func = pCallback->Func;
5564
5565 return true;
5566 }
5567
5568 /*******************************************************************************
5569 *
5570 ********************************************************************************/
5571 bool ISP_UnregCallback(ISP_CALLBACK_ENUM Type)
5572 {
5573 if(Type > ISP_CALLBACK_AMOUNT)
5574 {
5575 LOG_ERR("Type(%d) must smaller than %d",Type,ISP_CALLBACK_AMOUNT);
5576 return false;
5577 }
5578
5579 LOG_DBG("Type(%d)",Type);
5580 g_IspInfo.Callback[Type].Func = NULL;
5581
5582 return true;
5583 }
5584
5585 /*******************************************************************************
5586 *
5587 ********************************************************************************/
5588 void ISP_MCLK1_EN(bool En)
5589 {
5590 MUINT32 temp=0;
5591 temp = ISP_RD32((void *)(ISP_ADDR + 0x4300));
5592
5593 if(En)
5594 {
5595 temp |= 0x20000000;
5596 ISP_WR32((void *)(ISP_ADDR + 0x4300),temp);
5597 }
5598 else
5599 {
5600 temp &= 0xDFFFFFFF;
5601 ISP_WR32((void *)(ISP_ADDR + 0x4300),temp);
5602 }
5603 }
5604
5605 int m4u_reclaim_mva_callback_CAM(int moduleID, unsigned int va, unsigned int size, unsigned int mva)
5606 {
5607 if(CAM_IMGI == moduleID)
5608 {
5609 LOG_DBG("warning on Release MVA!"); // ISP need Release before M4U Release
5610 if(g_IspInfo.UserCount > 0)
5611 {
5612 LOG_DBG("UserCnt(%d),(pro, pid, tgid)=(%s, %d, %d)",g_IspInfo.UserCount,current->comm, current->pid, current->tgid);
5613 }
5614 }
5615 return true;
5616 }
5617 /*******************************************************************************
5618 *
5619 ********************************************************************************/
5620 module_init(ISP_Init);
5621 module_exit(ISP_Exit);
5622 MODULE_DESCRIPTION("Camera ISP driver");
5623 MODULE_AUTHOR("ME3");
5624 MODULE_LICENSE("GPL");
5625 EXPORT_SYMBOL(ISP_RegCallback);
5626 EXPORT_SYMBOL(ISP_UnregCallback);
5627 EXPORT_SYMBOL(ISP_MCLK1_EN);
5628
5629
5630
5631
5632
kernel source for telekom puls (alcatel/mediatek)