2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
19 #include <asm/domain.h>
20 #include <asm/ptrace.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/memory.h>
23 #include <asm/thread_info.h>
24 #include <asm/pgtable.h>
25 #include <asm/vfpmacros.h>
27 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
28 #include CONFIG_DEBUG_LL_INCLUDE
32 * swapper_pg_dir is the virtual address of the initial page table.
33 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
34 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
35 * the least significant 16 bits to be 0x8000, but we could probably
36 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
38 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
39 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
40 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
43 #ifdef CONFIG_ARM_LPAE
44 /* LPAE requires an additional page for the PGD */
45 #define PG_DIR_SIZE 0x5000
48 #define PG_DIR_SIZE 0x4000
53 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
55 .macro pgtbl, rd, phys
56 add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
60 * Kernel startup entry point.
61 * ---------------------------
63 * This is normally called from the decompressor code. The requirements
64 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
65 * r1 = machine nr, r2 = atags or dtb pointer.
67 * This code is mostly position independent, so if you link the kernel at
68 * 0xc0008000, you call this at __pa(0xc0008000).
70 * See linux/arch/arm/tools/mach-types for the complete list of machine
73 * We're trying to keep crap to a minimum; DO NOT add any machine specific
74 * crap here - that's what the boot loader (or in extreme, well justified
75 * circumstances, zImage) is for.
82 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
83 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
84 THUMB( .thumb ) @ switch to Thumb now.
87 #ifdef CONFIG_ARM_VIRT_EXT
90 @ ensure svc mode and all interrupts masked
91 safe_svcmode_maskall r9
93 mrc p15, 0, r9, c0, c0 @ get processor id
94 bl __lookup_processor_type @ r5=procinfo r9=cpuid
95 movs r10, r5 @ invalid processor (r5=0)?
96 THUMB( it eq ) @ force fixup-able long branch encoding
97 beq __error_p @ yes, error 'p'
99 #ifdef CONFIG_ARM_LPAE
100 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
101 and r3, r3, #0xf @ extract VMSA support
102 cmp r3, #5 @ long-descriptor translation table format?
103 THUMB( it lo ) @ force fixup-able long branch encoding
104 blo __error_p @ only classic page table format
107 #ifndef CONFIG_XIP_KERNEL
110 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
111 add r8, r8, r4 @ PHYS_OFFSET
113 ldr r8, =PHYS_OFFSET @ always constant in this case
117 * r1 = machine no, r2 = atags or dtb,
118 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
121 #ifdef CONFIG_SMP_ON_UP
124 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
127 bl __create_page_tables
130 * The following calls CPU specific code in a position independent
131 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
132 * xxx_proc_info structure selected by __lookup_processor_type
133 * above. On return, the CPU will be ready for the MMU to be
134 * turned on, and r0 will hold the CPU control register value.
136 ldr r13, =__mmap_switched @ address to jump to after
137 @ mmu has been enabled
138 adr lr, BSYM(1f) @ return (PIC) address
139 mov r8, r4 @ set TTBR1 to swapper_pg_dir
140 ARM( add pc, r10, #PROCINFO_INITFUNC )
141 THUMB( add r12, r10, #PROCINFO_INITFUNC )
146 #ifndef CONFIG_XIP_KERNEL
152 * Setup the initial page tables. We only setup the barest
153 * amount which are required to get the kernel running, which
154 * generally means mapping in the kernel code.
156 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
159 * r0, r3, r5-r7 corrupted
160 * r4 = physical page table address
162 __create_page_tables:
163 pgtbl r4, r8 @ page table address
166 * Clear the swapper page table
170 add r6, r0, #PG_DIR_SIZE
178 #ifdef CONFIG_ARM_LPAE
180 * Build the PGD table (first level) to point to the PMD table. A PGD
181 * entry is 64-bit wide.
184 add r3, r4, #0x1000 @ first PMD table address
185 orr r3, r3, #3 @ PGD block type
186 mov r6, #4 @ PTRS_PER_PGD
187 mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
189 #ifdef CONFIG_CPU_ENDIAN_BE8
190 str r7, [r0], #4 @ set top PGD entry bits
191 str r3, [r0], #4 @ set bottom PGD entry bits
193 str r3, [r0], #4 @ set bottom PGD entry bits
194 str r7, [r0], #4 @ set top PGD entry bits
196 add r3, r3, #0x1000 @ next PMD table
200 add r4, r4, #0x1000 @ point to the PMD tables
201 #ifdef CONFIG_CPU_ENDIAN_BE8
202 add r4, r4, #4 @ we only write the bottom word
206 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
209 * Create identity mapping to cater for __enable_mmu.
210 * This identity mapping will be removed by paging_init().
212 adr r0, __turn_mmu_on_loc
213 ldmia r0, {r3, r5, r6}
214 sub r0, r0, r3 @ virt->phys offset
215 add r5, r5, r0 @ phys __turn_mmu_on
216 add r6, r6, r0 @ phys __turn_mmu_on_end
217 mov r5, r5, lsr #SECTION_SHIFT
218 mov r6, r6, lsr #SECTION_SHIFT
220 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
221 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
223 addlo r5, r5, #1 @ next section
227 * Map our RAM from the start to the end of the kernel .bss section.
229 add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
232 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
233 1: str r3, [r0], #1 << PMD_ORDER
234 add r3, r3, #1 << SECTION_SHIFT
238 #ifdef CONFIG_XIP_KERNEL
240 * Map the kernel image separately as it is not located in RAM.
242 #define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
244 mov r3, r3, lsr #SECTION_SHIFT
245 orr r3, r7, r3, lsl #SECTION_SHIFT
246 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
247 str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
248 ldr r6, =(_edata_loc - 1)
249 add r0, r0, #1 << PMD_ORDER
250 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
252 add r3, r3, #1 << SECTION_SHIFT
253 strls r3, [r0], #1 << PMD_ORDER
258 * Then map boot params address in r2 if specified.
259 * We map 2 sections in case the ATAGs/DTB crosses a section boundary.
261 mov r0, r2, lsr #SECTION_SHIFT
262 movs r0, r0, lsl #SECTION_SHIFT
264 addne r3, r3, #PAGE_OFFSET
265 addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
267 strne r6, [r3], #1 << PMD_ORDER
268 addne r6, r6, #1 << SECTION_SHIFT
271 #if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
272 sub r4, r4, #4 @ Fixup page table pointer
273 @ for 64-bit descriptors
276 #ifdef CONFIG_DEBUG_LL
277 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
279 * Map in IO space for serial debugging.
280 * This allows debug messages to be output
281 * via a serial console before paging_init.
285 mov r3, r3, lsr #SECTION_SHIFT
286 mov r3, r3, lsl #PMD_ORDER
289 mov r3, r7, lsr #SECTION_SHIFT
290 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
291 orr r3, r7, r3, lsl #SECTION_SHIFT
292 #ifdef CONFIG_ARM_LPAE
293 mov r7, #1 << (54 - 32) @ XN
294 #ifdef CONFIG_CPU_ENDIAN_BE8
302 orr r3, r3, #PMD_SECT_XN
306 #else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
307 /* we don't need any serial debugging mappings */
308 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
311 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
313 * If we're using the NetWinder or CATS, we also need to map
314 * in the 16550-type serial port for the debug messages
316 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
317 orr r3, r7, #0x7c000000
320 #ifdef CONFIG_ARCH_RPC
322 * Map in screen at 0x02000000 & SCREEN2_BASE
323 * Similar reasons here - for debug. This is
324 * only for Acorn RiscPC architectures.
326 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
327 orr r3, r7, #0x02000000
329 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
333 #ifdef CONFIG_ARM_LPAE
334 sub r4, r4, #0x1000 @ point to the PGD table
337 ENDPROC(__create_page_tables)
343 .long __turn_mmu_on_end
345 #if defined(CONFIG_SMP)
347 ENTRY(secondary_startup)
348 #ifdef CONFIG_VFP_OPT
349 ldr r10, =(0xF << 20)
350 mcr p15, 0, r10, c1, c0, 2
351 VFPFMRX r10, FPEXC @ Is the VFP enabled?
352 orr r10, r10, #FPEXC_EN @ user FPEXC has the enable bit set
353 bic r10, r10, #FPEXC_EX @ make sure exceptions are disabled
354 VFPFMXR FPEXC, r10 @ enable VFP, disable any pending
355 @ exceptions, so we can get at the
360 * Common entry point for secondary CPUs.
362 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
363 * the processor type - there is no need to check the machine type
364 * as it has already been validated by the primary processor.
366 #ifdef CONFIG_ARM_VIRT_EXT
367 bl __hyp_stub_install_secondary
369 safe_svcmode_maskall r9
371 mrc p15, 0, r9, c0, c0 @ get processor id
372 bl __lookup_processor_type
373 movs r10, r5 @ invalid processor?
374 moveq r0, #'p' @ yes, error 'p'
375 THUMB( it eq ) @ force fixup-able long branch encoding
379 * Use the page tables supplied from __cpu_up.
381 adr r4, __secondary_data
382 ldmia r4, {r5, r7, r12} @ address to jump to after
383 sub lr, r4, r5 @ mmu has been enabled
384 ldr r4, [r7, lr] @ get secondary_data.pgdir
386 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
387 adr lr, BSYM(__enable_mmu) @ return address
388 mov r13, r12 @ __secondary_switched address
389 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
390 @ (return control reg)
391 THUMB( add r12, r10, #PROCINFO_INITFUNC )
393 ENDPROC(secondary_startup)
396 * r6 = &secondary_data
398 ENTRY(__secondary_switched)
399 ldr sp, [r7, #4] @ get secondary_data.stack
401 b secondary_start_kernel
402 ENDPROC(__secondary_switched)
406 .type __secondary_data, %object
410 .long __secondary_switched
411 #endif /* defined(CONFIG_SMP) */
416 * Setup common bits before finally enabling the MMU. Essentially
417 * this is just loading the page table pointer and domain access
420 * r0 = cp#15 control register
422 * r2 = atags or dtb pointer
423 * r4 = page table pointer
425 * r13 = *virtual* address to jump to upon completion
428 #if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
433 #ifdef CONFIG_CPU_DCACHE_DISABLE
436 #ifdef CONFIG_CPU_BPREDICT_DISABLE
439 #ifdef CONFIG_CPU_ICACHE_DISABLE
442 #ifdef CONFIG_ARM_LPAE
444 mcrr p15, 0, r4, r5, c2 @ load TTBR0
446 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
447 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
448 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
449 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
450 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
451 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
454 ENDPROC(__enable_mmu)
457 * Enable the MMU. This completely changes the structure of the visible
458 * memory space. You will not be able to trace execution through this.
459 * If you have an enquiry about this, *please* check the linux-arm-kernel
460 * mailing list archives BEFORE sending another post to the list.
462 * r0 = cp#15 control register
464 * r2 = atags or dtb pointer
466 * r13 = *virtual* address to jump to upon completion
468 * other registers depend on the function called upon completion
471 .pushsection .idmap.text, "ax"
475 mcr p15, 0, r0, c1, c0, 0 @ write control reg
476 mrc p15, 0, r3, c0, c0, 0 @ read id reg
482 ENDPROC(__turn_mmu_on)
486 #ifdef CONFIG_SMP_ON_UP
489 and r3, r9, #0x000f0000 @ architecture version
490 teq r3, #0x000f0000 @ CPU ID supported?
491 bne __fixup_smp_on_up @ no, assume UP
493 bic r3, r9, #0x00ff0000
494 bic r3, r3, #0x0000000f @ mask 0xff00fff0
496 orr r4, r4, #0x0000b000
497 orr r4, r4, #0x00000020 @ val 0x4100b020
498 teq r3, r4 @ ARM 11MPCore?
499 moveq pc, lr @ yes, assume SMP
501 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
502 and r0, r0, #0xc0000000 @ multiprocessing extensions and
503 teq r0, #0x80000000 @ not part of a uniprocessor system?
504 moveq pc, lr @ yes, assume SMP
512 b __do_fixup_smp_on_up
529 __do_fixup_smp_on_up:
533 ARM( str r6, [r0, r3] )
534 THUMB( add r0, r0, r3 )
536 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
538 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
539 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
540 THUMB( strh r6, [r0] )
541 b __do_fixup_smp_on_up
542 ENDPROC(__do_fixup_smp_on_up)
545 stmfd sp!, {r4 - r6, lr}
549 bl __do_fixup_smp_on_up
550 ldmfd sp!, {r4 - r6, pc}
553 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
555 /* __fixup_pv_table - patch the stub instructions with the delta between
556 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
557 * can be expressed by an immediate shifter operand. The stub instruction
558 * has a form of '(add|sub) rd, rn, #imm'.
563 ldmia r0, {r3-r5, r7}
564 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
565 add r4, r4, r3 @ adjust table start address
566 add r5, r5, r3 @ adjust table end address
567 add r7, r7, r3 @ adjust __pv_phys_offset address
568 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
569 mov r6, r3, lsr #24 @ constant for add/sub instructions
570 teq r3, r6, lsl #24 @ must be 16MiB aligned
571 THUMB( it ne @ cross section branch )
573 str r6, [r7, #4] @ save to __pv_offset
575 ENDPROC(__fixup_pv_table)
579 .long __pv_table_begin
581 2: .long __pv_phys_offset
585 #ifdef CONFIG_THUMB2_KERNEL
594 orr r6, r6, r7, lsl #12
600 orr ip, r6 @ mask in offset bits 31-24
603 ldrcc r7, [r4], #4 @ use branch for delay slot
609 bic ip, ip, #0x000000ff
610 orr ip, ip, r6 @ mask in offset bits 31-24
613 ldrcc r7, [r4], #4 @ use branch for delay slot
617 ENDPROC(__fixup_a_pv_table)
619 ENTRY(fixup_pv_table)
620 stmfd sp!, {r4 - r7, lr}
621 ldr r2, 2f @ get address of __pv_phys_offset
622 mov r3, #0 @ no offset
623 mov r4, r0 @ r0 = table start
624 add r5, r0, r1 @ r1 = table size
625 ldr r6, [r2, #4] @ get __pv_offset
626 bl __fixup_a_pv_table
627 ldmfd sp!, {r4 - r7, pc}
628 ENDPROC(fixup_pv_table)
631 2: .long __pv_phys_offset
634 .globl __pv_phys_offset
635 .type __pv_phys_offset, %object
638 .size __pv_phys_offset, . - __pv_phys_offset
643 #include "head-common.S"