arch/arm/include/asm/pmu.h

   1 /*
   2  *  linux/arch/arm/include/asm/pmu.h
   3  *
   4  *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #ifndef __ARM_PMU_H__
  13 #define __ARM_PMU_H__
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/perf_event.h>
  17
  18 /*
  19  * struct arm_pmu_platdata - ARM PMU platform data
  20  *
  21  * @handle_irq: an optional handler which will be called from the
  22  *      interrupt and passed the address of the low level handler,
  23  *      and can be used to implement any platform specific handling
  24  *      before or after calling it.
  25  * @runtime_resume: an optional handler which will be called by the
  26  *      runtime PM framework following a call to pm_runtime_get().
  27  *      Note that if pm_runtime_get() is called more than once in
  28  *      succession this handler will only be called once.
  29  * @runtime_suspend: an optional handler which will be called by the
  30  *      runtime PM framework following a call to pm_runtime_put().
  31  *      Note that if pm_runtime_get() is called more than once in
  32  *      succession this handler will only be called following the
  33  *      final call to pm_runtime_put() that actually disables the
  34  *      hardware.
  35  */
  36 struct arm_pmu_platdata {
  37         irqreturn_t (*handle_irq)(int irq, void *dev,
  38                                   irq_handler_t pmu_handler);
  39         int (*runtime_resume)(struct device *dev);
  40         int (*runtime_suspend)(struct device *dev);
  41 };
  42
  43 #ifdef CONFIG_HW_PERF_EVENTS
  44
  45 /* The events for a given PMU register set. */
  46 struct pmu_hw_events {
  47         /*
  48          * The events that are active on the PMU for the given index.
  49          */
  50         struct perf_event       **events;
  51
  52         /*
  53          * A 1 bit for an index indicates that the counter is being used for
  54          * an event. A 0 means that the counter can be used.
  55          */
  56         unsigned long           *used_mask;
  57
  58         /*
  59          * Hardware lock to serialize accesses to PMU registers. Needed for the
  60          * read/modify/write sequences.
  61          */
  62         raw_spinlock_t          pmu_lock;
  63 };
  64
  65 struct cpupmu_regs {
  66         u32 pmc;
  67         u32 pmcntenset;
  68         u32 pmuseren;
  69         u32 pmintenset;
  70         u32 pmxevttype[8];
  71         u32 pmxevtcnt[8];
  72 };
  73
  74 struct arm_pmu {
  75         struct pmu      pmu;
  76         cpumask_t       active_irqs;
  77         cpumask_t       valid_cpus;
  78         char            *name;
  79         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
  80         void            (*enable)(struct perf_event *event);
  81         void            (*disable)(struct perf_event *event);
  82         int             (*get_event_idx)(struct pmu_hw_events *hw_events,
  83                                          struct perf_event *event);
  84         int             (*set_event_filter)(struct hw_perf_event *evt,
  85                                             struct perf_event_attr *attr);
  86         u32             (*read_counter)(struct perf_event *event);
  87         void            (*write_counter)(struct perf_event *event, u32 val);
  88         void            (*start)(struct arm_pmu *);
  89         void            (*stop)(struct arm_pmu *);
  90         void            (*reset)(void *);
  91         int             (*request_irq)(struct arm_pmu *, irq_handler_t handler);
  92         void            (*free_irq)(struct arm_pmu *);
  93         int             (*map_event)(struct perf_event *event);
  94         void            (*save_regs)(struct arm_pmu *, struct cpupmu_regs *);
  95         void            (*restore_regs)(struct arm_pmu *, struct cpupmu_regs *);
  96         int             num_events;
  97         atomic_t        active_events;
  98         struct mutex    reserve_mutex;
  99         u64             max_period;
 100         struct platform_device  *plat_device;
 101         struct pmu_hw_events    *(*get_hw_events)(void);
 102 };
 103
 104 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
 105
 106 extern const struct dev_pm_ops armpmu_dev_pm_ops;
 107
 108 int armpmu_register(struct arm_pmu *armpmu, int type);
 109
 110 u64 armpmu_event_update(struct perf_event *event);
 111
 112 int armpmu_event_set_period(struct perf_event *event);
 113
 114 int armpmu_map_event(struct perf_event *event,
 115                      const unsigned (*event_map)[PERF_COUNT_HW_MAX],
 116                      const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
 117                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 118                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
 119                      u32 raw_event_mask);
 120
 121 #endif /* CONFIG_HW_PERF_EVENTS */
 122
 123 #endif /* __ARM_PMU_H__ */