arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts

   1 /*
   2  * ARM Ltd. Versatile Express
   3  *
   4  * CoreTile Express A15x2 A7x3
   5  * Cortex-A15_A7 MPCore (V2P-CA15_A7)
   6  *
   7  * HBI-0249A
   8  */
   9
  10 /dts-v1/;
  11
  12 / {
  13         model = "V2P-CA15_CA7";
  14         arm,hbi = <0x249>;
  15         arm,vexpress,site = <0xf>;
  16         compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         chosen { };
  22
  23         aliases {
  24                 serial0 = &v2m_serial0;
  25                 serial1 = &v2m_serial1;
  26                 serial2 = &v2m_serial2;
  27                 serial3 = &v2m_serial3;
  28                 i2c0 = &v2m_i2c_dvi;
  29                 i2c1 = &v2m_i2c_pcie;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@0 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0>;
  40                         cci-control-port = <&cci_control1>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a15";
  46                         reg = <1>;
  47                         cci-control-port = <&cci_control1>;
  48                 };
  49
  50                 cpu2: cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0x100>;
  54                         cci-control-port = <&cci_control2>;
  55                 };
  56
  57                 cpu3: cpu@3 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <0x101>;
  61                         cci-control-port = <&cci_control2>;
  62                 };
  63
  64                 cpu4: cpu@4 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0x102>;
  68                         cci-control-port = <&cci_control2>;
  69                 };
  70         };
  71
  72         memory@80000000 {
  73                 device_type = "memory";
  74                 reg = <0 0x80000000 0 0x40000000>;
  75         };
  76
  77         wdt@2a490000 {
  78                 compatible = "arm,sp805", "arm,primecell";
  79                 reg = <0 0x2a490000 0 0x1000>;
  80                 interrupts = <0 98 4>;
  81                 clocks = <&oscclk6a>, <&oscclk6a>;
  82                 clock-names = "wdogclk", "apb_pclk";
  83         };
  84
  85         hdlcd@2b000000 {
  86                 compatible = "arm,hdlcd";
  87                 reg = <0 0x2b000000 0 0x1000>;
  88                 interrupts = <0 85 4>;
  89                 clocks = <&oscclk5>;
  90                 clock-names = "pxlclk";
  91         };
  92
  93         memory-controller@2b0a0000 {
  94                 compatible = "arm,pl341", "arm,primecell";
  95                 reg = <0 0x2b0a0000 0 0x1000>;
  96                 clocks = <&oscclk6a>;
  97                 clock-names = "apb_pclk";
  98         };
  99
 100         gic: interrupt-controller@2c001000 {
 101                 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 102                 #interrupt-cells = <3>;
 103                 #address-cells = <0>;
 104                 interrupt-controller;
 105                 reg = <0 0x2c001000 0 0x1000>,
 106                       <0 0x2c002000 0 0x1000>,
 107                       <0 0x2c004000 0 0x2000>,
 108                       <0 0x2c006000 0 0x2000>;
 109                 interrupts = <1 9 0xf04>;
 110         };
 111
 112         cci@2c090000 {
 113                 compatible = "arm,cci-400";
 114                 #address-cells = <1>;
 115                 #size-cells = <1>;
 116                 reg = <0 0x2c090000 0 0x1000>;
 117                 ranges = <0x0 0x0 0x2c090000 0x10000>;
 118
 119                 cci_control1: slave-if@4000 {
 120                         compatible = "arm,cci-400-ctrl-if";
 121                         interface-type = "ace";
 122                         reg = <0x4000 0x1000>;
 123                 };
 124
 125                 cci_control2: slave-if@5000 {
 126                         compatible = "arm,cci-400-ctrl-if";
 127                         interface-type = "ace";
 128                         reg = <0x5000 0x1000>;
 129                 };
 130         };
 131
 132         cci-pmu@2c099000 {
 133                 compatible = "arm,cci-400-pmu";
 134                 reg = <0 0x2c099000 0 0x6000>;
 135                 interrupts = <0 101 4>,
 136                              <0 102 4>,
 137                              <0 103 4>,
 138                              <0 104 4>,
 139                              <0 105 4>;
 140         };
 141
 142         memory-controller@7ffd0000 {
 143                 compatible = "arm,pl354", "arm,primecell";
 144                 reg = <0 0x7ffd0000 0 0x1000>;
 145                 interrupts = <0 86 4>,
 146                              <0 87 4>;
 147                 clocks = <&oscclk6a>;
 148                 clock-names = "apb_pclk";
 149         };
 150
 151         dma@7ff00000 {
 152                 compatible = "arm,pl330", "arm,primecell";
 153                 reg = <0 0x7ff00000 0 0x1000>;
 154                 interrupts = <0 92 4>,
 155                              <0 88 4>,
 156                              <0 89 4>,
 157                              <0 90 4>,
 158                              <0 91 4>;
 159                 clocks = <&oscclk6a>;
 160                 clock-names = "apb_pclk";
 161         };
 162
 163         timer {
 164                 compatible = "arm,armv7-timer";
 165                 interrupts = <1 13 0xf08>,
 166                              <1 14 0xf08>,
 167                              <1 11 0xf08>,
 168                              <1 10 0xf08>;
 169         };
 170
 171         pmu {
 172                 compatible = "arm,cortex-a15-pmu";
 173                 interrupts = <0 68 4>,
 174                              <0 69 4>;
 175         };
 176
 177         oscclk6a: oscclk6a {
 178                 /* Reference 24MHz clock */
 179                 compatible = "fixed-clock";
 180                 #clock-cells = <0>;
 181                 clock-frequency = <24000000>;
 182                 clock-output-names = "oscclk6a";
 183         };
 184
 185         dcc {
 186                 compatible = "arm,vexpress,config-bus";
 187                 arm,vexpress,config-bridge = <&v2m_sysreg>;
 188
 189                 osc@0 {
 190                         /* A15 PLL 0 reference clock */
 191                         compatible = "arm,vexpress-osc";
 192                         arm,vexpress-sysreg,func = <1 0>;
 193                         freq-range = <17000000 50000000>;
 194                         #clock-cells = <0>;
 195                         clock-output-names = "oscclk0";
 196                 };
 197
 198                 osc@1 {
 199                         /* A15 PLL 1 reference clock */
 200                         compatible = "arm,vexpress-osc";
 201                         arm,vexpress-sysreg,func = <1 1>;
 202                         freq-range = <17000000 50000000>;
 203                         #clock-cells = <0>;
 204                         clock-output-names = "oscclk1";
 205                 };
 206
 207                 osc@2 {
 208                         /* A7 PLL 0 reference clock */
 209                         compatible = "arm,vexpress-osc";
 210                         arm,vexpress-sysreg,func = <1 2>;
 211                         freq-range = <17000000 50000000>;
 212                         #clock-cells = <0>;
 213                         clock-output-names = "oscclk2";
 214                 };
 215
 216                 osc@3 {
 217                         /* A7 PLL 1 reference clock */
 218                         compatible = "arm,vexpress-osc";
 219                         arm,vexpress-sysreg,func = <1 3>;
 220                         freq-range = <17000000 50000000>;
 221                         #clock-cells = <0>;
 222                         clock-output-names = "oscclk3";
 223                 };
 224
 225                 osc@4 {
 226                         /* External AXI master clock */
 227                         compatible = "arm,vexpress-osc";
 228                         arm,vexpress-sysreg,func = <1 4>;
 229                         freq-range = <20000000 40000000>;
 230                         #clock-cells = <0>;
 231                         clock-output-names = "oscclk4";
 232                 };
 233
 234                 oscclk5: osc@5 {
 235                         /* HDLCD PLL reference clock */
 236                         compatible = "arm,vexpress-osc";
 237                         arm,vexpress-sysreg,func = <1 5>;
 238                         freq-range = <23750000 165000000>;
 239                         #clock-cells = <0>;
 240                         clock-output-names = "oscclk5";
 241                 };
 242
 243                 smbclk: osc@6 {
 244                         /* Static memory controller clock */
 245                         compatible = "arm,vexpress-osc";
 246                         arm,vexpress-sysreg,func = <1 6>;
 247                         freq-range = <20000000 40000000>;
 248                         #clock-cells = <0>;
 249                         clock-output-names = "oscclk6";
 250                 };
 251
 252                 osc@7 {
 253                         /* SYS PLL reference clock */
 254                         compatible = "arm,vexpress-osc";
 255                         arm,vexpress-sysreg,func = <1 7>;
 256                         freq-range = <17000000 50000000>;
 257                         #clock-cells = <0>;
 258                         clock-output-names = "oscclk7";
 259                 };
 260
 261                 osc@8 {
 262                         /* DDR2 PLL reference clock */
 263                         compatible = "arm,vexpress-osc";
 264                         arm,vexpress-sysreg,func = <1 8>;
 265                         freq-range = <20000000 50000000>;
 266                         #clock-cells = <0>;
 267                         clock-output-names = "oscclk8";
 268                 };
 269
 270                 volt@0 {
 271                         /* A15 CPU core voltage */
 272                         compatible = "arm,vexpress-volt";
 273                         arm,vexpress-sysreg,func = <2 0>;
 274                         regulator-name = "A15 Vcore";
 275                         regulator-min-microvolt = <800000>;
 276                         regulator-max-microvolt = <1050000>;
 277                         regulator-always-on;
 278                         label = "A15 Vcore";
 279                 };
 280
 281                 volt@1 {
 282                         /* A7 CPU core voltage */
 283                         compatible = "arm,vexpress-volt";
 284                         arm,vexpress-sysreg,func = <2 1>;
 285                         regulator-name = "A7 Vcore";
 286                         regulator-min-microvolt = <800000>;
 287                         regulator-max-microvolt = <1050000>;
 288                         regulator-always-on;
 289                         label = "A7 Vcore";
 290                 };
 291
 292                 amp@0 {
 293                         /* Total current for the two A15 cores */
 294                         compatible = "arm,vexpress-amp";
 295                         arm,vexpress-sysreg,func = <3 0>;
 296                         label = "A15 Icore";
 297                 };
 298
 299                 amp@1 {
 300                         /* Total current for the three A7 cores */
 301                         compatible = "arm,vexpress-amp";
 302                         arm,vexpress-sysreg,func = <3 1>;
 303                         label = "A7 Icore";
 304                 };
 305
 306                 temp@0 {
 307                         /* DCC internal temperature */
 308                         compatible = "arm,vexpress-temp";
 309                         arm,vexpress-sysreg,func = <4 0>;
 310                         label = "DCC";
 311                 };
 312
 313                 power@0 {
 314                         /* Total power for the two A15 cores */
 315                         compatible = "arm,vexpress-power";
 316                         arm,vexpress-sysreg,func = <12 0>;
 317                         label = "A15 Pcore";
 318                 };
 319                 power@1 {
 320                         /* Total power for the three A7 cores */
 321                         compatible = "arm,vexpress-power";
 322                         arm,vexpress-sysreg,func = <12 1>;
 323                         label = "A7 Pcore";
 324                 };
 325
 326                 energy@0 {
 327                         /* Total energy for the two A15 cores */
 328                         compatible = "arm,vexpress-energy";
 329                         arm,vexpress-sysreg,func = <13 0>;
 330                         label = "A15 Jcore";
 331                 };
 332
 333                 energy@2 {
 334                         /* Total energy for the three A7 cores */
 335                         compatible = "arm,vexpress-energy";
 336                         arm,vexpress-sysreg,func = <13 2>;
 337                         label = "A7 Jcore";
 338                 };
 339         };
 340
 341         smb {
 342                 compatible = "simple-bus";
 343
 344                 #address-cells = <2>;
 345                 #size-cells = <1>;
 346                 ranges = <0 0 0 0x08000000 0x04000000>,
 347                          <1 0 0 0x14000000 0x04000000>,
 348                          <2 0 0 0x18000000 0x04000000>,
 349                          <3 0 0 0x1c000000 0x04000000>,
 350                          <4 0 0 0x0c000000 0x04000000>,
 351                          <5 0 0 0x10000000 0x04000000>;
 352
 353                 #interrupt-cells = <1>;
 354                 interrupt-map-mask = <0 0 63>;
 355                 interrupt-map = <0 0  0 &gic 0  0 4>,
 356                                 <0 0  1 &gic 0  1 4>,
 357                                 <0 0  2 &gic 0  2 4>,
 358                                 <0 0  3 &gic 0  3 4>,
 359                                 <0 0  4 &gic 0  4 4>,
 360                                 <0 0  5 &gic 0  5 4>,
 361                                 <0 0  6 &gic 0  6 4>,
 362                                 <0 0  7 &gic 0  7 4>,
 363                                 <0 0  8 &gic 0  8 4>,
 364                                 <0 0  9 &gic 0  9 4>,
 365                                 <0 0 10 &gic 0 10 4>,
 366                                 <0 0 11 &gic 0 11 4>,
 367                                 <0 0 12 &gic 0 12 4>,
 368                                 <0 0 13 &gic 0 13 4>,
 369                                 <0 0 14 &gic 0 14 4>,
 370                                 <0 0 15 &gic 0 15 4>,
 371                                 <0 0 16 &gic 0 16 4>,
 372                                 <0 0 17 &gic 0 17 4>,
 373                                 <0 0 18 &gic 0 18 4>,
 374                                 <0 0 19 &gic 0 19 4>,
 375                                 <0 0 20 &gic 0 20 4>,
 376                                 <0 0 21 &gic 0 21 4>,
 377                                 <0 0 22 &gic 0 22 4>,
 378                                 <0 0 23 &gic 0 23 4>,
 379                                 <0 0 24 &gic 0 24 4>,
 380                                 <0 0 25 &gic 0 25 4>,
 381                                 <0 0 26 &gic 0 26 4>,
 382                                 <0 0 27 &gic 0 27 4>,
 383                                 <0 0 28 &gic 0 28 4>,
 384                                 <0 0 29 &gic 0 29 4>,
 385                                 <0 0 30 &gic 0 30 4>,
 386                                 <0 0 31 &gic 0 31 4>,
 387                                 <0 0 32 &gic 0 32 4>,
 388                                 <0 0 33 &gic 0 33 4>,
 389                                 <0 0 34 &gic 0 34 4>,
 390                                 <0 0 35 &gic 0 35 4>,
 391                                 <0 0 36 &gic 0 36 4>,
 392                                 <0 0 37 &gic 0 37 4>,
 393                                 <0 0 38 &gic 0 38 4>,
 394                                 <0 0 39 &gic 0 39 4>,
 395                                 <0 0 40 &gic 0 40 4>,
 396                                 <0 0 41 &gic 0 41 4>,
 397                                 <0 0 42 &gic 0 42 4>;
 398
 399                 /include/ "vexpress-v2m-rs1.dtsi"
 400         };
 401 };