2 * ARM Ltd. Versatile Express
4 * CoreTile Express A15x2 A7x3
5 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
13 model = "V2P-CA15_CA7";
15 arm,vexpress,site = <0xf>;
16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
17 interrupt-parent = <&gic>;
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
38 compatible = "arm,cortex-a15";
40 cci-control-port = <&cci_control1>;
45 compatible = "arm,cortex-a15";
47 cci-control-port = <&cci_control1>;
52 compatible = "arm,cortex-a7";
54 cci-control-port = <&cci_control2>;
59 compatible = "arm,cortex-a7";
61 cci-control-port = <&cci_control2>;
66 compatible = "arm,cortex-a7";
68 cci-control-port = <&cci_control2>;
73 device_type = "memory";
74 reg = <0 0x80000000 0 0x40000000>;
78 compatible = "arm,sp805", "arm,primecell";
79 reg = <0 0x2a490000 0 0x1000>;
80 interrupts = <0 98 4>;
81 clocks = <&oscclk6a>, <&oscclk6a>;
82 clock-names = "wdogclk", "apb_pclk";
86 compatible = "arm,hdlcd";
87 reg = <0 0x2b000000 0 0x1000>;
88 interrupts = <0 85 4>;
90 clock-names = "pxlclk";
93 memory-controller@2b0a0000 {
94 compatible = "arm,pl341", "arm,primecell";
95 reg = <0 0x2b0a0000 0 0x1000>;
97 clock-names = "apb_pclk";
100 gic: interrupt-controller@2c001000 {
101 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
102 #interrupt-cells = <3>;
103 #address-cells = <0>;
104 interrupt-controller;
105 reg = <0 0x2c001000 0 0x1000>,
106 <0 0x2c002000 0 0x1000>,
107 <0 0x2c004000 0 0x2000>,
108 <0 0x2c006000 0 0x2000>;
109 interrupts = <1 9 0xf04>;
113 compatible = "arm,cci-400";
114 #address-cells = <1>;
116 reg = <0 0x2c090000 0 0x1000>;
117 ranges = <0x0 0x0 0x2c090000 0x10000>;
119 cci_control1: slave-if@4000 {
120 compatible = "arm,cci-400-ctrl-if";
121 interface-type = "ace";
122 reg = <0x4000 0x1000>;
125 cci_control2: slave-if@5000 {
126 compatible = "arm,cci-400-ctrl-if";
127 interface-type = "ace";
128 reg = <0x5000 0x1000>;
133 compatible = "arm,cci-400-pmu";
134 reg = <0 0x2c099000 0 0x6000>;
135 interrupts = <0 101 4>,
142 memory-controller@7ffd0000 {
143 compatible = "arm,pl354", "arm,primecell";
144 reg = <0 0x7ffd0000 0 0x1000>;
145 interrupts = <0 86 4>,
147 clocks = <&oscclk6a>;
148 clock-names = "apb_pclk";
152 compatible = "arm,pl330", "arm,primecell";
153 reg = <0 0x7ff00000 0 0x1000>;
154 interrupts = <0 92 4>,
159 clocks = <&oscclk6a>;
160 clock-names = "apb_pclk";
164 compatible = "arm,armv7-timer";
165 interrupts = <1 13 0xf08>,
172 compatible = "arm,cortex-a15-pmu";
173 interrupts = <0 68 4>,
178 /* Reference 24MHz clock */
179 compatible = "fixed-clock";
181 clock-frequency = <24000000>;
182 clock-output-names = "oscclk6a";
186 compatible = "arm,vexpress,config-bus";
187 arm,vexpress,config-bridge = <&v2m_sysreg>;
190 /* A15 PLL 0 reference clock */
191 compatible = "arm,vexpress-osc";
192 arm,vexpress-sysreg,func = <1 0>;
193 freq-range = <17000000 50000000>;
195 clock-output-names = "oscclk0";
199 /* A15 PLL 1 reference clock */
200 compatible = "arm,vexpress-osc";
201 arm,vexpress-sysreg,func = <1 1>;
202 freq-range = <17000000 50000000>;
204 clock-output-names = "oscclk1";
208 /* A7 PLL 0 reference clock */
209 compatible = "arm,vexpress-osc";
210 arm,vexpress-sysreg,func = <1 2>;
211 freq-range = <17000000 50000000>;
213 clock-output-names = "oscclk2";
217 /* A7 PLL 1 reference clock */
218 compatible = "arm,vexpress-osc";
219 arm,vexpress-sysreg,func = <1 3>;
220 freq-range = <17000000 50000000>;
222 clock-output-names = "oscclk3";
226 /* External AXI master clock */
227 compatible = "arm,vexpress-osc";
228 arm,vexpress-sysreg,func = <1 4>;
229 freq-range = <20000000 40000000>;
231 clock-output-names = "oscclk4";
235 /* HDLCD PLL reference clock */
236 compatible = "arm,vexpress-osc";
237 arm,vexpress-sysreg,func = <1 5>;
238 freq-range = <23750000 165000000>;
240 clock-output-names = "oscclk5";
244 /* Static memory controller clock */
245 compatible = "arm,vexpress-osc";
246 arm,vexpress-sysreg,func = <1 6>;
247 freq-range = <20000000 40000000>;
249 clock-output-names = "oscclk6";
253 /* SYS PLL reference clock */
254 compatible = "arm,vexpress-osc";
255 arm,vexpress-sysreg,func = <1 7>;
256 freq-range = <17000000 50000000>;
258 clock-output-names = "oscclk7";
262 /* DDR2 PLL reference clock */
263 compatible = "arm,vexpress-osc";
264 arm,vexpress-sysreg,func = <1 8>;
265 freq-range = <20000000 50000000>;
267 clock-output-names = "oscclk8";
271 /* A15 CPU core voltage */
272 compatible = "arm,vexpress-volt";
273 arm,vexpress-sysreg,func = <2 0>;
274 regulator-name = "A15 Vcore";
275 regulator-min-microvolt = <800000>;
276 regulator-max-microvolt = <1050000>;
282 /* A7 CPU core voltage */
283 compatible = "arm,vexpress-volt";
284 arm,vexpress-sysreg,func = <2 1>;
285 regulator-name = "A7 Vcore";
286 regulator-min-microvolt = <800000>;
287 regulator-max-microvolt = <1050000>;
293 /* Total current for the two A15 cores */
294 compatible = "arm,vexpress-amp";
295 arm,vexpress-sysreg,func = <3 0>;
300 /* Total current for the three A7 cores */
301 compatible = "arm,vexpress-amp";
302 arm,vexpress-sysreg,func = <3 1>;
307 /* DCC internal temperature */
308 compatible = "arm,vexpress-temp";
309 arm,vexpress-sysreg,func = <4 0>;
314 /* Total power for the two A15 cores */
315 compatible = "arm,vexpress-power";
316 arm,vexpress-sysreg,func = <12 0>;
320 /* Total power for the three A7 cores */
321 compatible = "arm,vexpress-power";
322 arm,vexpress-sysreg,func = <12 1>;
327 /* Total energy for the two A15 cores */
328 compatible = "arm,vexpress-energy";
329 arm,vexpress-sysreg,func = <13 0>;
334 /* Total energy for the three A7 cores */
335 compatible = "arm,vexpress-energy";
336 arm,vexpress-sysreg,func = <13 2>;
342 compatible = "simple-bus";
344 #address-cells = <2>;
346 ranges = <0 0 0 0x08000000 0x04000000>,
347 <1 0 0 0x14000000 0x04000000>,
348 <2 0 0 0x18000000 0x04000000>,
349 <3 0 0 0x1c000000 0x04000000>,
350 <4 0 0 0x0c000000 0x04000000>,
351 <5 0 0 0x10000000 0x04000000>;
353 #interrupt-cells = <1>;
354 interrupt-map-mask = <0 0 63>;
355 interrupt-map = <0 0 0 &gic 0 0 4>,
365 <0 0 10 &gic 0 10 4>,
366 <0 0 11 &gic 0 11 4>,
367 <0 0 12 &gic 0 12 4>,
368 <0 0 13 &gic 0 13 4>,
369 <0 0 14 &gic 0 14 4>,
370 <0 0 15 &gic 0 15 4>,
371 <0 0 16 &gic 0 16 4>,
372 <0 0 17 &gic 0 17 4>,
373 <0 0 18 &gic 0 18 4>,
374 <0 0 19 &gic 0 19 4>,
375 <0 0 20 &gic 0 20 4>,
376 <0 0 21 &gic 0 21 4>,
377 <0 0 22 &gic 0 22 4>,
378 <0 0 23 &gic 0 23 4>,
379 <0 0 24 &gic 0 24 4>,
380 <0 0 25 &gic 0 25 4>,
381 <0 0 26 &gic 0 26 4>,
382 <0 0 27 &gic 0 27 4>,
383 <0 0 28 &gic 0 28 4>,
384 <0 0 29 &gic 0 29 4>,
385 <0 0 30 &gic 0 30 4>,
386 <0 0 31 &gic 0 31 4>,
387 <0 0 32 &gic 0 32 4>,
388 <0 0 33 &gic 0 33 4>,
389 <0 0 34 &gic 0 34 4>,
390 <0 0 35 &gic 0 35 4>,
391 <0 0 36 &gic 0 36 4>,
392 <0 0 37 &gic 0 37 4>,
393 <0 0 38 &gic 0 38 4>,
394 <0 0 39 &gic 0 39 4>,
395 <0 0 40 &gic 0 40 4>,
396 <0 0 41 &gic 0 41 4>,
397 <0 0 42 &gic 0 42 4>;
399 /include/ "vexpress-v2m-rs1.dtsi"